From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
Date: Wed, 4 Aug 2021 10:59:21 +1000 [thread overview]
Message-ID: <CAKmqyKMaVkaGgrqwVmr+r+5QuZtTovpE526iruf+qTiZRp08hA@mail.gmail.com> (raw)
In-Reply-To: <20210724122407.2486558-2-anup.patel@wdc.com>
On Sat, Jul 24, 2021 at 10:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
> implementation so let's first rename the sources.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/Kconfig | 2 +-
> hw/intc/meson.build | 2 +-
> hw/intc/{sifive_clint.c => riscv_aclint.c} | 2 +-
> hw/riscv/Kconfig | 12 ++++++------
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/shakti_c.c | 2 +-
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> include/hw/intc/{sifive_clint.h => riscv_aclint.h} | 0
> 11 files changed, 15 insertions(+), 15 deletions(-)
> rename hw/intc/{sifive_clint.c => riscv_aclint.c} (99%)
> rename include/hw/intc/{sifive_clint.h => riscv_aclint.h} (100%)
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f4694088a4..78aed93c45 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -62,7 +62,7 @@ config RX_ICU
> config LOONGSON_LIOINTC
> bool
>
> -config SIFIVE_CLINT
> +config RISCV_ACLINT
> bool
>
> config SIFIVE_PLIC
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 6e52a166e3..9c9338a9e4 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -46,7 +46,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
> specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
> specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
> specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
> -specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
> specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
> specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
> specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
> diff --git a/hw/intc/sifive_clint.c b/hw/intc/riscv_aclint.c
> similarity index 99%
> rename from hw/intc/sifive_clint.c
> rename to hw/intc/riscv_aclint.c
> index 8a460fdf00..0f940e332b 100644
> --- a/hw/intc/sifive_clint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -26,7 +26,7 @@
> #include "hw/sysbus.h"
> #include "target/riscv/cpu.h"
> #include "hw/qdev-properties.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "qemu/timer.h"
> #include "hw/irq.h"
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 86957ec7b0..bfa46694b7 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -9,7 +9,7 @@ config MICROCHIP_PFSOC
> select MCHP_PFSOC_MMUART
> select MCHP_PFSOC_SYSREG
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PDMA
> select SIFIVE_PLIC
> select UNIMP
> @@ -26,7 +26,7 @@ config SHAKTI_C
> bool
> select UNIMP
> select SHAKTI
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
>
> config RISCV_VIRT
> @@ -40,7 +40,7 @@ config RISCV_VIRT
> select PCI_EXPRESS_GENERIC_BRIDGE
> select PFLASH_CFI01
> select SERIAL
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
> select SIFIVE_TEST
> select VIRTIO_MMIO
> @@ -49,7 +49,7 @@ config RISCV_VIRT
> config SIFIVE_E
> bool
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PLIC
> select SIFIVE_UART
> @@ -60,7 +60,7 @@ config SIFIVE_U
> bool
> select CADENCE
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PDMA
> select SIFIVE_PLIC
> @@ -76,5 +76,5 @@ config SPIKE
> bool
> select HTIF
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index eef55f69fd..eed9e81355 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -49,7 +49,7 @@
> #include "hw/riscv/boot.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/microchip_pfsoc.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "sysemu/device_tree.h"
> #include "sysemu/sysemu.h"
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index 09d4e1433e..f9f0a45651 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -21,7 +21,7 @@
> #include "hw/riscv/shakti_c.h"
> #include "qapi/error.h"
> #include "hw/intc/sifive_plic.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "sysemu/sysemu.h"
> #include "hw/qdev-properties.h"
> #include "exec/address-spaces.h"
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 03bff21527..1c55435d8a 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -41,7 +41,7 @@
> #include "hw/riscv/sifive_e.h"
> #include "hw/riscv/boot.h"
> #include "hw/char/sifive_uart.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "hw/misc/sifive_e_prci.h"
> #include "chardev/char.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index e4eeb25596..d1211e1c3d 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -51,7 +51,7 @@
> #include "hw/riscv/sifive_u.h"
> #include "hw/riscv/boot.h"
> #include "hw/char/sifive_uart.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "chardev/char.h"
> #include "net/eth.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index fead77f0c4..f682b7ed4e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -35,7 +35,7 @@
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> #include "hw/char/riscv_htif.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "chardev/char.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 4db40bacae..66de5d3767 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -32,7 +32,7 @@
> #include "hw/riscv/virt.h"
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "hw/misc/sifive_test.h"
> #include "chardev/char.h"
> diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/riscv_aclint.h
> similarity index 100%
> rename from include/hw/intc/sifive_clint.h
> rename to include/hw/intc/riscv_aclint.h
> --
> 2.25.1
>
>
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Anup Patel <anup.patel@wdc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Atish Patra <atish.patra@wdc.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Anup Patel <anup@brainfault.org>
Subject: Re: [PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources
Date: Wed, 4 Aug 2021 10:59:21 +1000 [thread overview]
Message-ID: <CAKmqyKMaVkaGgrqwVmr+r+5QuZtTovpE526iruf+qTiZRp08hA@mail.gmail.com> (raw)
In-Reply-To: <20210724122407.2486558-2-anup.patel@wdc.com>
On Sat, Jul 24, 2021 at 10:24 PM Anup Patel <anup.patel@wdc.com> wrote:
>
> We will be upgrading SiFive CLINT implementation into RISC-V ACLINT
> implementation so let's first rename the sources.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/intc/Kconfig | 2 +-
> hw/intc/meson.build | 2 +-
> hw/intc/{sifive_clint.c => riscv_aclint.c} | 2 +-
> hw/riscv/Kconfig | 12 ++++++------
> hw/riscv/microchip_pfsoc.c | 2 +-
> hw/riscv/shakti_c.c | 2 +-
> hw/riscv/sifive_e.c | 2 +-
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> include/hw/intc/{sifive_clint.h => riscv_aclint.h} | 0
> 11 files changed, 15 insertions(+), 15 deletions(-)
> rename hw/intc/{sifive_clint.c => riscv_aclint.c} (99%)
> rename include/hw/intc/{sifive_clint.h => riscv_aclint.h} (100%)
>
> diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
> index f4694088a4..78aed93c45 100644
> --- a/hw/intc/Kconfig
> +++ b/hw/intc/Kconfig
> @@ -62,7 +62,7 @@ config RX_ICU
> config LOONGSON_LIOINTC
> bool
>
> -config SIFIVE_CLINT
> +config RISCV_ACLINT
> bool
>
> config SIFIVE_PLIC
> diff --git a/hw/intc/meson.build b/hw/intc/meson.build
> index 6e52a166e3..9c9338a9e4 100644
> --- a/hw/intc/meson.build
> +++ b/hw/intc/meson.build
> @@ -46,7 +46,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
> specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c'))
> specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kvm.c'))
> specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
> -specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c'))
> +specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
> specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
> specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
> specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
> diff --git a/hw/intc/sifive_clint.c b/hw/intc/riscv_aclint.c
> similarity index 99%
> rename from hw/intc/sifive_clint.c
> rename to hw/intc/riscv_aclint.c
> index 8a460fdf00..0f940e332b 100644
> --- a/hw/intc/sifive_clint.c
> +++ b/hw/intc/riscv_aclint.c
> @@ -26,7 +26,7 @@
> #include "hw/sysbus.h"
> #include "target/riscv/cpu.h"
> #include "hw/qdev-properties.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "qemu/timer.h"
> #include "hw/irq.h"
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 86957ec7b0..bfa46694b7 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -9,7 +9,7 @@ config MICROCHIP_PFSOC
> select MCHP_PFSOC_MMUART
> select MCHP_PFSOC_SYSREG
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PDMA
> select SIFIVE_PLIC
> select UNIMP
> @@ -26,7 +26,7 @@ config SHAKTI_C
> bool
> select UNIMP
> select SHAKTI
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
>
> config RISCV_VIRT
> @@ -40,7 +40,7 @@ config RISCV_VIRT
> select PCI_EXPRESS_GENERIC_BRIDGE
> select PFLASH_CFI01
> select SERIAL
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
> select SIFIVE_TEST
> select VIRTIO_MMIO
> @@ -49,7 +49,7 @@ config RISCV_VIRT
> config SIFIVE_E
> bool
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PLIC
> select SIFIVE_UART
> @@ -60,7 +60,7 @@ config SIFIVE_U
> bool
> select CADENCE
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_GPIO
> select SIFIVE_PDMA
> select SIFIVE_PLIC
> @@ -76,5 +76,5 @@ config SPIKE
> bool
> select HTIF
> select MSI_NONBROKEN
> - select SIFIVE_CLINT
> + select RISCV_ACLINT
> select SIFIVE_PLIC
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index eef55f69fd..eed9e81355 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -49,7 +49,7 @@
> #include "hw/riscv/boot.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/microchip_pfsoc.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "sysemu/device_tree.h"
> #include "sysemu/sysemu.h"
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index 09d4e1433e..f9f0a45651 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -21,7 +21,7 @@
> #include "hw/riscv/shakti_c.h"
> #include "qapi/error.h"
> #include "hw/intc/sifive_plic.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "sysemu/sysemu.h"
> #include "hw/qdev-properties.h"
> #include "exec/address-spaces.h"
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 03bff21527..1c55435d8a 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -41,7 +41,7 @@
> #include "hw/riscv/sifive_e.h"
> #include "hw/riscv/boot.h"
> #include "hw/char/sifive_uart.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "hw/misc/sifive_e_prci.h"
> #include "chardev/char.h"
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index e4eeb25596..d1211e1c3d 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -51,7 +51,7 @@
> #include "hw/riscv/sifive_u.h"
> #include "hw/riscv/boot.h"
> #include "hw/char/sifive_uart.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "chardev/char.h"
> #include "net/eth.h"
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index fead77f0c4..f682b7ed4e 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -35,7 +35,7 @@
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> #include "hw/char/riscv_htif.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "chardev/char.h"
> #include "sysemu/arch_init.h"
> #include "sysemu/device_tree.h"
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 4db40bacae..66de5d3767 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -32,7 +32,7 @@
> #include "hw/riscv/virt.h"
> #include "hw/riscv/boot.h"
> #include "hw/riscv/numa.h"
> -#include "hw/intc/sifive_clint.h"
> +#include "hw/intc/riscv_aclint.h"
> #include "hw/intc/sifive_plic.h"
> #include "hw/misc/sifive_test.h"
> #include "chardev/char.h"
> diff --git a/include/hw/intc/sifive_clint.h b/include/hw/intc/riscv_aclint.h
> similarity index 100%
> rename from include/hw/intc/sifive_clint.h
> rename to include/hw/intc/riscv_aclint.h
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-08-04 1:03 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-24 12:24 [PATCH v2 0/4] QEMU RISC-V ACLINT Support Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-07-24 12:24 ` [PATCH v2 1/4] hw/intc: Rename sifive_clint sources to riscv_aclint sources Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-04 0:59 ` Alistair Francis [this message]
2021-08-04 0:59 ` Alistair Francis
2021-08-06 1:34 ` Bin Meng
2021-08-06 1:34 ` Bin Meng
2021-07-24 12:24 ` [PATCH v2 2/4] hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-06 2:25 ` Bin Meng
2021-08-06 2:25 ` Bin Meng
2021-08-27 10:08 ` Anup Patel
2021-08-27 10:08 ` Anup Patel
2021-07-24 12:24 ` [PATCH v2 3/4] hw/riscv: virt: Re-factor FDT generation Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-05 6:08 ` Alistair Francis
2021-08-05 6:08 ` Alistair Francis
2021-08-06 2:26 ` Bin Meng
2021-08-06 2:26 ` Bin Meng
2021-07-24 12:24 ` [PATCH v2 4/4] hw/riscv: virt: Add optional ACLINT support to virt machine Anup Patel
2021-07-24 12:24 ` Anup Patel
2021-08-05 6:09 ` Alistair Francis
2021-08-05 6:09 ` Alistair Francis
2021-08-05 6:12 ` Alistair Francis
2021-08-05 6:12 ` Alistair Francis
2021-08-06 2:30 ` Bin Meng
2021-08-06 2:30 ` Bin Meng
2021-08-27 10:29 ` Anup Patel
2021-08-27 10:29 ` Anup Patel
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