From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Rob Herring <robh@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Kevin Hilman <khilman@baylibre.com>,
Yue Wang <yue.wang@amlogic.com>,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, Carlo Caione <carlo@caione.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Liang Yang <liang.yang@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Victor Wan <victor.wan@amlogic.com>,
Xingyu Chen <xingyu.chen@amlogic.com>
Subject: Re: [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
Date: Fri, 27 Dec 2019 17:40:31 +0100 [thread overview]
Message-ID: <CAFBinCCEz-xezKatuHDPRURRWa3YNmgMObbr85GSvaT_bLFcNQ@mail.gmail.com> (raw)
In-Reply-To: <1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com>
Hi Hanjie,
overall this looks good to me and I have one question
On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
[...]
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
...here we have some CLK_SEL bit
[...]
> - priv->clk = devm_clk_get(dev, "xtal");
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clk = devm_clk_get(dev, "xtal");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + }
but here we don't need any parent/input clock?
does this mean that the USB2 PHY on the A1 SoC doesn't have any clock
inputs? how does it generate the correct clock for itself then?
Martin
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>
Cc: Rob Herring <robh@kernel.org>,
Victor Wan <victor.wan@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-usb@vger.kernel.org, Yue Wang <yue.wang@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
devicetree@vger.kernel.org, Liang Yang <liang.yang@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Xingyu Chen <xingyu.chen@amlogic.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Carlo Caione <carlo@caione.org>,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
Date: Fri, 27 Dec 2019 17:40:31 +0100 [thread overview]
Message-ID: <CAFBinCCEz-xezKatuHDPRURRWa3YNmgMObbr85GSvaT_bLFcNQ@mail.gmail.com> (raw)
In-Reply-To: <1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com>
Hi Hanjie,
overall this looks good to me and I have one question
On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
[...]
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
...here we have some CLK_SEL bit
[...]
> - priv->clk = devm_clk_get(dev, "xtal");
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clk = devm_clk_get(dev, "xtal");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + }
but here we don't need any parent/input clock?
does this mean that the USB2 PHY on the A1 SoC doesn't have any clock
inputs? how does it generate the correct clock for itself then?
Martin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>
Cc: Rob Herring <robh@kernel.org>,
Victor Wan <victor.wan@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-usb@vger.kernel.org, Yue Wang <yue.wang@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
devicetree@vger.kernel.org, Liang Yang <liang.yang@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>,
Xingyu Chen <xingyu.chen@amlogic.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Carlo Caione <carlo@caione.org>,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
Date: Fri, 27 Dec 2019 17:40:31 +0100 [thread overview]
Message-ID: <CAFBinCCEz-xezKatuHDPRURRWa3YNmgMObbr85GSvaT_bLFcNQ@mail.gmail.com> (raw)
In-Reply-To: <1577428606-69855-4-git-send-email-hanjie.lin@amlogic.com>
Hi Hanjie,
overall this looks good to me and I have one question
On Fri, Dec 27, 2019 at 7:37 AM Hanjie Lin <hanjie.lin@amlogic.com> wrote:
[...]
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
...here we have some CLK_SEL bit
[...]
> - priv->clk = devm_clk_get(dev, "xtal");
> - if (IS_ERR(priv->clk))
> - return PTR_ERR(priv->clk);
> + if (priv->soc_id == MESON_SOC_G12A) {
> + priv->clk = devm_clk_get(dev, "xtal");
> + if (IS_ERR(priv->clk))
> + return PTR_ERR(priv->clk);
> + }
but here we don't need any parent/input clock?
does this mean that the USB2 PHY on the A1 SoC doesn't have any clock
inputs? how does it generate the correct clock for itself then?
Martin
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2019-12-27 16:40 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-27 6:36 [PATCH v3 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` [PATCH v3 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2020-01-04 0:28 ` Rob Herring
2020-01-04 0:28 ` Rob Herring
2020-01-04 0:28 ` Rob Herring
2020-01-07 2:35 ` Hanjie Lin
2020-01-07 2:35 ` Hanjie Lin
2020-01-07 2:35 ` Hanjie Lin
2019-12-27 6:36 ` [PATCH v3 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2020-01-04 0:32 ` Rob Herring
2020-01-04 0:32 ` Rob Herring
2020-01-04 0:32 ` Rob Herring
2020-01-07 2:43 ` Hanjie Lin
2020-01-07 2:43 ` Hanjie Lin
2020-01-07 2:43 ` Hanjie Lin
2019-12-27 6:36 ` [PATCH v3 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 16:40 ` Martin Blumenstingl [this message]
2019-12-27 16:40 ` Martin Blumenstingl
2019-12-27 16:40 ` Martin Blumenstingl
2020-01-02 0:10 ` Hanjie Lin
2020-01-02 0:10 ` Hanjie Lin
2020-01-02 0:10 ` Hanjie Lin
2019-12-28 2:53 ` Chunfeng Yun
2019-12-28 2:53 ` Chunfeng Yun
2019-12-28 2:53 ` Chunfeng Yun
2020-01-02 0:12 ` Hanjie Lin
2020-01-02 0:12 ` Hanjie Lin
2020-01-02 0:12 ` Hanjie Lin
2019-12-27 6:36 ` [PATCH v3 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 16:38 ` Martin Blumenstingl
2019-12-27 16:38 ` Martin Blumenstingl
2019-12-27 16:38 ` Martin Blumenstingl
2020-01-02 0:30 ` Hanjie Lin
2020-01-02 0:30 ` Hanjie Lin
2020-01-02 0:30 ` Hanjie Lin
2020-01-02 21:52 ` Martin Blumenstingl
2020-01-02 21:52 ` Martin Blumenstingl
2020-01-02 21:52 ` Martin Blumenstingl
2019-12-27 6:36 ` [PATCH v3 5/6] arm64: dts: meson: a1: Enable USB2 PHY Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` [PATCH v3 6/6] arm64: dts: meson: a1: Enable DWC3 controller Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
2019-12-27 6:36 ` Hanjie Lin
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