From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
LKML <linux-kernel@vger.kernel.org>,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 clock support
Date: Fri, 9 Jul 2021 16:51:35 +0800 [thread overview]
Message-ID: <CAGXv+5GHwmL82q5ibTAh_GVLPny7yzMacm34uUxdR33Pzc-t2g@mail.gmail.com> (raw)
In-Reply-To: <20210616224743.5109-16-chun-jie.chen@mediatek.com>
Hi,
On Thu, Jun 17, 2021 at 7:03 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdosys0 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 6 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8195-vdo0.c | 114 +++++++++++++++++++++++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index b7881b8ebb23..6602f9ba13c7 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -648,6 +648,12 @@ config COMMON_CLK_MT8195_VDECSYS
> help
> This driver supports MediaTek MT8195 vdecsys clocks.
>
> +config COMMON_CLK_MT8195_VDOSYS0
> + bool "Clock driver for MediaTek MT8195 vdosys0"
> + depends on COMMON_CLK_MT8195
> + help
> + This driver supports MediaTek MT8195 vdosys0 clocks.
> +
Same comments about commit log and Kconfig option.
> config COMMON_CLK_MT8516
> bool "Clock driver for MediaTek MT8516"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 9acfa705f1de..6aa1ba00342a 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -91,5 +91,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
> obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
> obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> new file mode 100644
> index 000000000000..4a34ccb0beed
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
Alphabetical order within the same group please.
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdo00_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo01_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo02_cg_regs = {
> + .set_ofs = 0x124,
> + .clr_ofs = 0x128,
> + .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO00(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO01(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO02(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> + /* VDO00 */
> + GATE_VDO00(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "vpp_sel", 0),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "vpp_sel", 2),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "vpp_sel", 3),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "vpp_sel", 4),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "vpp_sel", 5),
> + GATE_VDO00(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "vpp_sel", 6),
> + GATE_VDO00(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "vpp_sel", 7),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "vpp_sel", 8),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "vpp_sel", 9),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "vpp_sel", 10),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "vpp_sel", 11),
> + GATE_VDO00(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "vpp_sel", 16),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "vpp_sel", 17),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "vpp_sel", 18),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "vpp_sel", 19),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "vpp_sel", 20),
> + GATE_VDO00(CLK_VDO0_DSI0, "vdo0_dsi0", "vpp_sel", 21),
> + GATE_VDO00(CLK_VDO0_DSI1, "vdo0_dsi1", "vpp_sel", 22),
> + GATE_VDO00(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "vpp_sel", 23),
> + GATE_VDO00(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "vpp_sel", 24),
> + GATE_VDO00(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "vpp_sel", 25),
> + GATE_VDO00(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "vpp_sel", 26),
> + GATE_VDO00(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "vpp_sel", 27),
> + GATE_VDO00(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "vpp_sel", 28),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "vpp_sel", 29),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "vpp_sel", 30),
> + /* VDO01 */
> + GATE_VDO01(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "vpp_sel", 0),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "vpp_sel", 1),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "vpp_sel", 2),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "vpp_sel", 3),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "vpp_sel", 4),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "vpp_sel", 5),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "vpp_sel", 6),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "vpp_sel", 7),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "vpp_sel", 8),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "vpp_sel", 9),
> + GATE_VDO01(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "vpp_sel", 10),
> + GATE_VDO01(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "vpp_sel", 11),
> + GATE_VDO01(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "vpp_sel", 12),
> + GATE_VDO01(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "vpp_sel", 13),
> + GATE_VDO01(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "vpp_sel", 14),
> + GATE_VDO01(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "vpp_sel", 15),
> + /* VDO02 */
> + GATE_VDO02(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "dsi_occ_sel", 0),
> + GATE_VDO02(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "dsi_occ_sel", 8),
> + GATE_VDO02(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "edp_sel", 16),
> +};
> +
> +static const struct mtk_clk_desc vdo0_desc = {
> + .clks = vdo0_clks,
> + .num_clks = ARRAY_SIZE(vdo0_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> + {
> + .compatible = "mediatek,mt8195-vdosys0",
> + .data = &vdo0_desc,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct platform_driver clk_mt8195_vdo0_drv = {
> + .probe = mtk_clk_simple_probe,
> + .driver = {
> + .name = "clk-mt8195-vdo0",
> + .of_match_table = of_match_clk_mt8195_vdo0,
> + },
> +};
> +
Can drop the empty line here.
Overall the code looks good.
ChenYu
> +builtin_platform_driver(clk_mt8195_vdo0_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
LKML <linux-kernel@vger.kernel.org>,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 clock support
Date: Fri, 9 Jul 2021 16:51:35 +0800 [thread overview]
Message-ID: <CAGXv+5GHwmL82q5ibTAh_GVLPny7yzMacm34uUxdR33Pzc-t2g@mail.gmail.com> (raw)
In-Reply-To: <20210616224743.5109-16-chun-jie.chen@mediatek.com>
Hi,
On Thu, Jun 17, 2021 at 7:03 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdosys0 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 6 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8195-vdo0.c | 114 +++++++++++++++++++++++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index b7881b8ebb23..6602f9ba13c7 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -648,6 +648,12 @@ config COMMON_CLK_MT8195_VDECSYS
> help
> This driver supports MediaTek MT8195 vdecsys clocks.
>
> +config COMMON_CLK_MT8195_VDOSYS0
> + bool "Clock driver for MediaTek MT8195 vdosys0"
> + depends on COMMON_CLK_MT8195
> + help
> + This driver supports MediaTek MT8195 vdosys0 clocks.
> +
Same comments about commit log and Kconfig option.
> config COMMON_CLK_MT8516
> bool "Clock driver for MediaTek MT8516"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 9acfa705f1de..6aa1ba00342a 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -91,5 +91,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
> obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
> obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> new file mode 100644
> index 000000000000..4a34ccb0beed
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
Alphabetical order within the same group please.
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdo00_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo01_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo02_cg_regs = {
> + .set_ofs = 0x124,
> + .clr_ofs = 0x128,
> + .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO00(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO01(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO02(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> + /* VDO00 */
> + GATE_VDO00(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "vpp_sel", 0),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "vpp_sel", 2),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "vpp_sel", 3),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "vpp_sel", 4),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "vpp_sel", 5),
> + GATE_VDO00(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "vpp_sel", 6),
> + GATE_VDO00(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "vpp_sel", 7),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "vpp_sel", 8),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "vpp_sel", 9),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "vpp_sel", 10),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "vpp_sel", 11),
> + GATE_VDO00(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "vpp_sel", 16),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "vpp_sel", 17),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "vpp_sel", 18),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "vpp_sel", 19),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "vpp_sel", 20),
> + GATE_VDO00(CLK_VDO0_DSI0, "vdo0_dsi0", "vpp_sel", 21),
> + GATE_VDO00(CLK_VDO0_DSI1, "vdo0_dsi1", "vpp_sel", 22),
> + GATE_VDO00(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "vpp_sel", 23),
> + GATE_VDO00(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "vpp_sel", 24),
> + GATE_VDO00(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "vpp_sel", 25),
> + GATE_VDO00(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "vpp_sel", 26),
> + GATE_VDO00(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "vpp_sel", 27),
> + GATE_VDO00(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "vpp_sel", 28),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "vpp_sel", 29),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "vpp_sel", 30),
> + /* VDO01 */
> + GATE_VDO01(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "vpp_sel", 0),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "vpp_sel", 1),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "vpp_sel", 2),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "vpp_sel", 3),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "vpp_sel", 4),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "vpp_sel", 5),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "vpp_sel", 6),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "vpp_sel", 7),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "vpp_sel", 8),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "vpp_sel", 9),
> + GATE_VDO01(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "vpp_sel", 10),
> + GATE_VDO01(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "vpp_sel", 11),
> + GATE_VDO01(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "vpp_sel", 12),
> + GATE_VDO01(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "vpp_sel", 13),
> + GATE_VDO01(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "vpp_sel", 14),
> + GATE_VDO01(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "vpp_sel", 15),
> + /* VDO02 */
> + GATE_VDO02(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "dsi_occ_sel", 0),
> + GATE_VDO02(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "dsi_occ_sel", 8),
> + GATE_VDO02(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "edp_sel", 16),
> +};
> +
> +static const struct mtk_clk_desc vdo0_desc = {
> + .clks = vdo0_clks,
> + .num_clks = ARRAY_SIZE(vdo0_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> + {
> + .compatible = "mediatek,mt8195-vdosys0",
> + .data = &vdo0_desc,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct platform_driver clk_mt8195_vdo0_drv = {
> + .probe = mtk_clk_simple_probe,
> + .driver = {
> + .name = "clk-mt8195-vdo0",
> + .of_match_table = of_match_clk_mt8195_vdo0,
> + },
> +};
> +
Can drop the empty line here.
Overall the code looks good.
ChenYu
> +builtin_platform_driver(clk_mt8195_vdo0_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Chen-Yu Tsai <wenst@chromium.org>
To: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
LKML <linux-kernel@vger.kernel.org>,
linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 clock support
Date: Fri, 9 Jul 2021 16:51:35 +0800 [thread overview]
Message-ID: <CAGXv+5GHwmL82q5ibTAh_GVLPny7yzMacm34uUxdR33Pzc-t2g@mail.gmail.com> (raw)
In-Reply-To: <20210616224743.5109-16-chun-jie.chen@mediatek.com>
Hi,
On Thu, Jun 17, 2021 at 7:03 AM Chun-Jie Chen
<chun-jie.chen@mediatek.com> wrote:
>
> Add MT8195 vdosys0 clock provider
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> drivers/clk/mediatek/Kconfig | 6 ++
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8195-vdo0.c | 114 +++++++++++++++++++++++++
> 3 files changed, 121 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8195-vdo0.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index b7881b8ebb23..6602f9ba13c7 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -648,6 +648,12 @@ config COMMON_CLK_MT8195_VDECSYS
> help
> This driver supports MediaTek MT8195 vdecsys clocks.
>
> +config COMMON_CLK_MT8195_VDOSYS0
> + bool "Clock driver for MediaTek MT8195 vdosys0"
> + depends on COMMON_CLK_MT8195
> + help
> + This driver supports MediaTek MT8195 vdosys0 clocks.
> +
Same comments about commit log and Kconfig option.
> config COMMON_CLK_MT8516
> bool "Clock driver for MediaTek MT8516"
> depends on ARCH_MEDIATEK || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 9acfa705f1de..6aa1ba00342a 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -91,5 +91,6 @@ obj-$(CONFIG_COMMON_CLK_MT8195_MFGCFG) += clk-mt8195-mfg.o
> obj-$(CONFIG_COMMON_CLK_MT8195_SCP_ADSP) += clk-mt8195-scp_adsp.o
> obj-$(CONFIG_COMMON_CLK_MT8195_NNASYS) += clk-mt8195-nna.o
> obj-$(CONFIG_COMMON_CLK_MT8195_VDECSYS) += clk-mt8195-vdec.o
> +obj-$(CONFIG_COMMON_CLK_MT8195_VDOSYS0) += clk-mt8195-vdo0.o
> obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
> obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
> diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> new file mode 100644
> index 000000000000..4a34ccb0beed
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2021 MediaTek Inc.
> +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mtk.h"
> +#include "clk-gate.h"
Alphabetical order within the same group please.
> +
> +#include <dt-bindings/clock/mt8195-clk.h>
> +
> +static const struct mtk_gate_regs vdo00_cg_regs = {
> + .set_ofs = 0x104,
> + .clr_ofs = 0x108,
> + .sta_ofs = 0x100,
> +};
> +
> +static const struct mtk_gate_regs vdo01_cg_regs = {
> + .set_ofs = 0x114,
> + .clr_ofs = 0x118,
> + .sta_ofs = 0x110,
> +};
> +
> +static const struct mtk_gate_regs vdo02_cg_regs = {
> + .set_ofs = 0x124,
> + .clr_ofs = 0x128,
> + .sta_ofs = 0x120,
> +};
> +
> +#define GATE_VDO00(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo00_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO01(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo01_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +#define GATE_VDO02(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &vdo02_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate vdo0_clks[] = {
> + /* VDO00 */
> + GATE_VDO00(CLK_VDO0_DISP_OVL0, "vdo0_disp_ovl0", "vpp_sel", 0),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR0, "vdo0_disp_color0", "vpp_sel", 2),
> + GATE_VDO00(CLK_VDO0_DISP_COLOR1, "vdo0_disp_color1", "vpp_sel", 3),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR0, "vdo0_disp_ccorr0", "vpp_sel", 4),
> + GATE_VDO00(CLK_VDO0_DISP_CCORR1, "vdo0_disp_ccorr1", "vpp_sel", 5),
> + GATE_VDO00(CLK_VDO0_DISP_AAL0, "vdo0_disp_aal0", "vpp_sel", 6),
> + GATE_VDO00(CLK_VDO0_DISP_AAL1, "vdo0_disp_aal1", "vpp_sel", 7),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA0, "vdo0_disp_gamma0", "vpp_sel", 8),
> + GATE_VDO00(CLK_VDO0_DISP_GAMMA1, "vdo0_disp_gamma1", "vpp_sel", 9),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER0, "vdo0_disp_dither0", "vpp_sel", 10),
> + GATE_VDO00(CLK_VDO0_DISP_DITHER1, "vdo0_disp_dither1", "vpp_sel", 11),
> + GATE_VDO00(CLK_VDO0_DISP_OVL1, "vdo0_disp_ovl1", "vpp_sel", 16),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA0, "vdo0_disp_wdma0", "vpp_sel", 17),
> + GATE_VDO00(CLK_VDO0_DISP_WDMA1, "vdo0_disp_wdma1", "vpp_sel", 18),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA0, "vdo0_disp_rdma0", "vpp_sel", 19),
> + GATE_VDO00(CLK_VDO0_DISP_RDMA1, "vdo0_disp_rdma1", "vpp_sel", 20),
> + GATE_VDO00(CLK_VDO0_DSI0, "vdo0_dsi0", "vpp_sel", 21),
> + GATE_VDO00(CLK_VDO0_DSI1, "vdo0_dsi1", "vpp_sel", 22),
> + GATE_VDO00(CLK_VDO0_DSC_WRAP0, "vdo0_dsc_wrap0", "vpp_sel", 23),
> + GATE_VDO00(CLK_VDO0_VPP_MERGE0, "vdo0_vpp_merge0", "vpp_sel", 24),
> + GATE_VDO00(CLK_VDO0_DP_INTF0, "vdo0_dp_intf0", "vpp_sel", 25),
> + GATE_VDO00(CLK_VDO0_DISP_MUTEX0, "vdo0_disp_mutex0", "vpp_sel", 26),
> + GATE_VDO00(CLK_VDO0_DISP_IL_ROT0, "vdo0_disp_il_rot0", "vpp_sel", 27),
> + GATE_VDO00(CLK_VDO0_APB_BUS, "vdo0_apb_bus", "vpp_sel", 28),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG0, "vdo0_fake_eng0", "vpp_sel", 29),
> + GATE_VDO00(CLK_VDO0_FAKE_ENG1, "vdo0_fake_eng1", "vpp_sel", 30),
> + /* VDO01 */
> + GATE_VDO01(CLK_VDO0_DL_ASYNC0, "vdo0_dl_async0", "vpp_sel", 0),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC1, "vdo0_dl_async1", "vpp_sel", 1),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC2, "vdo0_dl_async2", "vpp_sel", 2),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC3, "vdo0_dl_async3", "vpp_sel", 3),
> + GATE_VDO01(CLK_VDO0_DL_ASYNC4, "vdo0_dl_async4", "vpp_sel", 4),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR0, "vdo0_disp_monitor0", "vpp_sel", 5),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR1, "vdo0_disp_monitor1", "vpp_sel", 6),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR2, "vdo0_disp_monitor2", "vpp_sel", 7),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR3, "vdo0_disp_monitor3", "vpp_sel", 8),
> + GATE_VDO01(CLK_VDO0_DISP_MONITOR4, "vdo0_disp_monitor4", "vpp_sel", 9),
> + GATE_VDO01(CLK_VDO0_SMI_GALS, "vdo0_smi_gals", "vpp_sel", 10),
> + GATE_VDO01(CLK_VDO0_SMI_COMMON, "vdo0_smi_common", "vpp_sel", 11),
> + GATE_VDO01(CLK_VDO0_SMI_EMI, "vdo0_smi_emi", "vpp_sel", 12),
> + GATE_VDO01(CLK_VDO0_SMI_IOMMU, "vdo0_smi_iommu", "vpp_sel", 13),
> + GATE_VDO01(CLK_VDO0_SMI_LARB, "vdo0_smi_larb", "vpp_sel", 14),
> + GATE_VDO01(CLK_VDO0_SMI_RSI, "vdo0_smi_rsi", "vpp_sel", 15),
> + /* VDO02 */
> + GATE_VDO02(CLK_VDO0_DSI0_DSI, "vdo0_dsi0_dsi", "dsi_occ_sel", 0),
> + GATE_VDO02(CLK_VDO0_DSI1_DSI, "vdo0_dsi1_dsi", "dsi_occ_sel", 8),
> + GATE_VDO02(CLK_VDO0_DP_INTF0_DP_INTF, "vdo0_dp_intf0_dp_intf", "edp_sel", 16),
> +};
> +
> +static const struct mtk_clk_desc vdo0_desc = {
> + .clks = vdo0_clks,
> + .num_clks = ARRAY_SIZE(vdo0_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8195_vdo0[] = {
> + {
> + .compatible = "mediatek,mt8195-vdosys0",
> + .data = &vdo0_desc,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static struct platform_driver clk_mt8195_vdo0_drv = {
> + .probe = mtk_clk_simple_probe,
> + .driver = {
> + .name = "clk-mt8195-vdo0",
> + .of_match_table = of_match_clk_mt8195_vdo0,
> + },
> +};
> +
Can drop the empty line here.
Overall the code looks good.
ChenYu
> +builtin_platform_driver(clk_mt8195_vdo0_drv);
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-07-09 8:51 UTC|newest]
Thread overview: 177+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-24 21:21 ` Rob Herring
2021-06-24 21:21 ` Rob Herring
2021-06-24 21:21 ` Rob Herring
2021-07-12 9:32 ` Chen-Yu Tsai
2021-07-12 9:32 ` Chen-Yu Tsai
2021-07-12 9:32 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-24 21:22 ` Rob Herring
2021-06-24 21:22 ` Rob Herring
2021-06-24 21:22 ` Rob Herring
2021-07-12 9:37 ` Chen-Yu Tsai
2021-07-12 9:37 ` Chen-Yu Tsai
2021-07-12 9:37 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:43 ` Matthias Brugger
2021-06-30 11:43 ` Matthias Brugger
2021-06-30 11:43 ` Matthias Brugger
2021-07-01 4:02 ` Chen-Yu Tsai
2021-07-01 4:02 ` Chen-Yu Tsai
2021-07-01 4:02 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-02 11:44 ` Chen-Yu Tsai
2021-07-02 11:44 ` Chen-Yu Tsai
2021-07-02 11:44 ` Chen-Yu Tsai
[not found] ` <1626913060.1546.4.camel@mtksdaap41>
2021-07-22 7:44 ` Chen-Yu Tsai
2021-07-22 7:44 ` Chen-Yu Tsai
2021-07-22 7:44 ` Chen-Yu Tsai
2021-08-11 4:31 ` Chun-Jie Chen
2021-08-11 4:31 ` Chun-Jie Chen
2021-08-11 4:31 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 7:06 ` Chen-Yu Tsai
2021-07-12 7:06 ` Chen-Yu Tsai
2021-07-12 7:06 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-05 10:07 ` Chen-Yu Tsai
2021-07-05 10:07 ` Chen-Yu Tsai
2021-07-05 10:07 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 8:53 ` Chen-Yu Tsai
2021-07-06 8:53 ` Chen-Yu Tsai
2021-07-06 8:53 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:00 ` Chen-Yu Tsai
2021-07-06 9:00 ` Chen-Yu Tsai
2021-07-06 9:00 ` Chen-Yu Tsai
2021-08-17 0:56 ` Chun-Jie Chen
2021-08-17 0:56 ` Chun-Jie Chen
2021-08-17 0:56 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:07 ` Chen-Yu Tsai
2021-07-06 9:07 ` Chen-Yu Tsai
2021-07-06 9:07 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:11 ` Chen-Yu Tsai
2021-07-06 9:11 ` Chen-Yu Tsai
2021-07-06 9:11 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 6:29 ` Chen-Yu Tsai
2021-07-09 6:29 ` Chen-Yu Tsai
2021-07-09 6:29 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 6:39 ` Chen-Yu Tsai
2021-07-09 6:39 ` Chen-Yu Tsai
2021-07-09 6:39 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:24 ` Chen-Yu Tsai
2021-07-09 8:24 ` Chen-Yu Tsai
2021-07-09 8:24 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-12 1:34 ` Chun-Jie Chen
2021-07-12 1:34 ` Chun-Jie Chen
2021-07-12 1:34 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:51 ` Chen-Yu Tsai [this message]
2021-07-09 8:51 ` Chen-Yu Tsai
2021-07-09 8:51 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 9:30 ` Chen-Yu Tsai
2021-07-09 9:30 ` Chen-Yu Tsai
2021-07-09 9:30 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:26 ` Chen-Yu Tsai
2021-07-09 10:26 ` Chen-Yu Tsai
2021-07-09 10:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:38 ` Chen-Yu Tsai
2021-07-09 10:38 ` Chen-Yu Tsai
2021-07-09 10:38 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:45 ` Chen-Yu Tsai
2021-07-09 10:45 ` Chen-Yu Tsai
2021-07-09 10:45 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-08-25 11:26 ` Chen-Yu Tsai
2021-08-25 11:26 ` Chen-Yu Tsai
2021-08-25 11:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-12 8:34 ` Chen-Yu Tsai
2021-07-12 8:34 ` Chen-Yu Tsai
2021-07-12 8:34 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-12 8:51 ` Chen-Yu Tsai
2021-07-12 8:51 ` Chen-Yu Tsai
2021-07-12 8:51 ` Chen-Yu Tsai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAGXv+5GHwmL82q5ibTAh_GVLPny7yzMacm34uUxdR33Pzc-t2g@mail.gmail.com \
--to=wenst@chromium.org \
--cc=Project_Global_Chrome_Upstream_Group@mediatek.com \
--cc=chun-jie.chen@mediatek.com \
--cc=devicetree@vger.kernel.org \
--cc=drinkcat@chromium.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mediatek@lists.infradead.org \
--cc=matthias.bgg@gmail.com \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=srv_heupstream@mediatek.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.