From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
Date: Wed, 30 Jun 2021 13:43:18 +0200 [thread overview]
Message-ID: <be824462-4c2f-3bde-0a3d-c5470a5b0fbb@gmail.com> (raw)
In-Reply-To: <CAGXv+5FXuMnhsnytLYKKA9YE97bps7KnkDNADvv8f_wdTqnrfg@mail.gmail.com>
On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>>
>>
>>
>> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
>>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
>>> <chun-jie.chen@mediatek.com> wrote:
>>>>
>>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>>>> If we only judge by tuner_en_reg, it may lead to wrong address.
>>>> Add tuner_en_bit to the check condition. And it has been confirmed,
>>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>>>> clock square control.
>>>>
>>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>> Though you might want to consider converting these types of checks into feature
>>> flags.
>>>
>>
>> Yes I think adding a feature flag is the way to go. Luckily there are only a few
>> SoCs that will need updates at the same time.
>
> I also see that the different clock modules are tied together using only clock
> names written in the drivers, instead of clock references in the device tree.
>
Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.
Regards,
Matthias
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139
> Unfortunately reworking this would likely require a lot more work. I previously
> did a bit of internal reworking for the sunxi drivers. While not the same, I
> think the plumbing required is comparable.
>
> ChenYu
>
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
Date: Wed, 30 Jun 2021 13:43:18 +0200 [thread overview]
Message-ID: <be824462-4c2f-3bde-0a3d-c5470a5b0fbb@gmail.com> (raw)
In-Reply-To: <CAGXv+5FXuMnhsnytLYKKA9YE97bps7KnkDNADvv8f_wdTqnrfg@mail.gmail.com>
On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>>
>>
>>
>> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
>>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
>>> <chun-jie.chen@mediatek.com> wrote:
>>>>
>>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>>>> If we only judge by tuner_en_reg, it may lead to wrong address.
>>>> Add tuner_en_bit to the check condition. And it has been confirmed,
>>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>>>> clock square control.
>>>>
>>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>> Though you might want to consider converting these types of checks into feature
>>> flags.
>>>
>>
>> Yes I think adding a feature flag is the way to go. Luckily there are only a few
>> SoCs that will need updates at the same time.
>
> I also see that the different clock modules are tied together using only clock
> names written in the drivers, instead of clock references in the device tree.
>
Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.
Regards,
Matthias
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139
> Unfortunately reworking this would likely require a lot more work. I previously
> did a bit of internal reworking for the sunxi drivers. While not the same, I
> think the plumbing required is comparable.
>
> ChenYu
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Matthias Brugger <matthias.bgg@gmail.com>
To: Chen-Yu Tsai <wenst@chromium.org>
Cc: Chun-Jie Chen <chun-jie.chen@mediatek.com>,
Stephen Boyd <sboyd@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
srv_heupstream@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg
Date: Wed, 30 Jun 2021 13:43:18 +0200 [thread overview]
Message-ID: <be824462-4c2f-3bde-0a3d-c5470a5b0fbb@gmail.com> (raw)
In-Reply-To: <CAGXv+5FXuMnhsnytLYKKA9YE97bps7KnkDNADvv8f_wdTqnrfg@mail.gmail.com>
On 30/06/2021 13:09, Chen-Yu Tsai wrote:
> On Wed, Jun 30, 2021 at 6:53 PM Matthias Brugger <matthias.bgg@gmail.com> wrote:
>>
>>
>>
>> On 30/06/2021 09:31, Chen-Yu Tsai wrote:
>>> On Thu, Jun 17, 2021 at 7:01 AM Chun-Jie Chen
>>> <chun-jie.chen@mediatek.com> wrote:
>>>>
>>>> On MT8195, tuner_en_reg is moved to register offest 0x0.
>>>> If we only judge by tuner_en_reg, it may lead to wrong address.
>>>> Add tuner_en_bit to the check condition. And it has been confirmed,
>>>> on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
>>>> clock square control.
>>>>
>>>> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
>>>
>>> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
>>>
>>> Though you might want to consider converting these types of checks into feature
>>> flags.
>>>
>>
>> Yes I think adding a feature flag is the way to go. Luckily there are only a few
>> SoCs that will need updates at the same time.
>
> I also see that the different clock modules are tied together using only clock
> names written in the drivers, instead of clock references in the device tree.
>
Not sure I understand what you mean. Do you refer to something like [1]? That's
because the clock is probed by the DRM driver, as they share the same compatible
and IP block.
Regards,
Matthias
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/mediatek/clk-mt8173-mm.c?h=v5.13#n139
> Unfortunately reworking this would likely require a lot more work. I previously
> did a bit of internal reworking for the sunxi drivers. While not the same, I
> think the plumbing required is comparable.
>
> ChenYu
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-06-30 11:43 UTC|newest]
Thread overview: 177+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 22:47 [PATCH 00/22] Mediatek MT8195 clock support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of MT8195 clock Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-24 21:21 ` Rob Herring
2021-06-24 21:21 ` Rob Herring
2021-06-24 21:21 ` Rob Herring
2021-07-12 9:32 ` Chen-Yu Tsai
2021-07-12 9:32 ` Chen-Yu Tsai
2021-07-12 9:32 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 02/22] clk: mediatek: Add dt-bindings of MT8195 clocks Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-24 21:22 ` Rob Herring
2021-06-24 21:22 ` Rob Herring
2021-06-24 21:22 ` Rob Herring
2021-07-12 9:37 ` Chen-Yu Tsai
2021-07-12 9:37 ` Chen-Yu Tsai
2021-07-12 9:37 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 03/22] clk: mediatek: Fix corner case of tuner_en_reg Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 7:31 ` Chen-Yu Tsai
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 10:53 ` Matthias Brugger
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:09 ` Chen-Yu Tsai
2021-06-30 11:43 ` Matthias Brugger [this message]
2021-06-30 11:43 ` Matthias Brugger
2021-06-30 11:43 ` Matthias Brugger
2021-07-01 4:02 ` Chen-Yu Tsai
2021-07-01 4:02 ` Chen-Yu Tsai
2021-07-01 4:02 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 04/22] clk: mediatek: Add MT8195 basic clocks support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-02 11:44 ` Chen-Yu Tsai
2021-07-02 11:44 ` Chen-Yu Tsai
2021-07-02 11:44 ` Chen-Yu Tsai
[not found] ` <1626913060.1546.4.camel@mtksdaap41>
2021-07-22 7:44 ` Chen-Yu Tsai
2021-07-22 7:44 ` Chen-Yu Tsai
2021-07-22 7:44 ` Chen-Yu Tsai
2021-08-11 4:31 ` Chun-Jie Chen
2021-08-11 4:31 ` Chun-Jie Chen
2021-08-11 4:31 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 05/22] clk: mediatek: Add MT8195 audio clock support Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-05 9:03 ` Chen-Yu Tsai
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 1:26 ` Chun-Jie Chen
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 2:09 ` Chen-Yu Tsai
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 4:35 ` Chun-Jie Chen
2021-07-12 7:06 ` Chen-Yu Tsai
2021-07-12 7:06 ` Chen-Yu Tsai
2021-07-12 7:06 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 06/22] clk: mediatek: Add MT8195 audio src " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-05 10:07 ` Chen-Yu Tsai
2021-07-05 10:07 ` Chen-Yu Tsai
2021-07-05 10:07 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 07/22] clk: mediatek: Add MT8195 camsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 8:53 ` Chen-Yu Tsai
2021-07-06 8:53 ` Chen-Yu Tsai
2021-07-06 8:53 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 08/22] clk: mediatek: Add MT8195 ccusys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:00 ` Chen-Yu Tsai
2021-07-06 9:00 ` Chen-Yu Tsai
2021-07-06 9:00 ` Chen-Yu Tsai
2021-08-17 0:56 ` Chun-Jie Chen
2021-08-17 0:56 ` Chun-Jie Chen
2021-08-17 0:56 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 09/22] clk: mediatek: Add MT8195 imgsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:07 ` Chen-Yu Tsai
2021-07-06 9:07 ` Chen-Yu Tsai
2021-07-06 9:07 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 10/22] clk: mediatek: Add MT8195 ipesys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-06 9:11 ` Chen-Yu Tsai
2021-07-06 9:11 ` Chen-Yu Tsai
2021-07-06 9:11 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 11/22] clk: mediatek: Add MT8195 mfgcfg " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 6:29 ` Chen-Yu Tsai
2021-07-09 6:29 ` Chen-Yu Tsai
2021-07-09 6:29 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 12/22] clk: mediatek: Add MT8195 scp adsp " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 6:39 ` Chen-Yu Tsai
2021-07-09 6:39 ` Chen-Yu Tsai
2021-07-09 6:39 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 13/22] clk: mediatek: Add MT8195 nnasys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:24 ` Chen-Yu Tsai
2021-07-09 8:24 ` Chen-Yu Tsai
2021-07-09 8:24 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 14/22] clk: mediatek: Add MT8195 vdecsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-09 8:40 ` Chen-Yu Tsai
2021-07-12 1:34 ` Chun-Jie Chen
2021-07-12 1:34 ` Chun-Jie Chen
2021-07-12 1:34 ` Chun-Jie Chen
2021-06-16 22:47 ` [PATCH 15/22] clk: mediatek: Add MT8195 vdosys0 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 8:51 ` Chen-Yu Tsai
2021-07-09 8:51 ` Chen-Yu Tsai
2021-07-09 8:51 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 16/22] clk: mediatek: Add MT8195 vdosys1 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 9:30 ` Chen-Yu Tsai
2021-07-09 9:30 ` Chen-Yu Tsai
2021-07-09 9:30 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 17/22] clk: mediatek: Add MT8195 vencsys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:26 ` Chen-Yu Tsai
2021-07-09 10:26 ` Chen-Yu Tsai
2021-07-09 10:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 18/22] clk: mediatek: Add MT8195 vppsys0 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:38 ` Chen-Yu Tsai
2021-07-09 10:38 ` Chen-Yu Tsai
2021-07-09 10:38 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 19/22] clk: mediatek: Add MT8195 vppsys1 " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-09 10:45 ` Chen-Yu Tsai
2021-07-09 10:45 ` Chen-Yu Tsai
2021-07-09 10:45 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 20/22] clk: mediatek: Add MT8195 wpesys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-08-25 11:26 ` Chen-Yu Tsai
2021-08-25 11:26 ` Chen-Yu Tsai
2021-08-25 11:26 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 21/22] clk: mediatek: Add MT8195 imp i2c wrapper " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-12 8:34 ` Chen-Yu Tsai
2021-07-12 8:34 ` Chen-Yu Tsai
2021-07-12 8:34 ` Chen-Yu Tsai
2021-06-16 22:47 ` [PATCH 22/22] clk: mediatek: Add MT8195 apusys " Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-06-16 22:47 ` Chun-Jie Chen
2021-07-12 8:51 ` Chen-Yu Tsai
2021-07-12 8:51 ` Chen-Yu Tsai
2021-07-12 8:51 ` Chen-Yu Tsai
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