From: Adam Ford <aford173@gmail.com> To: arm-soc <linux-arm-kernel@lists.infradead.org> Cc: Adam Ford-BE <aford@beaconembedded.com>, Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, devicetree <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH V2 5/9] soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl Date: Sat, 16 Oct 2021 16:02:31 -0500 [thread overview] Message-ID: <CAHCN7x+N2D85=KVxyZM1noG8ovBuasHkVHG3vzXOGzW3wxZFCw@mail.gmail.com> (raw) In-Reply-To: <20211009162700.1452857-6-aford173@gmail.com> On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <aford173@gmail.com> wrote: > > This adds the description for the i.MX8MN disp blk-ctrl. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- Does anyone from NXP have any feedback on this? I tried to look at the ISI driver and power domain and understand it, but it's not present in the 8mm, so I went off my best understanding of the datasheet. adam > drivers/soc/imx/imx8m-blk-ctrl.c | 75 +++++++++++++++++++++++++++++++- > 1 file changed, 74 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index e172d295c441..8d3bf7690383 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -14,6 +14,7 @@ > #include <linux/clk.h> > > #include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/power/imx8mn-power.h> > > #define BLK_SFT_RSTN 0x0 > #define BLK_CLK_EN 0x4 > @@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { > .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), > }; > > + > +static int imx8mn_disp_power_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, > + power_nb); > + > + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) > + return NOTIFY_OK; > + > + /* Enable bus clock and deassert bus reset */ > + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); > + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); > + > + /* > + * On power up we have no software backchannel to the GPC to > + * wait for the ADB handshake to happen, so we just delay for a > + * bit. On power down the GPC driver waits for the handshake. > + */ > + if (action == GENPD_NOTIFY_ON) > + udelay(5); > + > + > + return NOTIFY_OK; > +} > + > +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { > + [IMX8MN_DISPBLK_PD_MIPI_DSI] = { > + .name = "dispblk-mipi-dsi", > + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, > + .num_clks = 2, > + .gpc_name = "mipi-dsi", > + .rst_mask = BIT(0) | BIT(1), > + .clk_mask = BIT(0) | BIT(1), > + }, > + [IMX8MN_DISPBLK_PD_MIPI_CSI] = { > + .name = "dispblk-mipi-csi", > + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi", > + .rst_mask = BIT(2) | BIT(3), > + .clk_mask = BIT(2) | BIT(3), > + }, > + [IMX8MN_DISPBLK_PD_LCDIF] = { > + .name = "dispblk-lcdif", > + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, > + .num_clks = 3, > + .gpc_name = "lcdif", > + .rst_mask = BIT(4) | BIT(5), > + .clk_mask = BIT(4) | BIT(5), > + }, > + [IMX8MN_DISPBLK_PD_ISI] = { > + .name = "dispblk-isi", > + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", > + "disp_apb_root"}, > + .num_clks = 4, > + .gpc_name = "isi", > + .rst_mask = BIT(6) | BIT(7), > + .clk_mask = BIT(6) | BIT(7), > + }, > +}; > + > +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { > + .max_reg = 0x84, > + .power_notifier_fn = imx8mn_disp_power_notifier, > + .domains = imx8mn_disp_blk_ctl_domain_data, > + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), > +}; > + > static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > { > .compatible = "fsl,imx8mm-vpu-blk-ctrl", > @@ -505,7 +575,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > }, { > .compatible = "fsl,imx8mm-disp-blk-ctrl", > .data = &imx8mm_disp_blk_ctl_dev_data > - } ,{ > + }, { > + .compatible = "fsl,imx8mn-disp-blk-ctrl", > + .data = &imx8mn_disp_blk_ctl_dev_data > + }, { > /* Sentinel */ > } > }; > -- > 2.25.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Adam Ford <aford173@gmail.com> To: arm-soc <linux-arm-kernel@lists.infradead.org> Cc: Adam Ford-BE <aford@beaconembedded.com>, Rob Herring <robh+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>, Lucas Stach <l.stach@pengutronix.de>, devicetree <devicetree@vger.kernel.org>, Linux Kernel Mailing List <linux-kernel@vger.kernel.org> Subject: Re: [PATCH V2 5/9] soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl Date: Sat, 16 Oct 2021 16:02:31 -0500 [thread overview] Message-ID: <CAHCN7x+N2D85=KVxyZM1noG8ovBuasHkVHG3vzXOGzW3wxZFCw@mail.gmail.com> (raw) In-Reply-To: <20211009162700.1452857-6-aford173@gmail.com> On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <aford173@gmail.com> wrote: > > This adds the description for the i.MX8MN disp blk-ctrl. > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- Does anyone from NXP have any feedback on this? I tried to look at the ISI driver and power domain and understand it, but it's not present in the 8mm, so I went off my best understanding of the datasheet. adam > drivers/soc/imx/imx8m-blk-ctrl.c | 75 +++++++++++++++++++++++++++++++- > 1 file changed, 74 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index e172d295c441..8d3bf7690383 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -14,6 +14,7 @@ > #include <linux/clk.h> > > #include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/power/imx8mn-power.h> > > #define BLK_SFT_RSTN 0x0 > #define BLK_CLK_EN 0x4 > @@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { > .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), > }; > > + > +static int imx8mn_disp_power_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, > + power_nb); > + > + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) > + return NOTIFY_OK; > + > + /* Enable bus clock and deassert bus reset */ > + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); > + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); > + > + /* > + * On power up we have no software backchannel to the GPC to > + * wait for the ADB handshake to happen, so we just delay for a > + * bit. On power down the GPC driver waits for the handshake. > + */ > + if (action == GENPD_NOTIFY_ON) > + udelay(5); > + > + > + return NOTIFY_OK; > +} > + > +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { > + [IMX8MN_DISPBLK_PD_MIPI_DSI] = { > + .name = "dispblk-mipi-dsi", > + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, > + .num_clks = 2, > + .gpc_name = "mipi-dsi", > + .rst_mask = BIT(0) | BIT(1), > + .clk_mask = BIT(0) | BIT(1), > + }, > + [IMX8MN_DISPBLK_PD_MIPI_CSI] = { > + .name = "dispblk-mipi-csi", > + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi", > + .rst_mask = BIT(2) | BIT(3), > + .clk_mask = BIT(2) | BIT(3), > + }, > + [IMX8MN_DISPBLK_PD_LCDIF] = { > + .name = "dispblk-lcdif", > + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, > + .num_clks = 3, > + .gpc_name = "lcdif", > + .rst_mask = BIT(4) | BIT(5), > + .clk_mask = BIT(4) | BIT(5), > + }, > + [IMX8MN_DISPBLK_PD_ISI] = { > + .name = "dispblk-isi", > + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", > + "disp_apb_root"}, > + .num_clks = 4, > + .gpc_name = "isi", > + .rst_mask = BIT(6) | BIT(7), > + .clk_mask = BIT(6) | BIT(7), > + }, > +}; > + > +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { > + .max_reg = 0x84, > + .power_notifier_fn = imx8mn_disp_power_notifier, > + .domains = imx8mn_disp_blk_ctl_domain_data, > + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), > +}; > + > static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > { > .compatible = "fsl,imx8mm-vpu-blk-ctrl", > @@ -505,7 +575,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > }, { > .compatible = "fsl,imx8mm-disp-blk-ctrl", > .data = &imx8mm_disp_blk_ctl_dev_data > - } ,{ > + }, { > + .compatible = "fsl,imx8mn-disp-blk-ctrl", > + .data = &imx8mn_disp_blk_ctl_dev_data > + }, { > /* Sentinel */ > } > }; > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-16 21:02 UTC|newest] Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-09 16:26 [PATCH V2 0/9] arm64: imx8mn: Enable additional power domains and peripherals Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 1/9] soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 2/9] soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 3/9] dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 4/9] dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-10 19:31 ` Rob Herring 2021-10-10 19:31 ` Rob Herring 2021-10-09 16:26 ` [PATCH V2 5/9] soc: imx: imx8m-blk-ctrl: add " Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-16 21:02 ` Adam Ford [this message] 2021-10-16 21:02 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 6/9] arm64: dts: imx8mn: add GPC node Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 7/9] arm64: dts: imx8mn: put USB controller into power-domains Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 8/9] arm64: dts: imx8mn: add DISP blk-ctrl Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-09 16:26 ` [PATCH V2 9/9] arm64: dts: imx8mn: Enable GPU Adam Ford 2021-10-09 16:26 ` Adam Ford 2021-10-29 17:22 ` [PATCH V2 0/9] arm64: imx8mn: Enable additional power domains and peripherals Adam Ford 2021-10-29 17:22 ` Adam Ford
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