All of lore.kernel.org
 help / color / mirror / Atom feed
From: Guo Ren <guoren@kernel.org>
To: "Jernej Škrabec" <jernej.skrabec@gmail.com>
Cc: "Anup Patel" <anup.patel@wdc.com>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	wens@csie.org, maxime@cerno.tech,
	"Drew Fustini" <drew@beagleboard.org>,
	liush@allwinnertech.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
	wefu@redhat.com, linux-riscv <linux-riscv@lists.infradead.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	linux-sunxi@lists.linux.dev, "Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1
Date: Mon, 7 Jun 2021 07:42:18 +0800	[thread overview]
Message-ID: <CAJF2gTR6zV8GuftZ1M69Ma2rxy31KvMBVjyB8G40JnyY4D+0Gw@mail.gmail.com> (raw)
In-Reply-To: <1664140.l4xsYfQU8q@jernej-laptop>

On Mon, Jun 7, 2021 at 1:14 AM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> Dne nedelja, 06. junij 2021 ob 18:54:05 CEST je Guo Ren napisal(a):
> > V5 is not related to the patch series.
>
> Don't top post.
>
> If that's the case, then your e-mail client messed things up. I got V5 patches
> in the same thread as board enablement patches and so did mailing list [1].
I made mistake that make two patchset mixed in my linux directory.

git format-patch -11
git send-email *.patch

But there are still some last posted patches in *.patch.

I'll prevent it in the next patchset version.

>
> Best regards,
> Jernej
>
> [1] https://lore.kernel.org/linux-sunxi/
> CAJF2gTQ1yvSNthJ2yJkqaYGaJ6OYmf0vbG=hm4ocgnw4DiZbOw@mail.gmail.com/T/#t
>
> >
> > On Mon, Jun 7, 2021 at 12:29 AM Jernej Škrabec <jernej.skrabec@gmail.com>
> wrote:
> > > Hi!
> > >
> > > Dne nedelja, 06. junij 2021 ob 11:03:55 CEST je guoren@kernel.org
> napisal(a):
> > > > From: Guo Ren <guoren@linux.alibaba.com>
> > > >
> > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let
> > > > vendors define the custom properties of memory regions in PTE.
> > > >
> > > > This patchset helps SOC vendors to support their own custom interconnect
> > > > coherent solution with PTE attributes.
> > > >
> > > > For example, allwinner D1[1] uses T-HEAD C906 as main processor, C906
> > > > has
> > > >
> > > > two modes in MMU:
> > > >  - Compatible mode, the same as the definitions in spec.
> > > >  - Enhanced mode, add custom DMA_COHERENT attribute bits in PTE which
> > > >
> > > >    not mentioned in spec.
> > > >
> > > > Allwinner D1 needs the enhanced mode to support the DMA type device with
> > > > non-coherent interconnect in its SOC. C906 uses BITS(63 - 59) as custom
> > > > attribute bits in PTE.
> > > >
> > > > The patchset contain 4 parts (asid, pgtable, cmo, soc) which have been
> > > >
> > > > tested on D1:
> > > >  - asid: T-HEAD C906 of D1 contains full asid hw facilities which has no
> > > >
> > > >    conflict with RISC-V spec, and hope these patches soon could be
> > > >    approved.
> > > >
> > > >  - pgtable: Using a image-hdr to pass vendor specific information and
> > > >
> > > >    setup custom PTE attributes in a global struct variable during boot
> > > >    stage. Also it needs define custom protection_map in linux/mm.
> > > >
> > > >  - cmo: We need deal with dma_sync & icache_sync & __vdso_icache_sync.
> > > >
> > > >    In this patchset, I just show you how T-HEAD C9xx work, and seems
> > > >    Atish
> > > >    is working for the DMA infrustructure, please let me know the idea.
> > > >
> > > >  - soc: Add allwinner gmac driver & dts & Kconfig for sunxi test.
> > > >
> > > > The patchset could work with linux-5.13-rc4, here is the steps for D1:
> > > >  - Download linux-5.13-rc4 and apply the patchset
> > > >  - make ARCH=riscv CROSS_COMPILE=riscv64-linux- defconfig
> > > >  - make ARCH=riscv CROSS_COMPILE=riscv64-linux- Image modules dtbs
> > > >  - mkimage -A riscv -O linux -T kernel -C none -a 0x00200000 -e
> > > >  0x00200000
> > > >
> > > > -n Linux -d arch/riscv/boot/Image uImage - Download newest opensbi [2],
> > > > build with [3], and get fw_dynamic.bin - Copy uImage, fw_dynamic.bin,
> > > > allwinner-d1-nezha-kit.dtb into boot partition of TF card.
> > > >
> > > >  - Plugin the TF card and power on D1.
> > > >
> > > > Link: https://linux-sunxi.org/D1 [1]
> > > > Link: https://github.com/riscv/opensbi branch:master [2]
> > > > Link:
> > > > https://github.com/riscv/opensbi/blob/master/docs/platform/thead-c9xx.md
> > > > [3]
> > >
> > > Some patches are marked with v2 and some V5. It's very confusing. Mark
> > > them
> > > with same version in next revision.
> > >
> > > Best regards,
> > > Jernej
> > >
> > > > Changes since v1:
> > > >  - Rebase on linux-5.13-rc4
> > > >  - Support defconfig for different PTE attributes
> > > >  - Support C906 icache_sync
> > > >  - Add Allwinner D1 dts & Kconfig & gmac for testing
> > > >  - Add asid optimization for D1 usage
> > > >
> > > > Guo Ren (10):
> > > >   riscv: asid: Use global mappings for kernel pages
> > > >   riscv: asid: Add ASID-based tlbflushing methods
> > > >   riscv: asid: Optimize tlbflush coding convention
> > > >   riscv: pgtable: Fixup _PAGE_CHG_MASK usage
> > > >   riscv: pgtable: Add custom protection_map init
> > > >   riscv: pgtable: Add DMA_COHERENT with custom PTE attributes
> > > >   riscv: cmo: Add dma-noncoherency support
> > > >   riscv: cmo: Add vendor custom icache sync
> > > >   riscv: soc: Initial DTS for Allwinner D1 NeZha board
> > > >   riscv: soc: Add Allwinner SoC kconfig option
> > > >
> > > > liush (1):
> > > >   riscv: soc: Allwinner D1 GMAC driver only for temp use
> > > >
> > > >  arch/riscv/Kconfig                                 |    9 +
> > > >  arch/riscv/Kconfig.socs                            |   12 +
> > > >  arch/riscv/boot/dts/Makefile                       |    1 +
> > > >  arch/riscv/boot/dts/allwinner/Makefile             |    2 +
> > > >  .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  |   29 +
> > > >  arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    |  100 +
> > > >  arch/riscv/configs/defconfig                       |    1 +
> > > >  arch/riscv/include/asm/cacheflush.h                |   48 +-
> > > >  arch/riscv/include/asm/mmu_context.h               |    2 +
> > > >  arch/riscv/include/asm/pgtable-64.h                |    8 +-
> > > >  arch/riscv/include/asm/pgtable-bits.h              |   20 +-
> > > >  arch/riscv/include/asm/pgtable.h                   |   44 +-
> > > >  arch/riscv/include/asm/sbi.h                       |   15 +
> > > >  arch/riscv/include/asm/soc.h                       |    1 +
> > > >  arch/riscv/include/asm/tlbflush.h                  |   22 +
> > > >  arch/riscv/include/asm/vendorid_list.h             |    1 +
> > > >  arch/riscv/kernel/sbi.c                            |   19 +
> > > >  arch/riscv/kernel/soc.c                            |   22 +
> > > >  arch/riscv/kernel/vdso/flush_icache.S              |   33 +-
> > > >  arch/riscv/mm/Makefile                             |    1 +
> > > >  arch/riscv/mm/cacheflush.c                         |    3 +-
> > > >  arch/riscv/mm/context.c                            |    2 +-
> > > >  arch/riscv/mm/dma-mapping.c                        |   53 +
> > > >  arch/riscv/mm/init.c                               |   26 +
> > > >  arch/riscv/mm/tlbflush.c                           |   57 +-
> > > >  drivers/net/ethernet/Kconfig                       |    1 +
> > > >  drivers/net/ethernet/Makefile                      |    1 +
> > > >  drivers/net/ethernet/allwinnertmp/Kconfig          |   17 +
> > > >  drivers/net/ethernet/allwinnertmp/Makefile         |    7 +
> > > >  drivers/net/ethernet/allwinnertmp/sunxi-gmac-ops.c |  690 ++++++
> > > >  drivers/net/ethernet/allwinnertmp/sunxi-gmac.c     | 2240
> > > >
> > > > ++++++++++++++++++++ drivers/net/ethernet/allwinnertmp/sunxi-gmac.h
> > > > |
> > > > 258 +++
> > > >
> > > >  drivers/net/phy/realtek.c                          |    2 +-
> > > >  mm/mmap.c                                          |    4 +
> > > >  34 files changed, 3714 insertions(+), 37 deletions(-)
> > > >  create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> > > >  create mode 100644
> > > >  arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
> > > >
> > > > create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
> > > > create
> > > > mode 100644 arch/riscv/mm/dma-mapping.c
> > > >
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/Kconfig
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/Makefile
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac-ops.c
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac.c
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac.h
>
>
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

WARNING: multiple messages have this Message-ID (diff)
From: Guo Ren <guoren@kernel.org>
To: "Jernej Škrabec" <jernej.skrabec@gmail.com>
Cc: "Anup Patel" <anup.patel@wdc.com>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	wens@csie.org, maxime@cerno.tech,
	"Drew Fustini" <drew@beagleboard.org>,
	liush@allwinnertech.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
	wefu@redhat.com, linux-riscv <linux-riscv@lists.infradead.org>,
	"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	linux-sunxi@lists.linux.dev, "Guo Ren" <guoren@linux.alibaba.com>
Subject: Re: [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1
Date: Mon, 7 Jun 2021 07:42:18 +0800	[thread overview]
Message-ID: <CAJF2gTR6zV8GuftZ1M69Ma2rxy31KvMBVjyB8G40JnyY4D+0Gw@mail.gmail.com> (raw)
In-Reply-To: <1664140.l4xsYfQU8q@jernej-laptop>

On Mon, Jun 7, 2021 at 1:14 AM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> Dne nedelja, 06. junij 2021 ob 18:54:05 CEST je Guo Ren napisal(a):
> > V5 is not related to the patch series.
>
> Don't top post.
>
> If that's the case, then your e-mail client messed things up. I got V5 patches
> in the same thread as board enablement patches and so did mailing list [1].
I made mistake that make two patchset mixed in my linux directory.

git format-patch -11
git send-email *.patch

But there are still some last posted patches in *.patch.

I'll prevent it in the next patchset version.

>
> Best regards,
> Jernej
>
> [1] https://lore.kernel.org/linux-sunxi/
> CAJF2gTQ1yvSNthJ2yJkqaYGaJ6OYmf0vbG=hm4ocgnw4DiZbOw@mail.gmail.com/T/#t
>
> >
> > On Mon, Jun 7, 2021 at 12:29 AM Jernej Škrabec <jernej.skrabec@gmail.com>
> wrote:
> > > Hi!
> > >
> > > Dne nedelja, 06. junij 2021 ob 11:03:55 CEST je guoren@kernel.org
> napisal(a):
> > > > From: Guo Ren <guoren@linux.alibaba.com>
> > > >
> > > > The RISC-V ISA doesn't yet specify how to query or modify PMAs, so let
> > > > vendors define the custom properties of memory regions in PTE.
> > > >
> > > > This patchset helps SOC vendors to support their own custom interconnect
> > > > coherent solution with PTE attributes.
> > > >
> > > > For example, allwinner D1[1] uses T-HEAD C906 as main processor, C906
> > > > has
> > > >
> > > > two modes in MMU:
> > > >  - Compatible mode, the same as the definitions in spec.
> > > >  - Enhanced mode, add custom DMA_COHERENT attribute bits in PTE which
> > > >
> > > >    not mentioned in spec.
> > > >
> > > > Allwinner D1 needs the enhanced mode to support the DMA type device with
> > > > non-coherent interconnect in its SOC. C906 uses BITS(63 - 59) as custom
> > > > attribute bits in PTE.
> > > >
> > > > The patchset contain 4 parts (asid, pgtable, cmo, soc) which have been
> > > >
> > > > tested on D1:
> > > >  - asid: T-HEAD C906 of D1 contains full asid hw facilities which has no
> > > >
> > > >    conflict with RISC-V spec, and hope these patches soon could be
> > > >    approved.
> > > >
> > > >  - pgtable: Using a image-hdr to pass vendor specific information and
> > > >
> > > >    setup custom PTE attributes in a global struct variable during boot
> > > >    stage. Also it needs define custom protection_map in linux/mm.
> > > >
> > > >  - cmo: We need deal with dma_sync & icache_sync & __vdso_icache_sync.
> > > >
> > > >    In this patchset, I just show you how T-HEAD C9xx work, and seems
> > > >    Atish
> > > >    is working for the DMA infrustructure, please let me know the idea.
> > > >
> > > >  - soc: Add allwinner gmac driver & dts & Kconfig for sunxi test.
> > > >
> > > > The patchset could work with linux-5.13-rc4, here is the steps for D1:
> > > >  - Download linux-5.13-rc4 and apply the patchset
> > > >  - make ARCH=riscv CROSS_COMPILE=riscv64-linux- defconfig
> > > >  - make ARCH=riscv CROSS_COMPILE=riscv64-linux- Image modules dtbs
> > > >  - mkimage -A riscv -O linux -T kernel -C none -a 0x00200000 -e
> > > >  0x00200000
> > > >
> > > > -n Linux -d arch/riscv/boot/Image uImage - Download newest opensbi [2],
> > > > build with [3], and get fw_dynamic.bin - Copy uImage, fw_dynamic.bin,
> > > > allwinner-d1-nezha-kit.dtb into boot partition of TF card.
> > > >
> > > >  - Plugin the TF card and power on D1.
> > > >
> > > > Link: https://linux-sunxi.org/D1 [1]
> > > > Link: https://github.com/riscv/opensbi branch:master [2]
> > > > Link:
> > > > https://github.com/riscv/opensbi/blob/master/docs/platform/thead-c9xx.md
> > > > [3]
> > >
> > > Some patches are marked with v2 and some V5. It's very confusing. Mark
> > > them
> > > with same version in next revision.
> > >
> > > Best regards,
> > > Jernej
> > >
> > > > Changes since v1:
> > > >  - Rebase on linux-5.13-rc4
> > > >  - Support defconfig for different PTE attributes
> > > >  - Support C906 icache_sync
> > > >  - Add Allwinner D1 dts & Kconfig & gmac for testing
> > > >  - Add asid optimization for D1 usage
> > > >
> > > > Guo Ren (10):
> > > >   riscv: asid: Use global mappings for kernel pages
> > > >   riscv: asid: Add ASID-based tlbflushing methods
> > > >   riscv: asid: Optimize tlbflush coding convention
> > > >   riscv: pgtable: Fixup _PAGE_CHG_MASK usage
> > > >   riscv: pgtable: Add custom protection_map init
> > > >   riscv: pgtable: Add DMA_COHERENT with custom PTE attributes
> > > >   riscv: cmo: Add dma-noncoherency support
> > > >   riscv: cmo: Add vendor custom icache sync
> > > >   riscv: soc: Initial DTS for Allwinner D1 NeZha board
> > > >   riscv: soc: Add Allwinner SoC kconfig option
> > > >
> > > > liush (1):
> > > >   riscv: soc: Allwinner D1 GMAC driver only for temp use
> > > >
> > > >  arch/riscv/Kconfig                                 |    9 +
> > > >  arch/riscv/Kconfig.socs                            |   12 +
> > > >  arch/riscv/boot/dts/Makefile                       |    1 +
> > > >  arch/riscv/boot/dts/allwinner/Makefile             |    2 +
> > > >  .../boot/dts/allwinner/allwinner-d1-nezha-kit.dts  |   29 +
> > > >  arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi    |  100 +
> > > >  arch/riscv/configs/defconfig                       |    1 +
> > > >  arch/riscv/include/asm/cacheflush.h                |   48 +-
> > > >  arch/riscv/include/asm/mmu_context.h               |    2 +
> > > >  arch/riscv/include/asm/pgtable-64.h                |    8 +-
> > > >  arch/riscv/include/asm/pgtable-bits.h              |   20 +-
> > > >  arch/riscv/include/asm/pgtable.h                   |   44 +-
> > > >  arch/riscv/include/asm/sbi.h                       |   15 +
> > > >  arch/riscv/include/asm/soc.h                       |    1 +
> > > >  arch/riscv/include/asm/tlbflush.h                  |   22 +
> > > >  arch/riscv/include/asm/vendorid_list.h             |    1 +
> > > >  arch/riscv/kernel/sbi.c                            |   19 +
> > > >  arch/riscv/kernel/soc.c                            |   22 +
> > > >  arch/riscv/kernel/vdso/flush_icache.S              |   33 +-
> > > >  arch/riscv/mm/Makefile                             |    1 +
> > > >  arch/riscv/mm/cacheflush.c                         |    3 +-
> > > >  arch/riscv/mm/context.c                            |    2 +-
> > > >  arch/riscv/mm/dma-mapping.c                        |   53 +
> > > >  arch/riscv/mm/init.c                               |   26 +
> > > >  arch/riscv/mm/tlbflush.c                           |   57 +-
> > > >  drivers/net/ethernet/Kconfig                       |    1 +
> > > >  drivers/net/ethernet/Makefile                      |    1 +
> > > >  drivers/net/ethernet/allwinnertmp/Kconfig          |   17 +
> > > >  drivers/net/ethernet/allwinnertmp/Makefile         |    7 +
> > > >  drivers/net/ethernet/allwinnertmp/sunxi-gmac-ops.c |  690 ++++++
> > > >  drivers/net/ethernet/allwinnertmp/sunxi-gmac.c     | 2240
> > > >
> > > > ++++++++++++++++++++ drivers/net/ethernet/allwinnertmp/sunxi-gmac.h
> > > > |
> > > > 258 +++
> > > >
> > > >  drivers/net/phy/realtek.c                          |    2 +-
> > > >  mm/mmap.c                                          |    4 +
> > > >  34 files changed, 3714 insertions(+), 37 deletions(-)
> > > >  create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
> > > >  create mode 100644
> > > >  arch/riscv/boot/dts/allwinner/allwinner-d1-nezha-kit.dts
> > > >
> > > > create mode 100644 arch/riscv/boot/dts/allwinner/allwinner-d1.dtsi
> > > > create
> > > > mode 100644 arch/riscv/mm/dma-mapping.c
> > > >
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/Kconfig
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/Makefile
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac-ops.c
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac.c
> > > >  create mode 100644 drivers/net/ethernet/allwinnertmp/sunxi-gmac.h
>
>
>
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-06-06 23:42 UTC|newest]

Thread overview: 107+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-06  9:03 [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 guoren
2021-06-06  9:03 ` guoren
2021-06-06  9:03 ` [RFC PATCH v2 01/11] riscv: asid: Use global mappings for kernel pages guoren
2021-06-06  9:03   ` guoren
2021-06-06  9:03 ` [PATCH V5 1/3] riscv: " guoren
2021-06-06  9:03   ` guoren
2021-06-06  9:03 ` [PATCH V5 2/3] riscv: Add ASID-based tlbflushing methods guoren
2021-06-06  9:03   ` guoren
2021-06-06 14:38   ` Christoph Hellwig
2021-06-06 14:38     ` Christoph Hellwig
2021-06-06  9:03 ` [RFC PATCH v2 02/11] riscv: asid: " guoren
2021-06-06  9:03   ` guoren
2021-06-06  9:04 ` [RFC PATCH v2 03/11] riscv: asid: Optimize tlbflush coding convention guoren
2021-06-06  9:04   ` guoren
2021-06-06  9:04 ` [PATCH V5 3/3] riscv: tlbflush: Optimize " guoren
2021-06-06  9:04   ` guoren
2021-06-06  9:04 ` [RFC PATCH v2 04/11] riscv: pgtable: Fixup _PAGE_CHG_MASK usage guoren
2021-06-06  9:04   ` guoren
2021-06-06  9:04 ` [RFC PATCH v2 05/11] riscv: pgtable: Add custom protection_map init guoren
2021-06-06  9:04   ` guoren
2021-06-06  9:04 ` [RFC PATCH v2 06/11] riscv: pgtable: Add DMA_COHERENT with custom PTE attributes guoren
2021-06-06  9:04   ` guoren
2021-06-06 14:39   ` Christoph Hellwig
2021-06-06 14:39     ` Christoph Hellwig
2021-06-06 15:08     ` Guo Ren
2021-06-06 15:08       ` Guo Ren
2021-06-06 17:22   ` Nick Kossifidis
2021-06-06 17:22     ` Nick Kossifidis
2021-06-07  6:19     ` Christoph Hellwig
2021-06-07  6:19       ` Christoph Hellwig
2021-06-06  9:04 ` [RFC PATCH v2 07/11] riscv: cmo: Add dma-noncoherency support guoren
2021-06-06  9:04   ` guoren
2021-10-17  9:28   ` twd2
2021-10-17  9:28     ` twd2
2021-10-20  8:11     ` Guo Ren
2021-10-20  8:11       ` Guo Ren
2021-06-06  9:04 ` [RFC PATCH v2 08/11] riscv: cmo: Add vendor custom icache sync guoren
2021-06-06  9:04   ` guoren
2021-06-06  9:04 ` [RFC PATCH v2 09/11] riscv: soc: Initial DTS for Allwinner D1 NeZha board guoren
2021-06-06  9:04   ` guoren
2021-06-06 16:26   ` Jernej Škrabec
2021-06-06 16:26     ` Jernej Škrabec
2021-06-06 17:05     ` Guo Ren
2021-06-06 17:05       ` Guo Ren
2021-06-07  3:44     ` Guo Ren
2021-06-07  3:44       ` Guo Ren
2021-06-07  7:27       ` Maxime Ripard
2021-06-07  7:27         ` Maxime Ripard
2021-06-07  7:53         ` Guo Ren
2021-06-07  7:53           ` Guo Ren
2021-06-07  7:24   ` Maxime Ripard
2021-06-07  7:24     ` Maxime Ripard
2021-06-07  8:07     ` Guo Ren
2021-06-07  8:07       ` Guo Ren
2021-06-14 15:33       ` Maxime Ripard
2021-06-14 15:33         ` Maxime Ripard
2021-06-14 16:28         ` Guo Ren
2021-06-14 16:28           ` Guo Ren
2021-06-14 16:31           ` Jernej Škrabec
2021-06-14 16:31             ` Jernej Škrabec
2021-06-06  9:04 ` [RFC PATCH v2 10/11] riscv: soc: Add Allwinner SoC kconfig option guoren
2021-06-06  9:04   ` guoren
2021-06-07  7:19   ` Maxime Ripard
2021-06-07  7:19     ` Maxime Ripard
2021-06-07  7:27     ` Arnd Bergmann
2021-06-07  7:27       ` Arnd Bergmann
2021-06-07  7:27       ` Arnd Bergmann
2021-06-07  7:45       ` Guo Ren
2021-06-07  7:45         ` Guo Ren
2021-06-07  7:43     ` Guo Ren
2021-06-07  7:43       ` Guo Ren
2021-06-07 12:12       ` Maxime Ripard
2021-06-07 12:12         ` Maxime Ripard
2021-06-07 12:39         ` Guo Ren
2021-06-07 12:39           ` Guo Ren
2021-06-06  9:04 ` [RFC PATCH v2 11/11] riscv: soc: Allwinner D1 GMAC driver only for temp use guoren
2021-06-06  9:04   ` guoren
2021-06-06 10:50   ` Andre Przywara
2021-06-06 10:50     ` Andre Przywara
2021-06-06 15:32     ` Guo Ren
2021-06-06 15:32       ` Guo Ren
2021-06-06 15:39       ` Jernej Škrabec
2021-06-06 15:39         ` Jernej Škrabec
2021-06-06 15:41         ` Guo Ren
2021-06-06 15:41           ` Guo Ren
2021-06-06 16:16   ` Arnd Bergmann
2021-06-06 16:16     ` Arnd Bergmann
2021-06-06 16:16     ` Arnd Bergmann
2021-06-06 16:32     ` Jernej Škrabec
2021-06-06 16:32       ` Jernej Škrabec
2021-06-06 16:53       ` Guo Ren
2021-06-06 16:53         ` Guo Ren
2021-06-06 16:53     ` Guo Ren
2021-06-06 16:53       ` Guo Ren
2021-06-06 16:29 ` [RFC PATCH v2 00/11] riscv: Add DMA_COHERENT support for Allwinner D1 Jernej Škrabec
2021-06-06 16:29   ` Jernej Škrabec
2021-06-06 16:54   ` Guo Ren
2021-06-06 16:54     ` Guo Ren
2021-06-06 17:14     ` Jernej Škrabec
2021-06-06 17:14       ` Jernej Škrabec
2021-06-06 23:42       ` Guo Ren [this message]
2021-06-06 23:42         ` Guo Ren
2021-06-07  3:44 ` Anup Patel
2021-06-07  3:44   ` Anup Patel
2021-06-07  4:36   ` Guo Ren
2021-06-07  4:36     ` Guo Ren
2021-06-07  4:36     ` Guo Ren

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAJF2gTR6zV8GuftZ1M69Ma2rxy31KvMBVjyB8G40JnyY4D+0Gw@mail.gmail.com \
    --to=guoren@kernel.org \
    --cc=anup.patel@wdc.com \
    --cc=arnd@arndb.de \
    --cc=drew@beagleboard.org \
    --cc=guoren@linux.alibaba.com \
    --cc=jernej.skrabec@gmail.com \
    --cc=lazyparser@gmail.com \
    --cc=linux-arch@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=liush@allwinnertech.com \
    --cc=maxime@cerno.tech \
    --cc=palmerdabbelt@google.com \
    --cc=wefu@redhat.com \
    --cc=wens@csie.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.