Re: [PATCH 14/22] hw/sd: ssi-sd: Support single block write

From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Qemu-block <qemu-block@nongnu.org>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"Alistair Francis" <alistair.francis@wdc.com>
Subject: Re: [PATCH 14/22] hw/sd: ssi-sd: Support single block write
Date: Wed, 13 Jan 2021 10:07:52 -0800	[thread overview]
Message-ID: <CAKmqyKM8=iv6_89AYcU5_WkagacVsOwj1Hiit6Aax+rJmLGUWQ@mail.gmail.com> (raw)
In-Reply-To: <20201231113010.27108-15-bmeng.cn@gmail.com>

On Thu, Dec 31, 2020 at 3:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Add 2 more states for the block write operation. The SPI host needs
> to send a data start tocken to start the transfer, and the data block
> written to the card will be acknowledged by a data response tocken.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/sd/ssi-sd.c | 37 ++++++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
> index 8eb48550cf..21a96e91f0 100644
> --- a/hw/sd/ssi-sd.c
> +++ b/hw/sd/ssi-sd.c
> @@ -42,6 +42,8 @@ typedef enum {
>      SSI_SD_DATA_START,
>      SSI_SD_DATA_READ,
>      SSI_SD_DATA_CRC16,
> +    SSI_SD_DATA_WRITE,
> +    SSI_SD_SKIP_CRC16,
>  } ssi_sd_mode;
>
>  struct ssi_sd_state {
> @@ -52,6 +54,7 @@ struct ssi_sd_state {
>      uint8_t response[5];
>      uint16_t crc16;
>      int32_t read_bytes;
> +    int32_t write_bytes;
>      int32_t arglen;
>      int32_t response_pos;
>      int32_t stopping;
> @@ -90,6 +93,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
>  /* dummy value - don't care */
>  #define SSI_DUMMY               0xff
>
> +/* data accepted */
> +#define DATA_RESPONSE_ACCEPTED  0x05
> +
>  static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
>  {
>      ssi_sd_state *s = SSI_SD(dev);
> @@ -103,10 +109,17 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
>
>      switch (s->mode) {
>      case SSI_SD_CMD:
> -        if (val == SSI_DUMMY) {
> +        switch (val) {
> +        case SSI_DUMMY:
>              DPRINTF("NULL command\n");
>              return SSI_DUMMY;
> +            break;
> +        case SSI_TOKEN_SINGLE:
> +            DPRINTF("Start write block\n");
> +            s->mode = SSI_SD_DATA_WRITE;
> +            return SSI_DUMMY;
>          }
> +
>          s->cmd = val & 0x3f;
>          s->mode = SSI_SD_CMDARG;
>          s->arglen = 0;
> @@ -235,6 +248,27 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
>              s->response_pos = 0;
>          }
>          return val;
> +    case SSI_SD_DATA_WRITE:
> +        sdbus_write_byte(&s->sdbus, val);
> +        s->write_bytes++;
> +        if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) {
> +            DPRINTF("Data write end\n");
> +            s->mode = SSI_SD_SKIP_CRC16;
> +            s->response_pos = 0;
> +        }
> +        return val;
> +    case SSI_SD_SKIP_CRC16:
> +        /* we don't verify the crc16 */
> +        s->response_pos++;
> +        if (s->response_pos == 2) {
> +            DPRINTF("CRC16 receive end\n");
> +            s->mode = SSI_SD_RESPONSE;
> +            s->write_bytes = 0;
> +            s->arglen = 1;
> +            s->response[0] = DATA_RESPONSE_ACCEPTED;
> +            s->response_pos = 0;
> +        }
> +        return SSI_DUMMY;
>      }
>      /* Should never happen.  */
>      return SSI_DUMMY;
> @@ -325,6 +359,7 @@ static void ssi_sd_reset(DeviceState *dev)
>      memset(s->response, 0, sizeof(s->response));
>      s->crc16 = 0;
>      s->read_bytes = 0;
> +    s->write_bytes = 0;
>      s->arglen = 0;
>      s->response_pos = 0;
>      s->stopping = 0;
> --
> 2.25.1
>
>