From: Alistair Francis <alistair23@gmail.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Anup Patel <Anup.Patel@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Atish Patra <Atish.Patra@wdc.com>
Subject: Re: [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode
Date: Wed, 16 Oct 2019 13:56:04 -0700 [thread overview]
Message-ID: <CAKmqyKMf1bPSpM7RP1ULmOK7sKcUFA5Rbb_TkD7f0vTtu5fa1Q@mail.gmail.com> (raw)
In-Reply-To: <mhng-afa69c9b-17b7-4043-b204-512c92cf618a@palmer-si-x1e>
On Tue, Sep 10, 2019 at 7:48 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Fri, 23 Aug 2019 16:38:00 PDT (-0700), Alistair Francis wrote:
> > Update the CSR permission checking to work correctly when we are in
> > HS-mode.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/csr.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index f767ad24be..471f23a1d0 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -799,9 +799,15 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> >
> > /* check privileges and return -1 if check fails */
> > #if !defined(CONFIG_USER_ONLY)
> > - int csr_priv = get_field(csrno, 0x300);
> > + int csr_priv = env->priv;
>
> This isn't really "csr_priv" (ie, the priv needed to access the CSR) any more,
> it's really the effective priv of the machine. Leaving the variable with the
> same name makes this hard to read, but I think it is correct.
I changed the name to effective_priv.
>
> > int read_only = get_field(csrno, 0xC00) == 3;
> > - if ((write_mask && read_only) || (env->priv < csr_priv)) {
> > +
> > + if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
> > + /* Plus 1 as we are in HS mode */
>
> The comment is useless, it doesn't say why we increment it. Also, I don't
> think this is correct: doesn't it allow U mode to access S CSRs when H is
> present and V is disabled?
Yes, you are correct. I have changed it to check that we are in S mode.
>
> Something like
>
> riscv_effective_priv(CPURISCVState *env)
> {
> if (riscv_has_ext(env, RVH) && env->priv == PRIV_S && !riscv_cpu_virt_enabled(env)) {
> return PRIV_HS;
I don't like this as there is no PRIV_HS. It seems like a bad idea to
start using a reserved privilege level, if it is ever used we will
then be stuck updating this. I also don't think this is used anywhere
else. I have just fixed up the if statement and comment.
Alistair
> }
>
> return env->priv;
> }
>
> would probably be used in a handful of places, and would be a drop in for
> env->priv here.
>
> > + csr_priv++;
> > + }
> > +
> > + if ((write_mask && read_only) || (csr_priv < get_field(csrno, 0x300))) {
> > return -1;
> > }
> > #endif
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Atish Patra <Atish.Patra@wdc.com>,
Anup Patel <Anup.Patel@wdc.com>
Subject: Re: [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode
Date: Wed, 16 Oct 2019 13:56:04 -0700 [thread overview]
Message-ID: <CAKmqyKMf1bPSpM7RP1ULmOK7sKcUFA5Rbb_TkD7f0vTtu5fa1Q@mail.gmail.com> (raw)
In-Reply-To: <mhng-afa69c9b-17b7-4043-b204-512c92cf618a@palmer-si-x1e>
On Tue, Sep 10, 2019 at 7:48 AM Palmer Dabbelt <palmer@sifive.com> wrote:
>
> On Fri, 23 Aug 2019 16:38:00 PDT (-0700), Alistair Francis wrote:
> > Update the CSR permission checking to work correctly when we are in
> > HS-mode.
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > target/riscv/csr.c | 10 ++++++++--
> > 1 file changed, 8 insertions(+), 2 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index f767ad24be..471f23a1d0 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -799,9 +799,15 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
> >
> > /* check privileges and return -1 if check fails */
> > #if !defined(CONFIG_USER_ONLY)
> > - int csr_priv = get_field(csrno, 0x300);
> > + int csr_priv = env->priv;
>
> This isn't really "csr_priv" (ie, the priv needed to access the CSR) any more,
> it's really the effective priv of the machine. Leaving the variable with the
> same name makes this hard to read, but I think it is correct.
I changed the name to effective_priv.
>
> > int read_only = get_field(csrno, 0xC00) == 3;
> > - if ((write_mask && read_only) || (env->priv < csr_priv)) {
> > +
> > + if (riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
> > + /* Plus 1 as we are in HS mode */
>
> The comment is useless, it doesn't say why we increment it. Also, I don't
> think this is correct: doesn't it allow U mode to access S CSRs when H is
> present and V is disabled?
Yes, you are correct. I have changed it to check that we are in S mode.
>
> Something like
>
> riscv_effective_priv(CPURISCVState *env)
> {
> if (riscv_has_ext(env, RVH) && env->priv == PRIV_S && !riscv_cpu_virt_enabled(env)) {
> return PRIV_HS;
I don't like this as there is no PRIV_HS. It seems like a bad idea to
start using a reserved privilege level, if it is ever used we will
then be stuck updating this. I also don't think this is used anywhere
else. I have just fixed up the if statement and comment.
Alistair
> }
>
> return env->priv;
> }
>
> would probably be used in a handful of places, and would be a drop in for
> env->priv here.
>
> > + csr_priv++;
> > + }
> > +
> > + if ((write_mask && read_only) || (csr_priv < get_field(csrno, 0x300))) {
> > return -1;
> > }
> > #endif
next prev parent reply other threads:[~2019-10-16 21:02 UTC|newest]
Thread overview: 150+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:26 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:26 ` [Qemu-riscv] " Chih-Min Chao
2019-09-10 13:43 ` Palmer Dabbelt
2019-09-10 13:43 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:44 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:44 ` Chih-Min Chao
2019-08-28 0:08 ` [Qemu-devel] " Alistair Francis
2019-08-28 0:08 ` Alistair Francis
2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 13:44 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-16 15:57 ` [Qemu-devel] " Alistair Francis
2019-09-16 15:57 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:46 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:46 ` [Qemu-riscv] " Chih-Min Chao
2019-09-10 14:48 ` Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-10-16 20:56 ` Alistair Francis [this message]
2019-10-16 20:56 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:50 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:50 ` Chih-Min Chao
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-11 8:24 ` [Qemu-devel] " Palmer Dabbelt
2019-09-11 8:24 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-11 14:54 ` [Qemu-devel] " Jonathan Behrens
2019-09-11 14:54 ` Jonathan Behrens
2019-09-17 23:33 ` [Qemu-devel] " Alistair Francis
2019-09-17 23:33 ` Alistair Francis
2019-09-18 1:59 ` [Qemu-devel] " Jonathan Behrens
2019-09-18 1:59 ` Jonathan Behrens
2019-09-18 23:47 ` [Qemu-devel] " Alistair Francis
2019-09-18 23:47 ` Alistair Francis
2019-09-19 14:50 ` [Qemu-devel] " Richard Henderson
2019-09-19 14:50 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson
2019-09-19 16:58 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-19 16:58 ` Jonathan Behrens
2019-10-25 20:28 ` Alistair Francis
2019-10-25 20:28 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-11 14:17 ` [Qemu-devel] " Palmer Dabbelt
2019-09-11 14:17 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:32 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:32 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-20 14:01 ` Palmer Dabbelt
2019-09-20 14:01 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:33 ` Palmer Dabbelt
2019-10-01 18:33 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-16 21:01 ` Alistair Francis
2019-10-16 21:01 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-07 18:05 ` Alistair Francis
2019-10-07 18:05 ` Alistair Francis
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 21:25 ` Alistair Francis
2019-10-16 21:25 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-07 16:15 ` Palmer Dabbelt
2019-10-07 16:15 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-08 17:54 ` Palmer Dabbelt
2019-10-08 17:54 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-08 18:36 ` Palmer Dabbelt
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-08-23 23:39 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-16 21:14 ` Alistair Francis
2019-10-16 21:14 ` Alistair Francis
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-08-23 23:39 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:53 ` Palmer Dabbelt
2019-10-08 18:53 ` Palmer Dabbelt
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