From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-riscv@nongnu.org, Anup Patel <Anup.Patel@wdc.com>,
qemu-devel@nongnu.org, Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com
Subject: Re: [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState
Date: Tue, 10 Sep 2019 07:48:05 -0700 (PDT) [thread overview]
Message-ID: <mhng-91f54d04-62bd-44b7-a4ce-d7f3631181c0@palmer-si-x1e> (raw)
In-Reply-To: <e959ee81e5121c74678d2383a28665e44db9e31d.1566603412.git.alistair.francis@wdc.com>
On Fri, 23 Aug 2019 16:38:02 PDT (-0700), Alistair Francis wrote:
> As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
> is 32-bit as well.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a95c41428..4c342e7a79 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -154,6 +154,23 @@ struct CPURISCVState {
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
>
> + /* Hypervisor CSRs */
> + target_ulong hstatus;
> + target_ulong hedeleg;
> + target_ulong hideleg;
> + target_ulong hgatp;
> +
> + /* Virtual CSRs */
> + target_ulong vsstatus;
> + uint32_t vsip;
> + target_ulong vsie;
> + target_ulong vstvec;
> + target_ulong vsscratch;
> + target_ulong vsepc;
> + target_ulong vscause;
> + target_ulong vstval;
> + target_ulong vsatp;
> +
> target_ulong scounteren;
> target_ulong mcounteren;
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
WARNING: multiple messages have this Message-ID (diff)
From: Palmer Dabbelt <palmer@sifive.com>
To: Alistair Francis <Alistair.Francis@wdc.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
Alistair Francis <Alistair.Francis@wdc.com>,
alistair23@gmail.com, Atish Patra <Atish.Patra@wdc.com>,
Anup Patel <Anup.Patel@wdc.com>
Subject: Re: [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState
Date: Tue, 10 Sep 2019 07:48:05 -0700 (PDT) [thread overview]
Message-ID: <mhng-91f54d04-62bd-44b7-a4ce-d7f3631181c0@palmer-si-x1e> (raw)
In-Reply-To: <e959ee81e5121c74678d2383a28665e44db9e31d.1566603412.git.alistair.francis@wdc.com>
On Fri, 23 Aug 2019 16:38:02 PDT (-0700), Alistair Francis wrote:
> As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
> is 32-bit as well.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/cpu.h | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a95c41428..4c342e7a79 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -154,6 +154,23 @@ struct CPURISCVState {
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
>
> + /* Hypervisor CSRs */
> + target_ulong hstatus;
> + target_ulong hedeleg;
> + target_ulong hideleg;
> + target_ulong hgatp;
> +
> + /* Virtual CSRs */
> + target_ulong vsstatus;
> + uint32_t vsip;
> + target_ulong vsie;
> + target_ulong vstvec;
> + target_ulong vsscratch;
> + target_ulong vsepc;
> + target_ulong vscause;
> + target_ulong vstval;
> + target_ulong vsatp;
> +
> target_ulong scounteren;
> target_ulong mcounteren;
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
next prev parent reply other threads:[~2019-09-10 15:10 UTC|newest]
Thread overview: 150+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 23:37 [Qemu-devel] [PATCH v1 00/28] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:26 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:26 ` [Qemu-riscv] " Chih-Min Chao
2019-09-10 13:43 ` Palmer Dabbelt
2019-09-10 13:43 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 02/28] target/riscv: Add the virtulisation mode Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:44 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:44 ` Chih-Min Chao
2019-08-28 0:08 ` [Qemu-devel] " Alistair Francis
2019-08-28 0:08 ` Alistair Francis
2019-09-10 13:44 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 13:44 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-16 15:57 ` [Qemu-devel] " Alistair Francis
2019-09-16 15:57 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:37 ` [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode Alistair Francis
2019-08-23 23:37 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:46 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:46 ` [Qemu-riscv] " Chih-Min Chao
2019-09-10 14:48 ` Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-10-16 20:56 ` Alistair Francis
2019-10-16 20:56 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-08-27 15:50 ` [Qemu-devel] " Chih-Min Chao
2019-08-27 15:50 ` Chih-Min Chao
2019-09-10 14:48 ` Palmer Dabbelt [this message]
2019-09-10 14:48 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-10 14:48 ` [Qemu-devel] " Palmer Dabbelt
2019-09-10 14:48 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-11 8:24 ` [Qemu-devel] " Palmer Dabbelt
2019-09-11 8:24 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-11 14:54 ` [Qemu-devel] " Jonathan Behrens
2019-09-11 14:54 ` Jonathan Behrens
2019-09-17 23:33 ` [Qemu-devel] " Alistair Francis
2019-09-17 23:33 ` Alistair Francis
2019-09-18 1:59 ` [Qemu-devel] " Jonathan Behrens
2019-09-18 1:59 ` Jonathan Behrens
2019-09-18 23:47 ` [Qemu-devel] " Alistair Francis
2019-09-18 23:47 ` Alistair Francis
2019-09-19 14:50 ` [Qemu-devel] " Richard Henderson
2019-09-19 14:50 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson
2019-09-19 16:58 ` [Qemu-devel] [Qemu-riscv] " Jonathan Behrens
2019-09-19 16:58 ` Jonathan Behrens
2019-10-25 20:28 ` Alistair Francis
2019-10-25 20:28 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 11/28] target/riscv: Add background register swapping function Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-11 14:17 ` [Qemu-devel] " Palmer Dabbelt
2019-09-11 14:17 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:30 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:30 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-14 20:32 ` [Qemu-devel] " Palmer Dabbelt
2019-09-14 20:32 ` [Qemu-riscv] " Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 16/28] target/riscv: Add hypvervisor trap support Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-09-20 14:01 ` Palmer Dabbelt
2019-09-20 14:01 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 17/28] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:33 ` Palmer Dabbelt
2019-10-01 18:33 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 18/28] target/riscv: Add hfence instructions Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 19/28] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 20/28] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-01 18:34 ` Palmer Dabbelt
2019-10-01 18:34 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 21/28] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-02 23:52 ` Palmer Dabbelt
2019-10-16 21:01 ` Alistair Francis
2019-10-16 21:01 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 22/28] target/riscv: Allow specifying MMU stage Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-03 15:53 ` Palmer Dabbelt
2019-10-07 18:05 ` Alistair Francis
2019-10-07 18:05 ` Alistair Francis
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 19:02 ` Palmer Dabbelt
2019-10-16 21:25 ` Alistair Francis
2019-10-16 21:25 ` Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 23/28] target/riscv: Allow specifying number of MMU stages Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 24/28] target/riscv: Implement second stage MMU Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-07 16:15 ` Palmer Dabbelt
2019-10-07 16:15 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 25/28] target/riscv: Call the second stage MMU in virtualisation mode Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-08 17:54 ` Palmer Dabbelt
2019-10-08 17:54 ` Palmer Dabbelt
2019-08-23 23:38 ` [Qemu-devel] [PATCH v1 26/28] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-08-23 23:38 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-08 18:36 ` Palmer Dabbelt
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 27/28] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-08-23 23:39 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-08 18:36 ` Palmer Dabbelt
2019-10-16 21:14 ` Alistair Francis
2019-10-16 21:14 ` Alistair Francis
2019-08-23 23:39 ` [Qemu-devel] [PATCH v1 28/28] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
2019-08-23 23:39 ` [Qemu-riscv] " Alistair Francis
2019-10-08 18:53 ` Palmer Dabbelt
2019-10-08 18:53 ` Palmer Dabbelt
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