From: Andrew Bresticker <abrestic@chromium.org> To: Mikko Perttunen <mperttunen@nvidia.com> Cc: Stephen Warren <swarren@wwwdotorg.org>, Thierry Reding <thierry.reding@gmail.com>, Tejun Heo <tj@kernel.org>, Peter De Schrijver <pdeschrijver@nvidia.com>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>, linux-ide@vger.kernel.org Subject: Re: [PATCH v2 4/7] clk: tegra: Enable hardware control of SATA PLL Date: Mon, 7 Jul 2014 18:26:33 -0700 [thread overview] Message-ID: <CAL1qeaHo_HEoXoCQjQuqux_BNPtz4BtOnrYTa4=vcNQCYxiDSg@mail.gmail.com> (raw) In-Reply-To: <1403101406-15439-5-git-send-email-mperttunen@nvidia.com> On Wed, Jun 18, 2014 at 7:23 AM, Mikko Perttunen <mperttunen@nvidia.com> wrote: > This makes the SATA PLL be controlled by hardware instead of software. > This is required for working SATA support. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > Acked-by: Stephen Warren <swarren@nvidia.com> I know Peter sent a pull request including this patch already, but I don't see it yet in Mike's tree, so perhaps it's possible to address my comment below (or else I'll include it in the next spin of my XUSB series. > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > @@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) > val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; > pll_writel(val, XUSBIO_PLL_CFG0, pll); > > + /* Enable hw control of SATA pll */ > + val = pll_readl(SATA_PLL_CFG0, pll); > + val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; > + pll_writel(val, SATA_PLL_CFG0, pll); > + Apparently the procedure for enabling the SATA PLL for XUSB (when the SATA lane is used) is slightly different. Specifically, it would be: val = pll_readl(SATA_PLL_CFG0, pll); val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; val |= SATA_PLL_CFG0_SEQ_START_STATE; pll_writel(val, SATA_PLL_CFG0, pll); udelay(1); val = pll_readl(SATA_PLL_CFG0, pll); val |= SATA_PLL_CFG0_SEQ_ENABLE; pll_writel(val, SATA_PLL_CFG0, pll); Do you know if this sequence also works when the SATA lane is used for SATA?
WARNING: multiple messages have this Message-ID (diff)
From: abrestic@chromium.org (Andrew Bresticker) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/7] clk: tegra: Enable hardware control of SATA PLL Date: Mon, 7 Jul 2014 18:26:33 -0700 [thread overview] Message-ID: <CAL1qeaHo_HEoXoCQjQuqux_BNPtz4BtOnrYTa4=vcNQCYxiDSg@mail.gmail.com> (raw) In-Reply-To: <1403101406-15439-5-git-send-email-mperttunen@nvidia.com> On Wed, Jun 18, 2014 at 7:23 AM, Mikko Perttunen <mperttunen@nvidia.com> wrote: > This makes the SATA PLL be controlled by hardware instead of software. > This is required for working SATA support. > > Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> > Acked-by: Stephen Warren <swarren@nvidia.com> I know Peter sent a pull request including this patch already, but I don't see it yet in Mike's tree, so perhaps it's possible to address my comment below (or else I'll include it in the next spin of my XUSB series. > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > @@ -1361,6 +1364,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) > val |= XUSBIO_PLL_CFG0_SEQ_ENABLE; > pll_writel(val, XUSBIO_PLL_CFG0, pll); > > + /* Enable hw control of SATA pll */ > + val = pll_readl(SATA_PLL_CFG0, pll); > + val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; > + pll_writel(val, SATA_PLL_CFG0, pll); > + Apparently the procedure for enabling the SATA PLL for XUSB (when the SATA lane is used) is slightly different. Specifically, it would be: val = pll_readl(SATA_PLL_CFG0, pll); val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; val |= SATA_PLL_CFG0_SEQ_START_STATE; pll_writel(val, SATA_PLL_CFG0, pll); udelay(1); val = pll_readl(SATA_PLL_CFG0, pll); val |= SATA_PLL_CFG0_SEQ_ENABLE; pll_writel(val, SATA_PLL_CFG0, pll); Do you know if this sequence also works when the SATA lane is used for SATA?
next prev parent reply other threads:[~2014-07-08 1:26 UTC|newest] Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top 2014-06-18 14:23 [PATCH v2 0/7] Serial ATA support for NVIDIA Tegra124 Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` [PATCH v2 1/7] of: Add NVIDIA Tegra SATA controller binding Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` [PATCH v2 2/7] ARM: tegra: Add SATA controller to Tegra124 device tree Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` [PATCH v2 3/7] ARM: tegra: Add SATA and SATA power to Jetson TK1 " Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` [PATCH v2 4/7] clk: tegra: Enable hardware control of SATA PLL Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-07-08 1:26 ` Andrew Bresticker [this message] 2014-07-08 1:26 ` Andrew Bresticker 2014-07-08 1:26 ` Andrew Bresticker 2014-07-08 7:30 ` [PATCH] clk: tegra: Use XUSB-compatible SATA PLL sequence Mikko Perttunen 2014-07-08 7:30 ` Mikko Perttunen 2014-07-08 7:30 ` Mikko Perttunen 2014-07-08 8:16 ` Peter De Schrijver 2014-07-08 8:16 ` Peter De Schrijver 2014-07-08 8:16 ` Peter De Schrijver 2014-06-18 14:23 ` [PATCH v2 5/7] clk: tegra: Add SATA clocks to Tegra124 initialization table Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-24 19:32 ` Stephen Warren 2014-06-24 19:32 ` Stephen Warren 2014-06-18 14:23 ` [PATCH v2 6/7] ata: Add support for the Tegra124 SATA controller Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen [not found] ` <1403101406-15439-7-git-send-email-mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-06-24 19:35 ` Stephen Warren 2014-06-24 19:35 ` Stephen Warren 2014-06-24 19:35 ` Stephen Warren 2014-06-26 11:18 ` Mikko Perttunen 2014-06-26 11:18 ` Mikko Perttunen 2014-06-26 11:18 ` Mikko Perttunen 2014-07-08 8:20 ` Mikko Perttunen 2014-07-08 8:20 ` Mikko Perttunen 2014-07-08 8:20 ` Mikko Perttunen 2014-07-09 6:49 ` Thierry Reding 2014-07-09 6:49 ` Thierry Reding 2014-07-09 6:49 ` Thierry Reding 2014-07-09 13:45 ` Mikko Perttunen 2014-07-09 13:45 ` Mikko Perttunen 2014-07-09 13:45 ` Mikko Perttunen 2014-07-08 13:22 ` Tejun Heo 2014-07-08 13:22 ` Tejun Heo 2014-07-08 13:38 ` Mikko Perttunen 2014-07-08 13:38 ` Mikko Perttunen 2014-07-08 13:38 ` Mikko Perttunen 2014-07-14 6:21 ` Mikko Perttunen 2014-07-14 6:21 ` Mikko Perttunen 2014-07-14 6:21 ` Mikko Perttunen [not found] ` <53C376FF.3060509-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2014-07-14 6:25 ` Hans de Goede 2014-07-14 6:25 ` Hans de Goede 2014-07-14 6:25 ` Hans de Goede 2014-07-14 6:28 ` Mikko Perttunen 2014-07-14 6:28 ` Mikko Perttunen 2014-07-14 6:28 ` Mikko Perttunen [not found] ` <20140708132216.GA4979-Gd/HAXX7CRxy/B6EtB590w@public.gmane.org> 2014-07-14 13:36 ` Hans de Goede 2014-07-14 13:36 ` Hans de Goede 2014-07-14 13:36 ` Hans de Goede 2014-07-15 7:12 ` Mikko Perttunen 2014-07-15 7:12 ` Mikko Perttunen 2014-07-15 7:12 ` Mikko Perttunen 2014-07-15 8:55 ` Hans de Goede 2014-07-15 8:55 ` Hans de Goede 2014-07-15 8:55 ` Hans de Goede [not found] ` <53C4EC81.1040304-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> 2014-07-15 9:03 ` Mikko Perttunen 2014-07-15 9:03 ` Mikko Perttunen 2014-07-15 9:03 ` Mikko Perttunen 2014-07-15 9:31 ` Thierry Reding 2014-07-15 9:31 ` Thierry Reding 2014-07-15 9:31 ` Thierry Reding 2014-06-18 14:23 ` [PATCH v2 7/7] ARM: tegra: Add options for Tegra AHCI support to tegra_defconfig Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen 2014-06-18 14:23 ` Mikko Perttunen
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