From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Tom Joseph <tjoseph@cadence.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
PCI <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Arnd Bergmann <arnd@arndb.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
devicetree@vger.kernel.org,
linux-omap <linux-omap@vger.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
Date: Fri, 22 May 2020 09:54:27 -0600 [thread overview]
Message-ID: <CAL_JsqJjXUUgTbSAi83w4Eie-sVTrkLLMGh_PRQsd8k2vuua4Q@mail.gmail.com> (raw)
In-Reply-To: <20200522033631.32574-4-kishon@ti.com>
On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
> for adding PCIe support in TI's J721E SoC.
Looking more closely I don't think cdns_pcie_ep_assert_intx is okay
with this and never can be given the PCI_COMMAND and PCI_STATUS
registers are in the same word (IIRC, that's the main reason 32-bit
config space accesses are broken). So this isn't going to work at
least for EP accesses. And maybe you need a custom .raise_irq() hook
to minimize any problems (such as making the RMW atomic at least from
the endpoint's perspective).
Rob
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Arnd Bergmann <arnd@arndb.de>, PCI <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Tom Joseph <tjoseph@cadence.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Bjorn Helgaas <bhelgaas@google.com>,
linux-omap <linux-omap@vger.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses
Date: Fri, 22 May 2020 09:54:27 -0600 [thread overview]
Message-ID: <CAL_JsqJjXUUgTbSAi83w4Eie-sVTrkLLMGh_PRQsd8k2vuua4Q@mail.gmail.com> (raw)
In-Reply-To: <20200522033631.32574-4-kishon@ti.com>
On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Certain platforms like TI's J721E using Cadence PCIe IP can perform only
> 32-bit accesses for reading or writing to Cadence registers. Convert all
> read and write accesses to 32-bit in Cadence PCIe driver in preparation
> for adding PCIe support in TI's J721E SoC.
Looking more closely I don't think cdns_pcie_ep_assert_intx is okay
with this and never can be given the PCI_COMMAND and PCI_STATUS
registers are in the same word (IIRC, that's the main reason 32-bit
config space accesses are broken). So this isn't going to work at
least for EP accesses. And maybe you need a custom .raise_irq() hook
to minimize any problems (such as making the RMW atomic at least from
the endpoint's perspective).
Rob
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next prev parent reply other threads:[~2020-05-22 15:54 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-22 3:36 [PATCH v5 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 15:54 ` Rob Herring [this message]
2020-05-22 15:54 ` Rob Herring
2020-05-25 3:30 ` Kishon Vijay Abraham I
2020-05-25 3:30 ` Kishon Vijay Abraham I
2020-05-26 15:12 ` Rob Herring
2020-05-26 15:12 ` Rob Herring
2020-05-27 10:49 ` Kishon Vijay Abraham I
2020-05-27 10:49 ` Kishon Vijay Abraham I
2020-05-27 16:37 ` Rob Herring
2020-05-27 16:37 ` Rob Herring
2020-05-27 22:06 ` Kishon Vijay Abraham I
2020-05-27 22:06 ` Kishon Vijay Abraham I
2020-06-01 1:16 ` Kishon Vijay Abraham I
2020-06-01 1:16 ` Kishon Vijay Abraham I
2020-06-08 15:58 ` Kishon Vijay Abraham I
2020-06-08 15:58 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 05/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 06/14] dt-bindings: PCI: cadence: Remove "mem" from reg binding Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-26 22:53 ` Rob Herring
2020-05-26 22:53 ` Rob Herring
2020-05-22 3:36 ` [PATCH v5 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
2020-05-22 3:36 ` [PATCH v5 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-05-22 3:36 ` Kishon Vijay Abraham I
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