From: Nicolas Boichat <drinkcat@chromium.org> To: weiyi.lu@mediatek.com Cc: Matthias Brugger <matthias.bgg@gmail.com>, sboyd@codeaurora.org, Rob Herring <robh@kernel.org>, jamesjj.liao@mediatek.com, fan.chen@mediatek.com, linux-arm Mailing List <linux-arm-kernel@lists.infradead.org>, lkml <linux-kernel@vger.kernel.org>, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, srv_heupstream@mediatek.com, owen.chen@mediatek.com Subject: Re: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data Date: Tue, 13 Nov 2018 08:18:52 -0800 [thread overview] Message-ID: <CANMq1KBjtyQFyJ-mZBndPDSfSDnD0K8izy39jp9zKE4xfiCiog@mail.gmail.com> (raw) In-Reply-To: <20181106064206.17535-4-weiyi.lu@mediatek.com> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > From: Owen Chen <owen.chen@mediatek.com> > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > add a variable to indicate this change and > backward-compatible. > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to > 1.5Ghz, add a variable to indicate platform-dependent. > > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > --- > drivers/clk/mediatek/clk-mtk.h | 2 ++ > drivers/clk/mediatek/clk-pll.c | 10 +++++++--- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index f83c2bbb677e..1882221fe994 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -215,7 +215,9 @@ struct mtk_pll_data { > const struct clk_ops *ops; > u32 rst_bar_mask; > unsigned long fmax; > + unsigned long fmin; Minor nit: I'd put fmin before fmax in the structure. > int pcwbits; > + int pcwibits; > uint32_t pcw_reg; > int pcw_shift; > const struct mtk_pll_div_table *div_table; > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..0ec2c62d9383 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c I'd add a note next to: #define INTEGER_BITS 7 to say that this is the default, and can be overridden with pcwibits. > @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > { > int pcwbits = pll->data->pcwbits; > int pcwfbits; > + int ibits; > u64 vco; > u8 c = 0; > > /* The fractional part of the PLL divider. */ > - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; > > vco = (u64)fin * pcw; > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > u32 freq, u32 fin) > { > - unsigned long fmin = 1000 * MHZ; > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; I'd put parentheses around (1000 * MHZ), to avoid the need to think about precedence... > const struct mtk_pll_div_table *div_table = pll->data->div_table; > u64 _pcw; > + int ibits; > u32 val; > > if (freq > pll->data->fmax) > @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > } > > /* _pcw = freq * postdiv / fin * 2^pcwfbits */ > - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); > do_div(_pcw, fin); > > *pcw = (u32)_pcw; > -- > 2.18.0 >
WARNING: multiple messages have this Message-ID (diff)
From: drinkcat@chromium.org (Nicolas Boichat) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data Date: Tue, 13 Nov 2018 08:18:52 -0800 [thread overview] Message-ID: <CANMq1KBjtyQFyJ-mZBndPDSfSDnD0K8izy39jp9zKE4xfiCiog@mail.gmail.com> (raw) In-Reply-To: <20181106064206.17535-4-weiyi.lu@mediatek.com> On Mon, Nov 5, 2018 at 10:43 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > From: Owen Chen <owen.chen@mediatek.com> > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > add a variable to indicate this change and > backward-compatible. > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to > 1.5Ghz, add a variable to indicate platform-dependent. > > Signed-off-by: Owen Chen <owen.chen@mediatek.com> > --- > drivers/clk/mediatek/clk-mtk.h | 2 ++ > drivers/clk/mediatek/clk-pll.c | 10 +++++++--- > 2 files changed, 9 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h > index f83c2bbb677e..1882221fe994 100644 > --- a/drivers/clk/mediatek/clk-mtk.h > +++ b/drivers/clk/mediatek/clk-mtk.h > @@ -215,7 +215,9 @@ struct mtk_pll_data { > const struct clk_ops *ops; > u32 rst_bar_mask; > unsigned long fmax; > + unsigned long fmin; Minor nit: I'd put fmin before fmax in the structure. > int pcwbits; > + int pcwibits; > uint32_t pcw_reg; > int pcw_shift; > const struct mtk_pll_div_table *div_table; > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c > index f54e4015b0b1..0ec2c62d9383 100644 > --- a/drivers/clk/mediatek/clk-pll.c > +++ b/drivers/clk/mediatek/clk-pll.c I'd add a note next to: #define INTEGER_BITS 7 to say that this is the default, and can be overridden with pcwibits. > @@ -69,11 +69,13 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, > { > int pcwbits = pll->data->pcwbits; > int pcwfbits; > + int ibits; > u64 vco; > u8 c = 0; > > /* The fractional part of the PLL divider. */ > - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0; > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0; > > vco = (u64)fin * pcw; > > @@ -138,9 +140,10 @@ static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw, > static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > u32 freq, u32 fin) > { > - unsigned long fmin = 1000 * MHZ; > + unsigned long fmin = pll->data->fmin ? pll->data->fmin : 1000 * MHZ; I'd put parentheses around (1000 * MHZ), to avoid the need to think about precedence... > const struct mtk_pll_div_table *div_table = pll->data->div_table; > u64 _pcw; > + int ibits; > u32 val; > > if (freq > pll->data->fmax) > @@ -164,7 +167,8 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, > } > > /* _pcw = freq * postdiv / fin * 2^pcwfbits */ > - _pcw = ((u64)freq << val) << (pll->data->pcwbits - INTEGER_BITS); > + ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; > + _pcw = ((u64)freq << val) << (pll->data->pcwbits - ibits); > do_div(_pcw, fin); > > *pcw = (u32)_pcw; > -- > 2.18.0 >
next prev parent reply other threads:[~2018-11-13 16:19 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-06 6:41 [PATCH v1 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` [PATCH v1 01/11] clk: mediatek: add new clkmux register API Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-13 16:00 ` Nicolas Boichat 2018-11-13 16:00 ` Nicolas Boichat 2018-11-20 6:34 ` Weiyi Lu 2018-11-20 6:34 ` Weiyi Lu 2018-11-20 6:34 ` Weiyi Lu 2018-11-06 6:41 ` [PATCH v1 02/11] clk: mediatek: add new member to mtk_pll_data Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-13 16:18 ` Nicolas Boichat [this message] 2018-11-13 16:18 ` Nicolas Boichat 2018-11-20 3:51 ` Weiyi Lu 2018-11-20 3:51 ` Weiyi Lu 2018-11-20 3:51 ` Weiyi Lu 2018-11-21 8:03 ` Stephen Boyd 2018-11-21 8:03 ` Stephen Boyd 2018-11-06 6:41 ` [PATCH v1 03/11] clk: mediatek: Disable tuner_en before change PLL rate Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` [PATCH v1 04/11] soc: mediatek: add new flow for mtcmos power Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-06 6:41 ` Weiyi Lu 2018-11-13 19:31 ` Nicolas Boichat 2018-11-13 19:31 ` Nicolas Boichat 2018-11-20 2:37 ` Weiyi Lu 2018-11-20 2:37 ` Weiyi Lu 2018-11-20 2:37 ` Weiyi Lu 2018-11-21 8:07 ` Stephen Boyd 2018-11-21 8:07 ` Stephen Boyd 2018-11-21 9:21 ` Weiyi Lu 2018-11-21 9:21 ` Weiyi Lu 2018-11-21 9:21 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 05/11] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 06/11] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 07/11] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 08/11] clk: mediatek: Add MT8183 clock support Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-14 6:25 ` Nicolas Boichat 2018-11-14 6:25 ` Nicolas Boichat 2018-11-19 4:14 ` Weiyi Lu 2018-11-19 4:14 ` Weiyi Lu 2018-11-19 4:14 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 09/11] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 10/11] dt-bindings: soc: Add MT8183 " Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` [PATCH v1 11/11] soc: mediatek: Add MT8183 scpsys support Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-06 6:42 ` Weiyi Lu 2018-11-13 19:35 ` Nicolas Boichat 2018-11-13 19:35 ` Nicolas Boichat 2018-11-19 3:59 ` Weiyi Lu 2018-11-19 3:59 ` Weiyi Lu 2018-11-19 3:59 ` Weiyi Lu
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