From: Atish Patra <atishp@atishpatra.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
Date: Mon, 28 Nov 2022 13:04:42 -0800 [thread overview]
Message-ID: <CAOnJCULajHen9us+AePGKarM1xSXp0wVBXyz7ySQyZz9YQvFaQ@mail.gmail.com> (raw)
In-Reply-To: <20221128161424.608889-5-apatel@ventanamicro.com>
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
> because the else-if ladder is quite big now.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 982a3f5e7130..68c86f632d37 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> @@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <atishp@atishpatra.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Andrew Jones <ajones@ventanamicro.com>,
Anup Patel <anup@brainfault.org>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg()
Date: Mon, 28 Nov 2022 13:04:42 -0800 [thread overview]
Message-ID: <CAOnJCULajHen9us+AePGKarM1xSXp0wVBXyz7ySQyZz9YQvFaQ@mail.gmail.com> (raw)
In-Reply-To: <20221128161424.608889-5-apatel@ventanamicro.com>
On Mon, Nov 28, 2022 at 8:14 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> We should use switch-case in kvm_riscv_vcpu_set/get_reg() functions
> because the else-if ladder is quite big now.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/kvm/vcpu.c | 36 ++++++++++++++++++++++--------------
> 1 file changed, 22 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 982a3f5e7130..68c86f632d37 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -544,22 +544,26 @@ static int kvm_riscv_vcpu_set_reg_isa_ext(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_set_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_set_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_set_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_set_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_set_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_set_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> @@ -567,22 +571,26 @@ static int kvm_riscv_vcpu_set_reg(struct kvm_vcpu *vcpu,
> static int kvm_riscv_vcpu_get_reg(struct kvm_vcpu *vcpu,
> const struct kvm_one_reg *reg)
> {
> - if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG)
> + switch (reg->id & KVM_REG_RISCV_TYPE_MASK) {
> + case KVM_REG_RISCV_CONFIG:
> return kvm_riscv_vcpu_get_reg_config(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE)
> + case KVM_REG_RISCV_CORE:
> return kvm_riscv_vcpu_get_reg_core(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR)
> + case KVM_REG_RISCV_CSR:
> return kvm_riscv_vcpu_get_reg_csr(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER)
> + case KVM_REG_RISCV_TIMER:
> return kvm_riscv_vcpu_get_reg_timer(vcpu, reg);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F)
> + case KVM_REG_RISCV_FP_F:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_F);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D)
> + case KVM_REG_RISCV_FP_D:
> return kvm_riscv_vcpu_get_reg_fp(vcpu, reg,
> KVM_REG_RISCV_FP_D);
> - else if ((reg->id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT)
> + case KVM_REG_RISCV_ISA_EXT:
> return kvm_riscv_vcpu_get_reg_isa_ext(vcpu, reg);
> + default:
> + break;
> + }
>
> return -EINVAL;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
next prev parent reply other threads:[~2022-11-28 21:05 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 16:14 [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 16:14 ` [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:03 ` Atish Patra
2022-11-28 21:03 ` Atish Patra
2022-11-28 16:14 ` [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 21:04 ` Atish Patra
2022-11-29 5:20 ` Andrew Jones
2022-11-29 5:20 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:04 ` Atish Patra [this message]
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:06 ` Atish Patra
2022-11-28 21:06 ` Atish Patra
2022-11-29 5:21 ` Andrew Jones
2022-11-29 5:21 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:07 ` Atish Patra
2022-11-28 21:07 ` Atish Patra
2022-12-09 4:33 ` Palmer Dabbelt
2022-12-09 4:33 ` Palmer Dabbelt
2022-11-29 5:21 ` Andrew Jones
2022-11-29 5:21 ` Andrew Jones
2022-12-02 17:53 ` Palmer Dabbelt
2022-12-02 17:53 ` Palmer Dabbelt
2022-11-28 16:14 ` [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:08 ` Atish Patra
2022-11-28 21:08 ` Atish Patra
2022-11-29 5:22 ` Andrew Jones
2022-11-29 5:22 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-28 21:09 ` Atish Patra
2022-11-28 21:09 ` Atish Patra
2022-11-29 5:46 ` Andrew Jones
2022-11-29 5:46 ` Andrew Jones
2022-12-03 12:18 ` Anup Patel
2022-12-03 12:18 ` Anup Patel
2022-11-28 16:14 ` [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions Anup Patel
2022-11-28 16:14 ` Anup Patel
2022-11-29 6:09 ` Andrew Jones
2022-11-29 6:09 ` Andrew Jones
2022-12-03 12:39 ` [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-12-03 12:39 ` Anup Patel
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