Re: [PATCH 9/9] drm/i915/bxt: Fix the DSI enable sequence

From: "Srinivas, Vidya" <vidya.srinivas@intel.com>
To: "Paauwe, Bob J" <bob.j.paauwe@intel.com>
Cc: "Nikula, Jani" <jani.nikula@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 9/9] drm/i915/bxt: Fix the DSI enable sequence
Date: Mon, 20 Feb 2017 09:43:48 +0000	[thread overview]
Message-ID: <F653A0A18852B74D88578FA2EB7094EA8B506235@BGSMSX108.gar.corp.intel.com> (raw)
In-Reply-To: <20170215110048.041450da@bpaauwe-desk.fm.intel.com>

> -----Original Message-----
> From: Paauwe, Bob J
> Sent: Thursday, February 16, 2017 12:31 AM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>
> Subject: Re: [Intel-gfx] [PATCH 9/9] drm/i915/bxt: Fix the DSI enable
> sequence
> 
> On Wed, 8 Feb 2017 16:20:58 +0530
> Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> 
> > From: Uma Shankar <uma.shankar@intel.com>
> >
> > Device ready to be done after panel power on and before sending the
> > OTP commands. Patch fixes the enable sequence as per this.
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> 
> I think this will need to be rebased now.
> The sequence looks like it will be slightly different from what I'm currently
> using for Broxton.  But in general it seems correct.
> 
> Bob

Thanks Bob. I will rebase the rest of the changes and re-submit.

Regards
Vidya
> 
> > ---
> >  drivers/gpu/drm/i915/intel_dsi.c           | 12 ++++++++++++
> >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  4 +---
> >  2 files changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> > b/drivers/gpu/drm/i915/intel_dsi.c
> > index 60ca0b9..ac02fd8 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi.c
> > @@ -568,6 +568,12 @@ static void intel_dsi_pre_enable(struct
> > intel_encoder *encoder,
> >
> >  	intel_dsi_prepare(encoder, pipe_config);
> >
> > +	if (IS_BROXTON(dev_priv)) {
> > +		/* Panel Enable */
> > +		drm_panel_power_on(intel_dsi->panel);
> > +		msleep(intel_dsi->panel_on_delay);
> > +	}
> > +
> >  	/* Panel Enable over CRC PMIC */
> >  	if (intel_dsi->gpio_panel)
> >  		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); @@ -
> 586,6
> > +592,12 @@ static void intel_dsi_pre_enable(struct intel_encoder
> *encoder,
> >  	/* put device in ready state */
> >  	intel_dsi_device_ready(encoder);
> >
> > +	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > +		/* Panel Enable */
> > +		drm_panel_power_on(intel_dsi->panel);
> > +		msleep(intel_dsi->panel_on_delay);
> > +	}
> > +
> >  	drm_panel_prepare(intel_dsi->panel);
> >
> >  	for_each_dsi_port(port, intel_dsi->ports) diff --git
> > a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 4279279..aa73d22 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -493,9 +493,6 @@ static void generic_exec_sequence(struct
> drm_panel
> > *panel, enum mipi_seq seq_id)
> >
> >  static int vbt_panel_prepare(struct drm_panel *panel)  {
> > -	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> > -	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> > -	generic_exec_sequence(panel, MIPI_SEQ_DEASSERT_RESET);
> >  	generic_exec_sequence(panel, MIPI_SEQ_INIT_OTP);
> >
> >  	return 0;
> > @@ -550,6 +547,7 @@ static int vbt_panel_get_modes(struct drm_panel
> > *panel)  static int vbt_panel_power_on(struct drm_panel *panel)  {
> >  	generic_exec_sequence(panel, MIPI_SEQ_POWER_ON);
> > +	generic_exec_sequence(panel, MIPI_SEQ_ASSERT_RESET);
> >  	return 0;
> >  }
> >
> 
> 
> 
> --
> --
> Bob Paauwe
> Bob.J.Paauwe@intel.com
> IOTG / PED Software Organization
> Intel Corp.  Folsom, CA
> (916) 356-6193

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