From: James Hogan <james.hogan@imgtec.com> To: <linux-mips@linux-mips.org>, <kvm@vger.kernel.org> Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Jonathan Corbet" <corbet@lwn.net>, linux-doc@vger.kernel.org Subject: [PATCH 26/32] KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig Date: Thu, 2 Mar 2017 09:36:53 +0000 [thread overview] Message-ID: <ab46aa284d5d271b0a6dda98a1153cdcb533b2a6.1488447004.git-series.james.hogan@imgtec.com> (raw) In-Reply-To: <cover.5cfb5298ebc2f5308f4f56aaac7fa31c39a8ab58.1488447004.git-series.james.hogan@imgtec.com> Add support for VZ guest CP0_ContextConfig and CP0_XContextConfig (MIPS64 only) registers, as found on P5600 and P6600 cores. These guest registers need initialising, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/virtual/kvm/api.txt | 2 +- arch/mips/include/asm/kvm_host.h | 4 ++- arch/mips/kvm/vz.c | 62 ++++++++++++++++++++++++++++++-- 3 files changed, 66 insertions(+), 2 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index a654a2133981..04e5c4dae523 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2073,7 +2073,9 @@ registers, find a list below: MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64 MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64 MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64 + MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32 MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64 + MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64 MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32 MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN | 32 MIPS | KVM_REG_MIPS_CP0_WIRED | 32 diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 53c92f34475f..d3b377dbed36 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -34,7 +34,9 @@ #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) +#define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1) #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) +#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3) #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) @@ -668,7 +670,9 @@ __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0) __BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0) __BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0) __BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0) +__BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1) __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2) +__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3) __BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0) __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 5fd14d35c146..b1a7485196a6 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -131,7 +131,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu) * Config: M, [MT] * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP * Config2: M - * Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP, CTXTC, ITL, LPA, VEIC, + * Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC, * VInt, SP, CDMM, MT, SM, TL] * Config4: M, [VTLBSizeExt, MMUSizeExt] * Config5: [MRP] @@ -161,7 +161,7 @@ static inline unsigned int kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu) static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu) { unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M | - MIPS_CONF3_ULRI; + MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC; /* Permit MSA to be present if MSA is supported */ if (kvm_mips_guest_can_have_msa(&vcpu->arch)) @@ -1204,6 +1204,13 @@ static u64 kvm_vz_get_one_regs[] = { KVM_REG_MIPS_COUNT_HZ, }; +static u64 kvm_vz_get_one_regs_contextconfig[] = { + KVM_REG_MIPS_CP0_CONTEXTCONFIG, +#ifdef CONFIG_64BIT + KVM_REG_MIPS_CP0_XCONTEXTCONFIG, +#endif +}; + static u64 kvm_vz_get_one_regs_kscratch[] = { KVM_REG_MIPS_CP0_KSCRATCH1, KVM_REG_MIPS_CP0_KSCRATCH2, @@ -1224,6 +1231,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu) ++ret; if (cpu_guest_has_badinstrp) ++ret; + if (cpu_guest_has_contextconfig) + ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask); return ret; @@ -1257,6 +1266,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) return -EFAULT; ++indices; } + if (cpu_guest_has_contextconfig) { + if (copy_to_user(indices, kvm_vz_get_one_regs_contextconfig, + sizeof(kvm_vz_get_one_regs_contextconfig))) + return -EFAULT; + indices += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); + } for (i = 0; i < 6; ++i) { if (!cpu_guest_has_kscr(i + 2)) continue; @@ -1322,11 +1337,23 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, case KVM_REG_MIPS_CP0_CONTEXT: *v = (long)read_gc0_context(); break; + case KVM_REG_MIPS_CP0_CONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + *v = read_gc0_contextconfig(); + break; case KVM_REG_MIPS_CP0_USERLOCAL: if (!cpu_guest_has_userlocal) return -EINVAL; *v = read_gc0_userlocal(); break; +#ifdef CONFIG_64BIT + case KVM_REG_MIPS_CP0_XCONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + *v = read_gc0_xcontextconfig(); + break; +#endif case KVM_REG_MIPS_CP0_PAGEMASK: *v = (long)read_gc0_pagemask(); break; @@ -1477,11 +1504,23 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, case KVM_REG_MIPS_CP0_CONTEXT: write_gc0_context(v); break; + case KVM_REG_MIPS_CP0_CONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + write_gc0_contextconfig(v); + break; case KVM_REG_MIPS_CP0_USERLOCAL: if (!cpu_guest_has_userlocal) return -EINVAL; write_gc0_userlocal(v); break; +#ifdef CONFIG_64BIT + case KVM_REG_MIPS_CP0_XCONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + write_gc0_xcontextconfig(v); + break; +#endif case KVM_REG_MIPS_CP0_PAGEMASK: write_gc0_pagemask(v); break; @@ -1873,8 +1912,12 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_restore_gc0_entrylo0(cop0); kvm_restore_gc0_entrylo1(cop0); kvm_restore_gc0_context(cop0); + if (cpu_guest_has_contextconfig) + kvm_restore_gc0_contextconfig(cop0); #ifdef CONFIG_64BIT kvm_restore_gc0_xcontext(cop0); + if (cpu_guest_has_contextconfig) + kvm_restore_gc0_xcontextconfig(cop0); #endif kvm_restore_gc0_pagemask(cop0); kvm_restore_gc0_pagegrain(cop0); @@ -1932,8 +1975,12 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu) kvm_save_gc0_entrylo0(cop0); kvm_save_gc0_entrylo1(cop0); kvm_save_gc0_context(cop0); + if (cpu_guest_has_contextconfig) + kvm_save_gc0_contextconfig(cop0); #ifdef CONFIG_64BIT kvm_save_gc0_xcontext(cop0); + if (cpu_guest_has_contextconfig) + kvm_save_gc0_xcontextconfig(cop0); #endif kvm_save_gc0_pagemask(cop0); kvm_save_gc0_pagegrain(cop0); @@ -2297,6 +2344,17 @@ static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu) kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP); } + if (cpu_guest_has_contextconfig) { + /* ContextConfig */ + kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0); +#ifdef CONFIG_64BIT + /* XContextConfig */ + /* bits SEGBITS-13+3:4 set */ + kvm_write_sw_gc0_xcontextconfig(cop0, + ((1ull << (cpu_vmbits - 13)) - 1) << 4); +#endif + } + /* start with no pending virtual guest interrupts */ if (cpu_has_guestctl2) cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0; -- git-series 0.8.10
WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com> To: linux-mips@linux-mips.org, kvm@vger.kernel.org Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Jonathan Corbet" <corbet@lwn.net>, linux-doc@vger.kernel.org Subject: [PATCH 26/32] KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig Date: Thu, 2 Mar 2017 09:36:53 +0000 [thread overview] Message-ID: <ab46aa284d5d271b0a6dda98a1153cdcb533b2a6.1488447004.git-series.james.hogan@imgtec.com> (raw) Message-ID: <20170302093653.2DPqunFA6UQUsBzXywZKyttf71wujaZU83xe0ire-1M@z> (raw) In-Reply-To: <cover.5cfb5298ebc2f5308f4f56aaac7fa31c39a8ab58.1488447004.git-series.james.hogan@imgtec.com> Add support for VZ guest CP0_ContextConfig and CP0_XContextConfig (MIPS64 only) registers, as found on P5600 and P6600 cores. These guest registers need initialising, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/virtual/kvm/api.txt | 2 +- arch/mips/include/asm/kvm_host.h | 4 ++- arch/mips/kvm/vz.c | 62 ++++++++++++++++++++++++++++++-- 3 files changed, 66 insertions(+), 2 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index a654a2133981..04e5c4dae523 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2073,7 +2073,9 @@ registers, find a list below: MIPS | KVM_REG_MIPS_CP0_ENTRYLO0 | 64 MIPS | KVM_REG_MIPS_CP0_ENTRYLO1 | 64 MIPS | KVM_REG_MIPS_CP0_CONTEXT | 64 + MIPS | KVM_REG_MIPS_CP0_CONTEXTCONFIG| 32 MIPS | KVM_REG_MIPS_CP0_USERLOCAL | 64 + MIPS | KVM_REG_MIPS_CP0_XCONTEXTCONFIG| 64 MIPS | KVM_REG_MIPS_CP0_PAGEMASK | 32 MIPS | KVM_REG_MIPS_CP0_PAGEGRAIN | 32 MIPS | KVM_REG_MIPS_CP0_WIRED | 32 diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index 53c92f34475f..d3b377dbed36 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -34,7 +34,9 @@ #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0) #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0) #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) +#define KVM_REG_MIPS_CP0_CONTEXTCONFIG MIPS_CP0_32(4, 1) #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) +#define KVM_REG_MIPS_CP0_XCONTEXTCONFIG MIPS_CP0_64(4, 3) #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) @@ -668,7 +670,9 @@ __BUILD_KVM_RW_HW(index, 32, MIPS_CP0_TLB_INDEX, 0) __BUILD_KVM_RW_HW(entrylo0, l, MIPS_CP0_TLB_LO0, 0) __BUILD_KVM_RW_HW(entrylo1, l, MIPS_CP0_TLB_LO1, 0) __BUILD_KVM_RW_HW(context, l, MIPS_CP0_TLB_CONTEXT, 0) +__BUILD_KVM_RW_HW(contextconfig, 32, MIPS_CP0_TLB_CONTEXT, 1) __BUILD_KVM_RW_HW(userlocal, l, MIPS_CP0_TLB_CONTEXT, 2) +__BUILD_KVM_RW_HW(xcontextconfig, l, MIPS_CP0_TLB_CONTEXT, 3) __BUILD_KVM_RW_HW(pagemask, l, MIPS_CP0_TLB_PG_MASK, 0) __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 5fd14d35c146..b1a7485196a6 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -131,7 +131,7 @@ static inline unsigned int kvm_vz_config5_guest_wrmask(struct kvm_vcpu *vcpu) * Config: M, [MT] * Config1: M, [MMUSize-1, C2, MD, PC, WR, CA], FP * Config2: M - * Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP, CTXTC, ITL, LPA, VEIC, + * Config3: M, MSAP, [BPG], ULRI, [DSP2P, DSPP], CTXTC, [ITL, LPA, VEIC, * VInt, SP, CDMM, MT, SM, TL] * Config4: M, [VTLBSizeExt, MMUSizeExt] * Config5: [MRP] @@ -161,7 +161,7 @@ static inline unsigned int kvm_vz_config2_user_wrmask(struct kvm_vcpu *vcpu) static inline unsigned int kvm_vz_config3_user_wrmask(struct kvm_vcpu *vcpu) { unsigned int mask = kvm_vz_config3_guest_wrmask(vcpu) | MIPS_CONF_M | - MIPS_CONF3_ULRI; + MIPS_CONF3_ULRI | MIPS_CONF3_CTXTC; /* Permit MSA to be present if MSA is supported */ if (kvm_mips_guest_can_have_msa(&vcpu->arch)) @@ -1204,6 +1204,13 @@ static u64 kvm_vz_get_one_regs[] = { KVM_REG_MIPS_COUNT_HZ, }; +static u64 kvm_vz_get_one_regs_contextconfig[] = { + KVM_REG_MIPS_CP0_CONTEXTCONFIG, +#ifdef CONFIG_64BIT + KVM_REG_MIPS_CP0_XCONTEXTCONFIG, +#endif +}; + static u64 kvm_vz_get_one_regs_kscratch[] = { KVM_REG_MIPS_CP0_KSCRATCH1, KVM_REG_MIPS_CP0_KSCRATCH2, @@ -1224,6 +1231,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu) ++ret; if (cpu_guest_has_badinstrp) ++ret; + if (cpu_guest_has_contextconfig) + ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask); return ret; @@ -1257,6 +1266,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) return -EFAULT; ++indices; } + if (cpu_guest_has_contextconfig) { + if (copy_to_user(indices, kvm_vz_get_one_regs_contextconfig, + sizeof(kvm_vz_get_one_regs_contextconfig))) + return -EFAULT; + indices += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); + } for (i = 0; i < 6; ++i) { if (!cpu_guest_has_kscr(i + 2)) continue; @@ -1322,11 +1337,23 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, case KVM_REG_MIPS_CP0_CONTEXT: *v = (long)read_gc0_context(); break; + case KVM_REG_MIPS_CP0_CONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + *v = read_gc0_contextconfig(); + break; case KVM_REG_MIPS_CP0_USERLOCAL: if (!cpu_guest_has_userlocal) return -EINVAL; *v = read_gc0_userlocal(); break; +#ifdef CONFIG_64BIT + case KVM_REG_MIPS_CP0_XCONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + *v = read_gc0_xcontextconfig(); + break; +#endif case KVM_REG_MIPS_CP0_PAGEMASK: *v = (long)read_gc0_pagemask(); break; @@ -1477,11 +1504,23 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, case KVM_REG_MIPS_CP0_CONTEXT: write_gc0_context(v); break; + case KVM_REG_MIPS_CP0_CONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + write_gc0_contextconfig(v); + break; case KVM_REG_MIPS_CP0_USERLOCAL: if (!cpu_guest_has_userlocal) return -EINVAL; write_gc0_userlocal(v); break; +#ifdef CONFIG_64BIT + case KVM_REG_MIPS_CP0_XCONTEXTCONFIG: + if (!cpu_guest_has_contextconfig) + return -EINVAL; + write_gc0_xcontextconfig(v); + break; +#endif case KVM_REG_MIPS_CP0_PAGEMASK: write_gc0_pagemask(v); break; @@ -1873,8 +1912,12 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_restore_gc0_entrylo0(cop0); kvm_restore_gc0_entrylo1(cop0); kvm_restore_gc0_context(cop0); + if (cpu_guest_has_contextconfig) + kvm_restore_gc0_contextconfig(cop0); #ifdef CONFIG_64BIT kvm_restore_gc0_xcontext(cop0); + if (cpu_guest_has_contextconfig) + kvm_restore_gc0_xcontextconfig(cop0); #endif kvm_restore_gc0_pagemask(cop0); kvm_restore_gc0_pagegrain(cop0); @@ -1932,8 +1975,12 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu) kvm_save_gc0_entrylo0(cop0); kvm_save_gc0_entrylo1(cop0); kvm_save_gc0_context(cop0); + if (cpu_guest_has_contextconfig) + kvm_save_gc0_contextconfig(cop0); #ifdef CONFIG_64BIT kvm_save_gc0_xcontext(cop0); + if (cpu_guest_has_contextconfig) + kvm_save_gc0_xcontextconfig(cop0); #endif kvm_save_gc0_pagemask(cop0); kvm_save_gc0_pagegrain(cop0); @@ -2297,6 +2344,17 @@ static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu) kvm_clear_sw_gc0_config5(cop0, MIPS_CONF5_MRP); } + if (cpu_guest_has_contextconfig) { + /* ContextConfig */ + kvm_write_sw_gc0_contextconfig(cop0, 0x007ffff0); +#ifdef CONFIG_64BIT + /* XContextConfig */ + /* bits SEGBITS-13+3:4 set */ + kvm_write_sw_gc0_xcontextconfig(cop0, + ((1ull << (cpu_vmbits - 13)) - 1) << 4); +#endif + } + /* start with no pending virtual guest interrupts */ if (cpu_has_guestctl2) cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0; -- git-series 0.8.10
next prev parent reply other threads:[~2017-03-02 9:49 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-02 9:36 [PATCH 0/32] KVM: MIPS: Add VZ support James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 1/32] MIPS: Add defs & probing of UFR James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 2/32] MIPS: Separate MAAR V bit into VL and VH for XPA James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 3/32] MIPS: Probe guest CP0_UserLocal James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 4/32] MIPS: Probe guest MVH James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 5/32] MIPS: Add some missing guest CP0 accessors & defs James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 6/32] MIPS: asm/tlb.h: Add UNIQUE_GUEST_ENTRYHI() macro James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 7/32] KVM: MIPS/Emulate: De-duplicate MMIO emulation James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 8/32] KVM: MIPS/Emulate: Implement 64-bit " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 9/32] KVM: MIPS: Update kvm_lose_fpu() for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 10/32] KVM: MIPS: Extend counters & events for VZ GExcCodes James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 11/32] KVM: MIPS: Add VZ capability James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 10:59 ` Paolo Bonzini 2017-03-02 11:39 ` James Hogan 2017-03-02 12:20 ` Paolo Bonzini 2017-03-02 22:34 ` James Hogan 2017-03-03 12:37 ` James Hogan 2017-03-03 12:41 ` Paolo Bonzini 2017-03-02 9:36 ` [PATCH 12/32] KVM: MIPS: Add 64BIT capability James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 13/32] KVM: MIPS: Init timer frequency from callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 14/32] KVM: MIPS: Add callback to check extension James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 15/32] KVM: MIPS: Add hardware_{enable,disable} callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 16/32] KVM: MIPS: Add guest exit exception callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 17/32] KVM: MIPS: Abstract guest CP0 register access for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 18/32] KVM: MIPS/Entry: Update entry code to support VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 19/32] KVM: MIPS/TLB: Add VZ TLB management James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 20/32] KVM: MIPS/Emulate: Update CP0_Compare emulation for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 21/32] KVM: MIPS/Emulate: Drop CACHE " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 22/32] KVM: MIPS: Update exit handler " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 23/32] KVM: MIPS: Implement VZ support James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 24/32] KVM: MIPS: Add VZ support to build system James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 25/32] KVM: MIPS/VZ: Support guest CP0_BadInstr[P] James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` James Hogan [this message] 2017-03-02 9:36 ` [PATCH 26/32] KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig James Hogan 2017-03-02 9:36 ` [PATCH 27/32] KVM: MIPS/VZ: Support guest segmentation control James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 28/32] KVM: MIPS/VZ: Support guest hardware page table walker James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 29/32] KVM: MIPS/VZ: Support guest load-linked bit James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 30/32] KVM: MIPS/VZ: Emulate MAARs when necessary James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 31/32] KVM: MIPS/VZ: Support hardware guest timer James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 32/32] KVM: MIPS/VZ: Trace guest mode changes James Hogan 2017-03-02 9:36 ` James Hogan
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