From: James Hogan <james.hogan@imgtec.com> To: <linux-mips@linux-mips.org>, <kvm@vger.kernel.org> Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Jonathan Corbet" <corbet@lwn.net>, linux-doc@vger.kernel.org Subject: [PATCH 28/32] KVM: MIPS/VZ: Support guest hardware page table walker Date: Thu, 2 Mar 2017 09:36:55 +0000 [thread overview] Message-ID: <effaa15b43a554d06534c38e0f6b9bcde64b3ef6.1488447004.git-series.james.hogan@imgtec.com> (raw) In-Reply-To: <cover.5cfb5298ebc2f5308f4f56aaac7fa31c39a8ab58.1488447004.git-series.james.hogan@imgtec.com> Add support for VZ guest CP0_PWBase, CP0_PWField, CP0_PWSize, and CP0_PWCtl registers for controlling the guest hardware page table walker (HTW) present on P5600 and P6600 cores. These guest registers need initialising on R6, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/virtual/kvm/api.txt | 4 ++- arch/mips/include/asm/kvm_host.h | 8 +++- arch/mips/kvm/vz.c | 80 ++++++++++++++++++++++++++++++++- 3 files changed, 92 insertions(+), 0 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 1116becf8d6f..a0430186dbd4 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2081,7 +2081,11 @@ registers, find a list below: MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64 MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64 MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64 + MIPS | KVM_REG_MIPS_CP0_PWBASE | 64 + MIPS | KVM_REG_MIPS_CP0_PWFIELD | 64 + MIPS | KVM_REG_MIPS_CP0_PWSIZE | 64 MIPS | KVM_REG_MIPS_CP0_WIRED | 32 + MIPS | KVM_REG_MIPS_CP0_PWCTL | 32 MIPS | KVM_REG_MIPS_CP0_HWRENA | 32 MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64 MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32 diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index f986907a7707..6b7d131565cd 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -42,7 +42,11 @@ #define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2) #define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3) #define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4) +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) #define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1) @@ -681,7 +685,11 @@ __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) __BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2) __BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3) __BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4) +__BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5) +__BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6) +__BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7) __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) +__BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6) __BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0) __BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0) __BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 373b954a9fd3..c7d15aa69259 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -1391,6 +1391,13 @@ static u64 kvm_vz_get_one_regs_segments[] = { KVM_REG_MIPS_CP0_SEGCTL2, }; +static u64 kvm_vz_get_one_regs_htw[] = { + KVM_REG_MIPS_CP0_PWBASE, + KVM_REG_MIPS_CP0_PWFIELD, + KVM_REG_MIPS_CP0_PWSIZE, + KVM_REG_MIPS_CP0_PWCTL, +}; + static u64 kvm_vz_get_one_regs_kscratch[] = { KVM_REG_MIPS_CP0_KSCRATCH1, KVM_REG_MIPS_CP0_KSCRATCH2, @@ -1415,6 +1422,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu) ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); if (cpu_guest_has_segments) ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments); + if (cpu_guest_has_htw) + ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw); ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask); return ret; @@ -1460,6 +1469,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) return -EFAULT; indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments); } + if (cpu_guest_has_htw) { + if (copy_to_user(indices, kvm_vz_get_one_regs_htw, + sizeof(kvm_vz_get_one_regs_htw))) + return -EFAULT; + indices += ARRAY_SIZE(kvm_vz_get_one_regs_htw); + } for (i = 0; i < 6; ++i) { if (!cpu_guest_has_kscr(i + 2)) continue; @@ -1563,9 +1578,29 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, return -EINVAL; *v = read_gc0_segctl2(); break; + case KVM_REG_MIPS_CP0_PWBASE: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwbase(); + break; + case KVM_REG_MIPS_CP0_PWFIELD: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwfield(); + break; + case KVM_REG_MIPS_CP0_PWSIZE: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwsize(); + break; case KVM_REG_MIPS_CP0_WIRED: *v = (long)read_gc0_wired(); break; + case KVM_REG_MIPS_CP0_PWCTL: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwctl(); + break; case KVM_REG_MIPS_CP0_HWRENA: *v = (long)read_gc0_hwrena(); break; @@ -1745,9 +1780,29 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, return -EINVAL; write_gc0_segctl2(v); break; + case KVM_REG_MIPS_CP0_PWBASE: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwbase(v); + break; + case KVM_REG_MIPS_CP0_PWFIELD: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwfield(v); + break; + case KVM_REG_MIPS_CP0_PWSIZE: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwsize(v); + break; case KVM_REG_MIPS_CP0_WIRED: change_gc0_wired(MIPSR6_WIRED_WIRED, v); break; + case KVM_REG_MIPS_CP0_PWCTL: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwctl(v); + break; case KVM_REG_MIPS_CP0_HWRENA: write_gc0_hwrena(v); break; @@ -2178,6 +2233,14 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_restore_gc0_segctl2(cop0); } + /* restore HTW registers */ + if (cpu_guest_has_htw) { + kvm_restore_gc0_pwbase(cop0); + kvm_restore_gc0_pwfield(cop0); + kvm_restore_gc0_pwsize(cop0); + kvm_restore_gc0_pwctl(cop0); + } + /* restore Root.GuestCtl2 from unused Guest guestctl2 register */ if (cpu_has_guestctl2) write_c0_guestctl2( @@ -2267,6 +2330,15 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu) kvm_save_gc0_segctl2(cop0); } + /* save HTW registers if enabled in guest */ + if (cpu_guest_has_htw && + kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) { + kvm_save_gc0_pwbase(cop0); + kvm_save_gc0_pwfield(cop0); + kvm_save_gc0_pwsize(cop0); + kvm_save_gc0_pwctl(cop0); + } + kvm_vz_save_timer(vcpu); /* save Root.GuestCtl2 in unused Guest guestctl2 register */ @@ -2595,6 +2667,14 @@ static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu) kvm_write_sw_gc0_segctl2(cop0, 0x00380438); } + /* reset HTW registers */ + if (cpu_guest_has_htw && cpu_has_mips_r6) { + /* PWField */ + kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302); + /* PWSize */ + kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT); + } + /* start with no pending virtual guest interrupts */ if (cpu_has_guestctl2) cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0; -- git-series 0.8.10
WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com> To: linux-mips@linux-mips.org, kvm@vger.kernel.org Cc: "James Hogan" <james.hogan@imgtec.com>, "Paolo Bonzini" <pbonzini@redhat.com>, "Radim Krčmář" <rkrcmar@redhat.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Jonathan Corbet" <corbet@lwn.net>, linux-doc@vger.kernel.org Subject: [PATCH 28/32] KVM: MIPS/VZ: Support guest hardware page table walker Date: Thu, 2 Mar 2017 09:36:55 +0000 [thread overview] Message-ID: <effaa15b43a554d06534c38e0f6b9bcde64b3ef6.1488447004.git-series.james.hogan@imgtec.com> (raw) Message-ID: <20170302093655.7428Qp_vXNAdZ6zcJU8GKVT7kGL0t55eNdK7PLlYorE@z> (raw) In-Reply-To: <cover.5cfb5298ebc2f5308f4f56aaac7fa31c39a8ab58.1488447004.git-series.james.hogan@imgtec.com> Add support for VZ guest CP0_PWBase, CP0_PWField, CP0_PWSize, and CP0_PWCtl registers for controlling the guest hardware page table walker (HTW) present on P5600 and P6600 cores. These guest registers need initialising on R6, context switching, and exposing via the KVM ioctl API when they are present. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonathan Corbet <corbet@lwn.net> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Cc: linux-doc@vger.kernel.org --- Documentation/virtual/kvm/api.txt | 4 ++- arch/mips/include/asm/kvm_host.h | 8 +++- arch/mips/kvm/vz.c | 80 ++++++++++++++++++++++++++++++++- 3 files changed, 92 insertions(+), 0 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 1116becf8d6f..a0430186dbd4 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2081,7 +2081,11 @@ registers, find a list below: MIPS | KVM_REG_MIPS_CP0_SEGCTL0 | 64 MIPS | KVM_REG_MIPS_CP0_SEGCTL1 | 64 MIPS | KVM_REG_MIPS_CP0_SEGCTL2 | 64 + MIPS | KVM_REG_MIPS_CP0_PWBASE | 64 + MIPS | KVM_REG_MIPS_CP0_PWFIELD | 64 + MIPS | KVM_REG_MIPS_CP0_PWSIZE | 64 MIPS | KVM_REG_MIPS_CP0_WIRED | 32 + MIPS | KVM_REG_MIPS_CP0_PWCTL | 32 MIPS | KVM_REG_MIPS_CP0_HWRENA | 32 MIPS | KVM_REG_MIPS_CP0_BADVADDR | 64 MIPS | KVM_REG_MIPS_CP0_BADINSTR | 32 diff --git a/arch/mips/include/asm/kvm_host.h b/arch/mips/include/asm/kvm_host.h index f986907a7707..6b7d131565cd 100644 --- a/arch/mips/include/asm/kvm_host.h +++ b/arch/mips/include/asm/kvm_host.h @@ -42,7 +42,11 @@ #define KVM_REG_MIPS_CP0_SEGCTL0 MIPS_CP0_64(5, 2) #define KVM_REG_MIPS_CP0_SEGCTL1 MIPS_CP0_64(5, 3) #define KVM_REG_MIPS_CP0_SEGCTL2 MIPS_CP0_64(5, 4) +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) #define KVM_REG_MIPS_CP0_BADINSTR MIPS_CP0_32(8, 1) @@ -681,7 +685,11 @@ __BUILD_KVM_RW_HW(pagegrain, 32, MIPS_CP0_TLB_PG_MASK, 1) __BUILD_KVM_RW_HW(segctl0, l, MIPS_CP0_TLB_PG_MASK, 2) __BUILD_KVM_RW_HW(segctl1, l, MIPS_CP0_TLB_PG_MASK, 3) __BUILD_KVM_RW_HW(segctl2, l, MIPS_CP0_TLB_PG_MASK, 4) +__BUILD_KVM_RW_HW(pwbase, l, MIPS_CP0_TLB_PG_MASK, 5) +__BUILD_KVM_RW_HW(pwfield, l, MIPS_CP0_TLB_PG_MASK, 6) +__BUILD_KVM_RW_HW(pwsize, l, MIPS_CP0_TLB_PG_MASK, 7) __BUILD_KVM_RW_HW(wired, 32, MIPS_CP0_TLB_WIRED, 0) +__BUILD_KVM_RW_HW(pwctl, 32, MIPS_CP0_TLB_WIRED, 6) __BUILD_KVM_RW_HW(hwrena, 32, MIPS_CP0_HWRENA, 0) __BUILD_KVM_RW_HW(badvaddr, l, MIPS_CP0_BAD_VADDR, 0) __BUILD_KVM_RW_HW(badinstr, 32, MIPS_CP0_BAD_VADDR, 1) diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 373b954a9fd3..c7d15aa69259 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -1391,6 +1391,13 @@ static u64 kvm_vz_get_one_regs_segments[] = { KVM_REG_MIPS_CP0_SEGCTL2, }; +static u64 kvm_vz_get_one_regs_htw[] = { + KVM_REG_MIPS_CP0_PWBASE, + KVM_REG_MIPS_CP0_PWFIELD, + KVM_REG_MIPS_CP0_PWSIZE, + KVM_REG_MIPS_CP0_PWCTL, +}; + static u64 kvm_vz_get_one_regs_kscratch[] = { KVM_REG_MIPS_CP0_KSCRATCH1, KVM_REG_MIPS_CP0_KSCRATCH2, @@ -1415,6 +1422,8 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu) ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig); if (cpu_guest_has_segments) ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments); + if (cpu_guest_has_htw) + ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw); ret += __arch_hweight8(cpu_data[0].guest.kscratch_mask); return ret; @@ -1460,6 +1469,12 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices) return -EFAULT; indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments); } + if (cpu_guest_has_htw) { + if (copy_to_user(indices, kvm_vz_get_one_regs_htw, + sizeof(kvm_vz_get_one_regs_htw))) + return -EFAULT; + indices += ARRAY_SIZE(kvm_vz_get_one_regs_htw); + } for (i = 0; i < 6; ++i) { if (!cpu_guest_has_kscr(i + 2)) continue; @@ -1563,9 +1578,29 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu, return -EINVAL; *v = read_gc0_segctl2(); break; + case KVM_REG_MIPS_CP0_PWBASE: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwbase(); + break; + case KVM_REG_MIPS_CP0_PWFIELD: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwfield(); + break; + case KVM_REG_MIPS_CP0_PWSIZE: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwsize(); + break; case KVM_REG_MIPS_CP0_WIRED: *v = (long)read_gc0_wired(); break; + case KVM_REG_MIPS_CP0_PWCTL: + if (!cpu_guest_has_htw) + return -EINVAL; + *v = read_gc0_pwctl(); + break; case KVM_REG_MIPS_CP0_HWRENA: *v = (long)read_gc0_hwrena(); break; @@ -1745,9 +1780,29 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu, return -EINVAL; write_gc0_segctl2(v); break; + case KVM_REG_MIPS_CP0_PWBASE: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwbase(v); + break; + case KVM_REG_MIPS_CP0_PWFIELD: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwfield(v); + break; + case KVM_REG_MIPS_CP0_PWSIZE: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwsize(v); + break; case KVM_REG_MIPS_CP0_WIRED: change_gc0_wired(MIPSR6_WIRED_WIRED, v); break; + case KVM_REG_MIPS_CP0_PWCTL: + if (!cpu_guest_has_htw) + return -EINVAL; + write_gc0_pwctl(v); + break; case KVM_REG_MIPS_CP0_HWRENA: write_gc0_hwrena(v); break; @@ -2178,6 +2233,14 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_restore_gc0_segctl2(cop0); } + /* restore HTW registers */ + if (cpu_guest_has_htw) { + kvm_restore_gc0_pwbase(cop0); + kvm_restore_gc0_pwfield(cop0); + kvm_restore_gc0_pwsize(cop0); + kvm_restore_gc0_pwctl(cop0); + } + /* restore Root.GuestCtl2 from unused Guest guestctl2 register */ if (cpu_has_guestctl2) write_c0_guestctl2( @@ -2267,6 +2330,15 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu) kvm_save_gc0_segctl2(cop0); } + /* save HTW registers if enabled in guest */ + if (cpu_guest_has_htw && + kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) { + kvm_save_gc0_pwbase(cop0); + kvm_save_gc0_pwfield(cop0); + kvm_save_gc0_pwsize(cop0); + kvm_save_gc0_pwctl(cop0); + } + kvm_vz_save_timer(vcpu); /* save Root.GuestCtl2 in unused Guest guestctl2 register */ @@ -2595,6 +2667,14 @@ static int kvm_vz_vcpu_setup(struct kvm_vcpu *vcpu) kvm_write_sw_gc0_segctl2(cop0, 0x00380438); } + /* reset HTW registers */ + if (cpu_guest_has_htw && cpu_has_mips_r6) { + /* PWField */ + kvm_write_sw_gc0_pwfield(cop0, 0x0c30c302); + /* PWSize */ + kvm_write_sw_gc0_pwsize(cop0, 1 << MIPS_PWSIZE_PTW_SHIFT); + } + /* start with no pending virtual guest interrupts */ if (cpu_has_guestctl2) cop0->reg[MIPS_CP0_GUESTCTL2][MIPS_CP0_GUESTCTL2_SEL] = 0; -- git-series 0.8.10
next prev parent reply other threads:[~2017-03-02 9:50 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-03-02 9:36 [PATCH 0/32] KVM: MIPS: Add VZ support James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 1/32] MIPS: Add defs & probing of UFR James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 2/32] MIPS: Separate MAAR V bit into VL and VH for XPA James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 3/32] MIPS: Probe guest CP0_UserLocal James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 4/32] MIPS: Probe guest MVH James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 5/32] MIPS: Add some missing guest CP0 accessors & defs James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 6/32] MIPS: asm/tlb.h: Add UNIQUE_GUEST_ENTRYHI() macro James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 7/32] KVM: MIPS/Emulate: De-duplicate MMIO emulation James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 8/32] KVM: MIPS/Emulate: Implement 64-bit " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 9/32] KVM: MIPS: Update kvm_lose_fpu() for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 10/32] KVM: MIPS: Extend counters & events for VZ GExcCodes James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 11/32] KVM: MIPS: Add VZ capability James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 10:59 ` Paolo Bonzini 2017-03-02 11:39 ` James Hogan 2017-03-02 12:20 ` Paolo Bonzini 2017-03-02 22:34 ` James Hogan 2017-03-03 12:37 ` James Hogan 2017-03-03 12:41 ` Paolo Bonzini 2017-03-02 9:36 ` [PATCH 12/32] KVM: MIPS: Add 64BIT capability James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 13/32] KVM: MIPS: Init timer frequency from callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 14/32] KVM: MIPS: Add callback to check extension James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 15/32] KVM: MIPS: Add hardware_{enable,disable} callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 16/32] KVM: MIPS: Add guest exit exception callback James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 17/32] KVM: MIPS: Abstract guest CP0 register access for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 18/32] KVM: MIPS/Entry: Update entry code to support VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 19/32] KVM: MIPS/TLB: Add VZ TLB management James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 20/32] KVM: MIPS/Emulate: Update CP0_Compare emulation for VZ James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 21/32] KVM: MIPS/Emulate: Drop CACHE " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 22/32] KVM: MIPS: Update exit handler " James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 23/32] KVM: MIPS: Implement VZ support James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 24/32] KVM: MIPS: Add VZ support to build system James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 25/32] KVM: MIPS/VZ: Support guest CP0_BadInstr[P] James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 26/32] KVM: MIPS/VZ: Support guest CP0_[X]ContextConfig James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 27/32] KVM: MIPS/VZ: Support guest segmentation control James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` James Hogan [this message] 2017-03-02 9:36 ` [PATCH 28/32] KVM: MIPS/VZ: Support guest hardware page table walker James Hogan 2017-03-02 9:36 ` [PATCH 29/32] KVM: MIPS/VZ: Support guest load-linked bit James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 30/32] KVM: MIPS/VZ: Emulate MAARs when necessary James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 31/32] KVM: MIPS/VZ: Support hardware guest timer James Hogan 2017-03-02 9:36 ` James Hogan 2017-03-02 9:36 ` [PATCH 32/32] KVM: MIPS/VZ: Trace guest mode changes James Hogan 2017-03-02 9:36 ` James Hogan
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