[PATCH v2 0/7] x86: efi: Add a 64-bit coreboot payload

[PATCH v2 0/7] x86: efi: Add a 64-bit coreboot payload

[Simon Glass]

This series creates a new 64-bit 'coreboot64' build which can be launched
from coreboot. It uses SPL to effect the jump to 64-bit mode.

This was done in an attempt to get the Ubuntu FirmwareTestSuite[1]
working. Unfortunately the latest version shows a splash screen and hangs,
perhaps due to some missing EFI support.

[1] https://wiki.ubuntu.com/FirmwareTestSuite

Changes in v2:
- Add a new patch to indicate 32/64-bit in bdinfo

Simon Glass (7):
  x86: Allow building an SPL image for coreboot
  x86: Move work-around out of cpu_jump_to_64bit_uboot()
  x86: Update SPL for coreboot
  x86: cbfs: Drop unwanted declaration
  x86: coreboot: Allow building an SPL image
  x86: Add an indication of 32/64-bit to bdinfo
  x86: Add a 64-bit coreboot build

 Makefile                             |  6 ++++
 arch/x86/cpu/Makefile                |  4 ++-
 arch/x86/cpu/coreboot/Kconfig        |  1 +
 arch/x86/cpu/coreboot/Makefile       |  8 ++++-
 arch/x86/cpu/coreboot/coreboot.c     |  3 +-
 arch/x86/cpu/coreboot/coreboot_spl.c | 12 +++++++
 arch/x86/cpu/i386/cpu.c              | 10 ------
 arch/x86/cpu/intel_common/Makefile   |  2 ++
 arch/x86/cpu/x86_64/cpu.c            |  2 ++
 arch/x86/dts/coreboot-u-boot.dtsi    | 18 +++++++++++
 arch/x86/lib/spl.c                   | 23 ++++++++++---
 board/coreboot/coreboot/MAINTAINERS  |  7 ++++
 cmd/bdinfo.c                         |  1 +
 configs/coreboot64_defconfig         | 48 ++++++++++++++++++++++++++++
 doc/board/coreboot/coreboot.rst      | 10 ++++++
 include/cbfs.h                       |  2 +-
 16 files changed, 139 insertions(+), 18 deletions(-)
 create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c
 create mode 100644 arch/x86/dts/coreboot-u-boot.dtsi
 create mode 100644 configs/coreboot64_defconfig

-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 1/7] x86: Allow building an SPL image for coreboot

[Simon Glass]

Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around
this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add
a build rule and binman definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 Makefile                          |  6 ++++++
 arch/x86/cpu/coreboot/Kconfig     |  1 +
 arch/x86/dts/coreboot-u-boot.dtsi | 18 ++++++++++++++++++
 3 files changed, 25 insertions(+)
 create mode 100644 arch/x86/dts/coreboot-u-boot.dtsi

diff --git a/Makefile b/Makefile
index b8a4b5058a..a6db812f6d 100644
--- a/Makefile
+++ b/Makefile
@@ -926,6 +926,9 @@ ALL-$(CONFIG_EFI_STUB) += u-boot-payload.efi
 ifneq ($(BUILD_ROM)$(CONFIG_BUILD_ROM),)
 ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
 endif
+ifeq ($(CONFIG_SYS_COREBOOT)$(CONFIG_SPL),yy)
+ALL-$(CONFIG_BINMAN) += u-boot-x86-with-spl.bin
+endif
 
 # Build a combined spl + u-boot image for sunxi
 ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
@@ -1611,6 +1614,9 @@ u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
 endif
 endif
 
+u-boot-x86-with-spl.bin: spl/u-boot-spl.bin u-boot.bin FORCE
+	$(call if_changed,binman)
+
 ifneq ($(CONFIG_TEGRA),)
 ifneq ($(CONFIG_BINMAN),)
 # Makes u-boot-dtb-tegra.bin u-boot-tegra.bin u-boot-nodtb-tegra.bin
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index c8e6a889d0..497d6284ac 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -25,5 +25,6 @@ config SYS_COREBOOT
 	imply FS_CBFS
 	imply CBMEM_CONSOLE
 	imply X86_TSC_READ_BASE
+	select BINMAN if X86_64
 
 endif
diff --git a/arch/x86/dts/coreboot-u-boot.dtsi b/arch/x86/dts/coreboot-u-boot.dtsi
new file mode 100644
index 0000000000..38efc48d83
--- /dev/null
+++ b/arch/x86/dts/coreboot-u-boot.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ * Written by Simon Glass <sjg@chromium.org>
+ */
+
+#include <config.h>
+
+/ {
+	binman {
+		filename = "u-boot-x86-with-spl.bin";
+		u-boot-spl {
+		};
+		u-boot {
+			offset = <0x10000>;
+		};
+	};
+};
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 2/7] x86: Move work-around out of cpu_jump_to_64bit_uboot()

[Simon Glass]

At present this function copies U-Boot from the last 1MB of ROM. This is
not the right way to do it. Instead, the binman symbol should provide the
location.

But in any case the code should live in the caller,
spl_board_load_image(), so that the 64-bit jump function can be used
elsewhere. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/i386/cpu.c | 10 ----------
 arch/x86/lib/spl.c      | 13 +++++++++++++
 2 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/i386/cpu.c b/arch/x86/cpu/i386/cpu.c
index c8da7f10e9..45416a9be5 100644
--- a/arch/x86/cpu/i386/cpu.c
+++ b/arch/x86/cpu/i386/cpu.c
@@ -611,16 +611,6 @@ int cpu_jump_to_64bit_uboot(ulong target)
 
 	func = (func_t)ptr;
 
-	/*
-	 * Copy U-Boot from ROM
-	 * TODO(sjg at chromium.org): Figure out a way to get the text base
-	 * correctly here, and in the device-tree binman definition.
-	 *
-	 * Also consider using FIT so we get the correct image length and
-	 * parameters.
-	 */
-	memcpy((char *)target, (char *)0xfff00000, 0x100000);
-
 	/* Jump to U-Boot */
 	func((ulong)pgtable, 0, (ulong)target);
 
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 90baec2a17..95a89c072d 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -207,6 +207,19 @@ static int spl_board_load_image(struct spl_image_info *spl_image,
 	spl_image->os = IH_OS_U_BOOT;
 	spl_image->name = "U-Boot";
 
+	if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
+		/*
+		 * Copy U-Boot from ROM
+		 * TODO(sjg at chromium.org): Figure out a way to get the text base
+		 * correctly here, and in the device-tree binman definition.
+		 *
+		 * Also consider using FIT so we get the correct image length
+		 * and parameters.
+		 */
+		memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
+		       0x100000);
+	}
+
 	debug("Loading to %lx\n", spl_image->load_addr);
 
 	return 0;
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 3/7] x86: Update SPL for coreboot

[Simon Glass]

At present SPL only works on bare-metal builds. With a few tweaks it can
be used for coreboot also.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/lib/spl.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 95a89c072d..212b4d596d 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -63,7 +63,7 @@ static int x86_spl_init(void)
 	 * is not needed. We could make this a CONFIG option or perhaps
 	 * place it immediately below CONFIG_SYS_TEXT_BASE.
 	 */
-	char *ptr = (char *)0x110000;
+	__maybe_unused char *ptr = (char *)0x110000;
 #else
 	struct udevice *punit;
 #endif
@@ -111,7 +111,8 @@ static int x86_spl_init(void)
 			      __func__, ret);
 	}
 
-#ifndef CONFIG_TPL
+#ifndef CONFIG_SYS_COREBOOT
+# ifndef CONFIG_TPL
 	memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
 
 	/* TODO(sjg at chromium.org): Consider calling cpu_init_r() here */
@@ -140,7 +141,7 @@ static int x86_spl_init(void)
 		return ret;
 	}
 	mtrr_commit(true);
-#else
+# else
 	ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
 	if (ret)
 		debug("Could not find PUNIT (err=%d)\n", ret);
@@ -148,6 +149,7 @@ static int x86_spl_init(void)
 	ret = set_max_freq();
 	if (ret)
 		debug("Failed to set CPU frequency (err=%d)\n", ret);
+# endif
 #endif
 
 	return 0;
@@ -162,7 +164,7 @@ void board_init_f(ulong flags)
 		debug("Error %d\n", ret);
 		panic("x86_spl_init fail");
 	}
-#ifdef CONFIG_TPL
+#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
 	gd->bd = malloc(sizeof(*gd->bd));
 	if (!gd->bd) {
 		printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 4/7] x86: cbfs: Drop unwanted declaration

[Simon Glass]

The intention here is add a forward declaration, not actually declare a
variable. Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 include/cbfs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/cbfs.h b/include/cbfs.h
index f3bc8ca24a..d915f9426d 100644
--- a/include/cbfs.h
+++ b/include/cbfs.h
@@ -135,7 +135,7 @@ void file_cbfs_get_next(const struct cbfs_cachenode **file);
  */
 const struct cbfs_cachenode *file_cbfs_find(const char *name);
 
-struct cbfs_priv *priv;
+struct cbfs_priv;
 
 /**
  * cbfs_find_file() - Find a file in a given CBFS
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 5/7] x86: coreboot: Allow building an SPL image

[Simon Glass]

Make a few adjustments to allow us to build an SPL image for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 arch/x86/cpu/Makefile                |  4 +++-
 arch/x86/cpu/coreboot/Makefile       |  8 +++++++-
 arch/x86/cpu/coreboot/coreboot.c     |  3 ++-
 arch/x86/cpu/coreboot/coreboot_spl.c | 12 ++++++++++++
 arch/x86/cpu/intel_common/Makefile   |  2 ++
 arch/x86/cpu/x86_64/cpu.c            |  2 ++
 6 files changed, 28 insertions(+), 3 deletions(-)
 create mode 100644 arch/x86/cpu/coreboot/coreboot_spl.c

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 307267a8fb..ee0499f5d7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -54,9 +54,11 @@ obj-$(CONFIG_INTEL_QUARK) += quark/
 obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
 obj-$(CONFIG_INTEL_TANGIER) += tangier/
 obj-$(CONFIG_APIC) += lapic.o ioapic.o
-obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
 obj-$(CONFIG_$(SPL_TPL_)ACPI_GPE) += acpi_gpe.o
 obj-$(CONFIG_QFW) += qfw_cpu.o
+ifndef CONFIG_SYS_COREBOOT
+obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
+endif
 ifndef CONFIG_$(SPL_)X86_64
 obj-$(CONFIG_SMP) += mp_init.o
 endif
diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 35b15bb1da..605f90304e 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -11,8 +11,14 @@
 # (C) Copyright 2002
 # Daniel Engstr?m, Omicron Ceti AB, daniel at omicron.se.
 
+ifndef CONFIG_SPL
 obj-y += car.o
+endif
+ifdef CONFIG_SPL_BUILD
+obj-y += coreboot_spl.o
+else
+obj-y += sdram.o
+endif
 obj-y += coreboot.o
 obj-y += tables.o
-obj-y += sdram.o
 obj-y += timestamp.o
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 0c4c6348d1..624caf67a6 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -27,7 +27,8 @@ int arch_cpu_init(void)
 
 	timestamp_init();
 
-	return x86_cpu_init_f();
+	return IS_ENABLED(CONFIG_X86_RUN_64BIT) ? x86_cpu_reinit_f() :
+		 x86_cpu_init_f();
 }
 
 int checkcpu(void)
diff --git a/arch/x86/cpu/coreboot/coreboot_spl.c b/arch/x86/cpu/coreboot/coreboot_spl.c
new file mode 100644
index 0000000000..36661871e9
--- /dev/null
+++ b/arch/x86/cpu/coreboot/coreboot_spl.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Google LLC
+ */
+
+#include <common.h>
+#include <init.h>
+
+int dram_init(void)
+{
+	return 0;
+}
diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile
index 1736bd2b53..374803b876 100644
--- a/arch/x86/cpu/intel_common/Makefile
+++ b/arch/x86/cpu/intel_common/Makefile
@@ -32,6 +32,8 @@ obj-$(CONFIG_HAVE_P2SB) += p2sb.o
 
 ifdef CONFIG_SPL
 ifndef CONFIG_SPL_BUILD
+ifndef CONFIG_SYS_COREBOOT
 obj-y += cpu_from_spl.o
 endif
 endif
+endif
diff --git a/arch/x86/cpu/x86_64/cpu.c b/arch/x86/cpu/x86_64/cpu.c
index 90925e46ea..4b64339f25 100644
--- a/arch/x86/cpu/x86_64/cpu.c
+++ b/arch/x86/cpu/x86_64/cpu.c
@@ -53,6 +53,7 @@ int misc_init_r(void)
 	return 0;
 }
 
+#ifndef CONFIG_SYS_COREBOOT
 int checkcpu(void)
 {
 	return 0;
@@ -62,6 +63,7 @@ int print_cpuinfo(void)
 {
 	return 0;
 }
+#endif
 
 int x86_cpu_reinit_f(void)
 {
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 6/7] x86: Add an indication of 32/64-bit to bdinfo

[Simon Glass]

It is useful to know what mode U-Boot is running in. Add a message at the
end of the 'bdinfo' output.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2:
- Add a new patch to indicate 32/64-bit in bdinfo

 cmd/bdinfo.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175b37..a3129c9fe1 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -388,6 +388,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	print_mhz("ethspeed",	    bd->bi_ethspeed);
 #endif
 	print_baudrate();
+	printf("Build: %d-bit\n", CONFIG_IS_ENABLED(X86_64) ? 64 : 32);
 
 	return 0;
 }
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 6/7] x86: Add an indication of 32/64-bit to bdinfo

[Heinrich Schuchardt]

On 4/26/20 9:38 PM, Simon Glass wrote:
> It is useful to know what mode U-Boot is running in. Add a message at the
> end of the 'bdinfo' output.

X86 is not the only architecture that can run both in 32bit and 64bit
mode. The same is true for ARM and SANDBOX. Shouldn't we provide the
information for these architecture too?

The Raspberry Pi 3 is an example of an ARM board where building either
32bit or 64bit U-Boot is used depending on the bitness of the OS.

Best regards

Heinrich

>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v2:
> - Add a new patch to indicate 32/64-bit in bdinfo
>
>  cmd/bdinfo.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
> index d6a7175b37..a3129c9fe1 100644
> --- a/cmd/bdinfo.c
> +++ b/cmd/bdinfo.c
> @@ -388,6 +388,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  	print_mhz("ethspeed",	    bd->bi_ethspeed);
>  #endif
>  	print_baudrate();
> +	printf("Build: %d-bit\n", CONFIG_IS_ENABLED(X86_64) ? 64 : 32);
>
>  	return 0;
>  }
>

[PATCH v2 6/7] x86: Add an indication of 32/64-bit to bdinfo

[Simon Glass]

Hi Heinrich,

On Sun, 26 Apr 2020 at 14:21, Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>
> On 4/26/20 9:38 PM, Simon Glass wrote:
> > It is useful to know what mode U-Boot is running in. Add a message at the
> > end of the 'bdinfo' output.
>
> X86 is not the only architecture that can run both in 32bit and 64bit
> mode. The same is true for ARM and SANDBOX. Shouldn't we provide the
> information for these architecture too?
>
> The Raspberry Pi 3 is an example of an ARM board where building either
> 32bit or 64bit U-Boot is used depending on the bitness of the OS.

Yes I think that would be good. But do we have a generic way to tell?
sizeof(int) ?

Regards,
Simon


>
> Best regards
>
> Heinrich
>
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > Changes in v2:
> > - Add a new patch to indicate 32/64-bit in bdinfo
> >
> >  cmd/bdinfo.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
> > index d6a7175b37..a3129c9fe1 100644
> > --- a/cmd/bdinfo.c
> > +++ b/cmd/bdinfo.c
> > @@ -388,6 +388,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> >       print_mhz("ethspeed",       bd->bi_ethspeed);
> >  #endif
> >       print_baudrate();
> > +     printf("Build: %d-bit\n", CONFIG_IS_ENABLED(X86_64) ? 64 : 32);
> >
> >       return 0;
> >  }
> >
>

[PATCH v2 6/7] x86: Add an indication of 32/64-bit to bdinfo

[Heinrich Schuchardt]

On 4/26/20 10:32 PM, Simon Glass wrote:
> Hi Heinrich,
>
> On Sun, 26 Apr 2020 at 14:21, Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
>>
>> On 4/26/20 9:38 PM, Simon Glass wrote:
>>> It is useful to know what mode U-Boot is running in. Add a message at the
>>> end of the 'bdinfo' output.
>>
>> X86 is not the only architecture that can run both in 32bit and 64bit
>> mode. The same is true for ARM and SANDBOX. Shouldn't we provide the
>> information for these architecture too?
>>
>> The Raspberry Pi 3 is an example of an ARM board where building either
>> 32bit or 64bit U-Boot is used depending on the bitness of the OS.
>
> Yes I think that would be good. But do we have a generic way to tell?
> sizeof(int) ?

sizeof(int) = 4 on aarch64.

Using these should be fine:

CONFIG_ARM64=y
CONFIG_ARCH_RV64I=y
CONFIG_SANDBOX64=y

(continued below)

>
> Regards,
> Simon
>
>
>>
>> Best regards
>>
>> Heinrich
>>
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> Changes in v2:
>>> - Add a new patch to indicate 32/64-bit in bdinfo
>>>
>>>  cmd/bdinfo.c | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
>>> index d6a7175b37..a3129c9fe1 100644
>>> --- a/cmd/bdinfo.c
>>> +++ b/cmd/bdinfo.c
>>> @@ -388,6 +388,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>>       print_mhz("ethspeed",       bd->bi_ethspeed);
>>>  #endif
>>>       print_baudrate();
>>> +     printf("Build: %d-bit\n", CONFIG_IS_ENABLED(X86_64) ? 64 : 32);

"Build" it usually used to refer to a software release.

Should this be:

    printf("bitness     = %d\n", ...

or simply

    printf("%d-bit\n", ...

Best regards

Heinrich

>>>
>>>       return 0;
>>>  }
>>>
>>

[PATCH v2 6/7] x86: Add an indication of 32/64-bit to bdinfo

[Mark Kettenis]

> From: Heinrich Schuchardt <xypron.glpk@gmx.de>
> Date: Sun, 26 Apr 2020 23:14:25 +0200
> 
> On 4/26/20 10:32 PM, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Sun, 26 Apr 2020 at 14:21, Heinrich Schuchardt <xypron.glpk@gmx.de> wrote:
> >>
> >> On 4/26/20 9:38 PM, Simon Glass wrote:
> >>> It is useful to know what mode U-Boot is running in. Add a message at the
> >>> end of the 'bdinfo' output.
> >>
> >> X86 is not the only architecture that can run both in 32bit and 64bit
> >> mode. The same is true for ARM and SANDBOX. Shouldn't we provide the
> >> information for these architecture too?
> >>
> >> The Raspberry Pi 3 is an example of an ARM board where building either
> >> 32bit or 64bit U-Boot is used depending on the bitness of the OS.
> >
> > Yes I think that would be good. But do we have a generic way to tell?
> > sizeof(int) ?
> 
> sizeof(int) = 4 on aarch64.

sizeof(void *) should work

(and sizeof(long) should work as well, but then there is Windows)

> Using these should be fine:
> 
> CONFIG_ARM64=y
> CONFIG_ARCH_RV64I=y
> CONFIG_SANDBOX64=y

MIPS and PowerPC can be 64-bit as well.  I don't think checking config
options scales.

[PATCH v2 7/7] x86: Add a 64-bit coreboot build

[Simon Glass]

Add a build for running 64-bit U-Boot from coreboot (which is 32-bit).
This uses binman to create an image with a 32-bit SPL and a 64-bit U-Boot.

Coreboot boots into SPL and then SPL boots into U-Boot.

This allows running 64-bit EFI images on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
---

Changes in v2: None

 board/coreboot/coreboot/MAINTAINERS |  7 +++++
 configs/coreboot64_defconfig        | 48 +++++++++++++++++++++++++++++
 doc/board/coreboot/coreboot.rst     | 10 ++++++
 3 files changed, 65 insertions(+)
 create mode 100644 configs/coreboot64_defconfig

diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
index 188906b080..a05673bb0b 100644
--- a/board/coreboot/coreboot/MAINTAINERS
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -4,3 +4,10 @@ S:	Maintained
 F:	board/coreboot/coreboot/
 F:	include/configs/chromebook_link.h
 F:	configs/coreboot_defconfig
+
+COREBOOT64 BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/coreboot/coreboot/
+F:	include/configs/chromebook_link.h
+F:	configs/coreboot64_defconfig
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
new file mode 100644
index 0000000000..80353b8eb3
--- /dev/null
+++ b/configs/coreboot64_defconfig
@@ -0,0 +1,48 @@
+CONFIG_X86=y
+CONFIG_SYS_TEXT_BASE=0x1120000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_NR_DRAM_BANKS=8
+CONFIG_PRE_CON_BUF_ADDR=0x100000
+CONFIG_X86_RUN_64BIT=y
+CONFIG_VENDOR_COREBOOT=y
+CONFIG_TARGET_COREBOOT=y
+CONFIG_SPL_TEXT_BASE=0x1110000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro"
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_LAST_STAGE_INIT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_IDE=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_SOUND=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_MAC_PARTITION=y
+# CONFIG_SPL_MAC_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_ISO_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="coreboot"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+# CONFIG_PCI_PNP is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_I8254=y
+CONFIG_CONSOLE_SCROLL_LINES=5
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index fd974229eb..9c44c025a4 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -40,3 +40,13 @@ To enable video you must enable these options in coreboot:
 At present it seems that for Minnowboard Max, coreboot does not pass through
 the video information correctly (it always says the resolution is 0x0). This
 works correctly for link though.
+
+64-bit U-Boot
+-------------
+
+In addition to the 32-bit 'coreboot' build there is a 'coreboot64' build. This
+produces an image which can be booted from coreboot (32-bit). Internally it
+works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It
+can be useful for running UEFI applications, for example.
+
+This has only been lightly tested.
-- 
2.26.2.303.gf8c07b1a785-goog

[PATCH v2 0/7] x86: efi: Add a 64-bit coreboot payload

[Bin Meng]

Hi Simon,

On Mon, Apr 27, 2020 at 3:38 AM Simon Glass <sjg@chromium.org> wrote:
>
> This series creates a new 64-bit 'coreboot64' build which can be launched
> from coreboot. It uses SPL to effect the jump to 64-bit mode.
>
> This was done in an attempt to get the Ubuntu FirmwareTestSuite[1]
> working. Unfortunately the latest version shows a splash screen and hangs,
> perhaps due to some missing EFI support.
>
> [1] https://wiki.ubuntu.com/FirmwareTestSuite
>
> Changes in v2:
> - Add a new patch to indicate 32/64-bit in bdinfo
>

When testing this series, it does not build on top of u-boot-x86/master.

arch/x86/cpu/built-in.o: In function `get_coreboot_info':
u-boot/arch/x86/cpu/coreboot/tables.c:228: undefined reference to
`locate_coreboot_table'
Segmentation fault (core dumped)
Makefile:1769: recipe for target 'u-boot' failed
make: *** [u-boot] Error 139
make: *** Deleting file 'u-boot'

Please take a look.

Regards,
Bin