All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
@ 2022-10-20  9:15 Prike Liang
  2022-10-20  9:15 ` [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting Prike Liang
  2022-10-20 16:02 ` [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Felix Kuehling
  0 siblings, 2 replies; 9+ messages in thread
From: Prike Liang @ 2022-10-20  9:15 UTC (permalink / raw)
  To: amd-gfx
  Cc: Alexander.Deucher, Yifan1.Zhang, Prike Liang, ray.huang, aaron.liu

This dummy cache info will enable kfd base function support.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
 1 file changed, 52 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index cd5f8b219bf9..960046e43b7a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
 	},
 };
 
+static struct kfd_gpu_cache_info dummy_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 2048,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 6,
+	},
+};
+
 static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
 		struct crat_subtype_computeunit *cu)
 {
@@ -1514,8 +1562,6 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 			num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
 			break;
 		case IP_VERSION(10, 3, 3):
-		case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
-		case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
 			pcache_info = yellow_carp_cache_info;
 			num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
 			break;
@@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 				kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
 			break;
 		default:
-			return -EINVAL;
+			pcache_info = dummy_cache_info;
+			num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
+			pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
+			break;
 		}
 	}
 
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting
  2022-10-20  9:15 [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Prike Liang
@ 2022-10-20  9:15 ` Prike Liang
  2022-10-20 13:15   ` Alex Deucher
  2022-10-20 16:02 ` [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Felix Kuehling
  1 sibling, 1 reply; 9+ messages in thread
From: Prike Liang @ 2022-10-20  9:15 UTC (permalink / raw)
  To: amd-gfx
  Cc: Alexander.Deucher, Yifan1.Zhang, Prike Liang, ray.huang, aaron.liu

Update the gfx1037 L1/L2/L3 cache setting.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 53 +++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 960046e43b7a..6e699cb9971f 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -795,6 +795,55 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
 	},
 };
 
+static struct kfd_gpu_cache_info gfx1037_cache_info[] = {
+	{
+		/* TCP L1 Cache per CU */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 1,
+	},
+	{
+		/* Scalar L1 Instruction Cache per SQC */
+		.cache_size = 32,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_INST_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* Scalar L1 Data Cache per SQC */
+		.cache_size = 16,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* GL1 Data Cache per SA */
+		.cache_size = 128,
+		.cache_level = 1,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+	{
+		/* L2 Data Cache per GPU (Total Tex Cache) */
+		.cache_size = 256,
+		.cache_level = 2,
+		.flags = (CRAT_CACHE_FLAGS_ENABLED |
+				CRAT_CACHE_FLAGS_DATA_CACHE |
+				CRAT_CACHE_FLAGS_SIMD_CACHE),
+		.num_cu_shared = 2,
+	},
+};
+
+
 static struct kfd_gpu_cache_info dummy_cache_info[] = {
 	{
 		/* TCP L1 Cache per CU */
@@ -1565,6 +1614,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
 			pcache_info = yellow_carp_cache_info;
 			num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
 			break;
+		case IP_VERSION(10, 3, 7):
+			pcache_info = gfx1037_cache_info;
+			num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);
+			break;
 		case IP_VERSION(11, 0, 0):
 		case IP_VERSION(11, 0, 1):
 		case IP_VERSION(11, 0, 2):
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread

* Re: [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting
  2022-10-20  9:15 ` [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting Prike Liang
@ 2022-10-20 13:15   ` Alex Deucher
  0 siblings, 0 replies; 9+ messages in thread
From: Alex Deucher @ 2022-10-20 13:15 UTC (permalink / raw)
  To: Prike Liang
  Cc: Alexander.Deucher, Yifan1.Zhang, ray.huang, aaron.liu, amd-gfx

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

On Thu, Oct 20, 2022 at 5:15 AM Prike Liang <Prike.Liang@amd.com> wrote:
>
> Update the gfx1037 L1/L2/L3 cache setting.
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 53 +++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 960046e43b7a..6e699cb9971f 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -795,6 +795,55 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
>         },
>  };
>
> +static struct kfd_gpu_cache_info gfx1037_cache_info[] = {
> +       {
> +               /* TCP L1 Cache per CU */
> +               .cache_size = 16,
> +               .cache_level = 1,
> +               .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                               CRAT_CACHE_FLAGS_DATA_CACHE |
> +                               CRAT_CACHE_FLAGS_SIMD_CACHE),
> +               .num_cu_shared = 1,
> +       },
> +       {
> +               /* Scalar L1 Instruction Cache per SQC */
> +               .cache_size = 32,
> +               .cache_level = 1,
> +               .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                               CRAT_CACHE_FLAGS_INST_CACHE |
> +                               CRAT_CACHE_FLAGS_SIMD_CACHE),
> +               .num_cu_shared = 2,
> +       },
> +       {
> +               /* Scalar L1 Data Cache per SQC */
> +               .cache_size = 16,
> +               .cache_level = 1,
> +               .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                               CRAT_CACHE_FLAGS_DATA_CACHE |
> +                               CRAT_CACHE_FLAGS_SIMD_CACHE),
> +               .num_cu_shared = 2,
> +       },
> +       {
> +               /* GL1 Data Cache per SA */
> +               .cache_size = 128,
> +               .cache_level = 1,
> +               .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                               CRAT_CACHE_FLAGS_DATA_CACHE |
> +                               CRAT_CACHE_FLAGS_SIMD_CACHE),
> +               .num_cu_shared = 2,
> +       },
> +       {
> +               /* L2 Data Cache per GPU (Total Tex Cache) */
> +               .cache_size = 256,
> +               .cache_level = 2,
> +               .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                               CRAT_CACHE_FLAGS_DATA_CACHE |
> +                               CRAT_CACHE_FLAGS_SIMD_CACHE),
> +               .num_cu_shared = 2,
> +       },
> +};
> +
> +
>  static struct kfd_gpu_cache_info dummy_cache_info[] = {
>         {
>                 /* TCP L1 Cache per CU */
> @@ -1565,6 +1614,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>                         pcache_info = yellow_carp_cache_info;
>                         num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
>                         break;
> +               case IP_VERSION(10, 3, 7):
> +                       pcache_info = gfx1037_cache_info;
> +                       num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);
> +                       break;
>                 case IP_VERSION(11, 0, 0):
>                 case IP_VERSION(11, 0, 1):
>                 case IP_VERSION(11, 0, 2):
> --
> 2.25.1
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-20  9:15 [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Prike Liang
  2022-10-20  9:15 ` [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting Prike Liang
@ 2022-10-20 16:02 ` Felix Kuehling
  2022-10-21  1:50   ` Liang, Prike
  1 sibling, 1 reply; 9+ messages in thread
From: Felix Kuehling @ 2022-10-20 16:02 UTC (permalink / raw)
  To: Prike Liang, amd-gfx
  Cc: Alexander.Deucher, Yifan1.Zhang, ray.huang, aaron.liu


Am 2022-10-20 um 05:15 schrieb Prike Liang:
> This dummy cache info will enable kfd base function support.
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>   1 file changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index cd5f8b219bf9..960046e43b7a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
>   	},
>   };
>   
> +static struct kfd_gpu_cache_info dummy_cache_info[] = {
> +	{
> +		/* TCP L1 Cache per CU */
> +		.cache_size = 16,
> +		.cache_level = 1,
> +		.flags = (CRAT_CACHE_FLAGS_ENABLED |
> +				CRAT_CACHE_FLAGS_DATA_CACHE |
> +				CRAT_CACHE_FLAGS_SIMD_CACHE),
> +		.num_cu_shared = 1,
> +	},
> +	{
> +		/* Scalar L1 Instruction Cache per SQC */
> +		.cache_size = 32,
> +		.cache_level = 1,
> +		.flags = (CRAT_CACHE_FLAGS_ENABLED |
> +				CRAT_CACHE_FLAGS_INST_CACHE |
> +				CRAT_CACHE_FLAGS_SIMD_CACHE),
> +		.num_cu_shared = 2,
> +	},
> +	{
> +		/* Scalar L1 Data Cache per SQC */
> +		.cache_size = 16,
> +		.cache_level = 1,
> +		.flags = (CRAT_CACHE_FLAGS_ENABLED |
> +				CRAT_CACHE_FLAGS_DATA_CACHE |
> +				CRAT_CACHE_FLAGS_SIMD_CACHE),
> +		.num_cu_shared = 2,
> +	},
> +	{
> +		/* GL1 Data Cache per SA */
> +		.cache_size = 128,
> +		.cache_level = 1,
> +		.flags = (CRAT_CACHE_FLAGS_ENABLED |
> +				CRAT_CACHE_FLAGS_DATA_CACHE |
> +				CRAT_CACHE_FLAGS_SIMD_CACHE),
> +		.num_cu_shared = 6,
> +	},
> +	{
> +		/* L2 Data Cache per GPU (Total Tex Cache) */
> +		.cache_size = 2048,
> +		.cache_level = 2,
> +		.flags = (CRAT_CACHE_FLAGS_ENABLED |
> +				CRAT_CACHE_FLAGS_DATA_CACHE |
> +				CRAT_CACHE_FLAGS_SIMD_CACHE),
> +		.num_cu_shared = 6,
> +	},
> +};
> +
>   static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
>   		struct crat_subtype_computeunit *cu)
>   {
> @@ -1514,8 +1562,6 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>   			num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
>   			break;
>   		case IP_VERSION(10, 3, 3):
> -		case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
> -		case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
>   			pcache_info = yellow_carp_cache_info;
>   			num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
>   			break;
> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>   				kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>   			break;
>   		default:
> -			return -EINVAL;
> +			pcache_info = dummy_cache_info;
> +			num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
> +			pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
> +			break;

Could we make this return an error if the amdgpu.exp_hw_support module 
parameter is not set?

Regards,
   Felix


>   		}
>   	}
>   

^ permalink raw reply	[flat|nested] 9+ messages in thread

* RE: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-20 16:02 ` [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Felix Kuehling
@ 2022-10-21  1:50   ` Liang, Prike
  2022-10-21  5:10     ` Felix Kuehling
  0 siblings, 1 reply; 9+ messages in thread
From: Liang, Prike @ 2022-10-21  1:50 UTC (permalink / raw)
  To: Kuehling, Felix, amd-gfx
  Cc: Deucher, Alexander, Zhang, Yifan, Huang, Ray, Liu, Aaron

[Public]

-----Original Message-----
From: Kuehling, Felix <Felix.Kuehling@amd.com>
Sent: Friday, October 21, 2022 12:03 AM
To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>
Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic


Am 2022-10-20 um 05:15 schrieb Prike Liang:
> This dummy cache info will enable kfd base function support.
>
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
> ---
>   drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>   1 file changed, 52 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index cd5f8b219bf9..960046e43b7a 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
>       },
>   };
>
> +static struct kfd_gpu_cache_info dummy_cache_info[] = {
> +     {
> +             /* TCP L1 Cache per CU */
> +             .cache_size = 16,
> +             .cache_level = 1,
> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
> +             .num_cu_shared = 1,
> +     },
> +     {
> +             /* Scalar L1 Instruction Cache per SQC */
> +             .cache_size = 32,
> +             .cache_level = 1,
> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                             CRAT_CACHE_FLAGS_INST_CACHE |
> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
> +             .num_cu_shared = 2,
> +     },
> +     {
> +             /* Scalar L1 Data Cache per SQC */
> +             .cache_size = 16,
> +             .cache_level = 1,
> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
> +             .num_cu_shared = 2,
> +     },
> +     {
> +             /* GL1 Data Cache per SA */
> +             .cache_size = 128,
> +             .cache_level = 1,
> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
> +             .num_cu_shared = 6,
> +     },
> +     {
> +             /* L2 Data Cache per GPU (Total Tex Cache) */
> +             .cache_size = 2048,
> +             .cache_level = 2,
> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
> +             .num_cu_shared = 6,
> +     },
> +};
> +
>   static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
>               struct crat_subtype_computeunit *cu)
>   {
> @@ -1514,8 +1562,6 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>                       num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
>                       break;
>               case IP_VERSION(10, 3, 3):
> -             case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
> -             case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
>                       pcache_info = yellow_carp_cache_info;
>                       num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
>                       break;
> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>                               kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>                       break;
>               default:
> -                     return -EINVAL;
> +                     pcache_info = dummy_cache_info;
> +                     num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
> +                     pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
> +                     break;

Could we make this return an error if the amdgpu.exp_hw_support module parameter is not set?

Regards,
   Felix

[Prike] It's fine to protect this dummy info by checking the parameter amdgpu_exp_hw_support, but it may not friendly to end user by adding the parameter and some guys will still report KFD not enabled for this parameter setting problem. The original idea is the end user will not aware the dummy cache info and only alert the warning message to developer.

>               }
>       }
>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-21  1:50   ` Liang, Prike
@ 2022-10-21  5:10     ` Felix Kuehling
  2022-10-21 13:05       ` Liang, Prike
  0 siblings, 1 reply; 9+ messages in thread
From: Felix Kuehling @ 2022-10-21  5:10 UTC (permalink / raw)
  To: Liang, Prike, amd-gfx
  Cc: Deucher, Alexander, Zhang, Yifan, Huang, Ray, Liu, Aaron

Am 2022-10-20 um 21:50 schrieb Liang, Prike:
> [Public]
>
> -----Original Message-----
> From: Kuehling, Felix <Felix.Kuehling@amd.com>
> Sent: Friday, October 21, 2022 12:03 AM
> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
>
>
> Am 2022-10-20 um 05:15 schrieb Prike Liang:
>> This dummy cache info will enable kfd base function support.
>>
>> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>>    1 file changed, 52 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> index cd5f8b219bf9..960046e43b7a 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
>>        },
>>    };
>>
>> +static struct kfd_gpu_cache_info dummy_cache_info[] = {
>> +     {
>> +             /* TCP L1 Cache per CU */
>> +             .cache_size = 16,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 1,
>> +     },
>> +     {
>> +             /* Scalar L1 Instruction Cache per SQC */
>> +             .cache_size = 32,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_INST_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 2,
>> +     },
>> +     {
>> +             /* Scalar L1 Data Cache per SQC */
>> +             .cache_size = 16,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 2,
>> +     },
>> +     {
>> +             /* GL1 Data Cache per SA */
>> +             .cache_size = 128,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 6,
>> +     },
>> +     {
>> +             /* L2 Data Cache per GPU (Total Tex Cache) */
>> +             .cache_size = 2048,
>> +             .cache_level = 2,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 6,
>> +     },
>> +};
>> +
>>    static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
>>                struct crat_subtype_computeunit *cu)
>>    {
>> @@ -1514,8 +1562,6 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>                        num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
>>                        break;
>>                case IP_VERSION(10, 3, 3):
>> -             case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
>> -             case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
>>                        pcache_info = yellow_carp_cache_info;
>>                        num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
>>                        break;
>> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>                                kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>>                        break;
>>                default:
>> -                     return -EINVAL;
>> +                     pcache_info = dummy_cache_info;
>> +                     num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
>> +                     pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
>> +                     break;
> Could we make this return an error if the amdgpu.exp_hw_support module parameter is not set?
>
> Regards,
>     Felix
>
> [Prike] It's fine to protect this dummy info by checking the parameter amdgpu_exp_hw_support, but it may not friendly to end user by adding the parameter and some guys will still report KFD not enabled for this parameter setting problem. The original idea is the end user will not aware the dummy cache info and only alert the warning message to developer.

I thought the intention was to simplify bring-up but make sure that 
valid cache info is available by the time a chip goes into production. 
Therefore, normal end users should never need to set the 
amdgpu_exp_hw_support option. I think you're saying that we would go to 
production with dummy info. That seems like a bad idea to me.

Regards,
   Felix


>
>>                }
>>        }
>>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* RE: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-21  5:10     ` Felix Kuehling
@ 2022-10-21 13:05       ` Liang, Prike
  2022-10-21 20:53         ` Felix Kuehling
  0 siblings, 1 reply; 9+ messages in thread
From: Liang, Prike @ 2022-10-21 13:05 UTC (permalink / raw)
  To: Kuehling, Felix, amd-gfx
  Cc: Deucher, Alexander, Zhang, Yifan, Huang, Ray, Liu, Aaron

[Public]

-----Original Message-----
From: Kuehling, Felix <Felix.Kuehling@amd.com>
Sent: Friday, October 21, 2022 1:11 PM
To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>
Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic

Am 2022-10-20 um 21:50 schrieb Liang, Prike:
> [Public]
>
> -----Original Message-----
> From: Kuehling, Felix <Felix.Kuehling@amd.com>
> Sent: Friday, October 21, 2022 12:03 AM
> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron
> <Aaron.Liu@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for
> property asic
>
>
> Am 2022-10-20 um 05:15 schrieb Prike Liang:
>> This dummy cache info will enable kfd base function support.
>>
>> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>>    1 file changed, 52 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> index cd5f8b219bf9..960046e43b7a 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
>> @@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
>>        },
>>    };
>>
>> +static struct kfd_gpu_cache_info dummy_cache_info[] = {
>> +     {
>> +             /* TCP L1 Cache per CU */
>> +             .cache_size = 16,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 1,
>> +     },
>> +     {
>> +             /* Scalar L1 Instruction Cache per SQC */
>> +             .cache_size = 32,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_INST_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 2,
>> +     },
>> +     {
>> +             /* Scalar L1 Data Cache per SQC */
>> +             .cache_size = 16,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 2,
>> +     },
>> +     {
>> +             /* GL1 Data Cache per SA */
>> +             .cache_size = 128,
>> +             .cache_level = 1,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 6,
>> +     },
>> +     {
>> +             /* L2 Data Cache per GPU (Total Tex Cache) */
>> +             .cache_size = 2048,
>> +             .cache_level = 2,
>> +             .flags = (CRAT_CACHE_FLAGS_ENABLED |
>> +                             CRAT_CACHE_FLAGS_DATA_CACHE |
>> +                             CRAT_CACHE_FLAGS_SIMD_CACHE),
>> +             .num_cu_shared = 6,
>> +     },
>> +};
>> +
>>    static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
>>                struct crat_subtype_computeunit *cu)
>>    {
>> @@ -1514,8 +1562,6 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>                        num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
>>                        break;
>>                case IP_VERSION(10, 3, 3):
>> -             case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */
>> -             case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */
>>                        pcache_info = yellow_carp_cache_info;
>>                        num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
>>                        break;
>> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>                                kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>>                        break;
>>                default:
>> -                     return -EINVAL;
>> +                     pcache_info = dummy_cache_info;
>> +                     num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
>> +                     pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
>> +                     break;
> Could we make this return an error if the amdgpu.exp_hw_support module parameter is not set?
>
> Regards,
>     Felix
>
> [Prike] It's fine to protect this dummy info by checking the parameter amdgpu_exp_hw_support, but it may not friendly to end user by adding the parameter and some guys will still report KFD not enabled for this parameter setting problem. The original idea is the end user will not aware the dummy cache info and only alert the warning message to developer.

I thought the intention was to simplify bring-up but make sure that valid cache info is available by the time a chip goes into production.
Therefore, normal end users should never need to set the amdgpu_exp_hw_support option. I think you're saying that we would go to production with dummy info. That seems like a bad idea to me.

Regards,
   Felix

[Prike]  Sorry for the confusion. In fact, this dummy cache info only used before production and meanwhile needn't require any parameter setting for CQE do KFD test. Anyway if you still have concern on this solution I will add the condition of checking amdgpu_exp_hw_support.

>
>>                }
>>        }
>>

^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-21 13:05       ` Liang, Prike
@ 2022-10-21 20:53         ` Felix Kuehling
  2022-10-24 13:11           ` Liang, Prike
  0 siblings, 1 reply; 9+ messages in thread
From: Felix Kuehling @ 2022-10-21 20:53 UTC (permalink / raw)
  To: Liang, Prike, amd-gfx
  Cc: Deucher, Alexander, Zhang, Yifan, Huang, Ray, Liu, Aaron

On 2022-10-21 09:05, Liang, Prike wrote:
> [Public]
>
> -----Original Message-----
> From: Kuehling, Felix <Felix.Kuehling@amd.com>
> Sent: Friday, October 21, 2022 1:11 PM
> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
>
> Am 2022-10-20 um 21:50 schrieb Liang, Prike:
>> [Public]
>>
>> -----Original Message-----
>> From: Kuehling, Felix <Felix.Kuehling@amd.com>
>> Sent: Friday, October 21, 2022 12:03 AM
>> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
>> <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron
>> <Aaron.Liu@amd.com>
>> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for
>> property asic
>>
>>
>> Am 2022-10-20 um 05:15 schrieb Prike Liang:
>>> This dummy cache info will enable kfd base function support.
>>>
>>> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
>>> ---
>>>     drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>>>     1 file changed, 52 insertions(+), 3 deletions(-)
>>>
[snip]
>>> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>>                                 kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>>>                         break;
>>>                 default:
>>> -                     return -EINVAL;
>>> +                     pcache_info = dummy_cache_info;
>>> +                     num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
>>> +                     pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
>>> +                     break;
>> Could we make this return an error if the amdgpu.exp_hw_support module parameter is not set?
>>
>> Regards,
>>      Felix
>>
>> [Prike] It's fine to protect this dummy info by checking the parameter amdgpu_exp_hw_support, but it may not friendly to end user by adding the parameter and some guys will still report KFD not enabled for this parameter setting problem. The original idea is the end user will not aware the dummy cache info and only alert the warning message to developer.
> I thought the intention was to simplify bring-up but make sure that valid cache info is available by the time a chip goes into production.
> Therefore, normal end users should never need to set the amdgpu_exp_hw_support option. I think you're saying that we would go to production with dummy info. That seems like a bad idea to me.
>
> Regards,
>     Felix
>
> [Prike]  Sorry for the confusion. In fact, this dummy cache info only used before production and meanwhile needn't require any parameter setting for CQE do KFD test. Anyway if you still have concern on this solution I will add the condition of checking amdgpu_exp_hw_support.

The idea to control this with a module parameter was to cause a more 
obvious failure if we don't have correct cache info before going to 
production. Just a warning in the log file is too easy to miss or 
ignore. Of course, if QA gets into the habit of testing with 
amdgpu_exp_hw_support, then this may not solve the problem. You need to 
have at least one test pass without amdgpu_exp_hw_support to catch 
missing cache info.

Regards,
   Felix



^ permalink raw reply	[flat|nested] 9+ messages in thread

* RE: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic
  2022-10-21 20:53         ` Felix Kuehling
@ 2022-10-24 13:11           ` Liang, Prike
  0 siblings, 0 replies; 9+ messages in thread
From: Liang, Prike @ 2022-10-24 13:11 UTC (permalink / raw)
  To: Kuehling, Felix, amd-gfx
  Cc: Deucher, Alexander, Zhang, Yifan, Huang, Ray, Liu, Aaron

[Public]

-----Original Message-----
From: Kuehling, Felix <Felix.Kuehling@amd.com>
Sent: Saturday, October 22, 2022 4:53 AM
To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>
Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic

On 2022-10-21 09:05, Liang, Prike wrote:
> [Public]
>
> -----Original Message-----
> From: Kuehling, Felix <Felix.Kuehling@amd.com>
> Sent: Friday, October 21, 2022 1:11 PM
> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron
> <Aaron.Liu@amd.com>
> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for
> property asic
>
> Am 2022-10-20 um 21:50 schrieb Liang, Prike:
>> [Public]
>>
>> -----Original Message-----
>> From: Kuehling, Felix <Felix.Kuehling@amd.com>
>> Sent: Friday, October 21, 2022 12:03 AM
>> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org
>> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
>> <Yifan1.Zhang@amd.com>; Huang, Ray <Ray.Huang@amd.com>; Liu, Aaron
>> <Aaron.Liu@amd.com>
>> Subject: Re: [PATCH 1/2] drm/amdkfd: introduce dummy cache info for
>> property asic
>>
>>
>> Am 2022-10-20 um 05:15 schrieb Prike Liang:
>>> This dummy cache info will enable kfd base function support.
>>>
>>> Signed-off-by: Prike Liang <Prike.Liang@amd.com>
>>> ---
>>>     drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 55 +++++++++++++++++++++++++--
>>>     1 file changed, 52 insertions(+), 3 deletions(-)
>>>
[snip]
>>> @@ -1528,7 +1574,10 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,
>>>                                 kfd_fill_gpu_cache_info_from_gfx_config(kdev, pcache_info);
>>>                         break;
>>>                 default:
>>> -                     return -EINVAL;
>>> +                     pcache_info = dummy_cache_info;
>>> +                     num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
>>> +                     pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
>>> +                     break;
>> Could we make this return an error if the amdgpu.exp_hw_support module parameter is not set?
>>
>> Regards,
>>      Felix
>>
>> [Prike] It's fine to protect this dummy info by checking the parameter amdgpu_exp_hw_support, but it may not friendly to end user by adding the parameter and some guys will still report KFD not enabled for this parameter setting problem. The original idea is the end user will not aware the dummy cache info and only alert the warning message to developer.
> I thought the intention was to simplify bring-up but make sure that valid cache info is available by the time a chip goes into production.
> Therefore, normal end users should never need to set the amdgpu_exp_hw_support option. I think you're saying that we would go to production with dummy info. That seems like a bad idea to me.
>
> Regards,
>     Felix
>
> [Prike]  Sorry for the confusion. In fact, this dummy cache info only used before production and meanwhile needn't require any parameter setting for CQE do KFD test. Anyway if you still have concern on this solution I will add the condition of checking amdgpu_exp_hw_support.

The idea to control this with a module parameter was to cause a more obvious failure if we don't have correct cache info before going to production. Just a warning in the log file is too easy to miss or ignore. Of course, if QA gets into the habit of testing with amdgpu_exp_hw_support, then this may not solve the problem. You need to have at least one test pass without amdgpu_exp_hw_support to catch missing cache info.

Regards,
   Felix

Get your point. As to the KFD support on a NPI will be tracked by a ticket which make sure the real cache info update later after this dummy cache info assigned in the early BU phase.

Thanks,
Prike

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2022-10-24 13:11 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-20  9:15 [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Prike Liang
2022-10-20  9:15 ` [PATCH 2/2] drm/amdkfd: update gfx1037 Lx cache setting Prike Liang
2022-10-20 13:15   ` Alex Deucher
2022-10-20 16:02 ` [PATCH 1/2] drm/amdkfd: introduce dummy cache info for property asic Felix Kuehling
2022-10-21  1:50   ` Liang, Prike
2022-10-21  5:10     ` Felix Kuehling
2022-10-21 13:05       ` Liang, Prike
2022-10-21 20:53         ` Felix Kuehling
2022-10-24 13:11           ` Liang, Prike

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.