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From: "Jongsung Kim" <neidhard.kim@lge.com>
To: "'Stephen Warren'" <swarren@wwwdotorg.org>
Cc: "'Russell King'" <linux@arm.linux.org.uk>,
	"'Greg Kroah-Hartman'" <gregkh@linuxfoundation.org>,
	<jslaby@suse.cz>, <linux-serial@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-rpi-kernel@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Date: Wed, 15 May 2013 10:00:07 +0900	[thread overview]
Message-ID: <022d01ce5107$8bc668e0$a3533aa0$@lge.com> (raw)
In-Reply-To: <5192A692.4010700@wwwdotorg.org>

Stephen Warren <swarren@wwwdotorg.org> :
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
> the BCM2835 chip), I see:
>
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO.
> Perhaps this is a configurable property of the IP block, not something
that
> all r1p5 have?

All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:

r1p4-r1p5	Contains the following differences in functionality:
		* The receive and transmit FIFOs are increased to a depth of
32.
		* The Revision field in the UARTPeriphID2 Register on page
3-24
		  bits [7:4] now reads back as 0x3.


WARNING: multiple messages have this Message-ID (diff)
From: "Jongsung Kim" <neidhard.kim@lge.com>
To: 'Stephen Warren' <swarren@wwwdotorg.org>
Cc: 'Russell King' <linux@arm.linux.org.uk>,
	'Greg Kroah-Hartman' <gregkh@linuxfoundation.org>,
	jslaby@suse.cz, linux-serial@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-rpi-kernel@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org
Subject: RE: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Date: Wed, 15 May 2013 10:00:07 +0900	[thread overview]
Message-ID: <022d01ce5107$8bc668e0$a3533aa0$@lge.com> (raw)
In-Reply-To: <5192A692.4010700@wwwdotorg.org>

Stephen Warren <swarren@wwwdotorg.org> :
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
> the BCM2835 chip), I see:
>
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO.
> Perhaps this is a configurable property of the IP block, not something
that
> all r1p5 have?

All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:

r1p4-r1p5	Contains the following differences in functionality:
		* The receive and transmit FIFOs are increased to a depth of
32.
		* The Revision field in the UARTPeriphID2 Register on page
3-24
		  bits [7:4] now reads back as 0x3.


WARNING: multiple messages have this Message-ID (diff)
From: neidhard.kim@lge.com (Jongsung Kim)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5
Date: Wed, 15 May 2013 10:00:07 +0900	[thread overview]
Message-ID: <022d01ce5107$8bc668e0$a3533aa0$@lge.com> (raw)
In-Reply-To: <5192A692.4010700@wwwdotorg.org>

Stephen Warren <swarren@wwwdotorg.org> :
> Looking at BCM2835-ARM-Peripherals.pdf (i.e. the public documentation for
> the BCM2835 chip), I see:
>
> =====
> The UART provides:
> * Separate 16x8 transmit and 16x12 receive FIFO memory.
> ...
> For the in-depth UART overview, please, refer to the ARM PrimeCell UART
> (PL011) Revision: r1p5 Technical Reference Manual.
> =====
>
> That seems to imply that not all r1p5 PL011s actually have a depth-32
FIFO.
> Perhaps this is a configurable property of the IP block, not something
that
> all r1p5 have?

All r1p5 have 32-byte FIFO depth and it's not configurable. From the PL011
TRM:

r1p4-r1p5	Contains the following differences in functionality:
		* The receive and transmit FIFOs are increased to a depth of
32.
		* The Revision field in the UARTPeriphID2 Register on page
3-24
		  bits [7:4] now reads back as 0x3.

  parent reply	other threads:[~2013-05-15  1:00 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-04-12  9:18 [PATCH] ARM: PL011: add support for extended FIFO-size of PL011-r1p5 Jongsung Kim
2013-04-12  9:18 ` Jongsung Kim
2013-04-19 12:58 ` Russell King - ARM Linux
2013-05-14  5:56 ` Stephen Warren
2013-05-14  5:56   ` Stephen Warren
2013-05-14  5:56   ` Stephen Warren
2013-05-14  7:15   ` Jongsung Kim
2013-05-14  7:15     ` Jongsung Kim
2013-05-14  7:15     ` Jongsung Kim
2013-05-14 21:03     ` Stephen Warren
2013-05-14 21:03       ` Stephen Warren
2013-05-14 22:50       ` Russell King - ARM Linux
2013-05-14 22:50         ` Russell King - ARM Linux
2013-05-15  1:00       ` Jongsung Kim [this message]
2013-05-15  1:00         ` Jongsung Kim
2013-05-15  1:00         ` Jongsung Kim
2013-05-15  4:59         ` Stephen Warren
2013-05-15  4:59           ` Stephen Warren
2013-05-15  9:37           ` Russell King - ARM Linux
2013-05-15  9:37             ` Russell King - ARM Linux
2013-05-16 13:26           ` Jongsung Kim
2013-05-16 13:26             ` Jongsung Kim
2013-05-16 13:26             ` Jongsung Kim
2013-05-21  1:39           ` Jongsung Kim
2013-05-21  1:39             ` Jongsung Kim
2013-05-21  1:39             ` Jongsung Kim
2013-05-21  2:12             ` Stephen Warren
2013-05-21  2:12               ` Stephen Warren
2013-05-21  6:02               ` [PATCH] ARM: bcm2835: override the HW UART periphid Jongsung Kim
2013-05-21  6:02                 ` Jongsung Kim
2013-05-21  6:07                 ` Jongsung Kim
2013-05-21  6:07                   ` Jongsung Kim
2013-05-21  6:07                   ` Jongsung Kim
2013-05-21  9:00                   ` Gordon Hollingworth
2013-05-21  9:00                     ` Gordon Hollingworth
2013-05-21  9:00                     ` Gordon Hollingworth
2013-05-21 16:34                 ` Stephen Warren
2013-05-21 16:34                   ` Stephen Warren
2013-05-22  1:43                   ` Stephen Warren
2013-05-22  1:43                     ` Stephen Warren
2013-05-22  1:52                     ` Jongsung Kim
2013-05-22  1:52                       ` Jongsung Kim
2013-05-22  1:52                       ` Jongsung Kim

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