* [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:27 ` Murthy, Arun R
2022-08-17 1:23 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs Jani Nikula
` (43 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
In another long-overdue cleanup, add a display sub-struct to
drm_i915_private, and start moving display related members there. Start
with display funcs that need a rename anyway to not collide with the new
display member.
Add a new header under display/ for defining struct intel_display.
Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++-------
.../gpu/drm/i915/display/intel_display_core.h | 38 +++++++++++++++++++
.../drm/i915/display/intel_modeset_setup.c | 2 +-
.../drm/i915/display/intel_plane_initial.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 21 ++--------
5 files changed, 57 insertions(+), 34 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_core.h
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f143adefdf38..24ab1501beea 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display->get_pipe_config(crtc, crtc_state))
+ if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display->crtc_enable(state, crtc);
+ dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
return;
@@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display->crtc_disable(state, crtc);
+ dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display->commit_modeset_enables(state);
+ dev_priv->display.funcs.crtc->commit_modeset_enables(state);
intel_encoders_update_complete(state);
@@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
-static const struct drm_i915_display_funcs skl_display_funcs = {
+static const struct intel_display_funcs skl_display_funcs = {
.get_pipe_config = hsw_get_pipe_config,
.crtc_enable = hsw_crtc_enable,
.crtc_disable = hsw_crtc_disable,
@@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs skl_display_funcs = {
.get_initial_plane_config = skl_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs ddi_display_funcs = {
+static const struct intel_display_funcs ddi_display_funcs = {
.get_pipe_config = hsw_get_pipe_config,
.crtc_enable = hsw_crtc_enable,
.crtc_disable = hsw_crtc_disable,
@@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs ddi_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs pch_split_display_funcs = {
+static const struct intel_display_funcs pch_split_display_funcs = {
.get_pipe_config = ilk_get_pipe_config,
.crtc_enable = ilk_crtc_enable,
.crtc_disable = ilk_crtc_disable,
@@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs pch_split_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs vlv_display_funcs = {
+static const struct intel_display_funcs vlv_display_funcs = {
.get_pipe_config = i9xx_get_pipe_config,
.crtc_enable = valleyview_crtc_enable,
.crtc_disable = i9xx_crtc_disable,
@@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs vlv_display_funcs = {
.get_initial_plane_config = i9xx_get_initial_plane_config,
};
-static const struct drm_i915_display_funcs i9xx_display_funcs = {
+static const struct intel_display_funcs i9xx_display_funcs = {
.get_pipe_config = i9xx_get_pipe_config,
.crtc_enable = i9xx_crtc_enable,
.crtc_disable = i9xx_crtc_disable,
@@ -8372,16 +8372,16 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display = &skl_display_funcs;
+ dev_priv->display.funcs.crtc = &skl_display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display = &ddi_display_funcs;
+ dev_priv->display.funcs.crtc = &ddi_display_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display = &pch_split_display_funcs;
+ dev_priv->display.funcs.crtc = &pch_split_display_funcs;
} else if (IS_CHERRYVIEW(dev_priv) ||
IS_VALLEYVIEW(dev_priv)) {
- dev_priv->display = &vlv_display_funcs;
+ dev_priv->display.funcs.crtc = &vlv_display_funcs;
} else {
- dev_priv->display = &i9xx_display_funcs;
+ dev_priv->display.funcs.crtc = &i9xx_display_funcs;
}
intel_fdi_init_hook(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
new file mode 100644
index 000000000000..aafe548875cc
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_CORE_H__
+#define __INTEL_DISPLAY_CORE_H__
+
+#include <linux/types.h>
+
+struct intel_atomic_state;
+struct intel_crtc;
+struct intel_crtc_state;
+struct intel_initial_plane_config;
+
+struct intel_display_funcs {
+ /* Returns the active state of the crtc, and if the crtc is active,
+ * fills out the pipe-config with the hw state. */
+ bool (*get_pipe_config)(struct intel_crtc *,
+ struct intel_crtc_state *);
+ void (*get_initial_plane_config)(struct intel_crtc *,
+ struct intel_initial_plane_config *);
+ void (*crtc_enable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*crtc_disable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*commit_modeset_enables)(struct intel_atomic_state *state);
+};
+
+struct intel_display {
+ /* Display functions */
+ struct {
+ /* Top level crtc-ish functions */
+ const struct intel_display_funcs *crtc;
+ } funcs;
+};
+
+#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index f0e04d3904c6..e0d5c58c2037 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -70,7 +70,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
- i915->display->crtc_disable(to_intel_atomic_state(state), crtc);
+ i915->display.funcs.crtc->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index d10f27d0b7b0..10e10ffdc13c 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -311,7 +311,7 @@ void intel_crtc_initial_plane_config(struct intel_crtc *crtc)
* can even allow for smooth boot transitions if the BIOS
* fb is large enough for the active pipe configuration.
*/
- dev_priv->display->get_initial_plane_config(crtc, &plane_config);
+ dev_priv->display.funcs.crtc->get_initial_plane_config(crtc, &plane_config);
/*
* If the fb is shared between multiple heads, we'll
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 086bbe8945d6..3df38531a54b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -39,6 +39,7 @@
#include "display/intel_cdclk.h"
#include "display/intel_display.h"
+#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
@@ -96,7 +97,6 @@ struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_gmbus;
struct intel_hotplug_funcs;
-struct intel_initial_plane_config;
struct intel_limit;
struct intel_overlay;
struct intel_overlay_error_state;
@@ -177,20 +177,6 @@ struct drm_i915_wm_disp_funcs {
int (*compute_global_watermarks)(struct intel_atomic_state *state);
};
-struct drm_i915_display_funcs {
- /* Returns the active state of the crtc, and if the crtc is active,
- * fills out the pipe-config with the hw state. */
- bool (*get_pipe_config)(struct intel_crtc *,
- struct intel_crtc_state *);
- void (*get_initial_plane_config)(struct intel_crtc *,
- struct intel_initial_plane_config *);
- void (*crtc_enable)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*crtc_disable)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*commit_modeset_enables)(struct intel_atomic_state *state);
-};
-
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -374,6 +360,8 @@ struct intel_audio_private {
struct drm_i915_private {
struct drm_device drm;
+ struct intel_display display;
+
/* FIXME: Device release actions should all be moved to drmm_ */
bool do_release;
@@ -532,9 +520,6 @@ struct drm_i915_private {
/* display pll funcs */
const struct intel_dpll_funcs *dpll_funcs;
- /* Display functions */
- const struct drm_i915_display_funcs *display;
-
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 ` [Intel-gfx] [PATCH 01/39] " Jani Nikula
@ 2022-08-12 4:27 ` Murthy, Arun R
2022-08-12 6:40 ` Jani Nikula
2022-08-17 1:23 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:27 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to
> drm_i915_private
>
> In another long-overdue cleanup, add a display sub-struct to
> drm_i915_private, and start moving display related members there. Start
> with display funcs that need a rename anyway to not collide with the new
> display member.
>
> Add a new header under display/ for defining struct intel_display.
>
> Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++-------
> .../gpu/drm/i915/display/intel_display_core.h | 38 +++++++++++++++++++
> .../drm/i915/display/intel_modeset_setup.c | 2 +-
> .../drm/i915/display/intel_plane_initial.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 21 ++--------
> 5 files changed, 57 insertions(+), 34 deletions(-) create mode 100644
> drivers/gpu/drm/i915/display/intel_display_core.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index f143adefdf38..24ab1501beea 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct
> intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> - if (!i915->display->get_pipe_config(crtc, crtc_state))
> + if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
> return false;
>
> crtc_state->hw.active = true;
> @@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct
> intel_atomic_state *state,
>
> intel_crtc_update_active_timings(new_crtc_state);
>
> - dev_priv->display->crtc_enable(state, crtc);
> + dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
>
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> return;
> @@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct
> intel_atomic_state *state,
> */
> intel_crtc_disable_pipe_crc(crtc);
>
> - dev_priv->display->crtc_disable(state, crtc);
> + dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
> @@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct
> intel_atomic_state *state)
> }
>
> /* Now enable the clocks, plane, pipe, and connectors that we set
> up. */
> - dev_priv->display->commit_modeset_enables(state);
> + dev_priv->display.funcs.crtc->commit_modeset_enables(state);
>
> intel_encoders_update_complete(state);
>
> @@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs
> intel_mode_funcs = {
> .atomic_state_free = intel_atomic_state_free, };
>
> -static const struct drm_i915_display_funcs skl_display_funcs = {
> +static const struct intel_display_funcs skl_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
> @@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs
> skl_display_funcs = {
> .get_initial_plane_config = skl_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs ddi_display_funcs = {
> +static const struct intel_display_funcs ddi_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
> @@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs
> ddi_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs pch_split_display_funcs = {
> +static const struct intel_display_funcs pch_split_display_funcs = {
> .get_pipe_config = ilk_get_pipe_config,
> .crtc_enable = ilk_crtc_enable,
> .crtc_disable = ilk_crtc_disable,
> @@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs
> pch_split_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs vlv_display_funcs = {
> +static const struct intel_display_funcs vlv_display_funcs = {
> .get_pipe_config = i9xx_get_pipe_config,
> .crtc_enable = valleyview_crtc_enable,
> .crtc_disable = i9xx_crtc_disable,
> @@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs
> vlv_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config, };
>
> -static const struct drm_i915_display_funcs i9xx_display_funcs = {
> +static const struct intel_display_funcs i9xx_display_funcs = {
> .get_pipe_config = i9xx_get_pipe_config,
> .crtc_enable = i9xx_crtc_enable,
> .crtc_disable = i9xx_crtc_disable,
> @@ -8372,16 +8372,16 @@ void intel_init_display_hooks(struct
> drm_i915_private *dev_priv)
> intel_dpll_init_clock_hook(dev_priv);
>
> if (DISPLAY_VER(dev_priv) >= 9) {
> - dev_priv->display = &skl_display_funcs;
> + dev_priv->display.funcs.crtc = &skl_display_funcs;
> } else if (HAS_DDI(dev_priv)) {
> - dev_priv->display = &ddi_display_funcs;
> + dev_priv->display.funcs.crtc = &ddi_display_funcs;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->display = &pch_split_display_funcs;
> + dev_priv->display.funcs.crtc = &pch_split_display_funcs;
> } else if (IS_CHERRYVIEW(dev_priv) ||
> IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->display = &vlv_display_funcs;
> + dev_priv->display.funcs.crtc = &vlv_display_funcs;
> } else {
> - dev_priv->display = &i9xx_display_funcs;
> + dev_priv->display.funcs.crtc = &i9xx_display_funcs;
> }
>
> intel_fdi_init_hook(dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> new file mode 100644
> index 000000000000..aafe548875cc
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_CORE_H__
> +#define __INTEL_DISPLAY_CORE_H__
> +
> +#include <linux/types.h>
> +
> +struct intel_atomic_state;
> +struct intel_crtc;
> +struct intel_crtc_state;
> +struct intel_initial_plane_config;
> +
> +struct intel_display_funcs {
> + /* Returns the active state of the crtc, and if the crtc is active,
> + * fills out the pipe-config with the hw state. */
Can this be changed to multi-line commenting style.
/*
*
*/
> + bool (*get_pipe_config)(struct intel_crtc *,
> + struct intel_crtc_state *);
> + void (*get_initial_plane_config)(struct intel_crtc *,
> + struct intel_initial_plane_config *);
> + void (*crtc_enable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*crtc_disable)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*commit_modeset_enables)(struct intel_atomic_state *state);
Can this be changed to something meaningful word, something like update_modeset()
> };
> +
> +struct intel_display {
> + /* Display functions */
> + struct {
> + /* Top level crtc-ish functions */
> + const struct intel_display_funcs *crtc;
> + } funcs;
> +};
> +
> +#endif /* __INTEL_DISPLAY_CORE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> index f0e04d3904c6..e0d5c58c2037 100644
> --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
> @@ -70,7 +70,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
> *crtc,
>
> drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
>
> - i915->display->crtc_disable(to_intel_atomic_state(state), crtc);
> + i915->display.funcs.crtc->crtc_disable(to_intel_atomic_state(state),
> +crtc);
>
> drm_atomic_state_put(state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index d10f27d0b7b0..10e10ffdc13c 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -311,7 +311,7 @@ void intel_crtc_initial_plane_config(struct intel_crtc
> *crtc)
> * can even allow for smooth boot transitions if the BIOS
> * fb is large enough for the active pipe configuration.
> */
> - dev_priv->display->get_initial_plane_config(crtc, &plane_config);
> + dev_priv->display.funcs.crtc->get_initial_plane_config(crtc,
> +&plane_config);
>
> /*
> * If the fb is shared between multiple heads, we'll diff --git
> a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 086bbe8945d6..3df38531a54b 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -39,6 +39,7 @@
>
> #include "display/intel_cdclk.h"
> #include "display/intel_display.h"
> +#include "display/intel_display_core.h"
> #include "display/intel_display_power.h"
> #include "display/intel_dmc.h"
> #include "display/intel_dpll_mgr.h"
> @@ -96,7 +97,6 @@ struct intel_fbdev;
> struct intel_fdi_funcs;
> struct intel_gmbus;
> struct intel_hotplug_funcs;
> -struct intel_initial_plane_config;
> struct intel_limit;
> struct intel_overlay;
> struct intel_overlay_error_state;
> @@ -177,20 +177,6 @@ struct drm_i915_wm_disp_funcs {
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> };
>
> -struct drm_i915_display_funcs {
> - /* Returns the active state of the crtc, and if the crtc is active,
> - * fills out the pipe-config with the hw state. */
> - bool (*get_pipe_config)(struct intel_crtc *,
> - struct intel_crtc_state *);
> - void (*get_initial_plane_config)(struct intel_crtc *,
> - struct intel_initial_plane_config *);
> - void (*crtc_enable)(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> - void (*crtc_disable)(struct intel_atomic_state *state,
> - struct intel_crtc *crtc);
> - void (*commit_modeset_enables)(struct intel_atomic_state *state);
> -};
> -
> #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address
> space */
>
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> @@ -374,6 +360,8 @@ struct intel_audio_private { struct drm_i915_private
> {
> struct drm_device drm;
>
> + struct intel_display display;
> +
> /* FIXME: Device release actions should all be moved to drmm_ */
> bool do_release;
>
> @@ -532,9 +520,6 @@ struct drm_i915_private {
> /* display pll funcs */
> const struct intel_dpll_funcs *dpll_funcs;
>
> - /* Display functions */
> - const struct drm_i915_display_funcs *display;
> -
> /* Display internal color functions */
> const struct intel_color_funcs *color_funcs;
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-12 4:27 ` Murthy, Arun R
@ 2022-08-12 6:40 ` Jani Nikula
2022-08-16 3:31 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:40 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -0,0 +1,38 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2022 Intel Corporation
>> + */
>> +
>> +#ifndef __INTEL_DISPLAY_CORE_H__
>> +#define __INTEL_DISPLAY_CORE_H__
>> +
>> +#include <linux/types.h>
>> +
>> +struct intel_atomic_state;
>> +struct intel_crtc;
>> +struct intel_crtc_state;
>> +struct intel_initial_plane_config;
>> +
>> +struct intel_display_funcs {
>> + /* Returns the active state of the crtc, and if the crtc is active,
>> + * fills out the pipe-config with the hw state. */
> Can this be changed to multi-line commenting style.
Yeah.
> /*
> *
> */
>> + bool (*get_pipe_config)(struct intel_crtc *,
>> + struct intel_crtc_state *);
>> + void (*get_initial_plane_config)(struct intel_crtc *,
>> + struct intel_initial_plane_config *);
>> + void (*crtc_enable)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*crtc_disable)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*commit_modeset_enables)(struct intel_atomic_state *state);
>
> Can this be changed to something meaningful word, something like update_modeset()
It's already borderline doing too much in one patch to rename the
struct, and definitely too much to rename the hook. Maybe in another
patch.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-12 6:40 ` Jani Nikula
@ 2022-08-16 3:31 ` Murthy, Arun R
2022-08-16 7:37 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 3:31 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:10 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to
> drm_i915_private
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -0,0 +1,38 @@
> >> +/* SPDX-License-Identifier: MIT */
> >> +/*
> >> + * Copyright © 2022 Intel Corporation */
> >> +
> >> +#ifndef __INTEL_DISPLAY_CORE_H__
> >> +#define __INTEL_DISPLAY_CORE_H__
> >> +
> >> +#include <linux/types.h>
> >> +
> >> +struct intel_atomic_state;
> >> +struct intel_crtc;
> >> +struct intel_crtc_state;
> >> +struct intel_initial_plane_config;
> >> +
> >> +struct intel_display_funcs {
> >> + /* Returns the active state of the crtc, and if the crtc is active,
> >> + * fills out the pipe-config with the hw state. */
> > Can this be changed to multi-line commenting style.
>
> Yeah.
>
> > /*
> > *
> > */
> >> + bool (*get_pipe_config)(struct intel_crtc *,
> >> + struct intel_crtc_state *);
> >> + void (*get_initial_plane_config)(struct intel_crtc *,
> >> + struct intel_initial_plane_config *);
> >> + void (*crtc_enable)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + void (*crtc_disable)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + void (*commit_modeset_enables)(struct intel_atomic_state
> >> + *state);
> >
> > Can this be changed to something meaningful word, something like
> > update_modeset()
>
> It's already borderline doing too much in one patch to rename the struct, and
> definitely too much to rename the hook. Maybe in another patch.
>
Thanks for accepting, would this come as part of this series itself?
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-16 3:31 ` Murthy, Arun R
@ 2022-08-16 7:37 ` Jani Nikula
2022-08-16 7:40 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-16 7:37 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Friday, August 12, 2022 12:10 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Subject: RE: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to
>> drm_i915_private
>>
>> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> @@ -0,0 +1,38 @@
>> >> +/* SPDX-License-Identifier: MIT */
>> >> +/*
>> >> + * Copyright © 2022 Intel Corporation */
>> >> +
>> >> +#ifndef __INTEL_DISPLAY_CORE_H__
>> >> +#define __INTEL_DISPLAY_CORE_H__
>> >> +
>> >> +#include <linux/types.h>
>> >> +
>> >> +struct intel_atomic_state;
>> >> +struct intel_crtc;
>> >> +struct intel_crtc_state;
>> >> +struct intel_initial_plane_config;
>> >> +
>> >> +struct intel_display_funcs {
>> >> + /* Returns the active state of the crtc, and if the crtc is active,
>> >> + * fills out the pipe-config with the hw state. */
>> > Can this be changed to multi-line commenting style.
>>
>> Yeah.
>>
>> > /*
>> > *
>> > */
>> >> + bool (*get_pipe_config)(struct intel_crtc *,
>> >> + struct intel_crtc_state *);
>> >> + void (*get_initial_plane_config)(struct intel_crtc *,
>> >> + struct intel_initial_plane_config *);
>> >> + void (*crtc_enable)(struct intel_atomic_state *state,
>> >> + struct intel_crtc *crtc);
>> >> + void (*crtc_disable)(struct intel_atomic_state *state,
>> >> + struct intel_crtc *crtc);
>> >> + void (*commit_modeset_enables)(struct intel_atomic_state
>> >> + *state);
>> >
>> > Can this be changed to something meaningful word, something like
>> > update_modeset()
>>
>> It's already borderline doing too much in one patch to rename the struct, and
>> definitely too much to rename the hook. Maybe in another patch.
>>
> Thanks for accepting, would this come as part of this series itself?
I think this series is already growing too big, I'll want to start
merging before adding new patches. But there's more things to move to
the display sub-struct too, so there'll be more patches.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-16 7:37 ` Jani Nikula
@ 2022-08-16 7:40 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 7:40 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, August 16, 2022 1:07 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to
> drm_i915_private
>
> On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Friday, August 12, 2022 12:10 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> >> Subject: RE: [Intel-gfx] [PATCH 01/39] drm/i915: add display
> >> sub-struct to drm_i915_private
> >>
> >> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> @@ -0,0 +1,38 @@
> >> >> +/* SPDX-License-Identifier: MIT */
> >> >> +/*
> >> >> + * Copyright © 2022 Intel Corporation */
> >> >> +
> >> >> +#ifndef __INTEL_DISPLAY_CORE_H__
> >> >> +#define __INTEL_DISPLAY_CORE_H__
> >> >> +
> >> >> +#include <linux/types.h>
> >> >> +
> >> >> +struct intel_atomic_state;
> >> >> +struct intel_crtc;
> >> >> +struct intel_crtc_state;
> >> >> +struct intel_initial_plane_config;
> >> >> +
> >> >> +struct intel_display_funcs {
> >> >> + /* Returns the active state of the crtc, and if the crtc is active,
> >> >> + * fills out the pipe-config with the hw state. */
> >> > Can this be changed to multi-line commenting style.
> >>
> >> Yeah.
> >>
> >> > /*
> >> > *
> >> > */
> >> >> + bool (*get_pipe_config)(struct intel_crtc *,
> >> >> + struct intel_crtc_state *);
> >> >> + void (*get_initial_plane_config)(struct intel_crtc *,
> >> >> + struct intel_initial_plane_config *);
> >> >> + void (*crtc_enable)(struct intel_atomic_state *state,
> >> >> + struct intel_crtc *crtc);
> >> >> + void (*crtc_disable)(struct intel_atomic_state *state,
> >> >> + struct intel_crtc *crtc);
> >> >> + void (*commit_modeset_enables)(struct intel_atomic_state
> >> >> + *state);
> >> >
> >> > Can this be changed to something meaningful word, something like
> >> > update_modeset()
> >>
> >> It's already borderline doing too much in one patch to rename the
> >> struct, and definitely too much to rename the hook. Maybe in another
> patch.
> >>
> > Thanks for accepting, would this come as part of this series itself?
>
> I think this series is already growing too big, I'll want to start merging before
> adding new patches. But there's more things to move to the display sub-
> struct too, so there'll be more patches.
>
I hope a TODO would be added for this!
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 ` [Intel-gfx] [PATCH 01/39] " Jani Nikula
2022-08-12 4:27 ` Murthy, Arun R
@ 2022-08-17 1:23 ` Lucas De Marchi
2022-08-17 6:48 ` Jani Nikula
1 sibling, 1 reply; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 1:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:12PM +0300, Jani Nikula wrote:
>In another long-overdue cleanup, add a display sub-struct to
>drm_i915_private, and start moving display related members there. Start
>with display funcs that need a rename anyway to not collide with the new
>display member.
>
>Add a new header under display/ for defining struct intel_display.
>
>Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++-------
> .../gpu/drm/i915/display/intel_display_core.h | 38 +++++++++++++++++++
> .../drm/i915/display/intel_modeset_setup.c | 2 +-
> .../drm/i915/display/intel_plane_initial.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 21 ++--------
> 5 files changed, 57 insertions(+), 34 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/intel_display_core.h
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index f143adefdf38..24ab1501beea 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
>- if (!i915->display->get_pipe_config(crtc, crtc_state))
>+ if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
> return false;
>
> crtc_state->hw.active = true;
>@@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>
> intel_crtc_update_active_timings(new_crtc_state);
>
>- dev_priv->display->crtc_enable(state, crtc);
>+ dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
>
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> return;
>@@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
> */
> intel_crtc_disable_pipe_crc(crtc);
>
>- dev_priv->display->crtc_disable(state, crtc);
>+ dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
lgtm. Regarding names: it's a little weird to have "crtc doubled in the funcs.crtc->crtc_
and it not being consistent accross all functions
> crtc->active = false;
> intel_fbc_disable(crtc);
> intel_disable_shared_dpll(old_crtc_state);
>@@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> }
>
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>- dev_priv->display->commit_modeset_enables(state);
>+ dev_priv->display.funcs.crtc->commit_modeset_enables(state);
>
> intel_encoders_update_complete(state);
>
>@@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
> .atomic_state_free = intel_atomic_state_free,
> };
>
>-static const struct drm_i915_display_funcs skl_display_funcs = {
>+static const struct intel_display_funcs skl_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
>@@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs skl_display_funcs = {
> .get_initial_plane_config = skl_get_initial_plane_config,
> };
>
>-static const struct drm_i915_display_funcs ddi_display_funcs = {
>+static const struct intel_display_funcs ddi_display_funcs = {
> .get_pipe_config = hsw_get_pipe_config,
> .crtc_enable = hsw_crtc_enable,
> .crtc_disable = hsw_crtc_disable,
>@@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs ddi_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config,
> };
>
>-static const struct drm_i915_display_funcs pch_split_display_funcs = {
>+static const struct intel_display_funcs pch_split_display_funcs = {
> .get_pipe_config = ilk_get_pipe_config,
> .crtc_enable = ilk_crtc_enable,
> .crtc_disable = ilk_crtc_disable,
>@@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs pch_split_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config,
> };
>
>-static const struct drm_i915_display_funcs vlv_display_funcs = {
>+static const struct intel_display_funcs vlv_display_funcs = {
> .get_pipe_config = i9xx_get_pipe_config,
> .crtc_enable = valleyview_crtc_enable,
> .crtc_disable = i9xx_crtc_disable,
>@@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs vlv_display_funcs = {
> .get_initial_plane_config = i9xx_get_initial_plane_config,
> };
>
>-static const struct drm_i915_display_funcs i9xx_display_funcs = {
>+static const struct intel_display_funcs i9xx_display_funcs = {
> .get_pipe_config = i9xx_get_pipe_config,
> .crtc_enable = i9xx_crtc_enable,
> .crtc_disable = i9xx_crtc_disable,
>@@ -8372,16 +8372,16 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
> intel_dpll_init_clock_hook(dev_priv);
>
> if (DISPLAY_VER(dev_priv) >= 9) {
>- dev_priv->display = &skl_display_funcs;
>+ dev_priv->display.funcs.crtc = &skl_display_funcs;
> } else if (HAS_DDI(dev_priv)) {
>- dev_priv->display = &ddi_display_funcs;
>+ dev_priv->display.funcs.crtc = &ddi_display_funcs;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
>- dev_priv->display = &pch_split_display_funcs;
>+ dev_priv->display.funcs.crtc = &pch_split_display_funcs;
> } else if (IS_CHERRYVIEW(dev_priv) ||
> IS_VALLEYVIEW(dev_priv)) {
>- dev_priv->display = &vlv_display_funcs;
>+ dev_priv->display.funcs.crtc = &vlv_display_funcs;
> } else {
>- dev_priv->display = &i9xx_display_funcs;
>+ dev_priv->display.funcs.crtc = &i9xx_display_funcs;
> }
>
> intel_fdi_init_hook(dev_priv);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>new file mode 100644
>index 000000000000..aafe548875cc
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -0,0 +1,38 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2022 Intel Corporation
>+ */
>+
>+#ifndef __INTEL_DISPLAY_CORE_H__
>+#define __INTEL_DISPLAY_CORE_H__
>+
>+#include <linux/types.h>
>+
>+struct intel_atomic_state;
>+struct intel_crtc;
>+struct intel_crtc_state;
>+struct intel_initial_plane_config;
>+
>+struct intel_display_funcs {
in the same line as comment above. Maybe we could give this struct a
better name? Because it's already inside a intel_display.funcs.crtc
display->funcs.crtc->get_pipe_config()
display->funcs.crtc->get_initial_plane_nfig()
display->funcs.crtc->enable()
display->funcs.crtc->disable()
display->funcs.crtc->commit_modeset_enables()
and then call this `struct intel_crtc_funcs`.
This can be done later as this commit itself is basically moving things
with the same name inside a substruct.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-17 1:23 ` Lucas De Marchi
@ 2022-08-17 6:48 ` Jani Nikula
2022-08-17 8:07 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-17 6:48 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Aug 11, 2022 at 06:07:12PM +0300, Jani Nikula wrote:
>>In another long-overdue cleanup, add a display sub-struct to
>>drm_i915_private, and start moving display related members there. Start
>>with display funcs that need a rename anyway to not collide with the new
>>display member.
>>
>>Add a new header under display/ for defining struct intel_display.
>>
>>Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>---
>> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++-------
>> .../gpu/drm/i915/display/intel_display_core.h | 38 +++++++++++++++++++
>> .../drm/i915/display/intel_modeset_setup.c | 2 +-
>> .../drm/i915/display/intel_plane_initial.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 21 ++--------
>> 5 files changed, 57 insertions(+), 34 deletions(-)
>> create mode 100644 drivers/gpu/drm/i915/display/intel_display_core.h
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>index f143adefdf38..24ab1501beea 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display.c
>>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>>@@ -4144,7 +4144,7 @@ bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>>
>>- if (!i915->display->get_pipe_config(crtc, crtc_state))
>>+ if (!i915->display.funcs.crtc->get_pipe_config(crtc, crtc_state))
>> return false;
>>
>> crtc_state->hw.active = true;
>>@@ -7119,7 +7119,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
>>
>> intel_crtc_update_active_timings(new_crtc_state);
>>
>>- dev_priv->display->crtc_enable(state, crtc);
>>+ dev_priv->display.funcs.crtc->crtc_enable(state, crtc);
>>
>> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
>> return;
>>@@ -7198,7 +7198,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
>> */
>> intel_crtc_disable_pipe_crc(crtc);
>>
>>- dev_priv->display->crtc_disable(state, crtc);
>>+ dev_priv->display.funcs.crtc->crtc_disable(state, crtc);
>
> lgtm. Regarding names: it's a little weird to have "crtc doubled in the funcs.crtc->crtc_
> and it not being consistent accross all functions
>
>
>> crtc->active = false;
>> intel_fbc_disable(crtc);
>> intel_disable_shared_dpll(old_crtc_state);
>>@@ -7586,7 +7586,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>> }
>>
>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>- dev_priv->display->commit_modeset_enables(state);
>>+ dev_priv->display.funcs.crtc->commit_modeset_enables(state);
>>
>> intel_encoders_update_complete(state);
>>
>>@@ -8317,7 +8317,7 @@ static const struct drm_mode_config_funcs intel_mode_funcs = {
>> .atomic_state_free = intel_atomic_state_free,
>> };
>>
>>-static const struct drm_i915_display_funcs skl_display_funcs = {
>>+static const struct intel_display_funcs skl_display_funcs = {
>> .get_pipe_config = hsw_get_pipe_config,
>> .crtc_enable = hsw_crtc_enable,
>> .crtc_disable = hsw_crtc_disable,
>>@@ -8325,7 +8325,7 @@ static const struct drm_i915_display_funcs skl_display_funcs = {
>> .get_initial_plane_config = skl_get_initial_plane_config,
>> };
>>
>>-static const struct drm_i915_display_funcs ddi_display_funcs = {
>>+static const struct intel_display_funcs ddi_display_funcs = {
>> .get_pipe_config = hsw_get_pipe_config,
>> .crtc_enable = hsw_crtc_enable,
>> .crtc_disable = hsw_crtc_disable,
>>@@ -8333,7 +8333,7 @@ static const struct drm_i915_display_funcs ddi_display_funcs = {
>> .get_initial_plane_config = i9xx_get_initial_plane_config,
>> };
>>
>>-static const struct drm_i915_display_funcs pch_split_display_funcs = {
>>+static const struct intel_display_funcs pch_split_display_funcs = {
>> .get_pipe_config = ilk_get_pipe_config,
>> .crtc_enable = ilk_crtc_enable,
>> .crtc_disable = ilk_crtc_disable,
>>@@ -8341,7 +8341,7 @@ static const struct drm_i915_display_funcs pch_split_display_funcs = {
>> .get_initial_plane_config = i9xx_get_initial_plane_config,
>> };
>>
>>-static const struct drm_i915_display_funcs vlv_display_funcs = {
>>+static const struct intel_display_funcs vlv_display_funcs = {
>> .get_pipe_config = i9xx_get_pipe_config,
>> .crtc_enable = valleyview_crtc_enable,
>> .crtc_disable = i9xx_crtc_disable,
>>@@ -8349,7 +8349,7 @@ static const struct drm_i915_display_funcs vlv_display_funcs = {
>> .get_initial_plane_config = i9xx_get_initial_plane_config,
>> };
>>
>>-static const struct drm_i915_display_funcs i9xx_display_funcs = {
>>+static const struct intel_display_funcs i9xx_display_funcs = {
>> .get_pipe_config = i9xx_get_pipe_config,
>> .crtc_enable = i9xx_crtc_enable,
>> .crtc_disable = i9xx_crtc_disable,
>>@@ -8372,16 +8372,16 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
>> intel_dpll_init_clock_hook(dev_priv);
>>
>> if (DISPLAY_VER(dev_priv) >= 9) {
>>- dev_priv->display = &skl_display_funcs;
>>+ dev_priv->display.funcs.crtc = &skl_display_funcs;
>> } else if (HAS_DDI(dev_priv)) {
>>- dev_priv->display = &ddi_display_funcs;
>>+ dev_priv->display.funcs.crtc = &ddi_display_funcs;
>> } else if (HAS_PCH_SPLIT(dev_priv)) {
>>- dev_priv->display = &pch_split_display_funcs;
>>+ dev_priv->display.funcs.crtc = &pch_split_display_funcs;
>> } else if (IS_CHERRYVIEW(dev_priv) ||
>> IS_VALLEYVIEW(dev_priv)) {
>>- dev_priv->display = &vlv_display_funcs;
>>+ dev_priv->display.funcs.crtc = &vlv_display_funcs;
>> } else {
>>- dev_priv->display = &i9xx_display_funcs;
>>+ dev_priv->display.funcs.crtc = &i9xx_display_funcs;
>> }
>>
>> intel_fdi_init_hook(dev_priv);
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>new file mode 100644
>>index 000000000000..aafe548875cc
>>--- /dev/null
>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>@@ -0,0 +1,38 @@
>>+/* SPDX-License-Identifier: MIT */
>>+/*
>>+ * Copyright © 2022 Intel Corporation
>>+ */
>>+
>>+#ifndef __INTEL_DISPLAY_CORE_H__
>>+#define __INTEL_DISPLAY_CORE_H__
>>+
>>+#include <linux/types.h>
>>+
>>+struct intel_atomic_state;
>>+struct intel_crtc;
>>+struct intel_crtc_state;
>>+struct intel_initial_plane_config;
>>+
>>+struct intel_display_funcs {
>
> in the same line as comment above. Maybe we could give this struct a
> better name? Because it's already inside a intel_display.funcs.crtc
>
> display->funcs.crtc->get_pipe_config()
> display->funcs.crtc->get_initial_plane_nfig()
> display->funcs.crtc->enable()
> display->funcs.crtc->disable()
> display->funcs.crtc->commit_modeset_enables()
>
> and then call this `struct intel_crtc_funcs`.
>
> This can be done later as this commit itself is basically moving things
> with the same name inside a substruct.
I guess my question is, are the functions inside "crtc enough" to be
called intel_crtc_funcs? Though intel_display_funcs is really too
generic too.
Maybe I'll just go with crtc.
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Thanks!
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-17 6:48 ` Jani Nikula
@ 2022-08-17 8:07 ` Jani Nikula
2022-08-18 21:25 ` Lucas De Marchi
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-17 8:07 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, 17 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Thu, Aug 11, 2022 at 06:07:12PM +0300, Jani Nikula wrote:
>>>In another long-overdue cleanup, add a display sub-struct to
>>>drm_i915_private, and start moving display related members there. Start
>>>with display funcs that need a rename anyway to not collide with the new
>>>display member.
>>>
>>>Add a new header under display/ for defining struct intel_display.
>>>
>>>Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
[...]
>>>+struct intel_display_funcs {
>>
>> in the same line as comment above. Maybe we could give this struct a
>> better name? Because it's already inside a intel_display.funcs.crtc
>>
>> display->funcs.crtc->get_pipe_config()
>> display->funcs.crtc->get_initial_plane_nfig()
>> display->funcs.crtc->enable()
>> display->funcs.crtc->disable()
>> display->funcs.crtc->commit_modeset_enables()
>>
>> and then call this `struct intel_crtc_funcs`.
>>
>> This can be done later as this commit itself is basically moving things
>> with the same name inside a substruct.
>
> I guess my question is, are the functions inside "crtc enough" to be
> called intel_crtc_funcs? Though intel_display_funcs is really too
> generic too.
>
> Maybe I'll just go with crtc.
Mmh, except we already have a bunch of struct drm_crtc_funcs with
<platform>_crtc_funcs in intel_crtc.c. Too confusing.
struct intel_random_collection_of_display_funcs. :p
The easy choice *for now* would be to stick with the struct
intel_display_funcs and live with the display->funcs.display tautology.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 01/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-17 8:07 ` Jani Nikula
@ 2022-08-18 21:25 ` Lucas De Marchi
0 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-18 21:25 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Aug 17, 2022 at 11:07:46AM +0300, Jani Nikula wrote:
>On Wed, 17 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
>> On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> On Thu, Aug 11, 2022 at 06:07:12PM +0300, Jani Nikula wrote:
>>>>In another long-overdue cleanup, add a display sub-struct to
>>>>drm_i915_private, and start moving display related members there. Start
>>>>with display funcs that need a rename anyway to not collide with the new
>>>>display member.
>>>>
>>>>Add a new header under display/ for defining struct intel_display.
>>>>
>>>>Rename struct drm_i915_display_funcs to intel_display_funcs while at it.
>
>[...]
>
>>>>+struct intel_display_funcs {
>>>
>>> in the same line as comment above. Maybe we could give this struct a
>>> better name? Because it's already inside a intel_display.funcs.crtc
>>>
>>> display->funcs.crtc->get_pipe_config()
>>> display->funcs.crtc->get_initial_plane_nfig()
>>> display->funcs.crtc->enable()
>>> display->funcs.crtc->disable()
>>> display->funcs.crtc->commit_modeset_enables()
>>>
>>> and then call this `struct intel_crtc_funcs`.
>>>
>>> This can be done later as this commit itself is basically moving things
>>> with the same name inside a substruct.
>>
>> I guess my question is, are the functions inside "crtc enough" to be
>> called intel_crtc_funcs? Though intel_display_funcs is really too
>> generic too.
>>
>> Maybe I'll just go with crtc.
>
>Mmh, except we already have a bunch of struct drm_crtc_funcs with
><platform>_crtc_funcs in intel_crtc.c. Too confusing.
>
>struct intel_random_collection_of_display_funcs. :p
>
>The easy choice *for now* would be to stick with the struct
>intel_display_funcs and live with the display->funcs.display tautology.
Acked-by: Lucas De Marchi <lucas.demarchi@intel.com>
thanks
Lucas De Marchi
>
>BR,
>Jani.
>
>
>
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 01/39] " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:32 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs " Jani Nikula
` (42 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 70 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 4 --
3 files changed, 39 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 86a22c3766e5..6095f5800a2e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -79,26 +79,26 @@ struct intel_cdclk_funcs {
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
+ dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state *cdclk_config)
{
- return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
+ return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
+ return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -2080,7 +2080,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
+ if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
return;
intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
@@ -3187,78 +3187,78 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
- dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
- dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- dev_priv->cdclk_funcs = &icl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
dev_priv->cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
- dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
dev_priv->cdclk.table = glk_cdclk_table;
else
dev_priv->cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
- dev_priv->cdclk_funcs = &skl_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
- dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
} else if (IS_HASWELL(dev_priv)) {
- dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs = &chv_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
} else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
- dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_IRONLAKE(dev_priv)) {
- dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
} else if (IS_GM45(dev_priv)) {
- dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
} else if (IS_G45(dev_priv)) {
- dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
} else if (IS_I965GM(dev_priv)) {
- dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
} else if (IS_I965G(dev_priv)) {
- dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
- dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
} else if (IS_G33(dev_priv)) {
- dev_priv->cdclk_funcs = &g33_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
} else if (IS_I945GM(dev_priv)) {
- dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
} else if (IS_I945G(dev_priv)) {
- dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
} else if (IS_I915GM(dev_priv)) {
- dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
} else if (IS_I915G(dev_priv)) {
- dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
} else if (IS_I865G(dev_priv)) {
- dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
} else if (IS_I85X(dev_priv)) {
- dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
} else if (IS_I845G(dev_priv)) {
- dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
} else if (IS_I830(dev_priv)) {
- dev_priv->cdclk_funcs = &i830_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
}
- if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
+ if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
"Unknown platform. Assuming i830\n"))
- dev_priv->cdclk_funcs = &i830_cdclk_funcs;
+ dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index aafe548875cc..74e4ae0609b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
struct intel_atomic_state;
+struct intel_cdclk_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_initial_plane_config;
@@ -32,6 +33,9 @@ struct intel_display {
struct {
/* Top level crtc-ish functions */
const struct intel_display_funcs *crtc;
+
+ /* Display CDCLK functions */
+ const struct intel_cdclk_funcs *cdclk;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3df38531a54b..104095ea3738 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -84,7 +84,6 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_config;
-struct intel_cdclk_funcs;
struct intel_cdclk_state;
struct intel_cdclk_vals;
struct intel_color_funcs;
@@ -523,9 +522,6 @@ struct drm_i915_private {
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
- /* Display CDCLK functions */
- const struct intel_cdclk_funcs *cdclk_funcs;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs Jani Nikula
@ 2022-08-12 4:32 ` Murthy, Arun R
2022-08-12 6:43 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:32 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 70 +++++++++----------
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> 3 files changed, 39 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 86a22c3766e5..6095f5800a2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -79,26 +79,26 @@ struct intel_cdclk_funcs { void
> intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_config *cdclk_config) {
> - dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
> + dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
> }
>
> static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe)
> {
> - dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
> + dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config,
> +pipe);
> }
>
> static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
> struct intel_cdclk_state
> *cdclk_config) {
> - return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
> + return
> +dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
> }
>
> static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
> int cdclk)
> {
> - return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
> + return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
> }
>
> static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, @@
> -2080,7 +2080,7 @@ static void intel_set_cdclk(struct drm_i915_private
> *dev_priv,
> if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
> return;
>
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->cdclk_funcs-
> >set_cdclk))
> + if (drm_WARN_ON_ONCE(&dev_priv->drm,
> +!dev_priv->display.funcs.cdclk->set_cdclk))
> return;
>
> intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK
> to"); @@ -3187,78 +3187,78 @@ static const struct intel_cdclk_funcs
> i830_cdclk_funcs = { void intel_init_cdclk_hooks(struct drm_i915_private
> *dev_priv) {
> if (IS_DG2(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = dg2_cdclk_table;
> } else if (IS_ALDERLAKE_P(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> /* Wa_22011320316:adl-p[a0] */
> if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
> dev_priv->cdclk.table = adlp_a_step_cdclk_table;
> else
> dev_priv->cdclk.table = adlp_cdclk_table;
> } else if (IS_ROCKETLAKE(dev_priv)) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = rkl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 12) {
> - dev_priv->cdclk_funcs = &tgl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_JSL_EHL(dev_priv)) {
> - dev_priv->cdclk_funcs = &ehl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) >= 11) {
> - dev_priv->cdclk_funcs = &icl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
> dev_priv->cdclk.table = icl_cdclk_table;
> } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
> - dev_priv->cdclk_funcs = &bxt_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
> if (IS_GEMINILAKE(dev_priv))
> dev_priv->cdclk.table = glk_cdclk_table;
> else
> dev_priv->cdclk.table = bxt_cdclk_table;
> } else if (DISPLAY_VER(dev_priv) == 9) {
> - dev_priv->cdclk_funcs = &skl_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
> } else if (IS_BROADWELL(dev_priv)) {
> - dev_priv->cdclk_funcs = &bdw_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
> } else if (IS_HASWELL(dev_priv)) {
> - dev_priv->cdclk_funcs = &hsw_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
> } else if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->cdclk_funcs = &chv_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
> } else if (IS_VALLEYVIEW(dev_priv)) {
> - dev_priv->cdclk_funcs = &vlv_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
> } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
> - dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_IRONLAKE(dev_priv)) {
> - dev_priv->cdclk_funcs = &ilk_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
> } else if (IS_GM45(dev_priv)) {
> - dev_priv->cdclk_funcs = &gm45_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
> } else if (IS_G45(dev_priv)) {
> - dev_priv->cdclk_funcs = &g33_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
> } else if (IS_I965GM(dev_priv)) {
> - dev_priv->cdclk_funcs = &i965gm_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
> } else if (IS_I965G(dev_priv)) {
> - dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_PINEVIEW(dev_priv)) {
> - dev_priv->cdclk_funcs = &pnv_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
> } else if (IS_G33(dev_priv)) {
> - dev_priv->cdclk_funcs = &g33_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
> } else if (IS_I945GM(dev_priv)) {
> - dev_priv->cdclk_funcs = &i945gm_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
> } else if (IS_I945G(dev_priv)) {
> - dev_priv->cdclk_funcs = &fixed_400mhz_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
> } else if (IS_I915GM(dev_priv)) {
> - dev_priv->cdclk_funcs = &i915gm_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
> } else if (IS_I915G(dev_priv)) {
> - dev_priv->cdclk_funcs = &i915g_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
> } else if (IS_I865G(dev_priv)) {
> - dev_priv->cdclk_funcs = &i865g_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
> } else if (IS_I85X(dev_priv)) {
> - dev_priv->cdclk_funcs = &i85x_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
> } else if (IS_I845G(dev_priv)) {
> - dev_priv->cdclk_funcs = &i845g_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
> } else if (IS_I830(dev_priv)) {
> - dev_priv->cdclk_funcs = &i830_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> }
>
> - if (drm_WARN(&dev_priv->drm, !dev_priv->cdclk_funcs,
> + if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
> "Unknown platform. Assuming i830\n"))
> - dev_priv->cdclk_funcs = &i830_cdclk_funcs;
> + dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index aafe548875cc..74e4ae0609b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -9,6 +9,7 @@
> #include <linux/types.h>
>
> struct intel_atomic_state;
> +struct intel_cdclk_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_initial_plane_config;
> @@ -32,6 +33,9 @@ struct intel_display {
> struct {
> /* Top level crtc-ish functions */
> const struct intel_display_funcs *crtc;
> +
> + /* Display CDCLK functions */
> + const struct intel_cdclk_funcs *cdclk;
Like having intel_cdclk_funcs *cdclk, will intel_display_funcs *display makes more sense and maintaining same terminology across the driver.
> } funcs;
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 3df38531a54b..104095ea3738
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -84,7 +84,6 @@ struct drm_i915_private; struct intel_atomic_state;
> struct intel_audio_funcs; struct intel_cdclk_config; -struct intel_cdclk_funcs;
> struct intel_cdclk_state; struct intel_cdclk_vals; struct intel_color_funcs; @@
> -523,9 +522,6 @@ struct drm_i915_private {
> /* Display internal color functions */
> const struct intel_color_funcs *color_funcs;
>
> - /* Display CDCLK functions */
> - const struct intel_cdclk_funcs *cdclk_funcs;
> -
> /* PCH chipset type */
> enum intel_pch pch_type;
> unsigned short pch_id;
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
2022-08-12 4:32 ` Murthy, Arun R
@ 2022-08-12 6:43 ` Jani Nikula
2022-08-16 3:42 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:43 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index aafe548875cc..74e4ae0609b9 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -9,6 +9,7 @@
>> #include <linux/types.h>
>>
>> struct intel_atomic_state;
>> +struct intel_cdclk_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_initial_plane_config;
>> @@ -32,6 +33,9 @@ struct intel_display {
>> struct {
>> /* Top level crtc-ish functions */
>> const struct intel_display_funcs *crtc;
>> +
>> + /* Display CDCLK functions */
>> + const struct intel_cdclk_funcs *cdclk;
>
> Like having intel_cdclk_funcs *cdclk, will intel_display_funcs
> *display makes more sense and maintaining same terminology across the
> driver.
I was considering renaming it struct intel_crtc_funcs but it's not all
crtc either. But display is both too generic (these are *all* display
functions) and has a tautology (display.funcs.display). Dunno.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs
2022-08-12 6:43 ` Jani Nikula
@ 2022-08-16 3:42 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 3:42 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:14 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to
> display.funcs
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index aafe548875cc..74e4ae0609b9 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -9,6 +9,7 @@
> >> #include <linux/types.h>
> >>
> >> struct intel_atomic_state;
> >> +struct intel_cdclk_funcs;
> >> struct intel_crtc;
> >> struct intel_crtc_state;
> >> struct intel_initial_plane_config;
> >> @@ -32,6 +33,9 @@ struct intel_display {
> >> struct {
> >> /* Top level crtc-ish functions */
> >> const struct intel_display_funcs *crtc;
> >> +
> >> + /* Display CDCLK functions */
> >> + const struct intel_cdclk_funcs *cdclk;
> >
> > Like having intel_cdclk_funcs *cdclk, will intel_display_funcs
> > *display makes more sense and maintaining same terminology across the
> > driver.
>
> I was considering renaming it struct intel_crtc_funcs but it's not all crtc either.
> But display is both too generic (these are *all* display
> functions) and has a tautology (display.funcs.display). Dunno.
>
I think this(display.funcs.display) should do. A struct display having funcs and inside that display_funcs.
Will leave it for others to comment.
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 01/39] " Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 02/39] drm/i915: move cdclk_funcs to display.funcs Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:33 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs " Jani Nikula
` (41 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++++
drivers/gpu/drm/i915/display/intel_dpll.c | 24 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 4 ----
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 74e4ae0609b9..f09bbb7b5cc9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -12,6 +12,7 @@ struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_dpll_funcs;
struct intel_initial_plane_config;
struct intel_display_funcs {
@@ -36,6 +37,9 @@ struct intel_display {
/* Display CDCLK functions */
const struct intel_cdclk_funcs *cdclk;
+
+ /* Display pll funcs */
+ const struct intel_dpll_funcs *dpll;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 5262f16b45ac..87899702a522 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1420,7 +1420,7 @@ int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
- ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc);
if (ret) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
crtc->base.base.id, crtc->base.name);
@@ -1446,10 +1446,10 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
if (!crtc_state->hw.enable)
return 0;
- if (!i915->dpll_funcs->crtc_get_shared_dpll)
+ if (!i915->display.funcs.dpll->crtc_get_shared_dpll)
return 0;
- ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc);
if (ret) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
crtc->base.base.id, crtc->base.name);
@@ -1463,23 +1463,23 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv))
- dev_priv->dpll_funcs = &dg2_dpll_funcs;
+ dev_priv->display.funcs.dpll = &dg2_dpll_funcs;
else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs = &hsw_dpll_funcs;
+ dev_priv->display.funcs.dpll = &hsw_dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs = &ilk_dpll_funcs;
+ dev_priv->display.funcs.dpll = &ilk_dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs = &chv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &chv_dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs = &vlv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &vlv_dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs = &g4x_dpll_funcs;
+ dev_priv->display.funcs.dpll = &g4x_dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs = &pnv_dpll_funcs;
+ dev_priv->display.funcs.dpll = &pnv_dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs = &i9xx_dpll_funcs;
+ dev_priv->display.funcs.dpll = &i9xx_dpll_funcs;
else
- dev_priv->dpll_funcs = &i8xx_dpll_funcs;
+ dev_priv->display.funcs.dpll = &i8xx_dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 104095ea3738..375f526215a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -90,7 +90,6 @@ struct intel_color_funcs;
struct intel_connector;
struct intel_crtc;
struct intel_dp;
-struct intel_dpll_funcs;
struct intel_encoder;
struct intel_fbdev;
struct intel_fdi_funcs;
@@ -516,9 +515,6 @@ struct drm_i915_private {
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
- /* display pll funcs */
- const struct intel_dpll_funcs *dpll_funcs;
-
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs " Jani Nikula
@ 2022-08-12 4:33 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:33 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs to display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (2 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 03/39] drm/i915: move dpll_funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:37 ` Murthy, Arun R
2022-08-17 1:28 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs " Jani Nikula
` (40 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++++
drivers/gpu/drm/i915/i915_drv.h | 4 ----
drivers/gpu/drm/i915/i915_irq.c | 20 +++++++++----------
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index f09bbb7b5cc9..ff76bd4079e4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -13,6 +13,7 @@ struct intel_cdclk_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
+struct intel_hotplug_funcs;
struct intel_initial_plane_config;
struct intel_display_funcs {
@@ -40,6 +41,9 @@ struct intel_display {
/* Display pll funcs */
const struct intel_dpll_funcs *dpll;
+
+ /* irq display functions */
+ const struct intel_hotplug_funcs *hotplug;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 375f526215a2..513fae9e7a81 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -94,7 +94,6 @@ struct intel_encoder;
struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_gmbus;
-struct intel_hotplug_funcs;
struct intel_limit;
struct intel_overlay;
struct intel_overlay_error_state;
@@ -509,9 +508,6 @@ struct drm_i915_private {
/* pm display functions */
const struct drm_i915_wm_disp_funcs *wm_disp;
- /* irq display functions */
- const struct intel_hotplug_funcs *hotplug_funcs;
-
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0389f532d926..c1b8f949c53d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4370,8 +4370,8 @@ HPD_FUNCS(ilk);
void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs)
- i915->hotplug_funcs->hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
+ i915->display.funcs.hotplug->hpd_irq_setup(i915);
}
/**
@@ -4424,22 +4424,22 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs = &i915_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &i915_hpd_funcs;
} else {
if (HAS_PCH_DG2(dev_priv))
- dev_priv->hotplug_funcs = &icp_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
else if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs = &dg1_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs = &gen11_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs = &bxt_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &bxt_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs = &icp_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs = &spt_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &spt_hpd_funcs;
else
- dev_priv->hotplug_funcs = &ilk_hpd_funcs;
+ dev_priv->display.funcs.hotplug = &ilk_hpd_funcs;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs " Jani Nikula
@ 2022-08-12 4:37 ` Murthy, Arun R
2022-08-12 6:45 ` Jani Nikula
2022-08-17 1:28 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:37 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
The commit msg becomes same for the patches. Can it be more precise as to move all hotplug related struct under display sub-struct?
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Upon adding proper commit msg
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
2022-08-12 4:37 ` Murthy, Arun R
@ 2022-08-12 6:45 ` Jani Nikula
0 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:45 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to
>> display.funcs
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
> The commit msg becomes same for the patches. Can it be more precise as
> to move all hotplug related struct under display sub-struct?
Yeah, just copy-pasted for now.
BR,
Jani.
>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
> Upon adding proper commit msg
> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs " Jani Nikula
2022-08-12 4:37 ` Murthy, Arun R
@ 2022-08-17 1:28 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 1:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:15PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++++
> drivers/gpu/drm/i915/i915_drv.h | 4 ----
> drivers/gpu/drm/i915/i915_irq.c | 20 +++++++++----------
> 3 files changed, 14 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index f09bbb7b5cc9..ff76bd4079e4 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -13,6 +13,7 @@ struct intel_cdclk_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
>+struct intel_hotplug_funcs;
> struct intel_initial_plane_config;
>
> struct intel_display_funcs {
>@@ -40,6 +41,9 @@ struct intel_display {
>
> /* Display pll funcs */
> const struct intel_dpll_funcs *dpll;
>+
>+ /* irq display functions */
>+ const struct intel_hotplug_funcs *hotplug;
> } funcs;
> };
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 375f526215a2..513fae9e7a81 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -94,7 +94,6 @@ struct intel_encoder;
> struct intel_fbdev;
> struct intel_fdi_funcs;
> struct intel_gmbus;
>-struct intel_hotplug_funcs;
> struct intel_limit;
> struct intel_overlay;
> struct intel_overlay_error_state;
>@@ -509,9 +508,6 @@ struct drm_i915_private {
> /* pm display functions */
> const struct drm_i915_wm_disp_funcs *wm_disp;
>
>- /* irq display functions */
>- const struct intel_hotplug_funcs *hotplug_funcs;
>-
> /* fdi display functions */
> const struct intel_fdi_funcs *fdi_funcs;
>
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 0389f532d926..c1b8f949c53d 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -4370,8 +4370,8 @@ HPD_FUNCS(ilk);
>
> void intel_hpd_irq_setup(struct drm_i915_private *i915)
> {
>- if (i915->display_irqs_enabled && i915->hotplug_funcs)
>- i915->hotplug_funcs->hpd_irq_setup(i915);
>+ if (i915->display_irqs_enabled && i915->display.funcs.hotplug)
>+ i915->display.funcs.hotplug->hpd_irq_setup(i915);
> }
>
> /**
>@@ -4424,22 +4424,22 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
>
> if (HAS_GMCH(dev_priv)) {
> if (I915_HAS_HOTPLUG(dev_priv))
>- dev_priv->hotplug_funcs = &i915_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &i915_hpd_funcs;
> } else {
> if (HAS_PCH_DG2(dev_priv))
>- dev_priv->hotplug_funcs = &icp_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
> else if (HAS_PCH_DG1(dev_priv))
>- dev_priv->hotplug_funcs = &dg1_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &dg1_hpd_funcs;
> else if (DISPLAY_VER(dev_priv) >= 11)
>- dev_priv->hotplug_funcs = &gen11_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &gen11_hpd_funcs;
> else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>- dev_priv->hotplug_funcs = &bxt_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &bxt_hpd_funcs;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
>- dev_priv->hotplug_funcs = &icp_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &icp_hpd_funcs;
> else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
>- dev_priv->hotplug_funcs = &spt_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &spt_hpd_funcs;
> else
>- dev_priv->hotplug_funcs = &ilk_hpd_funcs;
>+ dev_priv->display.funcs.hotplug = &ilk_hpd_funcs;
pass by comment: eventually we will want to move all these irq related
to display to display/, right?
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
> }
> }
>
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (3 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 04/39] drm/i915: move hotplug_funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:41 ` Murthy, Arun R
2022-08-17 1:38 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs " Jani Nikula
` (39 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while
at it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
drivers/gpu/drm/i915/i915_drv.h | 4 --
drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
3 files changed, 33 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index ff76bd4079e4..98c6ccdc9100 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -10,6 +10,7 @@
struct intel_atomic_state;
struct intel_cdclk_funcs;
+struct intel_clock_gating_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
@@ -44,6 +45,9 @@ struct intel_display {
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
+
+ /* pm private clock gating functions */
+ const struct intel_clock_gating_funcs *clock_gating;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 513fae9e7a81..216298d2d677 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -78,7 +78,6 @@
#include "intel_wopcm.h"
struct dpll;
-struct drm_i915_clock_gating_funcs;
struct drm_i915_gem_object;
struct drm_i915_private;
struct intel_atomic_state;
@@ -502,9 +501,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* pm private clock gating functions */
- const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
-
/* pm display functions */
const struct drm_i915_wm_disp_funcs *wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ef7553b494ea..043094573c20 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -59,7 +59,7 @@
static void skl_sagv_disable(struct drm_i915_private *dev_priv);
-struct drm_i915_clock_gating_funcs {
+struct intel_clock_gating_funcs {
void (*init_clock_gating)(struct drm_i915_private *i915);
};
@@ -8053,7 +8053,7 @@ static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
+ dev_priv->display.funcs.clock_gating->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -8069,7 +8069,7 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
}
#define CG_FUNCS(platform) \
-static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs = { \
+static const struct intel_clock_gating_funcs platform##_clock_gating_funcs = { \
.init_clock_gating = platform##_init_clock_gating, \
}
@@ -8113,58 +8113,58 @@ CG_FUNCS(nop);
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_PONTEVECCHIO(dev_priv))
- dev_priv->clock_gating_funcs = &pvc_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &pvc_clock_gating_funcs;
else if (IS_DG2(dev_priv))
- dev_priv->clock_gating_funcs = &dg2_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &dg2_clock_gating_funcs;
else if (IS_XEHPSDV(dev_priv))
- dev_priv->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &xehpsdv_clock_gating_funcs;
else if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs = &adlp_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &adlp_clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs = &dg1_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &dg1_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs = &gen12lp_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &gen12lp_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs = &icl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &icl_clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &cfl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &cfl_clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &skl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &skl_clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs = &kbl_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &kbl_clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs = &bxt_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &bxt_clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs = &glk_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &glk_clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs = &bdw_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &bdw_clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs = &chv_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &chv_clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs = &hsw_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &hsw_clock_gating_funcs;
else if (IS_IVYBRIDGE(dev_priv))
- dev_priv->clock_gating_funcs = &ivb_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &ivb_clock_gating_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->clock_gating_funcs = &vlv_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &vlv_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 6)
- dev_priv->clock_gating_funcs = &gen6_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &gen6_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 5)
- dev_priv->clock_gating_funcs = &ilk_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &ilk_clock_gating_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->clock_gating_funcs = &g4x_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &g4x_clock_gating_funcs;
else if (IS_I965GM(dev_priv))
- dev_priv->clock_gating_funcs = &i965gm_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &i965gm_clock_gating_funcs;
else if (IS_I965G(dev_priv))
- dev_priv->clock_gating_funcs = &i965g_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &i965g_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 3)
- dev_priv->clock_gating_funcs = &gen3_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &gen3_clock_gating_funcs;
else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
- dev_priv->clock_gating_funcs = &i85x_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &i85x_clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 2)
- dev_priv->clock_gating_funcs = &i830_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &i830_clock_gating_funcs;
else {
MISSING_CASE(INTEL_DEVID(dev_priv));
- dev_priv->clock_gating_funcs = &nop_clock_gating_funcs;
+ dev_priv->display.funcs.clock_gating = &nop_clock_gating_funcs;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs " Jani Nikula
@ 2022-08-12 4:41 ` Murthy, Arun R
2022-08-12 6:48 ` Jani Nikula
2022-08-17 1:38 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:41 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
> it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
> 3 files changed, 33 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index ff76bd4079e4..98c6ccdc9100 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -10,6 +10,7 @@
>
> struct intel_atomic_state;
> struct intel_cdclk_funcs;
> +struct intel_clock_gating_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
> @@ -44,6 +45,9 @@ struct intel_display {
>
> /* irq display functions */
> const struct intel_hotplug_funcs *hotplug;
> +
> + /* pm private clock gating functions */
> + const struct intel_clock_gating_funcs *clock_gating;
Likewise having struct intel_display and all display related structs inside this, can this stuct be moved to intel_pm?
This is more related to a pm!
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-12 4:41 ` Murthy, Arun R
@ 2022-08-12 6:48 ` Jani Nikula
2022-08-12 6:51 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:48 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
>> display.funcs
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
>> it.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index ff76bd4079e4..98c6ccdc9100 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -10,6 +10,7 @@
>>
>> struct intel_atomic_state;
>> struct intel_cdclk_funcs;
>> +struct intel_clock_gating_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_dpll_funcs;
>> @@ -44,6 +45,9 @@ struct intel_display {
>>
>> /* irq display functions */
>> const struct intel_hotplug_funcs *hotplug;
>> +
>> + /* pm private clock gating functions */
>> + const struct intel_clock_gating_funcs *clock_gating;
> Likewise having struct intel_display and all display related structs inside this, can this stuct be moved to intel_pm?
> This is more related to a pm!
I'm undecided whether it's eventually better to group the functions
together, or spread the functions by, uh, functionality.
But I'm pretty sure I want to first group them like this, see how the
*other* named and anonymous sub-structs of intel_display shape up, and
spread them around if that feels like the right thing to do.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-12 6:48 ` Jani Nikula
@ 2022-08-12 6:51 ` Jani Nikula
2022-08-16 3:45 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:51 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>>> -----Original Message-----
>>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>>> Nikula
>>> Sent: Thursday, August 11, 2022 8:37 PM
>>> To: intel-gfx@lists.freedesktop.org
>>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>>> <lucas.demarchi@intel.com>
>>> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
>>> display.funcs
>>>
>>> Move display related members under drm_i915_private display sub-struct.
>>>
>>> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while at
>>> it.
>>>
>>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>> ---
>>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
>>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> index ff76bd4079e4..98c6ccdc9100 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>> @@ -10,6 +10,7 @@
>>>
>>> struct intel_atomic_state;
>>> struct intel_cdclk_funcs;
>>> +struct intel_clock_gating_funcs;
>>> struct intel_crtc;
>>> struct intel_crtc_state;
>>> struct intel_dpll_funcs;
>>> @@ -44,6 +45,9 @@ struct intel_display {
>>>
>>> /* irq display functions */
>>> const struct intel_hotplug_funcs *hotplug;
>>> +
>>> + /* pm private clock gating functions */
>>> + const struct intel_clock_gating_funcs *clock_gating;
>> Likewise having struct intel_display and all display related structs inside this, can this stuct be moved to intel_pm?
>> This is more related to a pm!
>
> I'm undecided whether it's eventually better to group the functions
> together, or spread the functions by, uh, functionality.
>
> But I'm pretty sure I want to first group them like this, see how the
> *other* named and anonymous sub-structs of intel_display shape up, and
> spread them around if that feels like the right thing to do.
Also, this series is going to be a lot of refactoring, and I'm
constantly trying to *not* incorporate too many changes, and mostly just
stick to straightforward movement. There's a lot more that should be
done wrt actually hiding this stuff within modules (using opaque
pointers etc) instead of exposing all of the data to all of the
drivers. It just can't all be done at once. This is the first step.
BR,
Jani.
>
> BR,
> Jani.
>
>
>>
>> Thanks and Regards,
>> Arun R Murthy
>> --------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-12 6:51 ` Jani Nikula
@ 2022-08-16 3:45 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 3:45 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:21 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to
> display.funcs
>
> On Fri, 12 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> > On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >>> -----Original Message-----
> >>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >>> Of Jani Nikula
> >>> Sent: Thursday, August 11, 2022 8:37 PM
> >>> To: intel-gfx@lists.freedesktop.org
> >>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >>> <lucas.demarchi@intel.com>
> >>> Subject: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs
> >>> to display.funcs
> >>>
> >>> Move display related members under drm_i915_private display sub-
> struct.
> >>>
> >>> Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs
> >>> while at it.
> >>>
> >>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >>> ---
> >>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> >>> drivers/gpu/drm/i915/i915_drv.h | 4 --
> >>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
> >>> 3 files changed, 33 insertions(+), 33 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >>> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >>> index ff76bd4079e4..98c6ccdc9100 100644
> >>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >>> @@ -10,6 +10,7 @@
> >>>
> >>> struct intel_atomic_state;
> >>> struct intel_cdclk_funcs;
> >>> +struct intel_clock_gating_funcs;
> >>> struct intel_crtc;
> >>> struct intel_crtc_state;
> >>> struct intel_dpll_funcs;
> >>> @@ -44,6 +45,9 @@ struct intel_display {
> >>>
> >>> /* irq display functions */
> >>> const struct intel_hotplug_funcs *hotplug;
> >>> +
> >>> + /* pm private clock gating functions */
> >>> + const struct intel_clock_gating_funcs *clock_gating;
> >> Likewise having struct intel_display and all display related structs inside
> this, can this stuct be moved to intel_pm?
> >> This is more related to a pm!
> >
> > I'm undecided whether it's eventually better to group the functions
> > together, or spread the functions by, uh, functionality.
> >
> > But I'm pretty sure I want to first group them like this, see how the
> > *other* named and anonymous sub-structs of intel_display shape up, and
> > spread them around if that feels like the right thing to do.
>
> Also, this series is going to be a lot of refactoring, and I'm constantly trying to
> *not* incorporate too many changes, and mostly just stick to straightforward
> movement. There's a lot more that should be done wrt actually hiding this
> stuff within modules (using opaque pointers etc) instead of exposing all of
> the data to all of the drivers. It just can't all be done at once. This is the first
> step.
>
Can we have a TODO, so that we don't miss this and it would be on track?
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs " Jani Nikula
2022-08-12 4:41 ` Murthy, Arun R
@ 2022-08-17 1:38 ` Lucas De Marchi
2022-08-17 6:50 ` Jani Nikula
1 sibling, 1 reply; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 1:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:16PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while
>at it.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> drivers/gpu/drm/i915/i915_drv.h | 4 --
> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
> 3 files changed, 33 insertions(+), 33 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index ff76bd4079e4..98c6ccdc9100 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -10,6 +10,7 @@
>
> struct intel_atomic_state;
> struct intel_cdclk_funcs;
>+struct intel_clock_gating_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
>@@ -44,6 +45,9 @@ struct intel_display {
>
> /* irq display functions */
> const struct intel_hotplug_funcs *hotplug;
>+
>+ /* pm private clock gating functions */
>+ const struct intel_clock_gating_funcs *clock_gating;
did we get this correct moving clock_gating to display? The question I'd
ask is: if a platform doesn't have display, would it need to do
anything clock-gating related? Looking at the current functions e.g.
gen9_init_clock_gating setting some chicken bits, I'd say yes.
Another reasoning I'd have is regarding the registers it touches.
And here they are not from display.
So, I don't really understand the reason for moving clock_gating here,
except that there are indeed several functions doing display-related
things. Should we rather split one for i915 and one for i915-display?
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-17 1:38 ` Lucas De Marchi
@ 2022-08-17 6:50 ` Jani Nikula
2022-08-17 7:20 ` Lucas De Marchi
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-17 6:50 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Aug 11, 2022 at 06:07:16PM +0300, Jani Nikula wrote:
>>Move display related members under drm_i915_private display sub-struct.
>>
>>Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while
>>at it.
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>---
>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>index ff76bd4079e4..98c6ccdc9100 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>@@ -10,6 +10,7 @@
>>
>> struct intel_atomic_state;
>> struct intel_cdclk_funcs;
>>+struct intel_clock_gating_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_dpll_funcs;
>>@@ -44,6 +45,9 @@ struct intel_display {
>>
>> /* irq display functions */
>> const struct intel_hotplug_funcs *hotplug;
>>+
>>+ /* pm private clock gating functions */
>>+ const struct intel_clock_gating_funcs *clock_gating;
>
> did we get this correct moving clock_gating to display? The question I'd
> ask is: if a platform doesn't have display, would it need to do
> anything clock-gating related? Looking at the current functions e.g.
> gen9_init_clock_gating setting some chicken bits, I'd say yes.
>
> Another reasoning I'd have is regarding the registers it touches.
> And here they are not from display.
>
> So, I don't really understand the reason for moving clock_gating here,
> except that there are indeed several functions doing display-related
> things. Should we rather split one for i915 and one for i915-display?
Mmmh, maybe. It's hard to split the driver nicely when the hardware
isn't!
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs to display.funcs
2022-08-17 6:50 ` Jani Nikula
@ 2022-08-17 7:20 ` Lucas De Marchi
0 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 7:20 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Aug 17, 2022 at 09:50:52AM +0300, Jani Nikula wrote:
>On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Thu, Aug 11, 2022 at 06:07:16PM +0300, Jani Nikula wrote:
>>>Move display related members under drm_i915_private display sub-struct.
>>>
>>>Rename struct i915_clock_gating_funcs to intel_clock_gating_funcs while
>>>at it.
>>>
>>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>>---
>>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>>> drivers/gpu/drm/i915/i915_drv.h | 4 --
>>> drivers/gpu/drm/i915/intel_pm.c | 58 +++++++++----------
>>> 3 files changed, 33 insertions(+), 33 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>>index ff76bd4079e4..98c6ccdc9100 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>>@@ -10,6 +10,7 @@
>>>
>>> struct intel_atomic_state;
>>> struct intel_cdclk_funcs;
>>>+struct intel_clock_gating_funcs;
>>> struct intel_crtc;
>>> struct intel_crtc_state;
>>> struct intel_dpll_funcs;
>>>@@ -44,6 +45,9 @@ struct intel_display {
>>>
>>> /* irq display functions */
>>> const struct intel_hotplug_funcs *hotplug;
>>>+
>>>+ /* pm private clock gating functions */
>>>+ const struct intel_clock_gating_funcs *clock_gating;
>>
>> did we get this correct moving clock_gating to display? The question I'd
>> ask is: if a platform doesn't have display, would it need to do
>> anything clock-gating related? Looking at the current functions e.g.
>> gen9_init_clock_gating setting some chicken bits, I'd say yes.
>>
>> Another reasoning I'd have is regarding the registers it touches.
>> And here they are not from display.
>>
>> So, I don't really understand the reason for moving clock_gating here,
>> except that there are indeed several functions doing display-related
>> things. Should we rather split one for i915 and one for i915-display?
>
>Mmmh, maybe. It's hard to split the driver nicely when the hardware
>isn't!
oh, maybe one alternative is to move most of those register settings
(that appear to be WAs) somewhere else. And then declare the
clock_gating stuff as "this is display stuff".
I don't mind if you move them inside display first just to get
the ball rolling and we move them to a better place later.
Lucas De Marchi
>
>BR,
>Jani.
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (4 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 05/39] drm/i915: move clock_gating_funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:45 ` Murthy, Arun R
2022-08-17 3:50 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs " Jani Nikula
` (38 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++--------
.../gpu/drm/i915/display/intel_display_core.h | 21 ++++++++++
drivers/gpu/drm/i915/i915_drv.h | 22 ----------
drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++----------
4 files changed, 59 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 24ab1501beea..7db4ac27364d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -164,16 +164,16 @@ static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
*/
void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp->update_wm)
- dev_priv->wm_disp->update_wm(dev_priv);
+ if (dev_priv->display.funcs.wm->update_wm)
+ dev_priv->display.funcs.wm->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->compute_pipe_wm)
- return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
+ if (dev_priv->display.funcs.wm->compute_pipe_wm)
+ return dev_priv->display.funcs.wm->compute_pipe_wm(state, crtc);
return 0;
}
@@ -181,20 +181,20 @@ static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->wm_disp->compute_intermediate_wm)
+ if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(&dev_priv->drm,
- !dev_priv->wm_disp->compute_pipe_wm))
+ !dev_priv->display.funcs.wm->compute_pipe_wm))
return 0;
- return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
+ return dev_priv->display.funcs.wm->compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->initial_watermarks) {
- dev_priv->wm_disp->initial_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->initial_watermarks) {
+ dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -204,23 +204,23 @@ static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->atomic_update_watermarks)
- dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->atomic_update_watermarks)
+ dev_priv->display.funcs.wm->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->optimize_watermarks)
- dev_priv->wm_disp->optimize_watermarks(state, crtc);
+ if (dev_priv->display.funcs.wm->optimize_watermarks)
+ dev_priv->display.funcs.wm->optimize_watermarks(state, crtc);
}
static int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp->compute_global_watermarks)
- return dev_priv->wm_disp->compute_global_watermarks(state);
+ if (dev_priv->display.funcs.wm->compute_global_watermarks)
+ return dev_priv->display.funcs.wm->compute_global_watermarks(state);
return 0;
}
@@ -2400,7 +2400,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp->initial_watermarks)
+ if (!dev_priv->display.funcs.wm->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -8454,7 +8454,7 @@ static void sanitize_watermarks(struct drm_i915_private *dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp->optimize_watermarks)
+ if (!dev_priv->display.funcs.wm->optimize_watermarks)
return;
state = drm_atomic_state_alloc(&dev_priv->drm);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 98c6ccdc9100..a6843ebcca5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
+struct drm_i915_private;
struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_clock_gating_funcs;
@@ -31,6 +32,23 @@ struct intel_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
};
+/* functions used for watermark calcs for display. */
+struct intel_wm_funcs {
+ /* update_wm is for legacy wm management */
+ void (*update_wm)(struct drm_i915_private *dev_priv);
+ int (*compute_pipe_wm)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ int (*compute_intermediate_wm)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*initial_watermarks)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*atomic_update_watermarks)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*optimize_watermarks)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ int (*compute_global_watermarks)(struct intel_atomic_state *state);
+};
+
struct intel_display {
/* Display functions */
struct {
@@ -48,6 +66,9 @@ struct intel_display {
/* pm private clock gating functions */
const struct intel_clock_gating_funcs *clock_gating;
+
+ /* pm display functions */
+ const struct intel_wm_funcs *wm;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 216298d2d677..69a8cce48fc4 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -80,14 +80,12 @@
struct dpll;
struct drm_i915_gem_object;
struct drm_i915_private;
-struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_config;
struct intel_cdclk_state;
struct intel_cdclk_vals;
struct intel_color_funcs;
struct intel_connector;
-struct intel_crtc;
struct intel_dp;
struct intel_encoder;
struct intel_fbdev;
@@ -156,23 +154,6 @@ struct sdvo_device_mapping {
u8 ddc_pin;
};
-/* functions used for watermark calcs for display. */
-struct drm_i915_wm_disp_funcs {
- /* update_wm is for legacy wm management */
- void (*update_wm)(struct drm_i915_private *dev_priv);
- int (*compute_pipe_wm)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- int (*compute_intermediate_wm)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc *crtc);
- int (*compute_global_watermarks)(struct intel_atomic_state *state);
-};
-
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -501,9 +482,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* pm display functions */
- const struct drm_i915_wm_disp_funcs *wm_disp;
-
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 043094573c20..5febe91e44a0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8168,18 +8168,18 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
}
}
-static const struct drm_i915_wm_disp_funcs skl_wm_funcs = {
+static const struct intel_wm_funcs skl_wm_funcs = {
.compute_global_watermarks = skl_compute_wm,
};
-static const struct drm_i915_wm_disp_funcs ilk_wm_funcs = {
+static const struct intel_wm_funcs ilk_wm_funcs = {
.compute_pipe_wm = ilk_compute_pipe_wm,
.compute_intermediate_wm = ilk_compute_intermediate_wm,
.initial_watermarks = ilk_initial_watermarks,
.optimize_watermarks = ilk_optimize_watermarks,
};
-static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
+static const struct intel_wm_funcs vlv_wm_funcs = {
.compute_pipe_wm = vlv_compute_pipe_wm,
.compute_intermediate_wm = vlv_compute_intermediate_wm,
.initial_watermarks = vlv_initial_watermarks,
@@ -8187,30 +8187,30 @@ static const struct drm_i915_wm_disp_funcs vlv_wm_funcs = {
.atomic_update_watermarks = vlv_atomic_update_fifo,
};
-static const struct drm_i915_wm_disp_funcs g4x_wm_funcs = {
+static const struct intel_wm_funcs g4x_wm_funcs = {
.compute_pipe_wm = g4x_compute_pipe_wm,
.compute_intermediate_wm = g4x_compute_intermediate_wm,
.initial_watermarks = g4x_initial_watermarks,
.optimize_watermarks = g4x_optimize_watermarks,
};
-static const struct drm_i915_wm_disp_funcs pnv_wm_funcs = {
+static const struct intel_wm_funcs pnv_wm_funcs = {
.update_wm = pnv_update_wm,
};
-static const struct drm_i915_wm_disp_funcs i965_wm_funcs = {
+static const struct intel_wm_funcs i965_wm_funcs = {
.update_wm = i965_update_wm,
};
-static const struct drm_i915_wm_disp_funcs i9xx_wm_funcs = {
+static const struct intel_wm_funcs i9xx_wm_funcs = {
.update_wm = i9xx_update_wm,
};
-static const struct drm_i915_wm_disp_funcs i845_wm_funcs = {
+static const struct intel_wm_funcs i845_wm_funcs = {
.update_wm = i845_update_wm,
};
-static const struct drm_i915_wm_disp_funcs nop_funcs = {
+static const struct intel_wm_funcs nop_funcs = {
};
/* Set up chip specific power management-related functions */
@@ -8227,7 +8227,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
/* For FIFO watermark updates */
if (DISPLAY_VER(dev_priv) >= 9) {
skl_setup_wm_latency(dev_priv);
- dev_priv->wm_disp = &skl_wm_funcs;
+ dev_priv->display.funcs.wm = &skl_wm_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
@@ -8235,19 +8235,19 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
(DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
- dev_priv->wm_disp = &ilk_wm_funcs;
+ dev_priv->display.funcs.wm = &ilk_wm_funcs;
} else {
drm_dbg_kms(&dev_priv->drm,
"Failed to read display plane latency. "
"Disable CxSR\n");
- dev_priv->wm_disp = &nop_funcs;
+ dev_priv->display.funcs.wm = &nop_funcs;
}
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_setup_wm_latency(dev_priv);
- dev_priv->wm_disp = &vlv_wm_funcs;
+ dev_priv->display.funcs.wm = &vlv_wm_funcs;
} else if (IS_G4X(dev_priv)) {
g4x_setup_wm_latency(dev_priv);
- dev_priv->wm_disp = &g4x_wm_funcs;
+ dev_priv->display.funcs.wm = &g4x_wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!intel_get_cxsr_latency(!IS_MOBILE(dev_priv),
dev_priv->is_ddr3,
@@ -8261,22 +8261,22 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->fsb_freq, dev_priv->mem_freq);
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
- dev_priv->wm_disp = &nop_funcs;
+ dev_priv->display.funcs.wm = &nop_funcs;
} else
- dev_priv->wm_disp = &pnv_wm_funcs;
+ dev_priv->display.funcs.wm = &pnv_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 4) {
- dev_priv->wm_disp = &i965_wm_funcs;
+ dev_priv->display.funcs.wm = &i965_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 3) {
- dev_priv->wm_disp = &i9xx_wm_funcs;
+ dev_priv->display.funcs.wm = &i9xx_wm_funcs;
} else if (DISPLAY_VER(dev_priv) == 2) {
if (INTEL_NUM_PIPES(dev_priv) == 1)
- dev_priv->wm_disp = &i845_wm_funcs;
+ dev_priv->display.funcs.wm = &i845_wm_funcs;
else
- dev_priv->wm_disp = &i9xx_wm_funcs;
+ dev_priv->display.funcs.wm = &i9xx_wm_funcs;
} else {
drm_err(&dev_priv->drm,
"unexpected fall-through in %s\n", __func__);
- dev_priv->wm_disp = &nop_funcs;
+ dev_priv->display.funcs.wm = &nop_funcs;
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs " Jani Nikula
@ 2022-08-12 4:45 ` Murthy, Arun R
2022-08-12 6:54 ` Jani Nikula
2022-08-17 3:50 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:45 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 34 +++++++--------
> .../gpu/drm/i915/display/intel_display_core.h | 21 ++++++++++
> drivers/gpu/drm/i915/i915_drv.h | 22 ----------
> drivers/gpu/drm/i915/intel_pm.c | 42 +++++++++----------
> 4 files changed, 59 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 24ab1501beea..7db4ac27364d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -164,16 +164,16 @@ static void ilk_pfit_enable(const struct
> intel_crtc_state *crtc_state);
> */
> void intel_update_watermarks(struct drm_i915_private *dev_priv) {
> - if (dev_priv->wm_disp->update_wm)
> - dev_priv->wm_disp->update_wm(dev_priv);
> + if (dev_priv->display.funcs.wm->update_wm)
> + dev_priv->display.funcs.wm->update_wm(dev_priv);
> }
>
> static int intel_compute_pipe_wm(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->compute_pipe_wm)
> - return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
> + if (dev_priv->display.funcs.wm->compute_pipe_wm)
> + return dev_priv->display.funcs.wm-
> >compute_pipe_wm(state, crtc);
> return 0;
> }
>
> @@ -181,20 +181,20 @@ static int intel_compute_intermediate_wm(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (!dev_priv->wm_disp->compute_intermediate_wm)
> + if (!dev_priv->display.funcs.wm->compute_intermediate_wm)
> return 0;
> if (drm_WARN_ON(&dev_priv->drm,
> - !dev_priv->wm_disp->compute_pipe_wm))
> + !dev_priv->display.funcs.wm->compute_pipe_wm))
> return 0;
> - return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
> + return dev_priv->display.funcs.wm-
> >compute_intermediate_wm(state,
> +crtc);
> }
>
> static bool intel_initial_watermarks(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->initial_watermarks) {
> - dev_priv->wm_disp->initial_watermarks(state, crtc);
> + if (dev_priv->display.funcs.wm->initial_watermarks) {
> + dev_priv->display.funcs.wm->initial_watermarks(state, crtc);
> return true;
> }
> return false;
> @@ -204,23 +204,23 @@ static void intel_atomic_update_watermarks(struct
> intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->atomic_update_watermarks)
> - dev_priv->wm_disp->atomic_update_watermarks(state,
> crtc);
> + if (dev_priv->display.funcs.wm->atomic_update_watermarks)
> + dev_priv->display.funcs.wm-
> >atomic_update_watermarks(state, crtc);
> }
>
> static void intel_optimize_watermarks(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->optimize_watermarks)
> - dev_priv->wm_disp->optimize_watermarks(state, crtc);
> + if (dev_priv->display.funcs.wm->optimize_watermarks)
> + dev_priv->display.funcs.wm->optimize_watermarks(state,
> crtc);
> }
>
> static int intel_compute_global_watermarks(struct intel_atomic_state
> *state) {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - if (dev_priv->wm_disp->compute_global_watermarks)
> - return dev_priv->wm_disp-
> >compute_global_watermarks(state);
> + if (dev_priv->display.funcs.wm->compute_global_watermarks)
> + return dev_priv->display.funcs.wm-
> >compute_global_watermarks(state);
> return 0;
> }
>
> @@ -2400,7 +2400,7 @@ static void i9xx_crtc_disable(struct
> intel_atomic_state *state,
> if (DISPLAY_VER(dev_priv) != 2)
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe,
> false);
>
> - if (!dev_priv->wm_disp->initial_watermarks)
> + if (!dev_priv->display.funcs.wm->initial_watermarks)
> intel_update_watermarks(dev_priv);
>
> /* clock the pipe down to 640x480@60 to potentially save power */
> @@ -8454,7 +8454,7 @@ static void sanitize_watermarks(struct
> drm_i915_private *dev_priv)
> int i;
>
> /* Only supported on platforms that use atomic watermark design */
> - if (!dev_priv->wm_disp->optimize_watermarks)
> + if (!dev_priv->display.funcs.wm->optimize_watermarks)
> return;
>
> state = drm_atomic_state_alloc(&dev_priv->drm);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 98c6ccdc9100..a6843ebcca5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -8,6 +8,7 @@
>
> #include <linux/types.h>
>
> +struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_cdclk_funcs;
> struct intel_clock_gating_funcs;
> @@ -31,6 +32,23 @@ struct intel_display_funcs {
> void (*commit_modeset_enables)(struct intel_atomic_state *state);
> };
>
> +/* functions used for watermark calcs for display. */ struct
> +intel_wm_funcs {
> + /* update_wm is for legacy wm management */
> + void (*update_wm)(struct drm_i915_private *dev_priv);
> + int (*compute_pipe_wm)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + int (*compute_intermediate_wm)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*initial_watermarks)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + void (*optimize_watermarks)(struct intel_atomic_state *state,
> + struct intel_crtc *crtc);
> + int (*compute_global_watermarks)(struct intel_atomic_state *state);
> };
> +
> struct intel_display {
> /* Display functions */
> struct {
> @@ -48,6 +66,9 @@ struct intel_display {
>
> /* pm private clock gating functions */
> const struct intel_clock_gating_funcs *clock_gating;
> +
> + /* pm display functions */
> + const struct intel_wm_funcs *wm;
> } funcs;
Can the wm, dbuf, clock related move to a struct intel_pm ? which makes it more meaningful else again we end up creating a struct intel_display a long one like i915_private.
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
2022-08-12 4:45 ` Murthy, Arun R
@ 2022-08-12 6:54 ` Jani Nikula
2022-08-16 3:48 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:54 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 98c6ccdc9100..a6843ebcca5a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -8,6 +8,7 @@
>>
>> #include <linux/types.h>
>>
>> +struct drm_i915_private;
>> struct intel_atomic_state;
>> struct intel_cdclk_funcs;
>> struct intel_clock_gating_funcs;
>> @@ -31,6 +32,23 @@ struct intel_display_funcs {
>> void (*commit_modeset_enables)(struct intel_atomic_state *state);
>> };
>>
>> +/* functions used for watermark calcs for display. */ struct
>> +intel_wm_funcs {
>> + /* update_wm is for legacy wm management */
>> + void (*update_wm)(struct drm_i915_private *dev_priv);
>> + int (*compute_pipe_wm)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + int (*compute_intermediate_wm)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*initial_watermarks)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*atomic_update_watermarks)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + void (*optimize_watermarks)(struct intel_atomic_state *state,
>> + struct intel_crtc *crtc);
>> + int (*compute_global_watermarks)(struct intel_atomic_state *state);
>> };
>> +
>> struct intel_display {
>> /* Display functions */
>> struct {
>> @@ -48,6 +66,9 @@ struct intel_display {
>>
>> /* pm private clock gating functions */
>> const struct intel_clock_gating_funcs *clock_gating;
>> +
>> + /* pm display functions */
>> + const struct intel_wm_funcs *wm;
>> } funcs;
>
> Can the wm, dbuf, clock related move to a struct intel_pm ? which
> makes it more meaningful else again we end up creating a struct
> intel_display a long one like i915_private.
Well, I think the display wm/dbuf stuff also needs to be split from
intel_pm.c so it's not so clear cut. And for now, I'm keeping the
functions together.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
2022-08-12 6:54 ` Jani Nikula
@ 2022-08-16 3:48 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 3:48 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:25 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to
> display.funcs
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index 98c6ccdc9100..a6843ebcca5a 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -8,6 +8,7 @@
> >>
> >> #include <linux/types.h>
> >>
> >> +struct drm_i915_private;
> >> struct intel_atomic_state;
> >> struct intel_cdclk_funcs;
> >> struct intel_clock_gating_funcs;
> >> @@ -31,6 +32,23 @@ struct intel_display_funcs {
> >> void (*commit_modeset_enables)(struct intel_atomic_state
> >> *state); };
> >>
> >> +/* functions used for watermark calcs for display. */ struct
> >> +intel_wm_funcs {
> >> + /* update_wm is for legacy wm management */
> >> + void (*update_wm)(struct drm_i915_private *dev_priv);
> >> + int (*compute_pipe_wm)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + int (*compute_intermediate_wm)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + void (*initial_watermarks)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + void (*atomic_update_watermarks)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + void (*optimize_watermarks)(struct intel_atomic_state *state,
> >> + struct intel_crtc *crtc);
> >> + int (*compute_global_watermarks)(struct intel_atomic_state
> >> +*state);
> >> };
> >> +
> >> struct intel_display {
> >> /* Display functions */
> >> struct {
> >> @@ -48,6 +66,9 @@ struct intel_display {
> >>
> >> /* pm private clock gating functions */
> >> const struct intel_clock_gating_funcs *clock_gating;
> >> +
> >> + /* pm display functions */
> >> + const struct intel_wm_funcs *wm;
> >> } funcs;
> >
> > Can the wm, dbuf, clock related move to a struct intel_pm ? which
> > makes it more meaningful else again we end up creating a struct
> > intel_display a long one like i915_private.
>
> Well, I think the display wm/dbuf stuff also needs to be split from intel_pm.c
> so it's not so clear cut. And for now, I'm keeping the functions together.
Ok, lets take it up in the later. But adding a TODO would make it clear that some more clean up in this regards is in queue.
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs " Jani Nikula
2022-08-12 4:45 ` Murthy, Arun R
@ 2022-08-17 3:50 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 3:50 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:17PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Rename struct drm_i915_wm_disp_funcs to intel_wm_funcs while at it.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (5 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 06/39] drm/i915: move wm_disp funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:48 ` Murthy, Arun R
2022-08-17 3:51 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs " Jani Nikula
` (37 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++++
drivers/gpu/drm/i915/display/intel_fdi.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 4 ----
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index a6843ebcca5a..7dbffaebd9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,6 +15,7 @@ struct intel_clock_gating_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
+struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
@@ -69,6 +70,9 @@ struct intel_display {
/* pm display functions */
const struct intel_wm_funcs *wm;
+
+ /* fdi display functions */
+ const struct intel_fdi_funcs *fdi;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 67d2484afbaa..03ad5f5c8417 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -113,7 +113,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
+ dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1066,11 +1066,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs = &ilk_funcs;
+ dev_priv->display.funcs.fdi = &ilk_funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs = &gen6_funcs;
+ dev_priv->display.funcs.fdi = &gen6_funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs = &ivb_funcs;
+ dev_priv->display.funcs.fdi = &ivb_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 69a8cce48fc4..8a9f2bf24186 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,7 +89,6 @@ struct intel_connector;
struct intel_dp;
struct intel_encoder;
struct intel_fbdev;
-struct intel_fdi_funcs;
struct intel_gmbus;
struct intel_limit;
struct intel_overlay;
@@ -482,9 +481,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* fdi display functions */
- const struct intel_fdi_funcs *fdi_funcs;
-
/* Display internal color functions */
const struct intel_color_funcs *color_funcs;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs " Jani Nikula
@ 2022-08-12 4:48 ` Murthy, Arun R
2022-08-17 3:51 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:48 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs " Jani Nikula
2022-08-12 4:48 ` Murthy, Arun R
@ 2022-08-17 3:51 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 3:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:18PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (6 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 07/39] drm/i915: move fdi_funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:49 ` Murthy, Arun R
2022-08-17 3:52 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus Jani Nikula
` (36 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 34 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 4 +++
drivers/gpu/drm/i915/i915_drv.h | 4 ---
3 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 9583d17e858d..ed98c732b24e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1167,22 +1167,22 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs->load_luts(crtc_state);
+ dev_priv->display.funcs.color->load_luts(crtc_state);
}
void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs->color_commit_noarm)
- dev_priv->color_funcs->color_commit_noarm(crtc_state);
+ if (dev_priv->display.funcs.color->color_commit_noarm)
+ dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
}
void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs->color_commit_arm(crtc_state);
+ dev_priv->display.funcs.color->color_commit_arm(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
@@ -1238,15 +1238,15 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs->color_check(crtc_state);
+ return dev_priv->display.funcs.color->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs->read_luts)
- dev_priv->color_funcs->read_luts(crtc_state);
+ if (dev_priv->display.funcs.color->read_luts)
+ dev_priv->display.funcs.color->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2225,28 +2225,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs = &chv_color_funcs;
+ dev_priv->display.funcs.color = &chv_color_funcs;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->color_funcs = &i965_color_funcs;
+ dev_priv->display.funcs.color = &i965_color_funcs;
} else {
- dev_priv->color_funcs = &i9xx_color_funcs;
+ dev_priv->display.funcs.color = &i9xx_color_funcs;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->color_funcs = &icl_color_funcs;
+ dev_priv->display.funcs.color = &icl_color_funcs;
else if (DISPLAY_VER(dev_priv) == 10)
- dev_priv->color_funcs = &glk_color_funcs;
+ dev_priv->display.funcs.color = &glk_color_funcs;
else if (DISPLAY_VER(dev_priv) == 9)
- dev_priv->color_funcs = &skl_color_funcs;
+ dev_priv->display.funcs.color = &skl_color_funcs;
else if (DISPLAY_VER(dev_priv) == 8)
- dev_priv->color_funcs = &bdw_color_funcs;
+ dev_priv->display.funcs.color = &bdw_color_funcs;
else if (DISPLAY_VER(dev_priv) == 7) {
if (IS_HASWELL(dev_priv))
- dev_priv->color_funcs = &hsw_color_funcs;
+ dev_priv->display.funcs.color = &hsw_color_funcs;
else
- dev_priv->color_funcs = &ivb_color_funcs;
+ dev_priv->display.funcs.color = &ivb_color_funcs;
} else
- dev_priv->color_funcs = &ilk_color_funcs;
+ dev_priv->display.funcs.color = &ilk_color_funcs;
}
drm_crtc_enable_color_mgmt(&crtc->base,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 7dbffaebd9c0..306584c038c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -12,6 +12,7 @@ struct drm_i915_private;
struct intel_atomic_state;
struct intel_cdclk_funcs;
struct intel_clock_gating_funcs;
+struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
@@ -73,6 +74,9 @@ struct intel_display {
/* fdi display functions */
const struct intel_fdi_funcs *fdi;
+
+ /* Display internal color functions */
+ const struct intel_color_funcs *color;
} funcs;
};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8a9f2bf24186..a2ce11f01a6d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -84,7 +84,6 @@ struct intel_audio_funcs;
struct intel_cdclk_config;
struct intel_cdclk_state;
struct intel_cdclk_vals;
-struct intel_color_funcs;
struct intel_connector;
struct intel_dp;
struct intel_encoder;
@@ -481,9 +480,6 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
- /* Display internal color functions */
- const struct intel_color_funcs *color_funcs;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs " Jani Nikula
@ 2022-08-12 4:49 ` Murthy, Arun R
2022-08-17 3:52 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:49 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to
> display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs to display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs " Jani Nikula
2022-08-12 4:49 ` Murthy, Arun R
@ 2022-08-17 3:52 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 3:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:19PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_color.c | 34 +++++++++----------
> .../gpu/drm/i915/display/intel_display_core.h | 4 +++
> drivers/gpu/drm/i915/i915_drv.h | 4 ---
> 3 files changed, 21 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
>index 9583d17e858d..ed98c732b24e 100644
>--- a/drivers/gpu/drm/i915/display/intel_color.c
>+++ b/drivers/gpu/drm/i915/display/intel_color.c
>@@ -1167,22 +1167,22 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
>- dev_priv->color_funcs->load_luts(crtc_state);
>+ dev_priv->display.funcs.color->load_luts(crtc_state);
> }
>
> void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>
>- if (dev_priv->color_funcs->color_commit_noarm)
>- dev_priv->color_funcs->color_commit_noarm(crtc_state);
>+ if (dev_priv->display.funcs.color->color_commit_noarm)
>+ dev_priv->display.funcs.color->color_commit_noarm(crtc_state);
similar comment as for crtc. Maybe later we can remove the color_
prefix?
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (7 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 08/39] drm/i915: move color_funcs " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:53 ` Murthy, Arun R
2022-08-17 3:56 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps Jani Nikula
` (35 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
.../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 16 -------
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 14 +++---
7 files changed, 59 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 6095f5800a2e..ea40c75c2986 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
* functions use cdclk. Not all platforms/ports do,
* but we'll lock them all for simplicity.
*/
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus.mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
- &dev_priv->gmbus_mutex);
+ &dev_priv->display.gmbus.mutex);
}
intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
@@ -2113,7 +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
mutex_unlock(&intel_dp->aux.hw_mutex);
}
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus.mutex);
for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 306584c038c9..fe19d4f9a9ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -6,7 +6,11 @@
#ifndef __INTEL_DISPLAY_CORE_H__
#define __INTEL_DISPLAY_CORE_H__
+#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/wait.h>
+
+#include "intel_gmbus.h"
struct drm_i915_private;
struct intel_atomic_state;
@@ -78,6 +82,25 @@ struct intel_display {
/* Display internal color functions */
const struct intel_color_funcs *color;
} funcs;
+
+ /* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /*
+ * Base address of where the gmbus and gpio blocks are located
+ * (either on PCH or on SoC for platforms without PCH).
+ */
+ u32 mmio_base;
+
+ /*
+ * gmbus.mutex protects against concurrent usage of the single
+ * hw gmbus controller on different i2c buses.
+ */
+ struct mutex mutex;
+
+ struct intel_gmbus *bus[GMBUS_NUM_PINS];
+
+ wait_queue_head_t wait_queue;
+ } gmbus;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2bc119374555..227fbee88b89 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -42,7 +42,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
bool done;
#define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
- done = wait_event_timeout(i915->gmbus_wait_queue, C,
+ done = wait_event_timeout(i915->display.gmbus.wait_queue, C,
msecs_to_jiffies_timeout(timeout_ms));
/* just trace the final value */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index a6ba7fb72339..c3992b1ca842 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -369,7 +369,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
if (!has_gmbus_irq(dev_priv))
irq_en = 0;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_en);
status |= GMBUS_SATOER;
@@ -380,7 +380,7 @@ static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
50);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -400,7 +400,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
if (has_gmbus_irq(dev_priv))
irq_enable = GMBUS_IDLE_EN;
- add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ add_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
intel_de_write_fw(dev_priv, GMBUS4, irq_enable);
ret = intel_wait_for_register_fw(&dev_priv->uncore,
@@ -408,7 +408,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
10);
intel_de_write_fw(dev_priv, GMBUS4, 0);
- remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
+ remove_wait_queue(&dev_priv->display.gmbus.wait_queue, &wait);
return ret;
}
@@ -791,7 +791,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
int ret;
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus.mutex);
/*
* In order to output Aksv to the receiver, use an indexed write to
@@ -800,7 +800,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
*/
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus.mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
return ret;
@@ -826,7 +826,7 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus.mutex);
}
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
@@ -835,7 +835,7 @@ static int gmbus_trylock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- return mutex_trylock(&dev_priv->gmbus_mutex);
+ return mutex_trylock(&dev_priv->display.gmbus.mutex);
}
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
@@ -844,7 +844,7 @@ static void gmbus_unlock_bus(struct i2c_adapter *adapter,
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus.mutex);
}
static const struct i2c_lock_operations gmbus_lock_ops = {
@@ -864,18 +864,18 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
int ret;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH(dev_priv))
/*
* Broxton uses the same PCH offsets for South Display Engine,
* even though it doesn't have a PCH.
*/
- dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
+ dev_priv->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
- mutex_init(&dev_priv->gmbus_mutex);
- init_waitqueue_head(&dev_priv->gmbus_wait_queue);
+ mutex_init(&dev_priv->display.gmbus.mutex);
+ init_waitqueue_head(&dev_priv->display.gmbus.wait_queue);
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
const struct gmbus_pin *gmbus_pin;
struct intel_gmbus *bus;
@@ -922,7 +922,7 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
goto err;
}
- dev_priv->gmbus[pin] = bus;
+ dev_priv->display.gmbus.bus[pin] = bus;
}
intel_gmbus_reset(dev_priv);
@@ -938,11 +938,11 @@ int intel_gmbus_setup(struct drm_i915_private *dev_priv)
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
unsigned int pin)
{
- if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->gmbus) ||
- !dev_priv->gmbus[pin]))
+ if (drm_WARN_ON(&dev_priv->drm, pin >= ARRAY_SIZE(dev_priv->display.gmbus.bus) ||
+ !dev_priv->display.gmbus.bus[pin]))
return NULL;
- return &dev_priv->gmbus[pin]->adapter;
+ return &dev_priv->display.gmbus.bus[pin]->adapter;
}
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
@@ -950,7 +950,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
struct intel_gmbus *bus = to_intel_gmbus(adapter);
struct drm_i915_private *dev_priv = bus->dev_priv;
- mutex_lock(&dev_priv->gmbus_mutex);
+ mutex_lock(&dev_priv->display.gmbus.mutex);
bus->force_bit += force_bit ? 1 : -1;
drm_dbg_kms(&dev_priv->drm,
@@ -958,7 +958,7 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
force_bit ? "en" : "dis", adapter->name,
bus->force_bit);
- mutex_unlock(&dev_priv->gmbus_mutex);
+ mutex_unlock(&dev_priv->display.gmbus.mutex);
}
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
@@ -972,16 +972,16 @@ void intel_gmbus_teardown(struct drm_i915_private *dev_priv)
{
unsigned int pin;
- for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(dev_priv->display.gmbus.bus); pin++) {
struct intel_gmbus *bus;
- bus = dev_priv->gmbus[pin];
+ bus = dev_priv->display.gmbus.bus[pin];
if (!bus)
continue;
i2c_del_adapter(&bus->adapter);
kfree(bus);
- dev_priv->gmbus[pin] = NULL;
+ dev_priv->display.gmbus.bus[pin] = NULL;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2ce11f01a6d..413d037a214d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -47,7 +47,6 @@
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "display/intel_global_state.h"
-#include "display/intel_gmbus.h"
#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
@@ -88,7 +87,6 @@ struct intel_connector;
struct intel_dp;
struct intel_encoder;
struct intel_fbdev;
-struct intel_gmbus;
struct intel_limit;
struct intel_overlay;
struct intel_overlay_error_state;
@@ -382,25 +380,11 @@ struct drm_i915_private {
struct intel_dmc dmc;
- struct intel_gmbus *gmbus[GMBUS_NUM_PINS];
-
- /** gmbus_mutex protects against concurrent usage of the single hw gmbus
- * controller on different i2c buses. */
- struct mutex gmbus_mutex;
-
- /**
- * Base address of where the gmbus and gpio blocks are located (either
- * on PCH or on SoC for platforms without PCH).
- */
- u32 gpio_mmio_base;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
u32 pps_mmio_base;
- wait_queue_head_t gmbus_wait_queue;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c1b8f949c53d..b0095b289a79 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1304,12 +1304,12 @@ static u32 intel_hpd_hotplug_enables(struct drm_i915_private *i915,
static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display.gmbus.wait_queue);
}
static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
{
- wake_up_all(&dev_priv->gmbus_wait_queue);
+ wake_up_all(&dev_priv->display.gmbus.wait_queue);
}
#if defined(CONFIG_DEBUG_FS)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ad2c441aceca..64342d8ccc5e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1464,7 +1464,7 @@
/*
* GPIO regs
*/
-#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
+#define GPIO(gpio) _MMIO(dev_priv->display.gmbus.mmio_base + 0x5010 + \
4 * (gpio))
# define GPIO_CLOCK_DIR_MASK (1 << 0)
@@ -1482,7 +1482,7 @@
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
-#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS0 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -1491,7 +1491,7 @@
#define GMBUS_HOLD_EXT (1 << 7) /* 300ns hold time, rsvd on Pineview */
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
-#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+#define GMBUS1 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -1506,7 +1506,7 @@
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
#define GMBUS_SLAVE_WRITE (0 << 0)
-#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
+#define GMBUS2 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5108) /* status */
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -1514,14 +1514,14 @@
#define GMBUS_HW_RDY (1 << 11)
#define GMBUS_SATOER (1 << 10)
#define GMBUS_ACTIVE (1 << 9)
-#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+#define GMBUS3 _MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */
+#define GMBUS4 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
#define GMBUS_HW_WAIT_EN (1 << 1)
#define GMBUS_HW_RDY_EN (1 << 0)
-#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+#define GMBUS5 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5120) /* byte index */
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-11 15:07 ` [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus Jani Nikula
@ 2022-08-12 4:53 ` Murthy, Arun R
2022-08-12 6:56 ` Jani Nikula
2022-08-17 3:56 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:53 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> members under display.gmbus
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
> drivers/gpu/drm/i915/i915_drv.h | 16 -------
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
> 7 files changed, 59 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 6095f5800a2e..ea40c75c2986 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
> drm_i915_private *dev_priv,
> * functions use cdclk. Not all platforms/ports do,
> * but we'll lock them all for simplicity.
> */
> - mutex_lock(&dev_priv->gmbus_mutex);
> + mutex_lock(&dev_priv->display.gmbus.mutex);
> for_each_intel_dp(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
> - &dev_priv->gmbus_mutex);
> + &dev_priv->display.gmbus.mutex);
> }
>
> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&intel_dp->aux.hw_mutex);
> }
> - mutex_unlock(&dev_priv->gmbus_mutex);
> + mutex_unlock(&dev_priv->display.gmbus.mutex);
>
> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --
> git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 306584c038c9..fe19d4f9a9ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -6,7 +6,11 @@
> #ifndef __INTEL_DISPLAY_CORE_H__
> #define __INTEL_DISPLAY_CORE_H__
>
> +#include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/wait.h>
> +
> +#include "intel_gmbus.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
> @@ -78,6 +82,25 @@ struct intel_display {
> /* Display internal color functions */
> const struct intel_color_funcs *color;
> } funcs;
> +
> + /* Grouping using anonymous structs. Keep sorted. */
> + struct {
> + /*
> + * Base address of where the gmbus and gpio blocks are
> located
> + * (either on PCH or on SoC for platforms without PCH).
> + */
> + u32 mmio_base;
> +
> + /*
> + * gmbus.mutex protects against concurrent usage of the
> single
> + * hw gmbus controller on different i2c buses.
> + */
> + struct mutex mutex;
> +
> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
> +
> + wait_queue_head_t wait_queue;
> + } gmbus;
> };
Can this be moved to struct intel_dp?
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-12 4:53 ` Murthy, Arun R
@ 2022-08-12 6:56 ` Jani Nikula
2022-08-16 3:59 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:56 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
>> members under display.gmbus
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
>> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
>> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
>> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
>> drivers/gpu/drm/i915/i915_drv.h | 16 -------
>> drivers/gpu/drm/i915/i915_irq.c | 4 +-
>> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
>> 7 files changed, 59 insertions(+), 52 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 6095f5800a2e..ea40c75c2986 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
>> drm_i915_private *dev_priv,
>> * functions use cdclk. Not all platforms/ports do,
>> * but we'll lock them all for simplicity.
>> */
>> - mutex_lock(&dev_priv->gmbus_mutex);
>> + mutex_lock(&dev_priv->display.gmbus.mutex);
>> for_each_intel_dp(&dev_priv->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>>
>> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
>> - &dev_priv->gmbus_mutex);
>> + &dev_priv->display.gmbus.mutex);
>> }
>>
>> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
>> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>>
>> mutex_unlock(&intel_dp->aux.hw_mutex);
>> }
>> - mutex_unlock(&dev_priv->gmbus_mutex);
>> + mutex_unlock(&dev_priv->display.gmbus.mutex);
>>
>> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> struct intel_dp *intel_dp = enc_to_intel_dp(encoder); diff --
>> git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 306584c038c9..fe19d4f9a9ab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -6,7 +6,11 @@
>> #ifndef __INTEL_DISPLAY_CORE_H__
>> #define __INTEL_DISPLAY_CORE_H__
>>
>> +#include <linux/mutex.h>
>> #include <linux/types.h>
>> +#include <linux/wait.h>
>> +
>> +#include "intel_gmbus.h"
>>
>> struct drm_i915_private;
>> struct intel_atomic_state;
>> @@ -78,6 +82,25 @@ struct intel_display {
>> /* Display internal color functions */
>> const struct intel_color_funcs *color;
>> } funcs;
>> +
>> + /* Grouping using anonymous structs. Keep sorted. */
>> + struct {
>> + /*
>> + * Base address of where the gmbus and gpio blocks are
>> located
>> + * (either on PCH or on SoC for platforms without PCH).
>> + */
>> + u32 mmio_base;
>> +
>> + /*
>> + * gmbus.mutex protects against concurrent usage of the
>> single
>> + * hw gmbus controller on different i2c buses.
>> + */
>> + struct mutex mutex;
>> +
>> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
>> +
>> + wait_queue_head_t wait_queue;
>> + } gmbus;
>> };
>
> Can this be moved to struct intel_dp?
Well, no. The data here is shared across all of them.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-12 6:56 ` Jani Nikula
@ 2022-08-16 3:59 ` Murthy, Arun R
2022-08-16 7:50 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 3:59 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:26 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> members under display.gmbus
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> <lucas.demarchi@intel.com>
> >> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> >> members under display.gmbus
> >>
> >> Move display related members under drm_i915_private display sub-
> struct.
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
> >> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
> >> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> >> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
> >> drivers/gpu/drm/i915/i915_drv.h | 16 -------
> >> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> >> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
> >> 7 files changed, 59 insertions(+), 52 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 6095f5800a2e..ea40c75c2986 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
> >> drm_i915_private *dev_priv,
> >> * functions use cdclk. Not all platforms/ports do,
> >> * but we'll lock them all for simplicity.
> >> */
> >> - mutex_lock(&dev_priv->gmbus_mutex);
> >> + mutex_lock(&dev_priv->display.gmbus.mutex);
> >> for_each_intel_dp(&dev_priv->drm, encoder) {
> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >>
> >> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
> >> - &dev_priv->gmbus_mutex);
> >> + &dev_priv->display.gmbus.mutex);
> >> }
> >>
> >> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
> >> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private
> >> +*dev_priv,
> >>
> >> mutex_unlock(&intel_dp->aux.hw_mutex);
> >> }
> >> - mutex_unlock(&dev_priv->gmbus_mutex);
> >> + mutex_unlock(&dev_priv->display.gmbus.mutex);
> >>
> >> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> >> diff -- git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index 306584c038c9..fe19d4f9a9ab 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -6,7 +6,11 @@
> >> #ifndef __INTEL_DISPLAY_CORE_H__
> >> #define __INTEL_DISPLAY_CORE_H__
> >>
> >> +#include <linux/mutex.h>
> >> #include <linux/types.h>
> >> +#include <linux/wait.h>
> >> +
> >> +#include "intel_gmbus.h"
> >>
> >> struct drm_i915_private;
> >> struct intel_atomic_state;
> >> @@ -78,6 +82,25 @@ struct intel_display {
> >> /* Display internal color functions */
> >> const struct intel_color_funcs *color;
> >> } funcs;
> >> +
> >> + /* Grouping using anonymous structs. Keep sorted. */
> >> + struct {
> >> + /*
> >> + * Base address of where the gmbus and gpio blocks are
> >> located
> >> + * (either on PCH or on SoC for platforms without PCH).
> >> + */
> >> + u32 mmio_base;
> >> +
> >> + /*
> >> + * gmbus.mutex protects against concurrent usage of the
> >> single
> >> + * hw gmbus controller on different i2c buses.
> >> + */
> >> + struct mutex mutex;
> >> +
> >> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
> >> +
> >> + wait_queue_head_t wait_queue;
> >> + } gmbus;
> >> };
> >
> > Can this be moved to struct intel_dp?
>
> Well, no. The data here is shared across all of them.
>
Then maybe we might need to think on this. I somehow feel having this under display wont look good. Since it's a low level bus communication, can be tagged under bus related to interface.
I agree from your other comments that this is just a first step to cleanup i915 and there is scope to cleanup further.
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
-------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-16 3:59 ` Murthy, Arun R
@ 2022-08-16 7:50 ` Jani Nikula
2022-08-16 8:04 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-16 7:50 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Friday, August 12, 2022 12:26 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Subject: RE: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
>> members under display.gmbus
>>
>> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> >> -----Original Message-----
>> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
>> >> Of Jani Nikula
>> >> Sent: Thursday, August 11, 2022 8:37 PM
>> >> To: intel-gfx@lists.freedesktop.org
>> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> >> <lucas.demarchi@intel.com>
>> >> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
>> >> members under display.gmbus
>> >>
>> >> Move display related members under drm_i915_private display sub-
>> struct.
>> >>
>> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> >> ---
>> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
>> >> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
>> >> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
>> >> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
>> >> drivers/gpu/drm/i915/i915_drv.h | 16 -------
>> >> drivers/gpu/drm/i915/i915_irq.c | 4 +-
>> >> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
>> >> 7 files changed, 59 insertions(+), 52 deletions(-)
>> >>
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> >> b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> >> index 6095f5800a2e..ea40c75c2986 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> >> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
>> >> drm_i915_private *dev_priv,
>> >> * functions use cdclk. Not all platforms/ports do,
>> >> * but we'll lock them all for simplicity.
>> >> */
>> >> - mutex_lock(&dev_priv->gmbus_mutex);
>> >> + mutex_lock(&dev_priv->display.gmbus.mutex);
>> >> for_each_intel_dp(&dev_priv->drm, encoder) {
>> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >>
>> >> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
>> >> - &dev_priv->gmbus_mutex);
>> >> + &dev_priv->display.gmbus.mutex);
>> >> }
>> >>
>> >> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@ -2113,7
>> >> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private
>> >> +*dev_priv,
>> >>
>> >> mutex_unlock(&intel_dp->aux.hw_mutex);
>> >> }
>> >> - mutex_unlock(&dev_priv->gmbus_mutex);
>> >> + mutex_unlock(&dev_priv->display.gmbus.mutex);
>> >>
>> >> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
>> >> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> >> diff -- git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> index 306584c038c9..fe19d4f9a9ab 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> @@ -6,7 +6,11 @@
>> >> #ifndef __INTEL_DISPLAY_CORE_H__
>> >> #define __INTEL_DISPLAY_CORE_H__
>> >>
>> >> +#include <linux/mutex.h>
>> >> #include <linux/types.h>
>> >> +#include <linux/wait.h>
>> >> +
>> >> +#include "intel_gmbus.h"
>> >>
>> >> struct drm_i915_private;
>> >> struct intel_atomic_state;
>> >> @@ -78,6 +82,25 @@ struct intel_display {
>> >> /* Display internal color functions */
>> >> const struct intel_color_funcs *color;
>> >> } funcs;
>> >> +
>> >> + /* Grouping using anonymous structs. Keep sorted. */
>> >> + struct {
>> >> + /*
>> >> + * Base address of where the gmbus and gpio blocks are
>> >> located
>> >> + * (either on PCH or on SoC for platforms without PCH).
>> >> + */
>> >> + u32 mmio_base;
>> >> +
>> >> + /*
>> >> + * gmbus.mutex protects against concurrent usage of the
>> >> single
>> >> + * hw gmbus controller on different i2c buses.
>> >> + */
>> >> + struct mutex mutex;
>> >> +
>> >> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
>> >> +
>> >> + wait_queue_head_t wait_queue;
>> >> + } gmbus;
>> >> };
>> >
>> > Can this be moved to struct intel_dp?
>>
>> Well, no. The data here is shared across all of them.
>>
> Then maybe we might need to think on this. I somehow feel having this under display wont look good. Since it's a low level bus communication, can be tagged under bus related to interface.
> I agree from your other comments that this is just a first step to cleanup i915 and there is scope to cleanup further.
As I've explained elsewhere, the "display" here should be taken to be
very high level. Not "a display device", but "everything related to
display hardware". Only display needs gmbus, nothing else.
There may be further cleanups to be made, but this series has a very
specific purpose of splitting the display parts to a display sub-struct
of drm_i915_private. This is already 39 patches, it's not even complete
on that target, so need to not lose focus here.
BR,
Jani.
>
> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
>
> Thanks and Regards,
> Arun R Murthy
> -------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-16 7:50 ` Jani Nikula
@ 2022-08-16 8:04 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 8:04 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, August 16, 2022 1:21 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> members under display.gmbus
>
> On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Friday, August 12, 2022 12:26 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> >> Subject: RE: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> >> members under display.gmbus
> >>
> >> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> >> -----Original Message-----
> >> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> >> >> Behalf Of Jani Nikula
> >> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> >> To: intel-gfx@lists.freedesktop.org
> >> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> >> <lucas.demarchi@intel.com>
> >> >> Subject: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus
> >> >> members under display.gmbus
> >> >>
> >> >> Move display related members under drm_i915_private display sub-
> >> struct.
> >> >>
> >> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> >> ---
> >> >> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
> >> >> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
> >> >> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> >> >> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
> >> >> drivers/gpu/drm/i915/i915_drv.h | 16 -------
> >> >> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> >> >> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
> >> >> 7 files changed, 59 insertions(+), 52 deletions(-)
> >> >>
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> >> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> >> index 6095f5800a2e..ea40c75c2986 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> >> @@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct
> >> >> drm_i915_private *dev_priv,
> >> >> * functions use cdclk. Not all platforms/ports do,
> >> >> * but we'll lock them all for simplicity.
> >> >> */
> >> >> - mutex_lock(&dev_priv->gmbus_mutex);
> >> >> + mutex_lock(&dev_priv->display.gmbus.mutex);
> >> >> for_each_intel_dp(&dev_priv->drm, encoder) {
> >> >> struct intel_dp *intel_dp =
> >> >> enc_to_intel_dp(encoder);
> >> >>
> >> >> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
> >> >> - &dev_priv->gmbus_mutex);
> >> >> +
> >> >> + &dev_priv->display.gmbus.mutex);
> >> >> }
> >> >>
> >> >> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); @@
> >> >> -2113,7
> >> >> +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private
> >> >> +*dev_priv,
> >> >>
> >> >> mutex_unlock(&intel_dp->aux.hw_mutex);
> >> >> }
> >> >> - mutex_unlock(&dev_priv->gmbus_mutex);
> >> >> + mutex_unlock(&dev_priv->display.gmbus.mutex);
> >> >>
> >> >> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> >> >> struct intel_dp *intel_dp =
> >> >> enc_to_intel_dp(encoder); diff -- git
> >> >> a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> index 306584c038c9..fe19d4f9a9ab 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> @@ -6,7 +6,11 @@
> >> >> #ifndef __INTEL_DISPLAY_CORE_H__
> >> >> #define __INTEL_DISPLAY_CORE_H__
> >> >>
> >> >> +#include <linux/mutex.h>
> >> >> #include <linux/types.h>
> >> >> +#include <linux/wait.h>
> >> >> +
> >> >> +#include "intel_gmbus.h"
> >> >>
> >> >> struct drm_i915_private;
> >> >> struct intel_atomic_state;
> >> >> @@ -78,6 +82,25 @@ struct intel_display {
> >> >> /* Display internal color functions */
> >> >> const struct intel_color_funcs *color;
> >> >> } funcs;
> >> >> +
> >> >> + /* Grouping using anonymous structs. Keep sorted. */
> >> >> + struct {
> >> >> + /*
> >> >> + * Base address of where the gmbus and gpio blocks
> >> >> + are
> >> >> located
> >> >> + * (either on PCH or on SoC for platforms without PCH).
> >> >> + */
> >> >> + u32 mmio_base;
> >> >> +
> >> >> + /*
> >> >> + * gmbus.mutex protects against concurrent usage of
> >> >> + the
> >> >> single
> >> >> + * hw gmbus controller on different i2c buses.
> >> >> + */
> >> >> + struct mutex mutex;
> >> >> +
> >> >> + struct intel_gmbus *bus[GMBUS_NUM_PINS];
> >> >> +
> >> >> + wait_queue_head_t wait_queue;
> >> >> + } gmbus;
> >> >> };
> >> >
> >> > Can this be moved to struct intel_dp?
> >>
> >> Well, no. The data here is shared across all of them.
> >>
> > Then maybe we might need to think on this. I somehow feel having this
> under display wont look good. Since it's a low level bus communication, can
> be tagged under bus related to interface.
> > I agree from your other comments that this is just a first step to cleanup
> i915 and there is scope to cleanup further.
>
> As I've explained elsewhere, the "display" here should be taken to be very
> high level. Not "a display device", but "everything related to display
> hardware". Only display needs gmbus, nothing else.
>
> There may be further cleanups to be made, but this series has a very specific
> purpose of splitting the display parts to a display sub-struct of
> drm_i915_private. This is already 39 patches, it's not even complete on that
> target, so need to not lose focus here.
>
Totally agree, lets take it up later after this series gets merged.
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus
2022-08-11 15:07 ` [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus Jani Nikula
2022-08-12 4:53 ` Murthy, Arun R
@ 2022-08-17 3:56 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 3:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:20PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +--
> .../gpu/drm/i915/display/intel_display_core.h | 23 ++++++++++
> drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 46 +++++++++----------
> drivers/gpu/drm/i915/i915_drv.h | 16 -------
> drivers/gpu/drm/i915/i915_irq.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 14 +++---
> 7 files changed, 59 insertions(+), 52 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>index 6095f5800a2e..ea40c75c2986 100644
>--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>@@ -2098,12 +2098,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
> * functions use cdclk. Not all platforms/ports do,
> * but we'll lock them all for simplicity.
> */
>- mutex_lock(&dev_priv->gmbus_mutex);
>+ mutex_lock(&dev_priv->display.gmbus.mutex);
> for_each_intel_dp(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>
> mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
>- &dev_priv->gmbus_mutex);
>+ &dev_priv->display.gmbus.mutex);
> }
>
> intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
>@@ -2113,7 +2113,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
>
> mutex_unlock(&intel_dp->aux.hw_mutex);
> }
>- mutex_unlock(&dev_priv->gmbus_mutex);
>+ mutex_unlock(&dev_priv->display.gmbus.mutex);
>
> for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 306584c038c9..fe19d4f9a9ab 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -6,7 +6,11 @@
> #ifndef __INTEL_DISPLAY_CORE_H__
> #define __INTEL_DISPLAY_CORE_H__
>
>+#include <linux/mutex.h>
> #include <linux/types.h>
>+#include <linux/wait.h>
>+
>+#include "intel_gmbus.h"
>
> struct drm_i915_private;
> struct intel_atomic_state;
>@@ -78,6 +82,25 @@ struct intel_display {
> /* Display internal color functions */
> const struct intel_color_funcs *color;
> } funcs;
>+
>+ /* Grouping using anonymous structs. Keep sorted. */
this maybe deserves to be a comment on top of struct intel_display.
Maybe alsos s/Grouping/Group/
regardless,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (8 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 09/39] drm/i915: move and group gmbus members under display.gmbus Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:54 ` Murthy, Arun R
2022-08-17 3:57 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc Jani Nikula
` (34 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 7 +++
drivers/gpu/drm/i915/display/intel_pps.c | 48 +++++++++----------
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 5 --
drivers/gpu/drm/i915/i915_reg.h | 2 +-
5 files changed, 33 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index fe19d4f9a9ab..030ced4068bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -101,6 +101,13 @@ struct intel_display {
wait_queue_head_t wait_queue;
} gmbus;
+
+ struct {
+ u32 mmio_base;
+
+ /* protects panel power sequencer state */
+ struct mutex mutex;
+ } pps;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 1b21a341962f..9a66e03aa2d6 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -28,7 +28,7 @@ intel_wakeref_t intel_pps_lock(struct intel_dp *intel_dp)
* See intel_pps_reset_all() why we need a power domain reference here.
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
- mutex_lock(&dev_priv->pps_mutex);
+ mutex_lock(&dev_priv->display.pps.mutex);
return wakeref;
}
@@ -38,7 +38,7 @@ intel_wakeref_t intel_pps_unlock(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- mutex_unlock(&dev_priv->pps_mutex);
+ mutex_unlock(&dev_priv->display.pps.mutex);
intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
return 0;
@@ -163,7 +163,7 @@ vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum pipe pipe;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -212,7 +212,7 @@ bxt_power_sequencer_idx(struct intel_dp *intel_dp)
struct intel_connector *connector = intel_dp->attached_connector;
int backlight_controller = connector->panel.vbt.backlight.controller;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* We should never land here with regular DP ports */
drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
@@ -282,7 +282,7 @@ vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
enum port port = dig_port->base.port;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* try to find a pipe with this port selected */
/* first pick one where the panel is on */
@@ -407,7 +407,7 @@ static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -420,7 +420,7 @@ static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
intel_dp->pps.pps_pipe == INVALID_PIPE)
@@ -463,7 +463,7 @@ static void wait_panel_status(struct intel_dp *intel_dp,
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
intel_pps_verify_state(intel_dp);
@@ -556,7 +556,7 @@ static u32 ilk_get_pp_control(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u32 control;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
@@ -580,7 +580,7 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
i915_reg_t pp_stat_reg, pp_ctrl_reg;
bool need_to_disable = !intel_dp->pps.want_panel_vdd;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return false;
@@ -657,7 +657,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_stat_reg, pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.want_panel_vdd);
@@ -748,7 +748,7 @@ void intel_pps_vdd_off_unlocked(struct intel_dp *intel_dp, bool sync)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -771,7 +771,7 @@ void intel_pps_on_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -832,7 +832,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
u32 pp;
i915_reg_t pp_ctrl_reg;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!intel_dp_is_edp(intel_dp))
return;
@@ -991,7 +991,7 @@ static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
for_each_intel_dp(&dev_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -1021,7 +1021,7 @@ void vlv_pps_init(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE);
@@ -1064,7 +1064,7 @@ static void pps_vdd_init(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!edp_have_panel_vdd(intel_dp))
return;
@@ -1176,7 +1176,7 @@ static void pps_init_delays_bios(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
if (!pps_delays_valid(&intel_dp->pps.bios_pps_delays))
intel_pps_readout_hw_state(intel_dp, &intel_dp->pps.bios_pps_delays);
@@ -1223,7 +1223,7 @@ static void pps_init_delays_spec(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
* our hw here, which are all in 100usec. */
@@ -1246,7 +1246,7 @@ static void pps_init_delays(struct intel_dp *intel_dp)
struct edp_power_seq cur, vbt, spec,
*final = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
/* already initialized? */
if (pps_delays_valid(final))
@@ -1312,7 +1312,7 @@ static void pps_init_registers(struct intel_dp *intel_dp, bool force_disable_vdd
enum port port = dp_to_dig_port(intel_dp)->base.port;
const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;
- lockdep_assert_held(&dev_priv->pps_mutex);
+ lockdep_assert_held(&dev_priv->display.pps.mutex);
intel_pps_get_registers(intel_dp, ®s);
@@ -1487,11 +1487,11 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
void intel_pps_setup(struct drm_i915_private *i915)
{
if (HAS_PCH_SPLIT(i915) || IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- i915->pps_mmio_base = PCH_PPS_BASE;
+ i915->display.pps.mmio_base = PCH_PPS_BASE;
else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->pps_mmio_base = VLV_PPS_BASE;
+ i915->display.pps.mmio_base = VLV_PPS_BASE;
else
- i915->pps_mmio_base = PPS_BASE;
+ i915->display.pps.mmio_base = PPS_BASE;
}
void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index deb8a8b76965..694384e54fd7 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -337,7 +337,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->audio.mutex);
mutex_init(&dev_priv->wm.wm_mutex);
- mutex_init(&dev_priv->pps_mutex);
+ mutex_init(&dev_priv->display.pps.mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
i915_memcpy_init_early(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 413d037a214d..8ba133f37fb5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -383,8 +383,6 @@ struct drm_i915_private {
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
- u32 pps_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
@@ -421,9 +419,6 @@ struct drm_i915_private {
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
- /* protects panel power sequencer state */
- struct mutex pps_mutex;
-
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
unsigned int max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 64342d8ccc5e..0edb4490fc76 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2829,7 +2829,7 @@
#define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
#define PCH_PPS_BASE 0xC7200
-#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
+#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \
PPS_BASE + (reg) + \
(pps_idx) * 0x100)
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
2022-08-11 15:07 ` [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps Jani Nikula
@ 2022-08-12 4:54 ` Murthy, Arun R
2022-08-12 6:58 ` Jani Nikula
2022-08-17 3:57 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:54 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members
> under display.pps
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 7 +++
> drivers/gpu/drm/i915/display/intel_pps.c | 48 +++++++++----------
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 5 --
> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> 5 files changed, 33 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index fe19d4f9a9ab..030ced4068bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -101,6 +101,13 @@ struct intel_display {
>
> wait_queue_head_t wait_queue;
> } gmbus;
> +
> + struct {
> + u32 mmio_base;
> +
> + /* protects panel power sequencer state */
> + struct mutex mutex;
> + } pps;
> };
Again can this power related to be moved under a substruct intel_pm ?
Thanks and Regards
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
2022-08-12 4:54 ` Murthy, Arun R
@ 2022-08-12 6:58 ` Jani Nikula
2022-08-16 4:03 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 6:58 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members
>> under display.pps
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 7 +++
>> drivers/gpu/drm/i915/display/intel_pps.c | 48 +++++++++----------
>> drivers/gpu/drm/i915/i915_driver.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 5 --
>> drivers/gpu/drm/i915/i915_reg.h | 2 +-
>> 5 files changed, 33 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index fe19d4f9a9ab..030ced4068bb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -101,6 +101,13 @@ struct intel_display {
>>
>> wait_queue_head_t wait_queue;
>> } gmbus;
>> +
>> + struct {
>> + u32 mmio_base;
>> +
>> + /* protects panel power sequencer state */
>> + struct mutex mutex;
>> + } pps;
>> };
> Again can this power related to be moved under a substruct intel_pm ?
The pps is pretty well separated from rest of pm, so feels wrong to
shove it together with pm. And again, intel_pm makes me think intel_pm.c
which is not purely display, and needs to be reorganized.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
2022-08-12 6:58 ` Jani Nikula
@ 2022-08-16 4:03 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 4:03 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:28 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps
> members under display.pps
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> <lucas.demarchi@intel.com>
> >> Subject: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps
> >> members under display.pps
> >>
> >> Move display related members under drm_i915_private display sub-
> struct.
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> .../gpu/drm/i915/display/intel_display_core.h | 7 +++
> >> drivers/gpu/drm/i915/display/intel_pps.c | 48 +++++++++----------
> >> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> >> drivers/gpu/drm/i915/i915_drv.h | 5 --
> >> drivers/gpu/drm/i915/i915_reg.h | 2 +-
> >> 5 files changed, 33 insertions(+), 31 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index fe19d4f9a9ab..030ced4068bb 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -101,6 +101,13 @@ struct intel_display {
> >>
> >> wait_queue_head_t wait_queue;
> >> } gmbus;
> >> +
> >> + struct {
> >> + u32 mmio_base;
> >> +
> >> + /* protects panel power sequencer state */
> >> + struct mutex mutex;
> >> + } pps;
> >> };
> > Again can this power related to be moved under a substruct intel_pm ?
>
> The pps is pretty well separated from rest of pm, so feels wrong to shove it
> together with pm. And again, intel_pm makes me think intel_pm.c which is
> not purely display, and needs to be reorganized.
>
Maybe a subordinate of pm. Lets take it up later. I would prefer to have a TODO under all of these would lets us keep an eye on this part of the cleanup.
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps
2022-08-11 15:07 ` [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps Jani Nikula
2022-08-12 4:54 ` Murthy, Arun R
@ 2022-08-17 3:57 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 3:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:21PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (9 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 10/39] drm/i915: move and group pps members under display.pps Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 4:58 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs Jani Nikula
` (33 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
FIXME: dmc really needs to be abstracted and hidden inside intel_dmc.c
with display.dmc turned into a pointer
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 4 ++
.../drm/i915/display/intel_display_power.c | 18 +++----
.../i915/display/intel_display_power_well.c | 18 +++----
drivers/gpu/drm/i915/display/intel_dmc.c | 52 +++++++++----------
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 --
6 files changed, 49 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 030ced4068bb..ca22706e11e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -10,6 +10,7 @@
#include <linux/types.h>
#include <linux/wait.h>
+#include "intel_dmc.h"
#include "intel_gmbus.h"
struct drm_i915_private;
@@ -108,6 +109,9 @@ struct intel_display {
/* protects panel power sequencer state */
struct mutex mutex;
} pps;
+
+ /* Grouping using named structs. Keep sorted. */
+ struct intel_dmc dmc;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3f84af6beff3..07d083e95e37 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -268,7 +268,7 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
if (target_dc_state != states[i])
continue;
- if (dev_priv->dmc.allowed_dc_mask & target_dc_state)
+ if (dev_priv->display.dmc.allowed_dc_mask & target_dc_state)
break;
target_dc_state = states[i + 1];
@@ -301,7 +301,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
state = sanitize_target_dc_state(dev_priv, state);
- if (state == dev_priv->dmc.target_dc_state)
+ if (state == dev_priv->display.dmc.target_dc_state)
goto unlock;
dc_off_enabled = intel_power_well_is_enabled(dev_priv, power_well);
@@ -312,7 +312,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
if (!dc_off_enabled)
intel_power_well_enable(dev_priv, power_well);
- dev_priv->dmc.target_dc_state = state;
+ dev_priv->display.dmc.target_dc_state = state;
if (!dc_off_enabled)
intel_power_well_disable(dev_priv, power_well);
@@ -981,10 +981,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
dev_priv->params.disable_power_well);
- dev_priv->dmc.allowed_dc_mask =
+ dev_priv->display.dmc.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, dev_priv->params.enable_dc);
- dev_priv->dmc.target_dc_state =
+ dev_priv->display.dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
mutex_init(&power_domains->lock);
@@ -2050,7 +2050,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
* resources as required and also enable deeper system power states
* that would be blocked if the firmware was inactive.
*/
- if (!(i915->dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
+ if (!(i915->display.dmc.allowed_dc_mask & DC_STATE_EN_DC9) &&
suspend_mode == I915_DRM_SUSPEND_IDLE &&
intel_dmc_has_payload(i915)) {
intel_display_power_flush_work(i915);
@@ -2243,10 +2243,10 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
icl_display_core_init(i915, true);
if (intel_dmc_has_payload(i915)) {
- if (i915->dmc.allowed_dc_mask &
+ if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(i915);
- else if (i915->dmc.allowed_dc_mask &
+ else if (i915->display.dmc.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5)
gen9_enable_dc5(i915);
}
@@ -2254,7 +2254,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
bxt_disable_dc9(i915);
bxt_display_core_init(i915, true);
if (intel_dmc_has_payload(i915) &&
- (i915->dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
+ (i915->display.dmc.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
gen9_enable_dc5(i915);
} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
hsw_disable_pc8(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 91cfd5890f46..119e6134b789 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -710,8 +710,8 @@ void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Resetting DC state tracking from %02x to %02x\n",
- dev_priv->dmc.dc_state, val);
- dev_priv->dmc.dc_state = val;
+ dev_priv->display.dmc.dc_state, val);
+ dev_priv->display.dmc.dc_state = val;
}
/**
@@ -746,8 +746,8 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->dmc.allowed_dc_mask))
- state &= dev_priv->dmc.allowed_dc_mask;
+ state & ~dev_priv->display.dmc.allowed_dc_mask))
+ state &= dev_priv->display.dmc.allowed_dc_mask;
val = intel_de_read(dev_priv, DC_STATE_EN);
mask = gen9_dc_mask(dev_priv);
@@ -755,16 +755,16 @@ void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
val & mask, state);
/* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->dmc.dc_state)
+ if ((val & mask) != dev_priv->display.dmc.dc_state)
drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->dmc.dc_state, val & mask);
+ dev_priv->display.dmc.dc_state, val & mask);
val &= ~mask;
val |= state;
gen9_write_dc_state(dev_priv, val);
- dev_priv->dmc.dc_state = val & mask;
+ dev_priv->display.dmc.dc_state = val & mask;
}
static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
@@ -958,7 +958,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_config cdclk_config = {};
- if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
+ if (dev_priv->display.dmc.target_dc_state == DC_STATE_EN_DC3CO) {
tgl_disable_dc3co(dev_priv);
return;
}
@@ -1000,7 +1000,7 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!intel_dmc_has_payload(dev_priv))
return;
- switch (dev_priv->dmc.target_dc_state) {
+ switch (dev_priv->display.dmc.target_dc_state) {
case DC_STATE_EN_DC3CO:
tgl_enable_dc3co(dev_priv);
break;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 00e18a4a5a5a..21545fd72c1e 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -250,7 +250,7 @@ struct stepping_info {
static bool has_dmc_id_fw(struct drm_i915_private *i915, int dmc_id)
{
- return i915->dmc.dmc_info[dmc_id].payload;
+ return i915->display.dmc.dmc_info[dmc_id].payload;
}
bool intel_dmc_has_payload(struct drm_i915_private *i915)
@@ -393,7 +393,7 @@ static void disable_all_event_handlers(struct drm_i915_private *i915)
*/
void intel_dmc_load_program(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
u32 id, i;
if (!intel_dmc_has_payload(dev_priv))
@@ -422,7 +422,7 @@ void intel_dmc_load_program(struct drm_i915_private *dev_priv)
}
}
- dev_priv->dmc.dc_state = 0;
+ dev_priv->display.dmc.dc_state = 0;
gen9_set_dc_state_debugmask(dev_priv);
@@ -452,7 +452,7 @@ void intel_dmc_disable_program(struct drm_i915_private *i915)
void assert_dmc_loaded(struct drm_i915_private *i915)
{
drm_WARN_ONCE(&i915->drm,
- !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
"DMC program storage start is NULL\n");
drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE),
"DMC SSP Base Not fine\n");
@@ -489,7 +489,7 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc,
{
unsigned int i, id;
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
for (i = 0; i < num_entries; i++) {
id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id;
@@ -517,7 +517,7 @@ static bool dmc_mmio_addr_sanity_check(struct intel_dmc *dmc,
const u32 *mmioaddr, u32 mmio_count,
int header_ver, u8 dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
u32 start_range, end_range;
int i;
@@ -555,7 +555,7 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,
const struct intel_dmc_header_base *dmc_header,
size_t rem_size, u8 dmc_id)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id];
unsigned int header_len_bytes, dmc_header_size, payload_size, i;
const u32 *mmioaddr, *mmiodata;
@@ -666,7 +666,7 @@ parse_dmc_fw_package(struct intel_dmc *dmc,
const struct stepping_info *si,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
u32 package_size = sizeof(struct intel_package_header);
u32 num_entries, max_entries;
const struct intel_fw_info *fw_info;
@@ -720,7 +720,7 @@ static u32 parse_dmc_fw_css(struct intel_dmc *dmc,
struct intel_css_header *css_header,
size_t rem_size)
{
- struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc);
+ struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), display.dmc);
if (rem_size < sizeof(struct intel_css_header)) {
drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n");
@@ -757,7 +757,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
struct intel_css_header *css_header;
struct intel_package_header *package_header;
struct intel_dmc_header_base *dmc_header;
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
struct stepping_info display_info = { '*', '*'};
const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info);
u32 readcount = 0;
@@ -784,7 +784,7 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
readcount += r;
for (id = 0; id < DMC_FW_MAX; id++) {
- if (!dev_priv->dmc.dmc_info[id].present)
+ if (!dev_priv->display.dmc.dmc_info[id].present)
continue;
offset = readcount + dmc->dmc_info[id].dmc_offset * 4;
@@ -800,15 +800,15 @@ static void parse_dmc_fw(struct drm_i915_private *dev_priv,
static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv)
{
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
- dev_priv->dmc.wakeref =
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
+ dev_priv->display.dmc.wakeref =
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
}
static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&dev_priv->dmc.wakeref);
+ fetch_and_zero(&dev_priv->display.dmc.wakeref);
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
}
@@ -819,10 +819,10 @@ static void dmc_load_work_fn(struct work_struct *work)
struct intel_dmc *dmc;
const struct firmware *fw = NULL;
- dev_priv = container_of(work, typeof(*dev_priv), dmc.work);
- dmc = &dev_priv->dmc;
+ dev_priv = container_of(work, typeof(*dev_priv), display.dmc.work);
+ dmc = &dev_priv->display.dmc;
- request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev);
+ request_firmware(&fw, dev_priv->display.dmc.fw_path, dev_priv->drm.dev);
parse_dmc_fw(dev_priv, fw);
if (intel_dmc_has_payload(dev_priv)) {
@@ -831,7 +831,7 @@ static void dmc_load_work_fn(struct work_struct *work)
drm_info(&dev_priv->drm,
"Finished loading DMC firmware %s (v%u.%u)\n",
- dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
+ dev_priv->display.dmc.fw_path, DMC_VERSION_MAJOR(dmc->version),
DMC_VERSION_MINOR(dmc->version));
} else {
drm_notice(&dev_priv->drm,
@@ -854,9 +854,9 @@ static void dmc_load_work_fn(struct work_struct *work)
*/
void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
{
- struct intel_dmc *dmc = &dev_priv->dmc;
+ struct intel_dmc *dmc = &dev_priv->display.dmc;
- INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn);
+ INIT_WORK(&dev_priv->display.dmc.work, dmc_load_work_fn);
if (!HAS_DMC(dev_priv))
return;
@@ -939,7 +939,7 @@ void intel_dmc_ucode_init(struct drm_i915_private *dev_priv)
}
drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path);
- schedule_work(&dev_priv->dmc.work);
+ schedule_work(&dev_priv->display.dmc.work);
}
/**
@@ -955,7 +955,7 @@ void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv)
if (!HAS_DMC(dev_priv))
return;
- flush_work(&dev_priv->dmc.work);
+ flush_work(&dev_priv->display.dmc.work);
/* Drop the reference held in case DMC isn't loaded. */
if (!intel_dmc_has_payload(dev_priv))
@@ -997,16 +997,16 @@ void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv)
return;
intel_dmc_ucode_suspend(dev_priv);
- drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.dmc.wakeref);
for (id = 0; id < DMC_FW_MAX; id++)
- kfree(dev_priv->dmc.dmc_info[id].payload);
+ kfree(dev_priv->display.dmc.dmc_info[id].payload);
}
void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m,
struct drm_i915_private *i915)
{
- struct intel_dmc *dmc = &i915->dmc;
+ struct intel_dmc *dmc = &i915->display.dmc;
if (!HAS_DMC(i915))
return;
@@ -1028,7 +1028,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
if (!HAS_DMC(i915))
return -ENODEV;
- dmc = &i915->dmc;
+ dmc = &i915->display.dmc;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 98c3c8015a5c..079b7d3d0c53 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -706,7 +706,7 @@ tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
if (crtc_state->enable_psr2_sel_fetch)
return;
- if (!(dev_priv->dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ if (!(dev_priv->display.dmc.allowed_dc_mask & DC_STATE_EN_DC3CO))
return;
if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8ba133f37fb5..d1b51e2460e0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -41,7 +41,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
-#include "display/intel_dmc.h"
#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
@@ -378,8 +377,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- struct intel_dmc dmc;
-
/* MMIO base address for MIPI regs */
u32 mipi_mmio_base;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
2022-08-11 15:07 ` [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc Jani Nikula
@ 2022-08-12 4:58 ` Murthy, Arun R
2022-08-12 7:00 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 4:58 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
>
> Move display related members under drm_i915_private display sub-struct.
>
> FIXME: dmc really needs to be abstracted and hidden inside intel_dmc.c with
> display.dmc turned into a pointer
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> .../drm/i915/display/intel_display_power.c | 18 +++----
> .../i915/display/intel_display_power_well.c | 18 +++----
> drivers/gpu/drm/i915/display/intel_dmc.c | 52 +++++++++----------
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 --
> 6 files changed, 49 insertions(+), 48 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 030ced4068bb..ca22706e11e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -10,6 +10,7 @@
> #include <linux/types.h>
> #include <linux/wait.h>
>
> +#include "intel_dmc.h"
> #include "intel_gmbus.h"
>
> struct drm_i915_private;
> @@ -108,6 +109,9 @@ struct intel_display {
> /* protects panel power sequencer state */
> struct mutex mutex;
> } pps;
> +
> + /* Grouping using named structs. Keep sorted. */
> + struct intel_dmc dmc;
Wouldn't it be better to skip this patch for now?
Anyway the patch has a FIXME so can up with a proper patch later and avoid double work.
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
2022-08-12 4:58 ` Murthy, Arun R
@ 2022-08-12 7:00 ` Jani Nikula
2022-08-16 4:07 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 7:00 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> FIXME: dmc really needs to be abstracted and hidden inside intel_dmc.c with
>> display.dmc turned into a pointer
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
>> .../drm/i915/display/intel_display_power.c | 18 +++----
>> .../i915/display/intel_display_power_well.c | 18 +++----
>> drivers/gpu/drm/i915/display/intel_dmc.c | 52 +++++++++----------
>> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 3 --
>> 6 files changed, 49 insertions(+), 48 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 030ced4068bb..ca22706e11e6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -10,6 +10,7 @@
>> #include <linux/types.h>
>> #include <linux/wait.h>
>>
>> +#include "intel_dmc.h"
>> #include "intel_gmbus.h"
>>
>> struct drm_i915_private;
>> @@ -108,6 +109,9 @@ struct intel_display {
>> /* protects panel power sequencer state */
>> struct mutex mutex;
>> } pps;
>> +
>> + /* Grouping using named structs. Keep sorted. */
>> + struct intel_dmc dmc;
> Wouldn't it be better to skip this patch for now?
Why?
> Anyway the patch has a FIXME so can up with a proper patch later and avoid double work.
The FIXME is a long-term todo item, really, just logged it somewhere.
Basically this should be struct intel_dmc *dmc, struct intel_dmc should
be opaque and defined in intel_dmc.c. The patch at hand is really
trivial compared to that, and moves forward with the shorter term goal
of putting all the display stuff under i915->display.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
2022-08-12 7:00 ` Jani Nikula
@ 2022-08-16 4:07 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 4:07 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:31 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> <lucas.demarchi@intel.com>
> >> Subject: [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc
> >>
> >> Move display related members under drm_i915_private display sub-
> struct.
> >>
> >> FIXME: dmc really needs to be abstracted and hidden inside
> >> intel_dmc.c with display.dmc turned into a pointer
> >>
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >> .../gpu/drm/i915/display/intel_display_core.h | 4 ++
> >> .../drm/i915/display/intel_display_power.c | 18 +++----
> >> .../i915/display/intel_display_power_well.c | 18 +++----
> >> drivers/gpu/drm/i915/display/intel_dmc.c | 52 +++++++++----------
> >> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> >> drivers/gpu/drm/i915/i915_drv.h | 3 --
> >> 6 files changed, 49 insertions(+), 48 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index 030ced4068bb..ca22706e11e6 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -10,6 +10,7 @@
> >> #include <linux/types.h>
> >> #include <linux/wait.h>
> >>
> >> +#include "intel_dmc.h"
> >> #include "intel_gmbus.h"
> >>
> >> struct drm_i915_private;
> >> @@ -108,6 +109,9 @@ struct intel_display {
> >> /* protects panel power sequencer state */
> >> struct mutex mutex;
> >> } pps;
> >> +
> >> + /* Grouping using named structs. Keep sorted. */
> >> + struct intel_dmc dmc;
> > Wouldn't it be better to skip this patch for now?
>
> Why?
>
Since this struct wouldn't stay over here under display but eventually land up in intel_dmc.c, so was thinking why un-necessary intermediate step, let it be where is resides as is and once for all can be moved to its final destiny.
> > Anyway the patch has a FIXME so can up with a proper patch later and
> avoid double work.
>
> The FIXME is a long-term todo item, really, just logged it somewhere.
>
> Basically this should be struct intel_dmc *dmc, struct intel_dmc should be
> opaque and defined in intel_dmc.c. The patch at hand is really trivial
> compared to that, and moves forward with the shorter term goal of putting
> all the display stuff under i915->display.
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (10 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 11/39] drm/i915: move dmc to display.dmc Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-12 5:02 ` Murthy, Arun R
2022-08-17 4:14 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll Jani Nikula
` (32 subsequent siblings)
44 siblings, 2 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Split audio funcs to display.funcs to follow the same pattern as all the
other display functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 96 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 26 +++++
.../gpu/drm/i915/display/intel_lpe_audio.c | 42 ++++----
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 26 -----
5 files changed, 96 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 6c9ee905f132..a74fc79b7910 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
const struct dp_aud_n_m *nm;
@@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
enum port port = encoder->port;
int n, rate;
@@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
u32 tmp;
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
/* Disable timestamps */
tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
@@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder,
tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
}
static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
@@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
u32 tmp;
int len, i;
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
/* Enable Audio WA for 4k DSC usecases */
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP))
@@ -677,7 +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
/* Enable timestamps */
hsw_audio_config_update(encoder, crtc_state);
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
}
static void ilk_audio_codec_disable(struct intel_encoder *encoder,
@@ -814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
const struct drm_connector_state *conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_connector *connector = conn_state->connector;
const struct drm_display_mode *adjusted_mode =
@@ -838,17 +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio.funcs)
- dev_priv->audio.funcs->audio_codec_enable(encoder,
- crtc_state,
- conn_state);
+ if (dev_priv->display.funcs.audio)
+ dev_priv->display.funcs.audio->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
encoder->audio_connector = connector;
/* referred in audio callbacks */
- dev_priv->audio.encoder_map[pipe] = encoder;
- mutex_unlock(&dev_priv->audio.mutex);
+ dev_priv->display.audio.encoder_map[pipe] = encoder;
+ mutex_unlock(&dev_priv->display.audio.mutex);
if (acomp && acomp->base.audio_ops &&
acomp->base.audio_ops->pin_eld_notify) {
@@ -878,7 +878,7 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
const struct drm_connector_state *old_conn_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_connector *connector = old_conn_state->connector;
enum port port = encoder->port;
@@ -891,15 +891,15 @@ void intel_audio_codec_disable(struct intel_encoder *encoder,
connector->base.id, connector->name,
encoder->base.base.id, encoder->base.name, pipe_name(pipe));
- if (dev_priv->audio.funcs)
- dev_priv->audio.funcs->audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->display.funcs.audio)
+ dev_priv->display.funcs.audio->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
encoder->audio_connector = NULL;
- dev_priv->audio.encoder_map[pipe] = NULL;
- mutex_unlock(&dev_priv->audio.mutex);
+ dev_priv->display.audio.encoder_map[pipe] = NULL;
+ mutex_unlock(&dev_priv->display.audio.mutex);
if (acomp && acomp->base.audio_ops &&
acomp->base.audio_ops->pin_eld_notify) {
@@ -935,13 +935,13 @@ static const struct intel_audio_funcs hsw_audio_funcs = {
void intel_audio_hooks_init(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio.funcs = &g4x_audio_funcs;
+ dev_priv->display.funcs.audio = &g4x_audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio.funcs = &ilk_audio_funcs;
+ dev_priv->display.funcs.audio = &ilk_audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio.funcs = &hsw_audio_funcs;
+ dev_priv->display.funcs.audio = &hsw_audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio.funcs = &ilk_audio_funcs;
+ dev_priv->display.funcs.audio = &ilk_audio_funcs;
}
}
@@ -1046,13 +1046,13 @@ static unsigned long i915_audio_component_get_power(struct device *kdev)
ret = intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO_PLAYBACK);
- if (dev_priv->audio.power_refcount++ == 0) {
+ if (dev_priv->display.audio.power_refcount++ == 0) {
if (DISPLAY_VER(dev_priv) >= 9) {
intel_de_write(dev_priv, AUD_FREQ_CNTRL,
- dev_priv->audio.freq_cntrl);
+ dev_priv->display.audio.freq_cntrl);
drm_dbg_kms(&dev_priv->drm,
"restored AUD_FREQ_CNTRL to 0x%x\n",
- dev_priv->audio.freq_cntrl);
+ dev_priv->display.audio.freq_cntrl);
}
/* Force CDCLK to 2*BCLK as long as we need audio powered. */
@@ -1073,7 +1073,7 @@ static void i915_audio_component_put_power(struct device *kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
/* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */
- if (--dev_priv->audio.power_refcount == 0)
+ if (--dev_priv->display.audio.power_refcount == 0)
if (IS_GEMINILAKE(dev_priv))
glk_force_audio_cdclk(dev_priv, false);
@@ -1140,10 +1140,10 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
/* MST */
if (pipe >= 0) {
if (drm_WARN_ON(&dev_priv->drm,
- pipe >= ARRAY_SIZE(dev_priv->audio.encoder_map)))
+ pipe >= ARRAY_SIZE(dev_priv->display.audio.encoder_map)))
return NULL;
- encoder = dev_priv->audio.encoder_map[pipe];
+ encoder = dev_priv->display.audio.encoder_map[pipe];
/*
* when bootup, audio driver may not know it is
* MST or not. So it will poll all the port & pipe
@@ -1159,7 +1159,7 @@ static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
return NULL;
for_each_pipe(dev_priv, pipe) {
- encoder = dev_priv->audio.encoder_map[pipe];
+ encoder = dev_priv->display.audio.encoder_map[pipe];
if (encoder == NULL)
continue;
@@ -1177,7 +1177,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
int pipe, int rate)
{
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
- struct i915_audio_component *acomp = dev_priv->audio.component;
+ struct i915_audio_component *acomp = dev_priv->display.audio.component;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
unsigned long cookie;
@@ -1187,7 +1187,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
return 0;
cookie = i915_audio_component_get_power(kdev);
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
/* 1. get the pipe */
encoder = get_saved_enc(dev_priv, port, pipe);
@@ -1206,7 +1206,7 @@ static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
hsw_audio_config_update(encoder, crtc->config);
unlock:
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
i915_audio_component_put_power(kdev, cookie);
return err;
}
@@ -1220,13 +1220,13 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
const u8 *eld;
int ret = -EINVAL;
- mutex_lock(&dev_priv->audio.mutex);
+ mutex_lock(&dev_priv->display.audio.mutex);
intel_encoder = get_saved_enc(dev_priv, port, pipe);
if (!intel_encoder) {
drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
port_name(port));
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
return ret;
}
@@ -1238,7 +1238,7 @@ static int i915_audio_component_get_eld(struct device *kdev, int port,
memcpy(buf, eld, min(max_bytes, ret));
}
- mutex_unlock(&dev_priv->audio.mutex);
+ mutex_unlock(&dev_priv->display.audio.mutex);
return ret;
}
@@ -1273,7 +1273,7 @@ static int i915_audio_component_bind(struct device *i915_kdev,
BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
acomp->aud_sample_rate[i] = 0;
- dev_priv->audio.component = acomp;
+ dev_priv->display.audio.component = acomp;
drm_modeset_unlock_all(&dev_priv->drm);
return 0;
@@ -1288,14 +1288,14 @@ static void i915_audio_component_unbind(struct device *i915_kdev,
drm_modeset_lock_all(&dev_priv->drm);
acomp->base.ops = NULL;
acomp->base.dev = NULL;
- dev_priv->audio.component = NULL;
+ dev_priv->display.audio.component = NULL;
drm_modeset_unlock_all(&dev_priv->drm);
device_link_remove(hda_kdev, i915_kdev);
- if (dev_priv->audio.power_refcount)
+ if (dev_priv->display.audio.power_refcount)
drm_err(&dev_priv->drm, "audio power refcount %d after unbind\n",
- dev_priv->audio.power_refcount);
+ dev_priv->display.audio.power_refcount);
}
static const struct component_ops i915_audio_component_bind_ops = {
@@ -1359,13 +1359,13 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of 0x%x (init value 0x%x)\n",
aud_freq, aud_freq_init);
- dev_priv->audio.freq_cntrl = aud_freq;
+ dev_priv->display.audio.freq_cntrl = aud_freq;
}
/* init with current cdclk */
intel_audio_cdclk_change_post(dev_priv);
- dev_priv->audio.component_registered = true;
+ dev_priv->display.audio.component_registered = true;
}
/**
@@ -1377,11 +1377,11 @@ static void i915_audio_component_init(struct drm_i915_private *dev_priv)
*/
static void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
{
- if (!dev_priv->audio.component_registered)
+ if (!dev_priv->display.audio.component_registered)
return;
component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
- dev_priv->audio.component_registered = false;
+ dev_priv->display.audio.component_registered = false;
}
/**
@@ -1403,7 +1403,7 @@ void intel_audio_init(struct drm_i915_private *dev_priv)
*/
void intel_audio_deinit(struct drm_i915_private *dev_priv)
{
- if ((dev_priv)->audio.lpe.platdev != NULL)
+ if (dev_priv->display.audio.lpe.platdev != NULL)
intel_lpe_audio_teardown(dev_priv);
else
i915_audio_component_cleanup(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index ca22706e11e6..748d2a84e20e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -10,11 +10,14 @@
#include <linux/types.h>
#include <linux/wait.h>
+#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_gmbus.h"
struct drm_i915_private;
+struct i915_audio_component;
struct intel_atomic_state;
+struct intel_audio_funcs;
struct intel_cdclk_funcs;
struct intel_clock_gating_funcs;
struct intel_color_funcs;
@@ -56,6 +59,25 @@ struct intel_wm_funcs {
int (*compute_global_watermarks)(struct intel_atomic_state *state);
};
+struct intel_audio {
+ /* hda/i915 audio component */
+ struct i915_audio_component *component;
+ bool component_registered;
+ /* mutex for audio/video sync */
+ struct mutex mutex;
+ int power_refcount;
+ u32 freq_cntrl;
+
+ /* Used to save the pipe-to-encoder mapping for audio */
+ struct intel_encoder *encoder_map[I915_MAX_PIPES];
+
+ /* necessary resource sharing with HDMI LPE audio driver. */
+ struct {
+ struct platform_device *platdev;
+ int irq;
+ } lpe;
+};
+
struct intel_display {
/* Display functions */
struct {
@@ -82,6 +104,9 @@ struct intel_display {
/* Display internal color functions */
const struct intel_color_funcs *color;
+
+ /* Display internal audio functions */
+ const struct intel_audio_funcs *audio;
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
@@ -111,6 +136,7 @@ struct intel_display {
} pps;
/* Grouping using named structs. Keep sorted. */
+ struct intel_audio audio;
struct intel_dmc dmc;
};
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 1e18696aaecf..dca6003ccac8 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -75,7 +75,7 @@
#include "intel_lpe_audio.h"
#include "intel_pci_config.h"
-#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->audio.lpe.platdev != NULL)
+#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL)
static struct platform_device *
lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
@@ -97,7 +97,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
return ERR_PTR(-ENOMEM);
}
- rsc[0].start = rsc[0].end = dev_priv->audio.lpe.irq;
+ rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
rsc[0].flags = IORESOURCE_IRQ;
rsc[0].name = "hdmi-lpe-audio-irq";
@@ -149,7 +149,7 @@ static void lpe_audio_platdev_destroy(struct drm_i915_private *dev_priv)
* than us fiddle with its internals.
*/
- platform_device_unregister(dev_priv->audio.lpe.platdev);
+ platform_device_unregister(dev_priv->display.audio.lpe.platdev);
}
static void lpe_audio_irq_unmask(struct irq_data *d)
@@ -168,7 +168,7 @@ static struct irq_chip lpe_audio_irqchip = {
static int lpe_audio_irq_init(struct drm_i915_private *dev_priv)
{
- int irq = dev_priv->audio.lpe.irq;
+ int irq = dev_priv->display.audio.lpe.irq;
drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
irq_set_chip_and_handler_name(irq,
@@ -205,15 +205,15 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
{
int ret;
- dev_priv->audio.lpe.irq = irq_alloc_desc(0);
- if (dev_priv->audio.lpe.irq < 0) {
+ dev_priv->display.audio.lpe.irq = irq_alloc_desc(0);
+ if (dev_priv->display.audio.lpe.irq < 0) {
drm_err(&dev_priv->drm, "Failed to allocate IRQ desc: %d\n",
- dev_priv->audio.lpe.irq);
- ret = dev_priv->audio.lpe.irq;
+ dev_priv->display.audio.lpe.irq);
+ ret = dev_priv->display.audio.lpe.irq;
goto err;
}
- drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->audio.lpe.irq);
+ drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->display.audio.lpe.irq);
ret = lpe_audio_irq_init(dev_priv);
@@ -224,10 +224,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
goto err_free_irq;
}
- dev_priv->audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
+ dev_priv->display.audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
- if (IS_ERR(dev_priv->audio.lpe.platdev)) {
- ret = PTR_ERR(dev_priv->audio.lpe.platdev);
+ if (IS_ERR(dev_priv->display.audio.lpe.platdev)) {
+ ret = PTR_ERR(dev_priv->display.audio.lpe.platdev);
drm_err(&dev_priv->drm,
"Failed to create lpe audio platform device: %d\n",
ret);
@@ -242,10 +242,10 @@ static int lpe_audio_setup(struct drm_i915_private *dev_priv)
return 0;
err_free_irq:
- irq_free_desc(dev_priv->audio.lpe.irq);
+ irq_free_desc(dev_priv->display.audio.lpe.irq);
err:
- dev_priv->audio.lpe.irq = -1;
- dev_priv->audio.lpe.platdev = NULL;
+ dev_priv->display.audio.lpe.irq = -1;
+ dev_priv->display.audio.lpe.platdev = NULL;
return ret;
}
@@ -263,7 +263,7 @@ void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv)
if (!HAS_LPE_AUDIO(dev_priv))
return;
- ret = generic_handle_irq(dev_priv->audio.lpe.irq);
+ ret = generic_handle_irq(dev_priv->display.audio.lpe.irq);
if (ret)
drm_err_ratelimited(&dev_priv->drm,
"error handling LPE audio irq: %d\n", ret);
@@ -304,10 +304,10 @@ void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv)
lpe_audio_platdev_destroy(dev_priv);
- irq_free_desc(dev_priv->audio.lpe.irq);
+ irq_free_desc(dev_priv->display.audio.lpe.irq);
- dev_priv->audio.lpe.irq = -1;
- dev_priv->audio.lpe.platdev = NULL;
+ dev_priv->display.audio.lpe.irq = -1;
+ dev_priv->display.audio.lpe.platdev = NULL;
}
/**
@@ -334,7 +334,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
if (!HAS_LPE_AUDIO(dev_priv))
return;
- pdata = dev_get_platdata(&dev_priv->audio.lpe.platdev->dev);
+ pdata = dev_get_platdata(&dev_priv->display.audio.lpe.platdev->dev);
ppdata = &pdata->port[port - PORT_B];
spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags);
@@ -362,7 +362,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
}
if (pdata->notify_audio_lpe)
- pdata->notify_audio_lpe(dev_priv->audio.lpe.platdev, port - PORT_B);
+ pdata->notify_audio_lpe(dev_priv->display.audio.lpe.platdev, port - PORT_B);
spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 694384e54fd7..0d3993e51138 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -335,7 +335,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->sb_lock);
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
- mutex_init(&dev_priv->audio.mutex);
+ mutex_init(&dev_priv->display.audio.mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->display.pps.mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d1b51e2460e0..ebd96555ada0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -78,7 +78,6 @@
struct dpll;
struct drm_i915_gem_object;
struct drm_i915_private;
-struct intel_audio_funcs;
struct intel_cdclk_config;
struct intel_cdclk_state;
struct intel_cdclk_vals;
@@ -306,29 +305,6 @@ struct i915_selftest_stash {
struct ida mock_region_instances;
};
-/* intel_audio.c private */
-struct intel_audio_private {
- /* Display internal audio functions */
- const struct intel_audio_funcs *funcs;
-
- /* hda/i915 audio component */
- struct i915_audio_component *component;
- bool component_registered;
- /* mutex for audio/video sync */
- struct mutex mutex;
- int power_refcount;
- u32 freq_cntrl;
-
- /* Used to save the pipe-to-encoder mapping for audio */
- struct intel_encoder *encoder_map[I915_MAX_PIPES];
-
- /* necessary resource sharing with HDMI LPE audio driver. */
- struct {
- struct platform_device *platdev;
- int irq;
- } lpe;
-};
-
struct drm_i915_private {
struct drm_device drm;
@@ -671,8 +647,6 @@ struct drm_i915_private {
bool ipc_enabled;
- struct intel_audio_private audio;
-
struct i915_pmu pmu;
struct i915_drm_clients clients;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs Jani Nikula
@ 2022-08-12 5:02 ` Murthy, Arun R
2022-08-12 7:03 ` Jani Nikula
2022-08-17 4:14 ` Lucas De Marchi
1 sibling, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-12 5:02 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
> display.audio and display.funcs
>
> Move display related members under drm_i915_private display sub-struct.
>
> Split audio funcs to display.funcs to follow the same pattern as all the other
> display functions.
>
Audio is a feature as such so wouldn't intel_audio struct stand parallel to intel_display?
Thanks and Regards,
Arun R Murthy
--------------------
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_audio.c | 96 +++++++++----------
> .../gpu/drm/i915/display/intel_display_core.h | 26 +++++
> .../gpu/drm/i915/display/intel_lpe_audio.c | 42 ++++----
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 26 -----
> 5 files changed, 96 insertions(+), 96 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
> b/drivers/gpu/drm/i915/display/intel_audio.c
> index 6c9ee905f132..a74fc79b7910 100644
> --- a/drivers/gpu/drm/i915/display/intel_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
> @@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder
> *encoder,
> const struct intel_crtc_state *crtc_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum port port = encoder->port;
> const struct dp_aud_n_m *nm;
> @@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct
> intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> enum port port = encoder->port;
> int n, rate;
> @@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> u32 tmp;
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> /* Disable timestamps */
> tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
> @@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct
> intel_encoder *encoder,
> tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
> intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
>
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> }
>
> static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
> @@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct
> intel_encoder *encoder,
> u32 tmp;
> int len, i;
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> /* Enable Audio WA for 4k DSC usecases */
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) @@ -677,7
> +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
> *encoder,
> /* Enable timestamps */
> hsw_audio_config_update(encoder, crtc_state);
>
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> }
>
> static void ilk_audio_codec_disable(struct intel_encoder *encoder, @@ -
> 814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder
> *encoder,
> const struct drm_connector_state *conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_connector *connector = conn_state->connector;
> const struct drm_display_mode *adjusted_mode = @@ -838,17
> +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>
> connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode)
> / 2;
>
> - if (dev_priv->audio.funcs)
> - dev_priv->audio.funcs->audio_codec_enable(encoder,
> - crtc_state,
> - conn_state);
> + if (dev_priv->display.funcs.audio)
> + dev_priv->display.funcs.audio-
> >audio_codec_enable(encoder,
> + crtc_state,
> + conn_state);
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
> encoder->audio_connector = connector;
>
> /* referred in audio callbacks */
> - dev_priv->audio.encoder_map[pipe] = encoder;
> - mutex_unlock(&dev_priv->audio.mutex);
> + dev_priv->display.audio.encoder_map[pipe] = encoder;
> + mutex_unlock(&dev_priv->display.audio.mutex);
>
> if (acomp && acomp->base.audio_ops &&
> acomp->base.audio_ops->pin_eld_notify) { @@ -878,7 +878,7 @@
> void intel_audio_codec_disable(struct intel_encoder *encoder,
> const struct drm_connector_state
> *old_conn_state) {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_connector *connector = old_conn_state->connector;
> enum port port = encoder->port;
> @@ -891,15 +891,15 @@ void intel_audio_codec_disable(struct
> intel_encoder *encoder,
> connector->base.id, connector->name,
> encoder->base.base.id, encoder->base.name,
> pipe_name(pipe));
>
> - if (dev_priv->audio.funcs)
> - dev_priv->audio.funcs->audio_codec_disable(encoder,
> - old_crtc_state,
> - old_conn_state);
> + if (dev_priv->display.funcs.audio)
> + dev_priv->display.funcs.audio-
> >audio_codec_disable(encoder,
> +
> old_crtc_state,
> +
> old_conn_state);
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
> encoder->audio_connector = NULL;
> - dev_priv->audio.encoder_map[pipe] = NULL;
> - mutex_unlock(&dev_priv->audio.mutex);
> + dev_priv->display.audio.encoder_map[pipe] = NULL;
> + mutex_unlock(&dev_priv->display.audio.mutex);
>
> if (acomp && acomp->base.audio_ops &&
> acomp->base.audio_ops->pin_eld_notify) { @@ -935,13 +935,13
> @@ static const struct intel_audio_funcs hsw_audio_funcs = { void
> intel_audio_hooks_init(struct drm_i915_private *dev_priv) {
> if (IS_G4X(dev_priv)) {
> - dev_priv->audio.funcs = &g4x_audio_funcs;
> + dev_priv->display.funcs.audio = &g4x_audio_funcs;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->audio.funcs = &ilk_audio_funcs;
> + dev_priv->display.funcs.audio = &ilk_audio_funcs;
> } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
> - dev_priv->audio.funcs = &hsw_audio_funcs;
> + dev_priv->display.funcs.audio = &hsw_audio_funcs;
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> - dev_priv->audio.funcs = &ilk_audio_funcs;
> + dev_priv->display.funcs.audio = &ilk_audio_funcs;
> }
> }
>
> @@ -1046,13 +1046,13 @@ static unsigned long
> i915_audio_component_get_power(struct device *kdev)
>
> ret = intel_display_power_get(dev_priv,
> POWER_DOMAIN_AUDIO_PLAYBACK);
>
> - if (dev_priv->audio.power_refcount++ == 0) {
> + if (dev_priv->display.audio.power_refcount++ == 0) {
> if (DISPLAY_VER(dev_priv) >= 9) {
> intel_de_write(dev_priv, AUD_FREQ_CNTRL,
> - dev_priv->audio.freq_cntrl);
> + dev_priv->display.audio.freq_cntrl);
> drm_dbg_kms(&dev_priv->drm,
> "restored AUD_FREQ_CNTRL to 0x%x\n",
> - dev_priv->audio.freq_cntrl);
> + dev_priv->display.audio.freq_cntrl);
> }
>
> /* Force CDCLK to 2*BCLK as long as we need audio powered.
> */ @@ -1073,7 +1073,7 @@ static void
> i915_audio_component_put_power(struct device *kdev,
> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>
> /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered.
> */
> - if (--dev_priv->audio.power_refcount == 0)
> + if (--dev_priv->display.audio.power_refcount == 0)
> if (IS_GEMINILAKE(dev_priv))
> glk_force_audio_cdclk(dev_priv, false);
>
> @@ -1140,10 +1140,10 @@ static struct intel_encoder
> *get_saved_enc(struct drm_i915_private *dev_priv,
> /* MST */
> if (pipe >= 0) {
> if (drm_WARN_ON(&dev_priv->drm,
> - pipe >= ARRAY_SIZE(dev_priv-
> >audio.encoder_map)))
> + pipe >= ARRAY_SIZE(dev_priv-
> >display.audio.encoder_map)))
> return NULL;
>
> - encoder = dev_priv->audio.encoder_map[pipe];
> + encoder = dev_priv->display.audio.encoder_map[pipe];
> /*
> * when bootup, audio driver may not know it is
> * MST or not. So it will poll all the port & pipe @@ -1159,7
> +1159,7 @@ static struct intel_encoder *get_saved_enc(struct
> drm_i915_private *dev_priv,
> return NULL;
>
> for_each_pipe(dev_priv, pipe) {
> - encoder = dev_priv->audio.encoder_map[pipe];
> + encoder = dev_priv->display.audio.encoder_map[pipe];
> if (encoder == NULL)
> continue;
>
> @@ -1177,7 +1177,7 @@ static int
> i915_audio_component_sync_audio_rate(struct device *kdev, int port,
> int pipe, int rate)
> {
> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
> - struct i915_audio_component *acomp = dev_priv-
> >audio.component;
> + struct i915_audio_component *acomp =
> +dev_priv->display.audio.component;
> struct intel_encoder *encoder;
> struct intel_crtc *crtc;
> unsigned long cookie;
> @@ -1187,7 +1187,7 @@ static int
> i915_audio_component_sync_audio_rate(struct device *kdev, int port,
> return 0;
>
> cookie = i915_audio_component_get_power(kdev);
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> /* 1. get the pipe */
> encoder = get_saved_enc(dev_priv, port, pipe); @@ -1206,7 +1206,7
> @@ static int i915_audio_component_sync_audio_rate(struct device *kdev,
> int port,
> hsw_audio_config_update(encoder, crtc->config);
>
> unlock:
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> i915_audio_component_put_power(kdev, cookie);
> return err;
> }
> @@ -1220,13 +1220,13 @@ static int i915_audio_component_get_eld(struct
> device *kdev, int port,
> const u8 *eld;
> int ret = -EINVAL;
>
> - mutex_lock(&dev_priv->audio.mutex);
> + mutex_lock(&dev_priv->display.audio.mutex);
>
> intel_encoder = get_saved_enc(dev_priv, port, pipe);
> if (!intel_encoder) {
> drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
> port_name(port));
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> return ret;
> }
>
> @@ -1238,7 +1238,7 @@ static int i915_audio_component_get_eld(struct
> device *kdev, int port,
> memcpy(buf, eld, min(max_bytes, ret));
> }
>
> - mutex_unlock(&dev_priv->audio.mutex);
> + mutex_unlock(&dev_priv->display.audio.mutex);
> return ret;
> }
>
> @@ -1273,7 +1273,7 @@ static int i915_audio_component_bind(struct
> device *i915_kdev,
> BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
> for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
> acomp->aud_sample_rate[i] = 0;
> - dev_priv->audio.component = acomp;
> + dev_priv->display.audio.component = acomp;
> drm_modeset_unlock_all(&dev_priv->drm);
>
> return 0;
> @@ -1288,14 +1288,14 @@ static void
> i915_audio_component_unbind(struct device *i915_kdev,
> drm_modeset_lock_all(&dev_priv->drm);
> acomp->base.ops = NULL;
> acomp->base.dev = NULL;
> - dev_priv->audio.component = NULL;
> + dev_priv->display.audio.component = NULL;
> drm_modeset_unlock_all(&dev_priv->drm);
>
> device_link_remove(hda_kdev, i915_kdev);
>
> - if (dev_priv->audio.power_refcount)
> + if (dev_priv->display.audio.power_refcount)
> drm_err(&dev_priv->drm, "audio power refcount %d after
> unbind\n",
> - dev_priv->audio.power_refcount);
> + dev_priv->display.audio.power_refcount);
> }
>
> static const struct component_ops i915_audio_component_bind_ops = {
> @@ -1359,13 +1359,13 @@ static void i915_audio_component_init(struct
> drm_i915_private *dev_priv)
> drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of
> 0x%x (init value 0x%x)\n",
> aud_freq, aud_freq_init);
>
> - dev_priv->audio.freq_cntrl = aud_freq;
> + dev_priv->display.audio.freq_cntrl = aud_freq;
> }
>
> /* init with current cdclk */
> intel_audio_cdclk_change_post(dev_priv);
>
> - dev_priv->audio.component_registered = true;
> + dev_priv->display.audio.component_registered = true;
> }
>
> /**
> @@ -1377,11 +1377,11 @@ static void i915_audio_component_init(struct
> drm_i915_private *dev_priv)
> */
> static void i915_audio_component_cleanup(struct drm_i915_private
> *dev_priv) {
> - if (!dev_priv->audio.component_registered)
> + if (!dev_priv->display.audio.component_registered)
> return;
>
> component_del(dev_priv->drm.dev,
> &i915_audio_component_bind_ops);
> - dev_priv->audio.component_registered = false;
> + dev_priv->display.audio.component_registered = false;
> }
>
> /**
> @@ -1403,7 +1403,7 @@ void intel_audio_init(struct drm_i915_private
> *dev_priv)
> */
> void intel_audio_deinit(struct drm_i915_private *dev_priv) {
> - if ((dev_priv)->audio.lpe.platdev != NULL)
> + if (dev_priv->display.audio.lpe.platdev != NULL)
> intel_lpe_audio_teardown(dev_priv);
> else
> i915_audio_component_cleanup(dev_priv);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index ca22706e11e6..748d2a84e20e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -10,11 +10,14 @@
> #include <linux/types.h>
> #include <linux/wait.h>
>
> +#include "intel_display.h"
> #include "intel_dmc.h"
> #include "intel_gmbus.h"
>
> struct drm_i915_private;
> +struct i915_audio_component;
> struct intel_atomic_state;
> +struct intel_audio_funcs;
> struct intel_cdclk_funcs;
> struct intel_clock_gating_funcs;
> struct intel_color_funcs;
> @@ -56,6 +59,25 @@ struct intel_wm_funcs {
> int (*compute_global_watermarks)(struct intel_atomic_state *state);
> };
>
> +struct intel_audio {
> + /* hda/i915 audio component */
> + struct i915_audio_component *component;
> + bool component_registered;
> + /* mutex for audio/video sync */
> + struct mutex mutex;
> + int power_refcount;
> + u32 freq_cntrl;
> +
> + /* Used to save the pipe-to-encoder mapping for audio */
> + struct intel_encoder *encoder_map[I915_MAX_PIPES];
> +
> + /* necessary resource sharing with HDMI LPE audio driver. */
> + struct {
> + struct platform_device *platdev;
> + int irq;
> + } lpe;
> +};
> +
> struct intel_display {
> /* Display functions */
> struct {
> @@ -82,6 +104,9 @@ struct intel_display {
>
> /* Display internal color functions */
> const struct intel_color_funcs *color;
> +
> + /* Display internal audio functions */
> + const struct intel_audio_funcs *audio;
> } funcs;
>
> /* Grouping using anonymous structs. Keep sorted. */ @@ -111,6
> +136,7 @@ struct intel_display {
> } pps;
>
> /* Grouping using named structs. Keep sorted. */
> + struct intel_audio audio;
> struct intel_dmc dmc;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> index 1e18696aaecf..dca6003ccac8 100644
> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> @@ -75,7 +75,7 @@
> #include "intel_lpe_audio.h"
> #include "intel_pci_config.h"
>
> -#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->audio.lpe.platdev != NULL)
> +#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev
> +!= NULL)
>
> static struct platform_device *
> lpe_audio_platdev_create(struct drm_i915_private *dev_priv) @@ -97,7
> +97,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
> return ERR_PTR(-ENOMEM);
> }
>
> - rsc[0].start = rsc[0].end = dev_priv->audio.lpe.irq;
> + rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
> rsc[0].flags = IORESOURCE_IRQ;
> rsc[0].name = "hdmi-lpe-audio-irq";
>
> @@ -149,7 +149,7 @@ static void lpe_audio_platdev_destroy(struct
> drm_i915_private *dev_priv)
> * than us fiddle with its internals.
> */
>
> - platform_device_unregister(dev_priv->audio.lpe.platdev);
> + platform_device_unregister(dev_priv->display.audio.lpe.platdev);
> }
>
> static void lpe_audio_irq_unmask(struct irq_data *d) @@ -168,7 +168,7
> @@ static struct irq_chip lpe_audio_irqchip = {
>
> static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) {
> - int irq = dev_priv->audio.lpe.irq;
> + int irq = dev_priv->display.audio.lpe.irq;
>
> drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
> irq_set_chip_and_handler_name(irq,
> @@ -205,15 +205,15 @@ static int lpe_audio_setup(struct drm_i915_private
> *dev_priv) {
> int ret;
>
> - dev_priv->audio.lpe.irq = irq_alloc_desc(0);
> - if (dev_priv->audio.lpe.irq < 0) {
> + dev_priv->display.audio.lpe.irq = irq_alloc_desc(0);
> + if (dev_priv->display.audio.lpe.irq < 0) {
> drm_err(&dev_priv->drm, "Failed to allocate IRQ desc:
> %d\n",
> - dev_priv->audio.lpe.irq);
> - ret = dev_priv->audio.lpe.irq;
> + dev_priv->display.audio.lpe.irq);
> + ret = dev_priv->display.audio.lpe.irq;
> goto err;
> }
>
> - drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->audio.lpe.irq);
> + drm_dbg(&dev_priv->drm, "irq = %d\n",
> +dev_priv->display.audio.lpe.irq);
>
> ret = lpe_audio_irq_init(dev_priv);
>
> @@ -224,10 +224,10 @@ static int lpe_audio_setup(struct drm_i915_private
> *dev_priv)
> goto err_free_irq;
> }
>
> - dev_priv->audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
> + dev_priv->display.audio.lpe.platdev =
> +lpe_audio_platdev_create(dev_priv);
>
> - if (IS_ERR(dev_priv->audio.lpe.platdev)) {
> - ret = PTR_ERR(dev_priv->audio.lpe.platdev);
> + if (IS_ERR(dev_priv->display.audio.lpe.platdev)) {
> + ret = PTR_ERR(dev_priv->display.audio.lpe.platdev);
> drm_err(&dev_priv->drm,
> "Failed to create lpe audio platform device: %d\n",
> ret);
> @@ -242,10 +242,10 @@ static int lpe_audio_setup(struct drm_i915_private
> *dev_priv)
>
> return 0;
> err_free_irq:
> - irq_free_desc(dev_priv->audio.lpe.irq);
> + irq_free_desc(dev_priv->display.audio.lpe.irq);
> err:
> - dev_priv->audio.lpe.irq = -1;
> - dev_priv->audio.lpe.platdev = NULL;
> + dev_priv->display.audio.lpe.irq = -1;
> + dev_priv->display.audio.lpe.platdev = NULL;
> return ret;
> }
>
> @@ -263,7 +263,7 @@ void intel_lpe_audio_irq_handler(struct
> drm_i915_private *dev_priv)
> if (!HAS_LPE_AUDIO(dev_priv))
> return;
>
> - ret = generic_handle_irq(dev_priv->audio.lpe.irq);
> + ret = generic_handle_irq(dev_priv->display.audio.lpe.irq);
> if (ret)
> drm_err_ratelimited(&dev_priv->drm,
> "error handling LPE audio irq: %d\n", ret);
> @@ -304,10 +304,10 @@ void intel_lpe_audio_teardown(struct
> drm_i915_private *dev_priv)
>
> lpe_audio_platdev_destroy(dev_priv);
>
> - irq_free_desc(dev_priv->audio.lpe.irq);
> + irq_free_desc(dev_priv->display.audio.lpe.irq);
>
> - dev_priv->audio.lpe.irq = -1;
> - dev_priv->audio.lpe.platdev = NULL;
> + dev_priv->display.audio.lpe.irq = -1;
> + dev_priv->display.audio.lpe.platdev = NULL;
> }
>
> /**
> @@ -334,7 +334,7 @@ void intel_lpe_audio_notify(struct drm_i915_private
> *dev_priv,
> if (!HAS_LPE_AUDIO(dev_priv))
> return;
>
> - pdata = dev_get_platdata(&dev_priv->audio.lpe.platdev->dev);
> + pdata = dev_get_platdata(&dev_priv->display.audio.lpe.platdev-
> >dev);
> ppdata = &pdata->port[port - PORT_B];
>
> spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags); @@ -362,7
> +362,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
> }
>
> if (pdata->notify_audio_lpe)
> - pdata->notify_audio_lpe(dev_priv->audio.lpe.platdev, port -
> PORT_B);
> + pdata->notify_audio_lpe(dev_priv-
> >display.audio.lpe.platdev, port -
> +PORT_B);
>
> spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags); } diff --
> git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index 694384e54fd7..0d3993e51138 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -335,7 +335,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> mutex_init(&dev_priv->sb_lock);
> cpu_latency_qos_add_request(&dev_priv->sb_qos,
> PM_QOS_DEFAULT_VALUE);
>
> - mutex_init(&dev_priv->audio.mutex);
> + mutex_init(&dev_priv->display.audio.mutex);
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->display.pps.mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index d1b51e2460e0..ebd96555ada0
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -78,7 +78,6 @@
> struct dpll;
> struct drm_i915_gem_object;
> struct drm_i915_private;
> -struct intel_audio_funcs;
> struct intel_cdclk_config;
> struct intel_cdclk_state;
> struct intel_cdclk_vals;
> @@ -306,29 +305,6 @@ struct i915_selftest_stash {
> struct ida mock_region_instances;
> };
>
> -/* intel_audio.c private */
> -struct intel_audio_private {
> - /* Display internal audio functions */
> - const struct intel_audio_funcs *funcs;
> -
> - /* hda/i915 audio component */
> - struct i915_audio_component *component;
> - bool component_registered;
> - /* mutex for audio/video sync */
> - struct mutex mutex;
> - int power_refcount;
> - u32 freq_cntrl;
> -
> - /* Used to save the pipe-to-encoder mapping for audio */
> - struct intel_encoder *encoder_map[I915_MAX_PIPES];
> -
> - /* necessary resource sharing with HDMI LPE audio driver. */
> - struct {
> - struct platform_device *platdev;
> - int irq;
> - } lpe;
> -};
> -
> struct drm_i915_private {
> struct drm_device drm;
>
> @@ -671,8 +647,6 @@ struct drm_i915_private {
>
> bool ipc_enabled;
>
> - struct intel_audio_private audio;
> -
> struct i915_pmu pmu;
>
> struct i915_drm_clients clients;
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-12 5:02 ` Murthy, Arun R
@ 2022-08-12 7:03 ` Jani Nikula
2022-08-16 4:13 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-12 7:03 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
>> Nikula
>> Sent: Thursday, August 11, 2022 8:37 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> <lucas.demarchi@intel.com>
>> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
>> display.audio and display.funcs
>>
>> Move display related members under drm_i915_private display sub-struct.
>>
>> Split audio funcs to display.funcs to follow the same pattern as all the other
>> display functions.
>>
> Audio is a feature as such so wouldn't intel_audio struct stand parallel to intel_display?
For i915, audio doesn't exist other than as a display feature. Display
is a higher level split here, parallel to gt/gem.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_audio.c | 96 +++++++++----------
>> .../gpu/drm/i915/display/intel_display_core.h | 26 +++++
>> .../gpu/drm/i915/display/intel_lpe_audio.c | 42 ++++----
>> drivers/gpu/drm/i915/i915_driver.c | 2 +-
>> drivers/gpu/drm/i915/i915_drv.h | 26 -----
>> 5 files changed, 96 insertions(+), 96 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
>> b/drivers/gpu/drm/i915/display/intel_audio.c
>> index 6c9ee905f132..a74fc79b7910 100644
>> --- a/drivers/gpu/drm/i915/display/intel_audio.c
>> +++ b/drivers/gpu/drm/i915/display/intel_audio.c
>> @@ -393,7 +393,7 @@ hsw_dp_audio_config_update(struct intel_encoder
>> *encoder,
>> const struct intel_crtc_state *crtc_state) {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - struct i915_audio_component *acomp = dev_priv-
>> >audio.component;
>> + struct i915_audio_component *acomp =
>> +dev_priv->display.audio.component;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> enum port port = encoder->port;
>> const struct dp_aud_n_m *nm;
>> @@ -441,7 +441,7 @@ hsw_hdmi_audio_config_update(struct
>> intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state) {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - struct i915_audio_component *acomp = dev_priv-
>> >audio.component;
>> + struct i915_audio_component *acomp =
>> +dev_priv->display.audio.component;
>> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>> enum port port = encoder->port;
>> int n, rate;
>> @@ -496,7 +496,7 @@ static void hsw_audio_codec_disable(struct
>> intel_encoder *encoder,
>> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>> u32 tmp;
>>
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>>
>> /* Disable timestamps */
>> tmp = intel_de_read(dev_priv, HSW_AUD_CFG(cpu_transcoder));
>> @@ -514,7 +514,7 @@ static void hsw_audio_codec_disable(struct
>> intel_encoder *encoder,
>> tmp &= ~AUDIO_OUTPUT_ENABLE(cpu_transcoder);
>> intel_de_write(dev_priv, HSW_AUD_PIN_ELD_CP_VLD, tmp);
>>
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>> }
>>
>> static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
>> @@ -639,7 +639,7 @@ static void hsw_audio_codec_enable(struct
>> intel_encoder *encoder,
>> u32 tmp;
>> int len, i;
>>
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>>
>> /* Enable Audio WA for 4k DSC usecases */
>> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) @@ -677,7
>> +677,7 @@ static void hsw_audio_codec_enable(struct intel_encoder
>> *encoder,
>> /* Enable timestamps */
>> hsw_audio_config_update(encoder, crtc_state);
>>
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>> }
>>
>> static void ilk_audio_codec_disable(struct intel_encoder *encoder, @@ -
>> 814,7 +814,7 @@ void intel_audio_codec_enable(struct intel_encoder
>> *encoder,
>> const struct drm_connector_state *conn_state) {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - struct i915_audio_component *acomp = dev_priv-
>> >audio.component;
>> + struct i915_audio_component *acomp =
>> +dev_priv->display.audio.component;
>> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>> struct drm_connector *connector = conn_state->connector;
>> const struct drm_display_mode *adjusted_mode = @@ -838,17
>> +838,17 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
>>
>> connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode)
>> / 2;
>>
>> - if (dev_priv->audio.funcs)
>> - dev_priv->audio.funcs->audio_codec_enable(encoder,
>> - crtc_state,
>> - conn_state);
>> + if (dev_priv->display.funcs.audio)
>> + dev_priv->display.funcs.audio-
>> >audio_codec_enable(encoder,
>> + crtc_state,
>> + conn_state);
>>
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>> encoder->audio_connector = connector;
>>
>> /* referred in audio callbacks */
>> - dev_priv->audio.encoder_map[pipe] = encoder;
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + dev_priv->display.audio.encoder_map[pipe] = encoder;
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>>
>> if (acomp && acomp->base.audio_ops &&
>> acomp->base.audio_ops->pin_eld_notify) { @@ -878,7 +878,7 @@
>> void intel_audio_codec_disable(struct intel_encoder *encoder,
>> const struct drm_connector_state
>> *old_conn_state) {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - struct i915_audio_component *acomp = dev_priv-
>> >audio.component;
>> + struct i915_audio_component *acomp =
>> +dev_priv->display.audio.component;
>> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
>> struct drm_connector *connector = old_conn_state->connector;
>> enum port port = encoder->port;
>> @@ -891,15 +891,15 @@ void intel_audio_codec_disable(struct
>> intel_encoder *encoder,
>> connector->base.id, connector->name,
>> encoder->base.base.id, encoder->base.name,
>> pipe_name(pipe));
>>
>> - if (dev_priv->audio.funcs)
>> - dev_priv->audio.funcs->audio_codec_disable(encoder,
>> - old_crtc_state,
>> - old_conn_state);
>> + if (dev_priv->display.funcs.audio)
>> + dev_priv->display.funcs.audio-
>> >audio_codec_disable(encoder,
>> +
>> old_crtc_state,
>> +
>> old_conn_state);
>>
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>> encoder->audio_connector = NULL;
>> - dev_priv->audio.encoder_map[pipe] = NULL;
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + dev_priv->display.audio.encoder_map[pipe] = NULL;
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>>
>> if (acomp && acomp->base.audio_ops &&
>> acomp->base.audio_ops->pin_eld_notify) { @@ -935,13 +935,13
>> @@ static const struct intel_audio_funcs hsw_audio_funcs = { void
>> intel_audio_hooks_init(struct drm_i915_private *dev_priv) {
>> if (IS_G4X(dev_priv)) {
>> - dev_priv->audio.funcs = &g4x_audio_funcs;
>> + dev_priv->display.funcs.audio = &g4x_audio_funcs;
>> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>> - dev_priv->audio.funcs = &ilk_audio_funcs;
>> + dev_priv->display.funcs.audio = &ilk_audio_funcs;
>> } else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
>> - dev_priv->audio.funcs = &hsw_audio_funcs;
>> + dev_priv->display.funcs.audio = &hsw_audio_funcs;
>> } else if (HAS_PCH_SPLIT(dev_priv)) {
>> - dev_priv->audio.funcs = &ilk_audio_funcs;
>> + dev_priv->display.funcs.audio = &ilk_audio_funcs;
>> }
>> }
>>
>> @@ -1046,13 +1046,13 @@ static unsigned long
>> i915_audio_component_get_power(struct device *kdev)
>>
>> ret = intel_display_power_get(dev_priv,
>> POWER_DOMAIN_AUDIO_PLAYBACK);
>>
>> - if (dev_priv->audio.power_refcount++ == 0) {
>> + if (dev_priv->display.audio.power_refcount++ == 0) {
>> if (DISPLAY_VER(dev_priv) >= 9) {
>> intel_de_write(dev_priv, AUD_FREQ_CNTRL,
>> - dev_priv->audio.freq_cntrl);
>> + dev_priv->display.audio.freq_cntrl);
>> drm_dbg_kms(&dev_priv->drm,
>> "restored AUD_FREQ_CNTRL to 0x%x\n",
>> - dev_priv->audio.freq_cntrl);
>> + dev_priv->display.audio.freq_cntrl);
>> }
>>
>> /* Force CDCLK to 2*BCLK as long as we need audio powered.
>> */ @@ -1073,7 +1073,7 @@ static void
>> i915_audio_component_put_power(struct device *kdev,
>> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>>
>> /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered.
>> */
>> - if (--dev_priv->audio.power_refcount == 0)
>> + if (--dev_priv->display.audio.power_refcount == 0)
>> if (IS_GEMINILAKE(dev_priv))
>> glk_force_audio_cdclk(dev_priv, false);
>>
>> @@ -1140,10 +1140,10 @@ static struct intel_encoder
>> *get_saved_enc(struct drm_i915_private *dev_priv,
>> /* MST */
>> if (pipe >= 0) {
>> if (drm_WARN_ON(&dev_priv->drm,
>> - pipe >= ARRAY_SIZE(dev_priv-
>> >audio.encoder_map)))
>> + pipe >= ARRAY_SIZE(dev_priv-
>> >display.audio.encoder_map)))
>> return NULL;
>>
>> - encoder = dev_priv->audio.encoder_map[pipe];
>> + encoder = dev_priv->display.audio.encoder_map[pipe];
>> /*
>> * when bootup, audio driver may not know it is
>> * MST or not. So it will poll all the port & pipe @@ -1159,7
>> +1159,7 @@ static struct intel_encoder *get_saved_enc(struct
>> drm_i915_private *dev_priv,
>> return NULL;
>>
>> for_each_pipe(dev_priv, pipe) {
>> - encoder = dev_priv->audio.encoder_map[pipe];
>> + encoder = dev_priv->display.audio.encoder_map[pipe];
>> if (encoder == NULL)
>> continue;
>>
>> @@ -1177,7 +1177,7 @@ static int
>> i915_audio_component_sync_audio_rate(struct device *kdev, int port,
>> int pipe, int rate)
>> {
>> struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
>> - struct i915_audio_component *acomp = dev_priv-
>> >audio.component;
>> + struct i915_audio_component *acomp =
>> +dev_priv->display.audio.component;
>> struct intel_encoder *encoder;
>> struct intel_crtc *crtc;
>> unsigned long cookie;
>> @@ -1187,7 +1187,7 @@ static int
>> i915_audio_component_sync_audio_rate(struct device *kdev, int port,
>> return 0;
>>
>> cookie = i915_audio_component_get_power(kdev);
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>>
>> /* 1. get the pipe */
>> encoder = get_saved_enc(dev_priv, port, pipe); @@ -1206,7 +1206,7
>> @@ static int i915_audio_component_sync_audio_rate(struct device *kdev,
>> int port,
>> hsw_audio_config_update(encoder, crtc->config);
>>
>> unlock:
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>> i915_audio_component_put_power(kdev, cookie);
>> return err;
>> }
>> @@ -1220,13 +1220,13 @@ static int i915_audio_component_get_eld(struct
>> device *kdev, int port,
>> const u8 *eld;
>> int ret = -EINVAL;
>>
>> - mutex_lock(&dev_priv->audio.mutex);
>> + mutex_lock(&dev_priv->display.audio.mutex);
>>
>> intel_encoder = get_saved_enc(dev_priv, port, pipe);
>> if (!intel_encoder) {
>> drm_dbg_kms(&dev_priv->drm, "Not valid for port %c\n",
>> port_name(port));
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>> return ret;
>> }
>>
>> @@ -1238,7 +1238,7 @@ static int i915_audio_component_get_eld(struct
>> device *kdev, int port,
>> memcpy(buf, eld, min(max_bytes, ret));
>> }
>>
>> - mutex_unlock(&dev_priv->audio.mutex);
>> + mutex_unlock(&dev_priv->display.audio.mutex);
>> return ret;
>> }
>>
>> @@ -1273,7 +1273,7 @@ static int i915_audio_component_bind(struct
>> device *i915_kdev,
>> BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
>> for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
>> acomp->aud_sample_rate[i] = 0;
>> - dev_priv->audio.component = acomp;
>> + dev_priv->display.audio.component = acomp;
>> drm_modeset_unlock_all(&dev_priv->drm);
>>
>> return 0;
>> @@ -1288,14 +1288,14 @@ static void
>> i915_audio_component_unbind(struct device *i915_kdev,
>> drm_modeset_lock_all(&dev_priv->drm);
>> acomp->base.ops = NULL;
>> acomp->base.dev = NULL;
>> - dev_priv->audio.component = NULL;
>> + dev_priv->display.audio.component = NULL;
>> drm_modeset_unlock_all(&dev_priv->drm);
>>
>> device_link_remove(hda_kdev, i915_kdev);
>>
>> - if (dev_priv->audio.power_refcount)
>> + if (dev_priv->display.audio.power_refcount)
>> drm_err(&dev_priv->drm, "audio power refcount %d after
>> unbind\n",
>> - dev_priv->audio.power_refcount);
>> + dev_priv->display.audio.power_refcount);
>> }
>>
>> static const struct component_ops i915_audio_component_bind_ops = {
>> @@ -1359,13 +1359,13 @@ static void i915_audio_component_init(struct
>> drm_i915_private *dev_priv)
>> drm_dbg_kms(&dev_priv->drm, "use AUD_FREQ_CNTRL of
>> 0x%x (init value 0x%x)\n",
>> aud_freq, aud_freq_init);
>>
>> - dev_priv->audio.freq_cntrl = aud_freq;
>> + dev_priv->display.audio.freq_cntrl = aud_freq;
>> }
>>
>> /* init with current cdclk */
>> intel_audio_cdclk_change_post(dev_priv);
>>
>> - dev_priv->audio.component_registered = true;
>> + dev_priv->display.audio.component_registered = true;
>> }
>>
>> /**
>> @@ -1377,11 +1377,11 @@ static void i915_audio_component_init(struct
>> drm_i915_private *dev_priv)
>> */
>> static void i915_audio_component_cleanup(struct drm_i915_private
>> *dev_priv) {
>> - if (!dev_priv->audio.component_registered)
>> + if (!dev_priv->display.audio.component_registered)
>> return;
>>
>> component_del(dev_priv->drm.dev,
>> &i915_audio_component_bind_ops);
>> - dev_priv->audio.component_registered = false;
>> + dev_priv->display.audio.component_registered = false;
>> }
>>
>> /**
>> @@ -1403,7 +1403,7 @@ void intel_audio_init(struct drm_i915_private
>> *dev_priv)
>> */
>> void intel_audio_deinit(struct drm_i915_private *dev_priv) {
>> - if ((dev_priv)->audio.lpe.platdev != NULL)
>> + if (dev_priv->display.audio.lpe.platdev != NULL)
>> intel_lpe_audio_teardown(dev_priv);
>> else
>> i915_audio_component_cleanup(dev_priv);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index ca22706e11e6..748d2a84e20e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -10,11 +10,14 @@
>> #include <linux/types.h>
>> #include <linux/wait.h>
>>
>> +#include "intel_display.h"
>> #include "intel_dmc.h"
>> #include "intel_gmbus.h"
>>
>> struct drm_i915_private;
>> +struct i915_audio_component;
>> struct intel_atomic_state;
>> +struct intel_audio_funcs;
>> struct intel_cdclk_funcs;
>> struct intel_clock_gating_funcs;
>> struct intel_color_funcs;
>> @@ -56,6 +59,25 @@ struct intel_wm_funcs {
>> int (*compute_global_watermarks)(struct intel_atomic_state *state);
>> };
>>
>> +struct intel_audio {
>> + /* hda/i915 audio component */
>> + struct i915_audio_component *component;
>> + bool component_registered;
>> + /* mutex for audio/video sync */
>> + struct mutex mutex;
>> + int power_refcount;
>> + u32 freq_cntrl;
>> +
>> + /* Used to save the pipe-to-encoder mapping for audio */
>> + struct intel_encoder *encoder_map[I915_MAX_PIPES];
>> +
>> + /* necessary resource sharing with HDMI LPE audio driver. */
>> + struct {
>> + struct platform_device *platdev;
>> + int irq;
>> + } lpe;
>> +};
>> +
>> struct intel_display {
>> /* Display functions */
>> struct {
>> @@ -82,6 +104,9 @@ struct intel_display {
>>
>> /* Display internal color functions */
>> const struct intel_color_funcs *color;
>> +
>> + /* Display internal audio functions */
>> + const struct intel_audio_funcs *audio;
>> } funcs;
>>
>> /* Grouping using anonymous structs. Keep sorted. */ @@ -111,6
>> +136,7 @@ struct intel_display {
>> } pps;
>>
>> /* Grouping using named structs. Keep sorted. */
>> + struct intel_audio audio;
>> struct intel_dmc dmc;
>> };
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> index 1e18696aaecf..dca6003ccac8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
>> @@ -75,7 +75,7 @@
>> #include "intel_lpe_audio.h"
>> #include "intel_pci_config.h"
>>
>> -#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->audio.lpe.platdev != NULL)
>> +#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev
>> +!= NULL)
>>
>> static struct platform_device *
>> lpe_audio_platdev_create(struct drm_i915_private *dev_priv) @@ -97,7
>> +97,7 @@ lpe_audio_platdev_create(struct drm_i915_private *dev_priv)
>> return ERR_PTR(-ENOMEM);
>> }
>>
>> - rsc[0].start = rsc[0].end = dev_priv->audio.lpe.irq;
>> + rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
>> rsc[0].flags = IORESOURCE_IRQ;
>> rsc[0].name = "hdmi-lpe-audio-irq";
>>
>> @@ -149,7 +149,7 @@ static void lpe_audio_platdev_destroy(struct
>> drm_i915_private *dev_priv)
>> * than us fiddle with its internals.
>> */
>>
>> - platform_device_unregister(dev_priv->audio.lpe.platdev);
>> + platform_device_unregister(dev_priv->display.audio.lpe.platdev);
>> }
>>
>> static void lpe_audio_irq_unmask(struct irq_data *d) @@ -168,7 +168,7
>> @@ static struct irq_chip lpe_audio_irqchip = {
>>
>> static int lpe_audio_irq_init(struct drm_i915_private *dev_priv) {
>> - int irq = dev_priv->audio.lpe.irq;
>> + int irq = dev_priv->display.audio.lpe.irq;
>>
>> drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
>> irq_set_chip_and_handler_name(irq,
>> @@ -205,15 +205,15 @@ static int lpe_audio_setup(struct drm_i915_private
>> *dev_priv) {
>> int ret;
>>
>> - dev_priv->audio.lpe.irq = irq_alloc_desc(0);
>> - if (dev_priv->audio.lpe.irq < 0) {
>> + dev_priv->display.audio.lpe.irq = irq_alloc_desc(0);
>> + if (dev_priv->display.audio.lpe.irq < 0) {
>> drm_err(&dev_priv->drm, "Failed to allocate IRQ desc:
>> %d\n",
>> - dev_priv->audio.lpe.irq);
>> - ret = dev_priv->audio.lpe.irq;
>> + dev_priv->display.audio.lpe.irq);
>> + ret = dev_priv->display.audio.lpe.irq;
>> goto err;
>> }
>>
>> - drm_dbg(&dev_priv->drm, "irq = %d\n", dev_priv->audio.lpe.irq);
>> + drm_dbg(&dev_priv->drm, "irq = %d\n",
>> +dev_priv->display.audio.lpe.irq);
>>
>> ret = lpe_audio_irq_init(dev_priv);
>>
>> @@ -224,10 +224,10 @@ static int lpe_audio_setup(struct drm_i915_private
>> *dev_priv)
>> goto err_free_irq;
>> }
>>
>> - dev_priv->audio.lpe.platdev = lpe_audio_platdev_create(dev_priv);
>> + dev_priv->display.audio.lpe.platdev =
>> +lpe_audio_platdev_create(dev_priv);
>>
>> - if (IS_ERR(dev_priv->audio.lpe.platdev)) {
>> - ret = PTR_ERR(dev_priv->audio.lpe.platdev);
>> + if (IS_ERR(dev_priv->display.audio.lpe.platdev)) {
>> + ret = PTR_ERR(dev_priv->display.audio.lpe.platdev);
>> drm_err(&dev_priv->drm,
>> "Failed to create lpe audio platform device: %d\n",
>> ret);
>> @@ -242,10 +242,10 @@ static int lpe_audio_setup(struct drm_i915_private
>> *dev_priv)
>>
>> return 0;
>> err_free_irq:
>> - irq_free_desc(dev_priv->audio.lpe.irq);
>> + irq_free_desc(dev_priv->display.audio.lpe.irq);
>> err:
>> - dev_priv->audio.lpe.irq = -1;
>> - dev_priv->audio.lpe.platdev = NULL;
>> + dev_priv->display.audio.lpe.irq = -1;
>> + dev_priv->display.audio.lpe.platdev = NULL;
>> return ret;
>> }
>>
>> @@ -263,7 +263,7 @@ void intel_lpe_audio_irq_handler(struct
>> drm_i915_private *dev_priv)
>> if (!HAS_LPE_AUDIO(dev_priv))
>> return;
>>
>> - ret = generic_handle_irq(dev_priv->audio.lpe.irq);
>> + ret = generic_handle_irq(dev_priv->display.audio.lpe.irq);
>> if (ret)
>> drm_err_ratelimited(&dev_priv->drm,
>> "error handling LPE audio irq: %d\n", ret);
>> @@ -304,10 +304,10 @@ void intel_lpe_audio_teardown(struct
>> drm_i915_private *dev_priv)
>>
>> lpe_audio_platdev_destroy(dev_priv);
>>
>> - irq_free_desc(dev_priv->audio.lpe.irq);
>> + irq_free_desc(dev_priv->display.audio.lpe.irq);
>>
>> - dev_priv->audio.lpe.irq = -1;
>> - dev_priv->audio.lpe.platdev = NULL;
>> + dev_priv->display.audio.lpe.irq = -1;
>> + dev_priv->display.audio.lpe.platdev = NULL;
>> }
>>
>> /**
>> @@ -334,7 +334,7 @@ void intel_lpe_audio_notify(struct drm_i915_private
>> *dev_priv,
>> if (!HAS_LPE_AUDIO(dev_priv))
>> return;
>>
>> - pdata = dev_get_platdata(&dev_priv->audio.lpe.platdev->dev);
>> + pdata = dev_get_platdata(&dev_priv->display.audio.lpe.platdev-
>> >dev);
>> ppdata = &pdata->port[port - PORT_B];
>>
>> spin_lock_irqsave(&pdata->lpe_audio_slock, irqflags); @@ -362,7
>> +362,7 @@ void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
>> }
>>
>> if (pdata->notify_audio_lpe)
>> - pdata->notify_audio_lpe(dev_priv->audio.lpe.platdev, port -
>> PORT_B);
>> + pdata->notify_audio_lpe(dev_priv-
>> >display.audio.lpe.platdev, port -
>> +PORT_B);
>>
>> spin_unlock_irqrestore(&pdata->lpe_audio_slock, irqflags); } diff --
>> git a/drivers/gpu/drm/i915/i915_driver.c
>> b/drivers/gpu/drm/i915/i915_driver.c
>> index 694384e54fd7..0d3993e51138 100644
>> --- a/drivers/gpu/drm/i915/i915_driver.c
>> +++ b/drivers/gpu/drm/i915/i915_driver.c
>> @@ -335,7 +335,7 @@ static int i915_driver_early_probe(struct
>> drm_i915_private *dev_priv)
>> mutex_init(&dev_priv->sb_lock);
>> cpu_latency_qos_add_request(&dev_priv->sb_qos,
>> PM_QOS_DEFAULT_VALUE);
>>
>> - mutex_init(&dev_priv->audio.mutex);
>> + mutex_init(&dev_priv->display.audio.mutex);
>> mutex_init(&dev_priv->wm.wm_mutex);
>> mutex_init(&dev_priv->display.pps.mutex);
>> mutex_init(&dev_priv->hdcp_comp_mutex);
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h
>> b/drivers/gpu/drm/i915/i915_drv.h index d1b51e2460e0..ebd96555ada0
>> 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -78,7 +78,6 @@
>> struct dpll;
>> struct drm_i915_gem_object;
>> struct drm_i915_private;
>> -struct intel_audio_funcs;
>> struct intel_cdclk_config;
>> struct intel_cdclk_state;
>> struct intel_cdclk_vals;
>> @@ -306,29 +305,6 @@ struct i915_selftest_stash {
>> struct ida mock_region_instances;
>> };
>>
>> -/* intel_audio.c private */
>> -struct intel_audio_private {
>> - /* Display internal audio functions */
>> - const struct intel_audio_funcs *funcs;
>> -
>> - /* hda/i915 audio component */
>> - struct i915_audio_component *component;
>> - bool component_registered;
>> - /* mutex for audio/video sync */
>> - struct mutex mutex;
>> - int power_refcount;
>> - u32 freq_cntrl;
>> -
>> - /* Used to save the pipe-to-encoder mapping for audio */
>> - struct intel_encoder *encoder_map[I915_MAX_PIPES];
>> -
>> - /* necessary resource sharing with HDMI LPE audio driver. */
>> - struct {
>> - struct platform_device *platdev;
>> - int irq;
>> - } lpe;
>> -};
>> -
>> struct drm_i915_private {
>> struct drm_device drm;
>>
>> @@ -671,8 +647,6 @@ struct drm_i915_private {
>>
>> bool ipc_enabled;
>>
>> - struct intel_audio_private audio;
>> -
>> struct i915_pmu pmu;
>>
>> struct i915_drm_clients clients;
>> --
>> 2.34.1
>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-12 7:03 ` Jani Nikula
@ 2022-08-16 4:13 ` Murthy, Arun R
2022-08-16 8:02 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 4:13 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Friday, August 12, 2022 12:33 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
> display.audio and display.funcs
>
> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
> >> Of Jani Nikula
> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> To: intel-gfx@lists.freedesktop.org
> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> <lucas.demarchi@intel.com>
> >> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio
> >> under display.audio and display.funcs
> >>
> >> Move display related members under drm_i915_private display sub-
> struct.
> >>
> >> Split audio funcs to display.funcs to follow the same pattern as all
> >> the other display functions.
> >>
> > Audio is a feature as such so wouldn't intel_audio struct stand parallel to
> intel_display?
>
> For i915, audio doesn't exist other than as a display feature. Display is a
> higher level split here, parallel to gt/gem.
>
Will leave it to you, since you have started this huger series containing the cleanup and understand you also have some more cleanup in queue.
My small suggestion is not to mix audio with display and let this audi reside in i915_priv and let it leave in parallel similar to gt/gem.
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-16 4:13 ` Murthy, Arun R
@ 2022-08-16 8:02 ` Jani Nikula
2022-08-16 8:28 ` Murthy, Arun R
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-16 8:02 UTC (permalink / raw)
To: Murthy, Arun R, intel-gfx; +Cc: De Marchi, Lucas
On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Friday, August 12, 2022 12:33 PM
>> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
>> Subject: RE: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
>> display.audio and display.funcs
>>
>> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
>> >> -----Original Message-----
>> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf
>> >> Of Jani Nikula
>> >> Sent: Thursday, August 11, 2022 8:37 PM
>> >> To: intel-gfx@lists.freedesktop.org
>> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
>> >> <lucas.demarchi@intel.com>
>> >> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio
>> >> under display.audio and display.funcs
>> >>
>> >> Move display related members under drm_i915_private display sub-
>> struct.
>> >>
>> >> Split audio funcs to display.funcs to follow the same pattern as all
>> >> the other display functions.
>> >>
>> > Audio is a feature as such so wouldn't intel_audio struct stand parallel to
>> intel_display?
>>
>> For i915, audio doesn't exist other than as a display feature. Display is a
>> higher level split here, parallel to gt/gem.
>>
> Will leave it to you, since you have started this huger series containing the cleanup and understand you also have some more cleanup in queue.
> My small suggestion is not to mix audio with display and let this audi reside in i915_priv and let it leave in parallel similar to gt/gem.
No, I'm going to stick with this hierarchy. Audio is part of display
here.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --------------------
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-16 8:02 ` Jani Nikula
@ 2022-08-16 8:28 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-16 8:28 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: De Marchi, Lucas
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, August 16, 2022 1:32 PM
> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> Subject: RE: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under
> display.audio and display.funcs
>
> On Tue, 16 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> -----Original Message-----
> >> From: Nikula, Jani <jani.nikula@intel.com>
> >> Sent: Friday, August 12, 2022 12:33 PM
> >> To: Murthy, Arun R <arun.r.murthy@intel.com>; intel-
> >> gfx@lists.freedesktop.org
> >> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>
> >> Subject: RE: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio
> >> under display.audio and display.funcs
> >>
> >> On Fri, 12 Aug 2022, "Murthy, Arun R" <arun.r.murthy@intel.com> wrote:
> >> >> -----Original Message-----
> >> >> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On
> >> >> Behalf Of Jani Nikula
> >> >> Sent: Thursday, August 11, 2022 8:37 PM
> >> >> To: intel-gfx@lists.freedesktop.org
> >> >> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> >> >> <lucas.demarchi@intel.com>
> >> >> Subject: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio
> >> >> under display.audio and display.funcs
> >> >>
> >> >> Move display related members under drm_i915_private display sub-
> >> struct.
> >> >>
> >> >> Split audio funcs to display.funcs to follow the same pattern as
> >> >> all the other display functions.
> >> >>
> >> > Audio is a feature as such so wouldn't intel_audio struct stand
> >> > parallel to
> >> intel_display?
> >>
> >> For i915, audio doesn't exist other than as a display feature.
> >> Display is a higher level split here, parallel to gt/gem.
> >>
> > Will leave it to you, since you have started this huger series containing the
> cleanup and understand you also have some more cleanup in queue.
> > My small suggestion is not to mix audio with display and let this audi reside
> in i915_priv and let it leave in parallel similar to gt/gem.
>
> No, I'm going to stick with this hierarchy. Audio is part of display here.
>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
^ permalink raw reply [flat|nested] 110+ messages in thread
* Re: [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs
2022-08-11 15:07 ` [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs Jani Nikula
2022-08-12 5:02 ` Murthy, Arun R
@ 2022-08-17 4:14 ` Lucas De Marchi
1 sibling, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:23PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Split audio funcs to display.funcs to follow the same pattern as all the
>other display functions.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (11 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 12/39] drm/i915: move and split audio under display.audio and display.funcs Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:16 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev Jani Nikula
` (31 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++--
drivers/gpu/drm/i915/display/intel_display.c | 4 +-
.../gpu/drm/i915/display/intel_display_core.h | 21 ++++
.../drm/i915/display/intel_display_debugfs.c | 8 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 112 +++++++++---------
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 21 ----
9 files changed, 104 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 5dcfa7feffa9..49357e4ed3be 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -641,13 +641,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
@@ -657,13 +657,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
@@ -693,7 +693,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
@@ -709,7 +709,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index a4c8493f3ce7..23c8287b0262 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
@@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
*/
intel_de_rmw(i915, reg, clk_off, 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
u32 clk_off)
{
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, reg, 0, clk_off);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
@@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
intel_de_write(i915, DDI_CLK_SEL(port),
icl_pll_to_ddi_clk_sel(encoder, crtc_state));
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
@@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
enum port port = encoder->port;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
}
@@ -1824,7 +1824,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
if (drm_WARN_ON(&i915->drm, !pll))
return;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, DPLL_CTRL2,
DPLL_CTRL2_DDI_CLK_OFF(port) |
@@ -1832,7 +1832,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static void skl_ddi_disable_clock(struct intel_encoder *encoder)
@@ -1840,12 +1840,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum port port = encoder->port;
- mutex_lock(&i915->dpll.lock);
+ mutex_lock(&i915->display.dpll.lock);
intel_de_rmw(i915, DPLL_CTRL2,
0, DPLL_CTRL2_DDI_CLK_OFF(port));
- mutex_unlock(&i915->dpll.lock);
+ mutex_unlock(&i915->display.dpll.lock);
}
static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7db4ac27364d..efc0fa648736 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1487,7 +1487,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
* Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
* TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
*/
- if (i915->dpll.mgr) {
+ if (i915->display.dpll.mgr) {
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state))
continue;
@@ -5839,7 +5839,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(double_wide);
- if (dev_priv->dpll.mgr) {
+ if (dev_priv->display.dpll.mgr) {
PIPE_CONF_CHECK_P(shared_dpll);
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 748d2a84e20e..f12ff36fef07 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -12,6 +12,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
+#include "intel_dpll_mgr.h"
#include "intel_gmbus.h"
struct drm_i915_private;
@@ -24,6 +25,7 @@ struct intel_color_funcs;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
+struct intel_dpll_mgr;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
@@ -78,6 +80,24 @@ struct intel_audio {
} lpe;
};
+/*
+ * dpll and cdclk state is protected by connection_mutex dpll.lock serializes
+ * intel_{prepare,enable,disable}_shared_dpll. Must be global rather than per
+ * dpll, because on some platforms plls share registers.
+ */
+struct intel_dpll {
+ struct mutex lock;
+
+ int num_shared_dpll;
+ struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
+ const struct intel_dpll_mgr *mgr;
+
+ struct {
+ int nssc;
+ int ssc;
+ } ref_clks;
+};
+
struct intel_display {
/* Display functions */
struct {
@@ -138,6 +158,7 @@ struct intel_display {
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
+ struct intel_dpll dpll;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 225b6bfc783c..7994f78b889a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -933,11 +933,11 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
drm_modeset_lock_all(dev);
seq_printf(m, "PLL refclks: non-SSC: %d kHz, SSC: %d kHz\n",
- dev_priv->dpll.ref_clks.nssc,
- dev_priv->dpll.ref_clks.ssc);
+ dev_priv->display.dpll.ref_clks.nssc,
+ dev_priv->display.dpll.ref_clks.ssc);
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
+ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name,
pll->info->id);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 118598c9a809..bbe142056c7c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -113,8 +113,8 @@ intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
enum intel_dpll_id i;
/* Copy shared dpll state */
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
- struct intel_shared_dpll *pll = &dev_priv->dpll.shared_dplls[i];
+ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
+ struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
shared_dpll[i] = pll->state;
}
@@ -149,7 +149,7 @@ struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
enum intel_dpll_id id)
{
- return &dev_priv->dpll.shared_dplls[id];
+ return &dev_priv->display.dpll.shared_dplls[id];
}
/**
@@ -164,11 +164,11 @@ enum intel_dpll_id
intel_get_shared_dpll_id(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
- long pll_idx = pll - dev_priv->dpll.shared_dplls;
+ long pll_idx = pll - dev_priv->display.dpll.shared_dplls;
if (drm_WARN_ON(&dev_priv->drm,
pll_idx < 0 ||
- pll_idx >= dev_priv->dpll.num_shared_dpll))
+ pll_idx >= dev_priv->display.dpll.num_shared_dpll))
return -1;
return pll_idx;
@@ -245,7 +245,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
return;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
old_mask = pll->active_mask;
if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) ||
@@ -271,7 +271,7 @@ void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = true;
out:
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
/**
@@ -294,7 +294,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
if (pll == NULL)
return;
- mutex_lock(&dev_priv->dpll.lock);
+ mutex_lock(&dev_priv->display.dpll.lock);
if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
"%s not used by [CRTC:%d:%s]\n", pll->info->name,
crtc->base.base.id, crtc->base.name))
@@ -317,7 +317,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
pll->on = false;
out:
- mutex_unlock(&dev_priv->dpll.lock);
+ mutex_unlock(&dev_priv->display.dpll.lock);
}
static struct intel_shared_dpll *
@@ -336,7 +336,7 @@ intel_find_shared_dpll(struct intel_atomic_state *state,
drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
- pll = &dev_priv->dpll.shared_dplls[i];
+ pll = &dev_priv->display.dpll.shared_dplls[i];
/* Only want to check enabled timings first */
if (shared_dpll[i].pipe_mask == 0) {
@@ -436,9 +436,9 @@ void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
if (!state->dpll_set)
return;
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
struct intel_shared_dpll *pll =
- &dev_priv->dpll.shared_dplls[i];
+ &dev_priv->display.dpll.shared_dplls[i];
swap(pll->state, shared_dpll[i]);
}
@@ -537,7 +537,7 @@ static int ibx_get_dpll(struct intel_atomic_state *state,
if (HAS_PCH_IBX(dev_priv)) {
/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
i = (enum intel_dpll_id) crtc->pipe;
- pll = &dev_priv->dpll.shared_dplls[i];
+ pll = &dev_priv->display.dpll.shared_dplls[i];
drm_dbg_kms(&dev_priv->drm,
"[CRTC:%d:%s] using pre-allocated %s\n",
@@ -948,7 +948,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
case WRPLL_REF_SPECIAL_HSW:
/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
if (IS_HASWELL(dev_priv) && !IS_HSW_ULT(dev_priv)) {
- refclk = dev_priv->dpll.ref_clks.nssc;
+ refclk = dev_priv->display.dpll.ref_clks.nssc;
break;
}
fallthrough;
@@ -958,7 +958,7 @@ static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
* code only cares about 5% accuracy, and spread is a max of
* 0.5% downspread.
*/
- refclk = dev_priv->dpll.ref_clks.ssc;
+ refclk = dev_priv->display.dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
refclk = 2700000;
@@ -1145,12 +1145,12 @@ static int hsw_get_dpll(struct intel_atomic_state *state,
static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
{
- i915->dpll.ref_clks.ssc = 135000;
+ i915->display.dpll.ref_clks.ssc = 135000;
/* Non-SSC is only used on non-ULT HSW. */
if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
- i915->dpll.ref_clks.nssc = 24000;
+ i915->display.dpll.ref_clks.nssc = 24000;
else
- i915->dpll.ref_clks.nssc = 135000;
+ i915->display.dpll.ref_clks.nssc = 135000;
}
static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -1634,7 +1634,7 @@ static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
- i915->dpll.ref_clks.nssc, &wrpll_params);
+ i915->display.dpll.ref_clks.nssc, &wrpll_params);
if (ret)
return ret;
@@ -1659,7 +1659,7 @@ static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
const struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *pll_state)
{
- int ref_clock = i915->dpll.ref_clks.nssc;
+ int ref_clock = i915->display.dpll.ref_clks.nssc;
u32 p0, p1, p2, dco_freq;
p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
@@ -1858,7 +1858,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -2171,7 +2171,7 @@ static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
}
}
- chv_calc_dpll_params(i915->dpll.ref_clks.nssc, clk_div);
+ chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
clk_div->dot != crtc_state->port_clock);
@@ -2279,7 +2279,7 @@ static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
- return chv_calc_dpll_params(i915->dpll.ref_clks.nssc, &clock);
+ return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
}
static int bxt_compute_dpll(struct intel_atomic_state *state,
@@ -2324,8 +2324,8 @@ static int bxt_get_dpll(struct intel_atomic_state *state,
static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
{
- i915->dpll.ref_clks.ssc = 100000;
- i915->dpll.ref_clks.nssc = 100000;
+ i915->display.dpll.ref_clks.ssc = 100000;
+ i915->display.dpll.ref_clks.nssc = 100000;
/* DSI non-SSC ref 19.2MHz */
}
@@ -2468,7 +2468,7 @@ ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) &&
IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
- i915->dpll.ref_clks.nssc == 38400;
+ i915->display.dpll.ref_clks.nssc == 38400;
}
struct icl_combo_pll_params {
@@ -2562,7 +2562,7 @@ static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
const struct icl_combo_pll_params *params =
- dev_priv->dpll.ref_clks.nssc == 24000 ?
+ dev_priv->display.dpll.ref_clks.nssc == 24000 ?
icl_dp_combo_pll_24MHz_values :
icl_dp_combo_pll_19_2MHz_values;
int clock = crtc_state->port_clock;
@@ -2585,9 +2585,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
if (DISPLAY_VER(dev_priv) >= 12) {
- switch (dev_priv->dpll.ref_clks.nssc) {
+ switch (dev_priv->display.dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
+ MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2598,9 +2598,9 @@ static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
break;
}
} else {
- switch (dev_priv->dpll.ref_clks.nssc) {
+ switch (dev_priv->display.dpll.ref_clks.nssc) {
default:
- MISSING_CASE(dev_priv->dpll.ref_clks.nssc);
+ MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
fallthrough;
case 19200:
case 38400:
@@ -2630,7 +2630,7 @@ static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
{
- int ref_clock = i915->dpll.ref_clks.nssc;
+ int ref_clock = i915->display.dpll.ref_clks.nssc;
/*
* For ICL+, the spec states: if reference frequency is 38.4,
@@ -2857,7 +2857,7 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
struct intel_dpll_hw_state *pll_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- int refclk_khz = dev_priv->dpll.ref_clks.nssc;
+ int refclk_khz = dev_priv->display.dpll.ref_clks.nssc;
int clock = crtc_state->port_clock;
u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
u32 iref_ndiv, iref_trim, iref_pulse_w;
@@ -3063,7 +3063,7 @@ static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
u64 tmp;
- ref_clock = dev_priv->dpll.ref_clks.nssc;
+ ref_clock = dev_priv->display.dpll.ref_clks.nssc;
if (DISPLAY_VER(dev_priv) >= 12) {
m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
@@ -3440,7 +3440,7 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_tdc_coldst_bias =
intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
- if (dev_priv->dpll.ref_clks.nssc == 38400) {
+ if (dev_priv->display.dpll.ref_clks.nssc == 38400) {
hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
hw_state->mg_pll_bias_mask = 0;
} else {
@@ -3967,7 +3967,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -4192,7 +4192,7 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
dpll_mgr = &pch_pll_mgr;
if (!dpll_mgr) {
- dev_priv->dpll.num_shared_dpll = 0;
+ dev_priv->display.dpll.num_shared_dpll = 0;
return;
}
@@ -4200,14 +4200,14 @@ void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
for (i = 0; dpll_info[i].name; i++) {
drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
- dev_priv->dpll.shared_dplls[i].info = &dpll_info[i];
+ dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
}
- dev_priv->dpll.mgr = dpll_mgr;
- dev_priv->dpll.num_shared_dpll = i;
- mutex_init(&dev_priv->dpll.lock);
+ dev_priv->display.dpll.mgr = dpll_mgr;
+ dev_priv->display.dpll.num_shared_dpll = i;
+ mutex_init(&dev_priv->display.dpll.lock);
- BUG_ON(dev_priv->dpll.num_shared_dpll > I915_NUM_PLLS);
+ BUG_ON(dev_priv->display.dpll.num_shared_dpll > I915_NUM_PLLS);
}
/**
@@ -4229,7 +4229,7 @@ int intel_compute_shared_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return -EINVAL;
@@ -4262,7 +4262,7 @@ int intel_reserve_shared_dplls(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return -EINVAL;
@@ -4285,7 +4285,7 @@ void intel_release_shared_dplls(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
/*
* FIXME: this function is called for every platform having a
@@ -4314,7 +4314,7 @@ void intel_update_active_dpll(struct intel_atomic_state *state,
struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- const struct intel_dpll_mgr *dpll_mgr = dev_priv->dpll.mgr;
+ const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
return;
@@ -4385,16 +4385,16 @@ static void readout_dpll_hw_state(struct drm_i915_private *i915,
void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
{
- if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks)
- i915->dpll.mgr->update_ref_clks(i915);
+ if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
+ i915->display.dpll.mgr->update_ref_clks(i915);
}
void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->dpll.num_shared_dpll; i++)
- readout_dpll_hw_state(i915, &i915->dpll.shared_dplls[i]);
+ for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
+ readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]);
}
static void sanitize_dpll_state(struct drm_i915_private *i915,
@@ -4420,8 +4420,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->dpll.num_shared_dpll; i++)
- sanitize_dpll_state(i915, &i915->dpll.shared_dplls[i]);
+ for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
+ sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]);
}
/**
@@ -4434,8 +4434,8 @@ void intel_dpll_sanitize_state(struct drm_i915_private *i915)
void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
const struct intel_dpll_hw_state *hw_state)
{
- if (dev_priv->dpll.mgr) {
- dev_priv->dpll.mgr->dump_hw_state(dev_priv, hw_state);
+ if (dev_priv->display.dpll.mgr) {
+ dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state);
} else {
/* fallback for platforms that don't use the shared dpll
* infrastructure
@@ -4533,7 +4533,7 @@ void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915)
{
int i;
- for (i = 0; i < i915->dpll.num_shared_dpll; i++)
- verify_single_dpll_state(i915, &i915->dpll.shared_dplls[i],
+ for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
+ verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i],
NULL, NULL);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9934c8a9e240..ee72400759a3 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -522,7 +522,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
/* Check if any DPLLs are using the SSC source */
- for (i = 0; i < dev_priv->dpll.num_shared_dpll; i++) {
+ for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
u32 temp = intel_de_read(dev_priv, PCH_DPLL(i));
if (!(temp & DPLL_VCO_ENABLE))
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index beea5895e499..e7e33f95cc51 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -498,7 +498,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
switch (wrpll_ctl & WRPLL_REF_MASK) {
case WRPLL_REF_PCH_SSC:
- refclk = vgpu->gvt->gt->i915->dpll.ref_clks.ssc;
+ refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
break;
case WRPLL_REF_LCPLL:
refclk = 2700000;
@@ -529,7 +529,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port)
{
u32 dp_br = 0;
- int refclk = vgpu->gvt->gt->i915->dpll.ref_clks.nssc;
+ int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
enum dpio_phy phy = DPIO_PHY0;
enum dpio_channel ch = DPIO_CH0;
struct dpll clock = {0};
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ebd96555ada0..482a8c0d5a10 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -41,7 +41,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
-#include "display/intel_dpll_mgr.h"
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
@@ -75,7 +74,6 @@
#include "intel_uncore.h"
#include "intel_wopcm.h"
-struct dpll;
struct drm_i915_gem_object;
struct drm_i915_private;
struct intel_cdclk_config;
@@ -445,25 +443,6 @@ struct drm_i915_private {
/* Kernel Modesetting */
- /**
- * dpll and cdclk state is protected by connection_mutex
- * dpll.lock serializes intel_{prepare,enable,disable}_shared_dpll.
- * Must be global rather than per dpll, because on some platforms plls
- * share registers.
- */
- struct {
- struct mutex lock;
-
- int num_shared_dpll;
- struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
- const struct intel_dpll_mgr *mgr;
-
- struct {
- int nssc;
- int ssc;
- } ref_clks;
- } dpll;
-
struct list_head global_obj_list;
struct i915_frontbuffer_tracking fb_tracking;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll
2022-08-11 15:07 ` [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll Jani Nikula
@ 2022-08-17 4:16 ` Lucas De Marchi
2022-08-24 10:35 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:16 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:24PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/icl_dsi.c | 12 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 24 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 4 +-
> .../gpu/drm/i915/display/intel_display_core.h | 21 ++++
> .../drm/i915/display/intel_display_debugfs.c | 8 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 112 +++++++++---------
> .../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
> drivers/gpu/drm/i915/i915_drv.h | 21 ----
> 9 files changed, 104 insertions(+), 104 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>index 5dcfa7feffa9..49357e4ed3be 100644
>--- a/drivers/gpu/drm/i915/display/icl_dsi.c
>+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>@@ -641,13 +641,13 @@ static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> u32 tmp;
> enum phy phy;
>
>- mutex_lock(&dev_priv->dpll.lock);
>+ mutex_lock(&dev_priv->display.dpll.lock);
> tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys)
> tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>
> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
>- mutex_unlock(&dev_priv->dpll.lock);
>+ mutex_unlock(&dev_priv->display.dpll.lock);
> }
>
> static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
>@@ -657,13 +657,13 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
> u32 tmp;
> enum phy phy;
>
>- mutex_lock(&dev_priv->dpll.lock);
>+ mutex_lock(&dev_priv->display.dpll.lock);
> tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys)
> tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>
> intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
>- mutex_unlock(&dev_priv->dpll.lock);
>+ mutex_unlock(&dev_priv->display.dpll.lock);
> }
>
> static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
>@@ -693,7 +693,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> enum phy phy;
> u32 val;
>
>- mutex_lock(&dev_priv->dpll.lock);
>+ mutex_lock(&dev_priv->display.dpll.lock);
>
> val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys) {
>@@ -709,7 +709,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
>
> intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
>
>- mutex_unlock(&dev_priv->dpll.lock);
>+ mutex_unlock(&dev_priv->display.dpll.lock);
> }
>
> static void
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index a4c8493f3ce7..23c8287b0262 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -1425,7 +1425,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
> u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
> {
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
>
>@@ -1435,17 +1435,17 @@ static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
> */
> intel_de_rmw(i915, reg, clk_off, 0);
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
> }
>
> static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
> u32 clk_off)
> {
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, reg, 0, clk_off);
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
> }
>
> static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
>@@ -1720,12 +1720,12 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
> intel_de_write(i915, DDI_CLK_SEL(port),
> icl_pll_to_ddi_clk_sel(encoder, crtc_state));
>
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
> ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
> }
>
> static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
>@@ -1734,12 +1734,12 @@ static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
> enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
> enum port port = encoder->port;
>
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
> 0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
>
> intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
> }
>@@ -1824,7 +1824,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> if (drm_WARN_ON(&i915->drm, !pll))
> return;
>
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, DPLL_CTRL2,
> DPLL_CTRL2_DDI_CLK_OFF(port) |
>@@ -1832,7 +1832,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
> DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
> DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
> }
>
> static void skl_ddi_disable_clock(struct intel_encoder *encoder)
>@@ -1840,12 +1840,12 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> enum port port = encoder->port;
>
>- mutex_lock(&i915->dpll.lock);
>+ mutex_lock(&i915->display.dpll.lock);
>
> intel_de_rmw(i915, DPLL_CTRL2,
> 0, DPLL_CTRL2_DDI_CLK_OFF(port));
>
>- mutex_unlock(&i915->dpll.lock);
>+ mutex_unlock(&i915->display.dpll.lock);
> }
>
> static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
>diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>index 7db4ac27364d..efc0fa648736 100644
>--- a/drivers/gpu/drm/i915/display/intel_display.c
>+++ b/drivers/gpu/drm/i915/display/intel_display.c
>@@ -1487,7 +1487,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state)
> * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
> * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
> */
>- if (i915->dpll.mgr) {
>+ if (i915->display.dpll.mgr) {
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
> if (intel_crtc_needs_modeset(new_crtc_state))
> continue;
>@@ -5839,7 +5839,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>
> PIPE_CONF_CHECK_BOOL(double_wide);
>
>- if (dev_priv->dpll.mgr) {
>+ if (dev_priv->display.dpll.mgr) {
> PIPE_CONF_CHECK_P(shared_dpll);
>
> PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 748d2a84e20e..f12ff36fef07 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -12,6 +12,7 @@
>
> #include "intel_display.h"
> #include "intel_dmc.h"
>+#include "intel_dpll_mgr.h"
> #include "intel_gmbus.h"
>
> struct drm_i915_private;
>@@ -24,6 +25,7 @@ struct intel_color_funcs;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
>+struct intel_dpll_mgr;
if you include intel_dpll_mgr.h you don't need the fwd declaration?
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll
2022-08-17 4:16 ` Lucas De Marchi
@ 2022-08-24 10:35 ` Jani Nikula
0 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-24 10:35 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Aug 11, 2022 at 06:07:24PM +0300, Jani Nikula wrote:
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>index 748d2a84e20e..f12ff36fef07 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>@@ -12,6 +12,7 @@
>>
>> #include "intel_display.h"
>> #include "intel_dmc.h"
>>+#include "intel_dpll_mgr.h"
>> #include "intel_gmbus.h"
>>
>> struct drm_i915_private;
>>@@ -24,6 +25,7 @@ struct intel_color_funcs;
>> struct intel_crtc;
>> struct intel_crtc_state;
>> struct intel_dpll_funcs;
>>+struct intel_dpll_mgr;
>
> if you include intel_dpll_mgr.h you don't need the fwd declaration?
Funny as it is, intel_dpll_mgr.h does not define or forward declare
struct intel_dpll_mgr. :)
BR,
Jani.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>
> Lucas De Marchi
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (12 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 13/39] drm/i915: move dpll under display.dpll Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-22 3:58 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm Jani Nikula
` (30 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 8 ++++++
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/display/intel_fbdev.c | 26 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 5 ----
4 files changed, 22 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index f12ff36fef07..71434a922695 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -9,6 +9,7 @@
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
+#include <linux/workqueue.h>
#include "intel_display.h"
#include "intel_dmc.h"
@@ -26,6 +27,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_dpll_funcs;
struct intel_dpll_mgr;
+struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
@@ -130,6 +132,12 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /* list of fbdev register on this device */
+ struct intel_fbdev *fbdev;
+ struct work_struct suspend_work;
+ } fbdev;
+
struct {
/*
* Base address of where the gmbus and gpio blocks are located
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 7994f78b889a..e568590faa82 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -129,7 +129,7 @@ static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
struct drm_framebuffer *drm_fb;
#ifdef CONFIG_DRM_FBDEV_EMULATION
- fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev);
+ fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
if (fbdev_fb) {
seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
fbdev_fb->base.width,
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 221336178991..c08ff6a5c2e9 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -500,7 +500,7 @@ static void intel_fbdev_suspend_worker(struct work_struct *work)
{
intel_fbdev_set_suspend(&container_of(work,
struct drm_i915_private,
- fbdev_suspend_work)->drm,
+ display.fbdev.suspend_work)->drm,
FBINFO_STATE_RUNNING,
true);
}
@@ -530,8 +530,8 @@ int intel_fbdev_init(struct drm_device *dev)
return ret;
}
- dev_priv->fbdev = ifbdev;
- INIT_WORK(&dev_priv->fbdev_suspend_work, intel_fbdev_suspend_worker);
+ dev_priv->display.fbdev.fbdev = ifbdev;
+ INIT_WORK(&dev_priv->display.fbdev.suspend_work, intel_fbdev_suspend_worker);
return 0;
}
@@ -548,7 +548,7 @@ static void intel_fbdev_initial_config(void *data, async_cookie_t cookie)
void intel_fbdev_initial_config_async(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
if (!ifbdev)
return;
@@ -568,12 +568,12 @@ static void intel_fbdev_sync(struct intel_fbdev *ifbdev)
void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = dev_priv->fbdev;
+ struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
if (!ifbdev)
return;
- cancel_work_sync(&dev_priv->fbdev_suspend_work);
+ cancel_work_sync(&dev_priv->display.fbdev.suspend_work);
if (!current_is_async())
intel_fbdev_sync(ifbdev);
@@ -582,7 +582,7 @@ void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
void intel_fbdev_fini(struct drm_i915_private *dev_priv)
{
- struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev);
+ struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->display.fbdev.fbdev);
if (!ifbdev)
return;
@@ -596,7 +596,7 @@ void intel_fbdev_fini(struct drm_i915_private *dev_priv)
*/
static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state)
{
- struct intel_fbdev *ifbdev = i915->fbdev;
+ struct intel_fbdev *ifbdev = i915->display.fbdev.fbdev;
bool send_hpd = false;
mutex_lock(&ifbdev->hpd_lock);
@@ -614,7 +614,7 @@ static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int state
void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_fbdev *ifbdev = dev_priv->fbdev;
+ struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
struct fb_info *info;
if (!ifbdev || !ifbdev->vma)
@@ -631,7 +631,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
* ourselves, so only flush outstanding work upon suspend!
*/
if (state != FBINFO_STATE_RUNNING)
- flush_work(&dev_priv->fbdev_suspend_work);
+ flush_work(&dev_priv->display.fbdev.suspend_work);
console_lock();
} else {
@@ -645,7 +645,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
/* Don't block our own workqueue as this can
* be run in parallel with other i915.ko tasks.
*/
- schedule_work(&dev_priv->fbdev_suspend_work);
+ schedule_work(&dev_priv->display.fbdev.suspend_work);
return;
}
}
@@ -666,7 +666,7 @@ void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous
void intel_fbdev_output_poll_changed(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
bool send_hpd;
if (!ifbdev)
@@ -685,7 +685,7 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev)
void intel_fbdev_restore_mode(struct drm_device *dev)
{
- struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
+ struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
if (!ifbdev)
return;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 482a8c0d5a10..f1e47090c01e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -82,7 +82,6 @@ struct intel_cdclk_vals;
struct intel_connector;
struct intel_dp;
struct intel_encoder;
-struct intel_fbdev;
struct intel_limit;
struct intel_overlay;
struct intel_overlay_error_state;
@@ -474,10 +473,6 @@ struct drm_i915_private {
struct i915_gpu_error gpu_error;
- /* list of fbdev register on this device */
- struct intel_fbdev *fbdev;
- struct work_struct fbdev_suspend_work;
-
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev
2022-08-11 15:07 ` [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev Jani Nikula
@ 2022-08-22 3:58 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-22 3:58 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under
> display.fbdev
>
> Move display related members under drm_i915_private display sub-struct.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 8 ++++++
> .../drm/i915/display/intel_display_debugfs.c | 2 +-
> drivers/gpu/drm/i915/display/intel_fbdev.c | 26 +++++++++----------
> drivers/gpu/drm/i915/i915_drv.h | 5 ----
> 4 files changed, 22 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index f12ff36fef07..71434a922695 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -9,6 +9,7 @@
> #include <linux/mutex.h>
> #include <linux/types.h>
> #include <linux/wait.h>
> +#include <linux/workqueue.h>
>
> #include "intel_display.h"
> #include "intel_dmc.h"
> @@ -26,6 +27,7 @@ struct intel_crtc;
> struct intel_crtc_state;
> struct intel_dpll_funcs;
> struct intel_dpll_mgr;
> +struct intel_fbdev;
> struct intel_fdi_funcs;
> struct intel_hotplug_funcs;
> struct intel_initial_plane_config;
> @@ -130,6 +132,12 @@ struct intel_display {
> } funcs;
>
> /* Grouping using anonymous structs. Keep sorted. */
> + struct {
> + /* list of fbdev register on this device */
> + struct intel_fbdev *fbdev;
> + struct work_struct suspend_work;
> + } fbdev;
> +
> struct {
> /*
> * Base address of where the gmbus and gpio blocks are
> located diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index 7994f78b889a..e568590faa82 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -129,7 +129,7 @@ static int i915_gem_framebuffer_info(struct seq_file
> *m, void *data)
> struct drm_framebuffer *drm_fb;
>
> #ifdef CONFIG_DRM_FBDEV_EMULATION
> - fbdev_fb = intel_fbdev_framebuffer(dev_priv->fbdev);
> + fbdev_fb = intel_fbdev_framebuffer(dev_priv->display.fbdev.fbdev);
> if (fbdev_fb) {
> seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp,
> modifier 0x%llx, refcount %d, obj ",
> fbdev_fb->base.width,
> diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
> b/drivers/gpu/drm/i915/display/intel_fbdev.c
> index 221336178991..c08ff6a5c2e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
> @@ -500,7 +500,7 @@ static void intel_fbdev_suspend_worker(struct
> work_struct *work) {
> intel_fbdev_set_suspend(&container_of(work,
> struct drm_i915_private,
> - fbdev_suspend_work)->drm,
> + display.fbdev.suspend_work)-
> >drm,
> FBINFO_STATE_RUNNING,
> true);
> }
> @@ -530,8 +530,8 @@ int intel_fbdev_init(struct drm_device *dev)
> return ret;
> }
>
> - dev_priv->fbdev = ifbdev;
> - INIT_WORK(&dev_priv->fbdev_suspend_work,
> intel_fbdev_suspend_worker);
> + dev_priv->display.fbdev.fbdev = ifbdev;
> + INIT_WORK(&dev_priv->display.fbdev.suspend_work,
> +intel_fbdev_suspend_worker);
>
> return 0;
> }
> @@ -548,7 +548,7 @@ static void intel_fbdev_initial_config(void *data,
> async_cookie_t cookie)
>
> void intel_fbdev_initial_config_async(struct drm_device *dev) {
> - struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
> + struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
>
> if (!ifbdev)
> return;
> @@ -568,12 +568,12 @@ static void intel_fbdev_sync(struct intel_fbdev
> *ifbdev)
>
> void intel_fbdev_unregister(struct drm_i915_private *dev_priv) {
> - struct intel_fbdev *ifbdev = dev_priv->fbdev;
> + struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
>
> if (!ifbdev)
> return;
>
> - cancel_work_sync(&dev_priv->fbdev_suspend_work);
> + cancel_work_sync(&dev_priv->display.fbdev.suspend_work);
> if (!current_is_async())
> intel_fbdev_sync(ifbdev);
>
> @@ -582,7 +582,7 @@ void intel_fbdev_unregister(struct drm_i915_private
> *dev_priv)
>
> void intel_fbdev_fini(struct drm_i915_private *dev_priv) {
> - struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->fbdev);
> + struct intel_fbdev *ifbdev =
> +fetch_and_zero(&dev_priv->display.fbdev.fbdev);
>
> if (!ifbdev)
> return;
> @@ -596,7 +596,7 @@ void intel_fbdev_fini(struct drm_i915_private
> *dev_priv)
> */
> static void intel_fbdev_hpd_set_suspend(struct drm_i915_private *i915, int
> state) {
> - struct intel_fbdev *ifbdev = i915->fbdev;
> + struct intel_fbdev *ifbdev = i915->display.fbdev.fbdev;
> bool send_hpd = false;
>
> mutex_lock(&ifbdev->hpd_lock);
> @@ -614,7 +614,7 @@ static void intel_fbdev_hpd_set_suspend(struct
> drm_i915_private *i915, int state void intel_fbdev_set_suspend(struct
> drm_device *dev, int state, bool synchronous) {
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct intel_fbdev *ifbdev = dev_priv->fbdev;
> + struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev;
> struct fb_info *info;
>
> if (!ifbdev || !ifbdev->vma)
> @@ -631,7 +631,7 @@ void intel_fbdev_set_suspend(struct drm_device
> *dev, int state, bool synchronous
> * ourselves, so only flush outstanding work upon suspend!
> */
> if (state != FBINFO_STATE_RUNNING)
> - flush_work(&dev_priv->fbdev_suspend_work);
> + flush_work(&dev_priv-
> >display.fbdev.suspend_work);
>
> console_lock();
> } else {
> @@ -645,7 +645,7 @@ void intel_fbdev_set_suspend(struct drm_device
> *dev, int state, bool synchronous
> /* Don't block our own workqueue as this can
> * be run in parallel with other i915.ko tasks.
> */
> - schedule_work(&dev_priv->fbdev_suspend_work);
> + schedule_work(&dev_priv-
> >display.fbdev.suspend_work);
> return;
> }
> }
> @@ -666,7 +666,7 @@ void intel_fbdev_set_suspend(struct drm_device
> *dev, int state, bool synchronous
>
> void intel_fbdev_output_poll_changed(struct drm_device *dev) {
> - struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
> + struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
> bool send_hpd;
>
> if (!ifbdev)
> @@ -685,7 +685,7 @@ void intel_fbdev_output_poll_changed(struct
> drm_device *dev)
>
> void intel_fbdev_restore_mode(struct drm_device *dev) {
> - struct intel_fbdev *ifbdev = to_i915(dev)->fbdev;
> + struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev;
>
> if (!ifbdev)
> return;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 482a8c0d5a10..f1e47090c01e
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -82,7 +82,6 @@ struct intel_cdclk_vals; struct intel_connector; struct
> intel_dp; struct intel_encoder; -struct intel_fbdev; struct intel_limit; struct
> intel_overlay; struct intel_overlay_error_state; @@ -474,10 +473,6 @@
> struct drm_i915_private {
>
> struct i915_gpu_error gpu_error;
>
> - /* list of fbdev register on this device */
> - struct intel_fbdev *fbdev;
> - struct work_struct fbdev_suspend_work;
> -
> struct drm_property *broadcast_rgb_property;
> struct drm_property *force_audio_property;
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (13 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 14/39] drm/i915: move and group fbdev under display.fbdev Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-22 4:00 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp Jani Nikula
` (29 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
It's a bit arbitrary when to define a named struct for grouping, but
clearly intel_wm is big enough to warrant a separate definition.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 38 ++++
.../drm/i915/display/intel_display_debugfs.c | 24 +--
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 37 ----
drivers/gpu/drm/i915/intel_pm.c | 166 +++++++++---------
5 files changed, 134 insertions(+), 133 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 71434a922695..c2a79e487ee9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -15,6 +15,7 @@
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_gmbus.h"
+#include "intel_pm_types.h"
struct drm_i915_private;
struct i915_audio_component;
@@ -100,6 +101,42 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_wm {
+ /*
+ * Raw watermark latency values:
+ * in 0.1us units for WM0,
+ * in 0.5us units for WM1+.
+ */
+ /* primary */
+ u16 pri_latency[5];
+ /* sprite */
+ u16 spr_latency[5];
+ /* cursor */
+ u16 cur_latency[5];
+ /*
+ * Raw watermark memory latency values
+ * for SKL for all 8 levels
+ * in 1us units.
+ */
+ u16 skl_latency[8];
+
+ /* current hardware state */
+ union {
+ struct ilk_wm_values hw;
+ struct vlv_wm_values vlv;
+ struct g4x_wm_values g4x;
+ };
+
+ u8 max_level;
+
+ /*
+ * Should be held around atomic WM register writing; also
+ * protects * intel_crtc->wm.active and
+ * crtc_state->wm.need_postvbl_update.
+ */
+ struct mutex wm_mutex;
+};
+
struct intel_display {
/* Display functions */
struct {
@@ -167,6 +204,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_wm wm;
};
#endif /* __INTEL_DISPLAY_CORE_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index e568590faa82..395facf6c1aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1428,9 +1428,9 @@ static int pri_wm_latency_show(struct seq_file *m, void *data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.pri_latency;
+ latencies = dev_priv->display.wm.pri_latency;
wm_latency_show(m, latencies);
@@ -1443,9 +1443,9 @@ static int spr_wm_latency_show(struct seq_file *m, void *data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.spr_latency;
+ latencies = dev_priv->display.wm.spr_latency;
wm_latency_show(m, latencies);
@@ -1458,9 +1458,9 @@ static int cur_wm_latency_show(struct seq_file *m, void *data)
const u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.cur_latency;
+ latencies = dev_priv->display.wm.cur_latency;
wm_latency_show(m, latencies);
@@ -1551,9 +1551,9 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.pri_latency;
+ latencies = dev_priv->display.wm.pri_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -1566,9 +1566,9 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.spr_latency;
+ latencies = dev_priv->display.wm.spr_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
@@ -1581,9 +1581,9 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
u16 *latencies;
if (DISPLAY_VER(dev_priv) >= 9)
- latencies = dev_priv->wm.skl_latency;
+ latencies = dev_priv->display.wm.skl_latency;
else
- latencies = dev_priv->wm.cur_latency;
+ latencies = dev_priv->display.wm.cur_latency;
return wm_latency_write(file, ubuf, len, offp, latencies);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 0d3993e51138..f6841c1e5f0f 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -336,7 +336,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
mutex_init(&dev_priv->display.audio.mutex);
- mutex_init(&dev_priv->wm.wm_mutex);
+ mutex_init(&dev_priv->display.wm.wm_mutex);
mutex_init(&dev_priv->display.pps.mutex);
mutex_init(&dev_priv->hdcp_comp_mutex);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1e47090c01e..9ee08e80f0aa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -68,7 +68,6 @@
#include "intel_device_info.h"
#include "intel_memory_region.h"
#include "intel_pch.h"
-#include "intel_pm_types.h"
#include "intel_runtime_pm.h"
#include "intel_step.h"
#include "intel_uncore.h"
@@ -501,42 +500,6 @@ struct drm_i915_private {
u32 sagv_block_time_us;
- struct {
- /*
- * Raw watermark latency values:
- * in 0.1us units for WM0,
- * in 0.5us units for WM1+.
- */
- /* primary */
- u16 pri_latency[5];
- /* sprite */
- u16 spr_latency[5];
- /* cursor */
- u16 cur_latency[5];
- /*
- * Raw watermark memory latency values
- * for SKL for all 8 levels
- * in 1us units.
- */
- u16 skl_latency[8];
-
- /* current hardware state */
- union {
- struct ilk_wm_values hw;
- struct vlv_wm_values vlv;
- struct g4x_wm_values g4x;
- };
-
- u8 max_level;
-
- /*
- * Should be held around atomic WM register writing; also
- * protects * intel_crtc->wm.active and
- * crtc_state->wm.need_postvbl_update.
- */
- struct mutex wm_mutex;
- } wm;
-
struct dram_info {
bool wm_lv_0_adjust_needed;
u8 num_channels;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5febe91e44a0..14134e57034e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -468,13 +468,13 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
{
bool ret;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
ret = _intel_set_memory_cxsr(dev_priv, enable);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->wm.vlv.cxsr = enable;
+ dev_priv->display.wm.vlv.cxsr = enable;
else if (IS_G4X(dev_priv))
- dev_priv->wm.g4x.cxsr = enable;
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ dev_priv->display.wm.g4x.cxsr = enable;
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
return ret;
}
@@ -834,7 +834,7 @@ static bool is_enabling(int old, int new, int threshold)
static int intel_wm_num_levels(struct drm_i915_private *dev_priv)
{
- return dev_priv->wm.max_level + 1;
+ return dev_priv->display.wm.max_level + 1;
}
static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
@@ -1093,11 +1093,11 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv,
static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv)
{
/* all latencies in usec */
- dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
- dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
- dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
+ dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
+ dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
+ dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
- dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
+ dev_priv->display.wm.max_level = G4X_WM_LEVEL_HPLL;
}
static int g4x_plane_fifo_size(enum plane_id plane_id, int level)
@@ -1150,7 +1150,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_display_mode *pipe_mode =
&crtc_state->hw.pipe_mode;
- unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
+ unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;
unsigned int pixel_rate, htotal, cpp, width, wm;
if (latency == 0)
@@ -1324,7 +1324,7 @@ static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state,
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (level > dev_priv->wm.max_level)
+ if (level > dev_priv->display.wm.max_level)
return false;
return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) &&
@@ -1583,7 +1583,7 @@ static void g4x_merge_wm(struct drm_i915_private *dev_priv,
static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
+ struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;
struct g4x_wm_values new_wm = {};
g4x_merge_wm(dev_priv, &new_wm);
@@ -1609,10 +1609,10 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
g4x_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
@@ -1625,10 +1625,10 @@ static void g4x_optimize_watermarks(struct intel_atomic_state *state,
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
g4x_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
/* latency must be in 0.1us units. */
@@ -1650,15 +1650,15 @@ static unsigned int vlv_wm_method2(unsigned int pixel_rate,
static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
{
/* all latencies in usec */
- dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
+ dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
- dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
+ dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM2;
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
- dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
+ dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
+ dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
- dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
+ dev_priv->display.wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
}
}
@@ -1672,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
&crtc_state->hw.pipe_mode;
unsigned int pixel_rate, htotal, cpp, width, wm;
- if (dev_priv->wm.pri_latency[level] == 0)
+ if (dev_priv->display.wm.pri_latency[level] == 0)
return USHRT_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
@@ -1693,7 +1693,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
wm = 63;
} else {
wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
- dev_priv->wm.pri_latency[level] * 10);
+ dev_priv->display.wm.pri_latency[level] * 10);
}
return min_t(unsigned int, wm, USHRT_MAX);
@@ -2158,7 +2158,7 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
struct intel_crtc *crtc;
int num_active_pipes = 0;
- wm->level = dev_priv->wm.max_level;
+ wm->level = dev_priv->display.wm.max_level;
wm->cxsr = true;
for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -2197,7 +2197,7 @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
+ struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv;
struct vlv_wm_values new_wm = {};
vlv_merge_wm(dev_priv, &new_wm);
@@ -2235,10 +2235,10 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
vlv_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
@@ -2251,10 +2251,10 @@ static void vlv_optimize_watermarks(struct intel_atomic_state *state,
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
vlv_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
static void i965_update_wm(struct drm_i915_private *dev_priv)
@@ -2835,9 +2835,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_plane_state *curstate,
struct intel_wm_level *result)
{
- u16 pri_latency = dev_priv->wm.pri_latency[level];
- u16 spr_latency = dev_priv->wm.spr_latency[level];
- u16 cur_latency = dev_priv->wm.cur_latency[level];
+ u16 pri_latency = dev_priv->display.wm.pri_latency[level];
+ u16 spr_latency = dev_priv->display.wm.spr_latency[level];
+ u16 cur_latency = dev_priv->display.wm.cur_latency[level];
/* WM1+ latency values stored in 0.5us units */
if (level > 0) {
@@ -3061,18 +3061,18 @@ static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
* The BIOS provided WM memory latency values are often
* inadequate for high resolution displays. Adjust them.
*/
- changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12);
- changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12);
- changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
+ changed = ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.pri_latency, 12);
+ changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.spr_latency, 12);
+ changed |= ilk_increase_wm_latency(dev_priv, dev_priv->display.wm.cur_latency, 12);
if (!changed)
return;
drm_dbg_kms(&dev_priv->drm,
"WM latency values increased to avoid potential underruns\n");
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
}
static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
@@ -3088,37 +3088,37 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
* interrupts only. To play it safe we disable LP3
* watermarks entirely.
*/
- if (dev_priv->wm.pri_latency[3] == 0 &&
- dev_priv->wm.spr_latency[3] == 0 &&
- dev_priv->wm.cur_latency[3] == 0)
+ if (dev_priv->display.wm.pri_latency[3] == 0 &&
+ dev_priv->display.wm.spr_latency[3] == 0 &&
+ dev_priv->display.wm.cur_latency[3] == 0)
return;
- dev_priv->wm.pri_latency[3] = 0;
- dev_priv->wm.spr_latency[3] = 0;
- dev_priv->wm.cur_latency[3] = 0;
+ dev_priv->display.wm.pri_latency[3] = 0;
+ dev_priv->display.wm.spr_latency[3] = 0;
+ dev_priv->display.wm.cur_latency[3] = 0;
drm_dbg_kms(&dev_priv->drm,
"LP3 watermarks disabled due to potential for lost interrupts\n");
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
}
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
- intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
+ intel_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
- memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
- sizeof(dev_priv->wm.pri_latency));
- memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
- sizeof(dev_priv->wm.pri_latency));
+ memcpy(dev_priv->display.wm.spr_latency, dev_priv->display.wm.pri_latency,
+ sizeof(dev_priv->display.wm.pri_latency));
+ memcpy(dev_priv->display.wm.cur_latency, dev_priv->display.wm.pri_latency,
+ sizeof(dev_priv->display.wm.pri_latency));
- intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
- intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
+ intel_fixup_spr_wm_latency(dev_priv, dev_priv->display.wm.spr_latency);
+ intel_fixup_cur_wm_latency(dev_priv, dev_priv->display.wm.cur_latency);
- intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
- intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
- intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
+ intel_print_wm_latency(dev_priv, "Primary", dev_priv->display.wm.pri_latency);
+ intel_print_wm_latency(dev_priv, "Sprite", dev_priv->display.wm.spr_latency);
+ intel_print_wm_latency(dev_priv, "Cursor", dev_priv->display.wm.cur_latency);
if (DISPLAY_VER(dev_priv) == 6) {
snb_wm_latency_quirk(dev_priv);
@@ -3128,8 +3128,8 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
{
- intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
- intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
+ intel_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
+ intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->display.wm.skl_latency);
}
static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
@@ -3386,7 +3386,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
return 2 * level;
else
- return dev_priv->wm.pri_latency[level];
+ return dev_priv->display.wm.pri_latency[level];
}
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
@@ -3538,7 +3538,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
unsigned int dirty)
{
- struct ilk_wm_values *previous = &dev_priv->wm.hw;
+ struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
bool changed = false;
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
@@ -3572,7 +3572,7 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
struct ilk_wm_values *results)
{
- struct ilk_wm_values *previous = &dev_priv->wm.hw;
+ struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
unsigned int dirty;
u32 val;
@@ -3634,7 +3634,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK, results->wm_lp[2]);
- dev_priv->wm.hw = *results;
+ dev_priv->display.wm.hw = *results;
}
bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
@@ -4321,7 +4321,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
drm_WARN_ON(&dev_priv->drm, ret);
for (level = 0; level <= max_level; level++) {
- unsigned int latency = dev_priv->wm.skl_latency[level];
+ unsigned int latency = dev_priv->display.wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm);
if (wm.min_ddb_alloc == U16_MAX)
@@ -5576,7 +5576,7 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
for (level = 0; level <= max_level; level++) {
struct skl_wm_level *result = &levels[level];
- unsigned int latency = dev_priv->wm.skl_latency[level];
+ unsigned int latency = dev_priv->display.wm.skl_latency[level];
skl_compute_plane_wm(crtc_state, plane, level, latency,
wm_params, result_prev, result);
@@ -5596,7 +5596,7 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
unsigned int latency = 0;
if (dev_priv->sagv_block_time_us)
- latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];
+ latency = dev_priv->sagv_block_time_us + dev_priv->display.wm.skl_latency[0];
skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0],
@@ -6458,10 +6458,10 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
ilk_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
@@ -6474,10 +6474,10 @@ static void ilk_optimize_watermarks(struct intel_atomic_state *state,
if (!crtc_state->wm.need_postvbl_update)
return;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
ilk_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
@@ -6677,7 +6677,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
{
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- struct ilk_wm_values *hw = &dev_priv->wm.hw;
+ struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
@@ -6825,7 +6825,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct g4x_wm_values *wm = &dev_priv->wm.g4x;
+ struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
struct intel_crtc *crtc;
g4x_read_wm_values(dev_priv, wm);
@@ -6919,7 +6919,7 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
struct intel_plane *plane;
struct intel_crtc *crtc;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
for_each_intel_plane(&dev_priv->drm, plane) {
struct intel_crtc *crtc =
@@ -6967,12 +6967,12 @@ void g4x_wm_sanitize(struct drm_i915_private *dev_priv)
g4x_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct vlv_wm_values *wm = &dev_priv->wm.vlv;
+ struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
struct intel_crtc *crtc;
u32 val;
@@ -7006,7 +7006,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm,
"Punit not acking DDR DVFS request, "
"assuming DDR DVFS is disabled\n");
- dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
+ dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM5;
} else {
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
if ((val & FORCE_DDR_HIGH_FREQ) == 0)
@@ -7075,7 +7075,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
struct intel_plane *plane;
struct intel_crtc *crtc;
- mutex_lock(&dev_priv->wm.wm_mutex);
+ mutex_lock(&dev_priv->display.wm.wm_mutex);
for_each_intel_plane(&dev_priv->drm, plane) {
struct intel_crtc *crtc =
@@ -7116,7 +7116,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
vlv_program_watermarks(dev_priv);
- mutex_unlock(&dev_priv->wm.wm_mutex);
+ mutex_unlock(&dev_priv->display.wm.wm_mutex);
}
/*
@@ -7137,7 +7137,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct ilk_wm_values *hw = &dev_priv->wm.hw;
+ struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
struct intel_crtc *crtc;
ilk_init_lp_watermarks(dev_priv);
@@ -8231,10 +8231,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
} else if (HAS_PCH_SPLIT(dev_priv)) {
ilk_setup_wm_latency(dev_priv);
- if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->wm.pri_latency[1] &&
- dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
- (DISPLAY_VER(dev_priv) != 5 && dev_priv->wm.pri_latency[0] &&
- dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
+ if ((DISPLAY_VER(dev_priv) == 5 && dev_priv->display.wm.pri_latency[1] &&
+ dev_priv->display.wm.spr_latency[1] && dev_priv->display.wm.cur_latency[1]) ||
+ (DISPLAY_VER(dev_priv) != 5 && dev_priv->display.wm.pri_latency[0] &&
+ dev_priv->display.wm.spr_latency[0] && dev_priv->display.wm.cur_latency[0])) {
dev_priv->display.funcs.wm = &ilk_wm_funcs;
} else {
drm_dbg_kms(&dev_priv->drm,
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm
2022-08-11 15:07 ` [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm Jani Nikula
@ 2022-08-22 4:00 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-22 4:00 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm
>
> Move display related members under drm_i915_private display sub-struct.
>
> It's a bit arbitrary when to define a named struct for grouping, but clearly
> intel_wm is big enough to warrant a separate definition.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards
Arun R Murthy
--------------------
> ---
> .../gpu/drm/i915/display/intel_display_core.h | 38 ++++
> .../drm/i915/display/intel_display_debugfs.c | 24 +--
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 37 ----
> drivers/gpu/drm/i915/intel_pm.c | 166 +++++++++---------
> 5 files changed, 134 insertions(+), 133 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 71434a922695..c2a79e487ee9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -15,6 +15,7 @@
> #include "intel_dmc.h"
> #include "intel_dpll_mgr.h"
> #include "intel_gmbus.h"
> +#include "intel_pm_types.h"
>
> struct drm_i915_private;
> struct i915_audio_component;
> @@ -100,6 +101,42 @@ struct intel_dpll {
> } ref_clks;
> };
>
> +struct intel_wm {
> + /*
> + * Raw watermark latency values:
> + * in 0.1us units for WM0,
> + * in 0.5us units for WM1+.
> + */
> + /* primary */
> + u16 pri_latency[5];
> + /* sprite */
> + u16 spr_latency[5];
> + /* cursor */
> + u16 cur_latency[5];
> + /*
> + * Raw watermark memory latency values
> + * for SKL for all 8 levels
> + * in 1us units.
> + */
> + u16 skl_latency[8];
> +
> + /* current hardware state */
> + union {
> + struct ilk_wm_values hw;
> + struct vlv_wm_values vlv;
> + struct g4x_wm_values g4x;
> + };
> +
> + u8 max_level;
> +
> + /*
> + * Should be held around atomic WM register writing; also
> + * protects * intel_crtc->wm.active and
> + * crtc_state->wm.need_postvbl_update.
> + */
> + struct mutex wm_mutex;
> +};
> +
> struct intel_display {
> /* Display functions */
> struct {
> @@ -167,6 +204,7 @@ struct intel_display {
> struct intel_audio audio;
> struct intel_dmc dmc;
> struct intel_dpll dpll;
> + struct intel_wm wm;
> };
>
> #endif /* __INTEL_DISPLAY_CORE_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index e568590faa82..395facf6c1aa 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1428,9 +1428,9 @@ static int pri_wm_latency_show(struct seq_file *m,
> void *data)
> const u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.pri_latency;
> + latencies = dev_priv->display.wm.pri_latency;
>
> wm_latency_show(m, latencies);
>
> @@ -1443,9 +1443,9 @@ static int spr_wm_latency_show(struct seq_file
> *m, void *data)
> const u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.spr_latency;
> + latencies = dev_priv->display.wm.spr_latency;
>
> wm_latency_show(m, latencies);
>
> @@ -1458,9 +1458,9 @@ static int cur_wm_latency_show(struct seq_file
> *m, void *data)
> const u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.cur_latency;
> + latencies = dev_priv->display.wm.cur_latency;
>
> wm_latency_show(m, latencies);
>
> @@ -1551,9 +1551,9 @@ static ssize_t pri_wm_latency_write(struct file *file,
> const char __user *ubuf,
> u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.pri_latency;
> + latencies = dev_priv->display.wm.pri_latency;
>
> return wm_latency_write(file, ubuf, len, offp, latencies); } @@ -
> 1566,9 +1566,9 @@ static ssize_t spr_wm_latency_write(struct file *file,
> const char __user *ubuf,
> u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.spr_latency;
> + latencies = dev_priv->display.wm.spr_latency;
>
> return wm_latency_write(file, ubuf, len, offp, latencies); } @@ -
> 1581,9 +1581,9 @@ static ssize_t cur_wm_latency_write(struct file *file,
> const char __user *ubuf,
> u16 *latencies;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - latencies = dev_priv->wm.skl_latency;
> + latencies = dev_priv->display.wm.skl_latency;
> else
> - latencies = dev_priv->wm.cur_latency;
> + latencies = dev_priv->display.wm.cur_latency;
>
> return wm_latency_write(file, ubuf, len, offp, latencies); } diff --git
> a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
> index 0d3993e51138..f6841c1e5f0f 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -336,7 +336,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> cpu_latency_qos_add_request(&dev_priv->sb_qos,
> PM_QOS_DEFAULT_VALUE);
>
> mutex_init(&dev_priv->display.audio.mutex);
> - mutex_init(&dev_priv->wm.wm_mutex);
> + mutex_init(&dev_priv->display.wm.wm_mutex);
> mutex_init(&dev_priv->display.pps.mutex);
> mutex_init(&dev_priv->hdcp_comp_mutex);
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index f1e47090c01e..9ee08e80f0aa
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -68,7 +68,6 @@
> #include "intel_device_info.h"
> #include "intel_memory_region.h"
> #include "intel_pch.h"
> -#include "intel_pm_types.h"
> #include "intel_runtime_pm.h"
> #include "intel_step.h"
> #include "intel_uncore.h"
> @@ -501,42 +500,6 @@ struct drm_i915_private {
>
> u32 sagv_block_time_us;
>
> - struct {
> - /*
> - * Raw watermark latency values:
> - * in 0.1us units for WM0,
> - * in 0.5us units for WM1+.
> - */
> - /* primary */
> - u16 pri_latency[5];
> - /* sprite */
> - u16 spr_latency[5];
> - /* cursor */
> - u16 cur_latency[5];
> - /*
> - * Raw watermark memory latency values
> - * for SKL for all 8 levels
> - * in 1us units.
> - */
> - u16 skl_latency[8];
> -
> - /* current hardware state */
> - union {
> - struct ilk_wm_values hw;
> - struct vlv_wm_values vlv;
> - struct g4x_wm_values g4x;
> - };
> -
> - u8 max_level;
> -
> - /*
> - * Should be held around atomic WM register writing; also
> - * protects * intel_crtc->wm.active and
> - * crtc_state->wm.need_postvbl_update.
> - */
> - struct mutex wm_mutex;
> - } wm;
> -
> struct dram_info {
> bool wm_lv_0_adjust_needed;
> u8 num_channels;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c
> b/drivers/gpu/drm/i915/intel_pm.c index 5febe91e44a0..14134e57034e
> 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -468,13 +468,13 @@ bool intel_set_memory_cxsr(struct
> drm_i915_private *dev_priv, bool enable) {
> bool ret;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> ret = _intel_set_memory_cxsr(dev_priv, enable);
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - dev_priv->wm.vlv.cxsr = enable;
> + dev_priv->display.wm.vlv.cxsr = enable;
> else if (IS_G4X(dev_priv))
> - dev_priv->wm.g4x.cxsr = enable;
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + dev_priv->display.wm.g4x.cxsr = enable;
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
>
> return ret;
> }
> @@ -834,7 +834,7 @@ static bool is_enabling(int old, int new, int threshold)
>
> static int intel_wm_num_levels(struct drm_i915_private *dev_priv) {
> - return dev_priv->wm.max_level + 1;
> + return dev_priv->display.wm.max_level + 1;
> }
>
> static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,
> @@ -1093,11 +1093,11 @@ static void vlv_write_wm_values(struct
> drm_i915_private *dev_priv, static void g4x_setup_wm_latency(struct
> drm_i915_private *dev_priv) {
> /* all latencies in usec */
> - dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
> - dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
> - dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
> + dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
> + dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
> + dev_priv->display.wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
>
> - dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
> + dev_priv->display.wm.max_level = G4X_WM_LEVEL_HPLL;
> }
>
> static int g4x_plane_fifo_size(enum plane_id plane_id, int level) @@ -1150,7
> +1150,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state
> *crtc_state,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_display_mode *pipe_mode =
> &crtc_state->hw.pipe_mode;
> - unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> + unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10;
> unsigned int pixel_rate, htotal, cpp, width, wm;
>
> if (latency == 0)
> @@ -1324,7 +1324,7 @@ static bool g4x_raw_crtc_wm_is_valid(const struct
> intel_crtc_state *crtc_state, {
> struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc-
> >dev);
>
> - if (level > dev_priv->wm.max_level)
> + if (level > dev_priv->display.wm.max_level)
> return false;
>
> return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY,
> level) && @@ -1583,7 +1583,7 @@ static void g4x_merge_wm(struct
> drm_i915_private *dev_priv,
>
> static void g4x_program_watermarks(struct drm_i915_private *dev_priv) {
> - struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
> + struct g4x_wm_values *old_wm = &dev_priv->display.wm.g4x;
> struct g4x_wm_values new_wm = {};
>
> g4x_merge_wm(dev_priv, &new_wm);
> @@ -1609,10 +1609,10 @@ static void g4x_initial_watermarks(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
> g4x_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> static void g4x_optimize_watermarks(struct intel_atomic_state *state, @@ -
> 1625,10 +1625,10 @@ static void g4x_optimize_watermarks(struct
> intel_atomic_state *state,
> if (!crtc_state->wm.need_postvbl_update)
> return;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
> g4x_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> /* latency must be in 0.1us units. */
> @@ -1650,15 +1650,15 @@ static unsigned int vlv_wm_method2(unsigned
> int pixel_rate, static void vlv_setup_wm_latency(struct drm_i915_private
> *dev_priv) {
> /* all latencies in usec */
> - dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
> + dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
>
> - dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
> + dev_priv->display.wm.max_level = VLV_WM_LEVEL_PM2;
>
> if (IS_CHERRYVIEW(dev_priv)) {
> - dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
> - dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
> + dev_priv->display.wm.pri_latency[VLV_WM_LEVEL_PM5] =
> 12;
> + dev_priv-
> >display.wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
>
> - dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
> + dev_priv->display.wm.max_level =
> VLV_WM_LEVEL_DDR_DVFS;
> }
> }
>
> @@ -1672,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct
> intel_crtc_state *crtc_state,
> &crtc_state->hw.pipe_mode;
> unsigned int pixel_rate, htotal, cpp, width, wm;
>
> - if (dev_priv->wm.pri_latency[level] == 0)
> + if (dev_priv->display.wm.pri_latency[level] == 0)
> return USHRT_MAX;
>
> if (!intel_wm_plane_visible(crtc_state, plane_state)) @@ -1693,7
> +1693,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state
> *crtc_state,
> wm = 63;
> } else {
> wm = vlv_wm_method2(pixel_rate, htotal, width, cpp,
> - dev_priv->wm.pri_latency[level] * 10);
> + dev_priv->display.wm.pri_latency[level] *
> 10);
> }
>
> return min_t(unsigned int, wm, USHRT_MAX); @@ -2158,7 +2158,7
> @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
> struct intel_crtc *crtc;
> int num_active_pipes = 0;
>
> - wm->level = dev_priv->wm.max_level;
> + wm->level = dev_priv->display.wm.max_level;
> wm->cxsr = true;
>
> for_each_intel_crtc(&dev_priv->drm, crtc) { @@ -2197,7 +2197,7
> @@ static void vlv_merge_wm(struct drm_i915_private *dev_priv,
>
> static void vlv_program_watermarks(struct drm_i915_private *dev_priv) {
> - struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
> + struct vlv_wm_values *old_wm = &dev_priv->display.wm.vlv;
> struct vlv_wm_values new_wm = {};
>
> vlv_merge_wm(dev_priv, &new_wm);
> @@ -2235,10 +2235,10 @@ static void vlv_initial_watermarks(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
> vlv_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> static void vlv_optimize_watermarks(struct intel_atomic_state *state, @@ -
> 2251,10 +2251,10 @@ static void vlv_optimize_watermarks(struct
> intel_atomic_state *state,
> if (!crtc_state->wm.need_postvbl_update)
> return;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
> vlv_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> static void i965_update_wm(struct drm_i915_private *dev_priv) @@ -
> 2835,9 +2835,9 @@ static void ilk_compute_wm_level(const struct
> drm_i915_private *dev_priv,
> const struct intel_plane_state *curstate,
> struct intel_wm_level *result)
> {
> - u16 pri_latency = dev_priv->wm.pri_latency[level];
> - u16 spr_latency = dev_priv->wm.spr_latency[level];
> - u16 cur_latency = dev_priv->wm.cur_latency[level];
> + u16 pri_latency = dev_priv->display.wm.pri_latency[level];
> + u16 spr_latency = dev_priv->display.wm.spr_latency[level];
> + u16 cur_latency = dev_priv->display.wm.cur_latency[level];
>
> /* WM1+ latency values stored in 0.5us units */
> if (level > 0) {
> @@ -3061,18 +3061,18 @@ static void snb_wm_latency_quirk(struct
> drm_i915_private *dev_priv)
> * The BIOS provided WM memory latency values are often
> * inadequate for high resolution displays. Adjust them.
> */
> - changed = ilk_increase_wm_latency(dev_priv, dev_priv-
> >wm.pri_latency, 12);
> - changed |= ilk_increase_wm_latency(dev_priv, dev_priv-
> >wm.spr_latency, 12);
> - changed |= ilk_increase_wm_latency(dev_priv, dev_priv-
> >wm.cur_latency, 12);
> + changed = ilk_increase_wm_latency(dev_priv, dev_priv-
> >display.wm.pri_latency, 12);
> + changed |= ilk_increase_wm_latency(dev_priv, dev_priv-
> >display.wm.spr_latency, 12);
> + changed |= ilk_increase_wm_latency(dev_priv,
> +dev_priv->display.wm.cur_latency, 12);
>
> if (!changed)
> return;
>
> drm_dbg_kms(&dev_priv->drm,
> "WM latency values increased to avoid potential
> underruns\n");
> - intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >wm.pri_latency);
> - intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >wm.spr_latency);
> - intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
> >wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >display.wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >display.wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor",
> +dev_priv->display.wm.cur_latency);
> }
>
> static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv) @@ -
> 3088,37 +3088,37 @@ static void snb_wm_lp3_irq_quirk(struct
> drm_i915_private *dev_priv)
> * interrupts only. To play it safe we disable LP3
> * watermarks entirely.
> */
> - if (dev_priv->wm.pri_latency[3] == 0 &&
> - dev_priv->wm.spr_latency[3] == 0 &&
> - dev_priv->wm.cur_latency[3] == 0)
> + if (dev_priv->display.wm.pri_latency[3] == 0 &&
> + dev_priv->display.wm.spr_latency[3] == 0 &&
> + dev_priv->display.wm.cur_latency[3] == 0)
> return;
>
> - dev_priv->wm.pri_latency[3] = 0;
> - dev_priv->wm.spr_latency[3] = 0;
> - dev_priv->wm.cur_latency[3] = 0;
> + dev_priv->display.wm.pri_latency[3] = 0;
> + dev_priv->display.wm.spr_latency[3] = 0;
> + dev_priv->display.wm.cur_latency[3] = 0;
>
> drm_dbg_kms(&dev_priv->drm,
> "LP3 watermarks disabled due to potential for lost
> interrupts\n");
> - intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >wm.pri_latency);
> - intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >wm.spr_latency);
> - intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
> >wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >display.wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >display.wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor",
> +dev_priv->display.wm.cur_latency);
> }
>
> static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) {
> - intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
> + intel_read_wm_latency(dev_priv, dev_priv->display.wm.pri_latency);
>
> - memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
> - sizeof(dev_priv->wm.pri_latency));
> - memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
> - sizeof(dev_priv->wm.pri_latency));
> + memcpy(dev_priv->display.wm.spr_latency, dev_priv-
> >display.wm.pri_latency,
> + sizeof(dev_priv->display.wm.pri_latency));
> + memcpy(dev_priv->display.wm.cur_latency, dev_priv-
> >display.wm.pri_latency,
> + sizeof(dev_priv->display.wm.pri_latency));
>
> - intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
> - intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
> + intel_fixup_spr_wm_latency(dev_priv, dev_priv-
> >display.wm.spr_latency);
> + intel_fixup_cur_wm_latency(dev_priv,
> +dev_priv->display.wm.cur_latency);
>
> - intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >wm.pri_latency);
> - intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >wm.spr_latency);
> - intel_print_wm_latency(dev_priv, "Cursor", dev_priv-
> >wm.cur_latency);
> + intel_print_wm_latency(dev_priv, "Primary", dev_priv-
> >display.wm.pri_latency);
> + intel_print_wm_latency(dev_priv, "Sprite", dev_priv-
> >display.wm.spr_latency);
> + intel_print_wm_latency(dev_priv, "Cursor",
> +dev_priv->display.wm.cur_latency);
>
> if (DISPLAY_VER(dev_priv) == 6) {
> snb_wm_latency_quirk(dev_priv);
> @@ -3128,8 +3128,8 @@ static void ilk_setup_wm_latency(struct
> drm_i915_private *dev_priv)
>
> static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) {
> - intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
> - intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv-
> >wm.skl_latency);
> + intel_read_wm_latency(dev_priv, dev_priv->display.wm.skl_latency);
> + intel_print_wm_latency(dev_priv, "Gen9 Plane",
> +dev_priv->display.wm.skl_latency);
> }
>
> static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
> @@ -3386,7 +3386,7 @@ static unsigned int ilk_wm_lp_latency(struct
> drm_i915_private *dev_priv,
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> return 2 * level;
> else
> - return dev_priv->wm.pri_latency[level];
> + return dev_priv->display.wm.pri_latency[level];
> }
>
> static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, @@
> -3538,7 +3538,7 @@ static unsigned int ilk_compute_wm_dirty(struct
> drm_i915_private *dev_priv, static bool _ilk_disable_lp_wm(struct
> drm_i915_private *dev_priv,
> unsigned int dirty)
> {
> - struct ilk_wm_values *previous = &dev_priv->wm.hw;
> + struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
> bool changed = false;
>
> if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] &
> WM_LP_ENABLE) { @@ -3572,7 +3572,7 @@ static bool
> _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, static void
> ilk_write_wm_values(struct drm_i915_private *dev_priv,
> struct ilk_wm_values *results)
> {
> - struct ilk_wm_values *previous = &dev_priv->wm.hw;
> + struct ilk_wm_values *previous = &dev_priv->display.wm.hw;
> unsigned int dirty;
> u32 val;
>
> @@ -3634,7 +3634,7 @@ static void ilk_write_wm_values(struct
> drm_i915_private *dev_priv,
> if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results-
> >wm_lp[2])
> intel_uncore_write(&dev_priv->uncore, WM3_LP_ILK,
> results->wm_lp[2]);
>
> - dev_priv->wm.hw = *results;
> + dev_priv->display.wm.hw = *results;
> }
>
> bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) @@ -4321,7
> +4321,7 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
> drm_WARN_ON(&dev_priv->drm, ret);
>
> for (level = 0; level <= max_level; level++) {
> - unsigned int latency = dev_priv->wm.skl_latency[level];
> + unsigned int latency = dev_priv-
> >display.wm.skl_latency[level];
>
> skl_compute_plane_wm(crtc_state, plane, level, latency,
> &wp, &wm, &wm);
> if (wm.min_ddb_alloc == U16_MAX)
> @@ -5576,7 +5576,7 @@ skl_compute_wm_levels(const struct
> intel_crtc_state *crtc_state,
>
> for (level = 0; level <= max_level; level++) {
> struct skl_wm_level *result = &levels[level];
> - unsigned int latency = dev_priv->wm.skl_latency[level];
> + unsigned int latency = dev_priv-
> >display.wm.skl_latency[level];
>
> skl_compute_plane_wm(crtc_state, plane, level, latency,
> wm_params, result_prev, result); @@ -
> 5596,7 +5596,7 @@ static void tgl_compute_sagv_wm(const struct
> intel_crtc_state *crtc_state,
> unsigned int latency = 0;
>
> if (dev_priv->sagv_block_time_us)
> - latency = dev_priv->sagv_block_time_us + dev_priv-
> >wm.skl_latency[0];
> + latency = dev_priv->sagv_block_time_us +
> +dev_priv->display.wm.skl_latency[0];
>
> skl_compute_plane_wm(crtc_state, plane, 0, latency,
> wm_params, &levels[0],
> @@ -6458,10 +6458,10 @@ static void ilk_initial_watermarks(struct
> intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
> ilk_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> static void ilk_optimize_watermarks(struct intel_atomic_state *state, @@ -
> 6474,10 +6474,10 @@ static void ilk_optimize_watermarks(struct
> intel_atomic_state *state,
> if (!crtc_state->wm.need_postvbl_update)
> return;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
> crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
> ilk_program_watermarks(dev_priv);
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> static void skl_wm_level_from_reg_val(u32 val, struct skl_wm_level *level)
> @@ -6677,7 +6677,7 @@ static void ilk_pipe_wm_get_hw_state(struct
> intel_crtc *crtc) {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - struct ilk_wm_values *hw = &dev_priv->wm.hw;
> + struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
> struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc-
> >base.state);
> struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
> enum pipe pipe = crtc->pipe;
> @@ -6825,7 +6825,7 @@ static void vlv_read_wm_values(struct
> drm_i915_private *dev_priv,
>
> void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv) {
> - struct g4x_wm_values *wm = &dev_priv->wm.g4x;
> + struct g4x_wm_values *wm = &dev_priv->display.wm.g4x;
> struct intel_crtc *crtc;
>
> g4x_read_wm_values(dev_priv, wm);
> @@ -6919,7 +6919,7 @@ void g4x_wm_sanitize(struct drm_i915_private
> *dev_priv)
> struct intel_plane *plane;
> struct intel_crtc *crtc;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
>
> for_each_intel_plane(&dev_priv->drm, plane) {
> struct intel_crtc *crtc =
> @@ -6967,12 +6967,12 @@ void g4x_wm_sanitize(struct drm_i915_private
> *dev_priv)
>
> g4x_program_watermarks(dev_priv);
>
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv) {
> - struct vlv_wm_values *wm = &dev_priv->wm.vlv;
> + struct vlv_wm_values *wm = &dev_priv->display.wm.vlv;
> struct intel_crtc *crtc;
> u32 val;
>
> @@ -7006,7 +7006,7 @@ void vlv_wm_get_hw_state(struct
> drm_i915_private *dev_priv)
> drm_dbg_kms(&dev_priv->drm,
> "Punit not acking DDR DVFS request, "
> "assuming DDR DVFS is disabled\n");
> - dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
> + dev_priv->display.wm.max_level =
> VLV_WM_LEVEL_PM5;
> } else {
> val = vlv_punit_read(dev_priv,
> PUNIT_REG_DDR_SETUP2);
> if ((val & FORCE_DDR_HIGH_FREQ) == 0) @@ -7075,7
> +7075,7 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
> struct intel_plane *plane;
> struct intel_crtc *crtc;
>
> - mutex_lock(&dev_priv->wm.wm_mutex);
> + mutex_lock(&dev_priv->display.wm.wm_mutex);
>
> for_each_intel_plane(&dev_priv->drm, plane) {
> struct intel_crtc *crtc =
> @@ -7116,7 +7116,7 @@ void vlv_wm_sanitize(struct drm_i915_private
> *dev_priv)
>
> vlv_program_watermarks(dev_priv);
>
> - mutex_unlock(&dev_priv->wm.wm_mutex);
> + mutex_unlock(&dev_priv->display.wm.wm_mutex);
> }
>
> /*
> @@ -7137,7 +7137,7 @@ static void ilk_init_lp_watermarks(struct
> drm_i915_private *dev_priv)
>
> void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv) {
> - struct ilk_wm_values *hw = &dev_priv->wm.hw;
> + struct ilk_wm_values *hw = &dev_priv->display.wm.hw;
> struct intel_crtc *crtc;
>
> ilk_init_lp_watermarks(dev_priv);
> @@ -8231,10 +8231,10 @@ void intel_init_pm(struct drm_i915_private
> *dev_priv)
> } else if (HAS_PCH_SPLIT(dev_priv)) {
> ilk_setup_wm_latency(dev_priv);
>
> - if ((DISPLAY_VER(dev_priv) == 5 && dev_priv-
> >wm.pri_latency[1] &&
> - dev_priv->wm.spr_latency[1] && dev_priv-
> >wm.cur_latency[1]) ||
> - (DISPLAY_VER(dev_priv) != 5 && dev_priv-
> >wm.pri_latency[0] &&
> - dev_priv->wm.spr_latency[0] && dev_priv-
> >wm.cur_latency[0])) {
> + if ((DISPLAY_VER(dev_priv) == 5 && dev_priv-
> >display.wm.pri_latency[1] &&
> + dev_priv->display.wm.spr_latency[1] && dev_priv-
> >display.wm.cur_latency[1]) ||
> + (DISPLAY_VER(dev_priv) != 5 && dev_priv-
> >display.wm.pri_latency[0] &&
> + dev_priv->display.wm.spr_latency[0] &&
> +dev_priv->display.wm.cur_latency[0])) {
> dev_priv->display.funcs.wm = &ilk_wm_funcs;
> } else {
> drm_dbg_kms(&dev_priv->drm,
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (14 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 15/39] drm/i915: move wm to display.wm Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-22 4:02 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug Jani Nikula
` (28 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 9 ++
drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++++++++---------
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 6 -
4 files changed, 77 insertions(+), 74 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index c2a79e487ee9..8ac63352b27b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -19,6 +19,7 @@
struct drm_i915_private;
struct i915_audio_component;
+struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
@@ -193,6 +194,14 @@ struct intel_display {
wait_queue_head_t wait_queue;
} gmbus;
+ struct {
+ struct i915_hdcp_comp_master *master;
+ bool comp_added;
+
+ /* Mutex to protect the above hdcp component related values. */
+ struct mutex comp_mutex;
+ } hdcp;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index c5e9e86bb4cb..6f04dd69087e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -188,12 +188,12 @@ bool intel_hdcp2_capable(struct intel_connector *connector)
return false;
/* MEI interface is solid */
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ if (!dev_priv->display.hdcp.comp_added || !dev_priv->display.hdcp.master) {
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return false;
}
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
/* Sink's capability for HDCP2.2 */
hdcp->shim->hdcp_2_2_capable(dig_port, &capable);
@@ -1124,11 +1124,11 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1136,7 +1136,7 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
if (ret)
drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1154,11 +1154,11 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1168,7 +1168,7 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1182,18 +1182,18 @@ static int hdcp2_verify_hprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify hprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1208,11 +1208,11 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1220,7 +1220,7 @@ hdcp2_store_pairing_info(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Store pairing info failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1235,11 +1235,11 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1247,7 +1247,7 @@ hdcp2_prepare_lc_init(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1262,11 +1262,11 @@ hdcp2_verify_lprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1274,7 +1274,7 @@ hdcp2_verify_lprime(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1288,11 +1288,11 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1300,7 +1300,7 @@ static int hdcp2_prepare_skey(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Get session key failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1317,11 +1317,11 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1331,7 +1331,7 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
if (ret < 0)
drm_dbg_kms(&dev_priv->drm,
"Verify rep topology failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1346,18 +1346,18 @@ hdcp2_verify_mprime(struct intel_connector *connector,
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->verify_mprime(comp->mei_dev, data, stream_ready);
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Verify mprime failed. %d\n", ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1370,11 +1370,11 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
@@ -1382,7 +1382,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -1394,17 +1394,17 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
struct i915_hdcp_comp_master *comp;
int ret;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- comp = dev_priv->hdcp_master;
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ comp = dev_priv->display.hdcp.master;
if (!comp || !comp->ops) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return -EINVAL;
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
&dig_port->hdcp_port_data);
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return ret;
}
@@ -2122,10 +2122,10 @@ static int i915_hdcp_component_bind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data;
- dev_priv->hdcp_master->mei_dev = mei_kdev;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.master = (struct i915_hdcp_comp_master *)data;
+ dev_priv->display.hdcp.master->mei_dev = mei_kdev;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return 0;
}
@@ -2136,9 +2136,9 @@ static void i915_hdcp_component_unbind(struct device *i915_kdev,
struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n");
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_master = NULL;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.master = NULL;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
}
static const struct component_ops i915_hdcp_component_ops = {
@@ -2229,19 +2229,19 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
if (!is_hdcp2_supported(dev_priv))
return;
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ drm_WARN_ON(&dev_priv->drm, dev_priv->display.hdcp.comp_added);
- dev_priv->hdcp_comp_added = true;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display.hdcp.comp_added = true;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
ret = component_add_typed(dev_priv->drm.dev, &i915_hdcp_component_ops,
I915_COMPONENT_HDCP);
if (ret < 0) {
drm_dbg_kms(&dev_priv->drm, "Failed at component add(%d)\n",
ret);
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ dev_priv->display.hdcp.comp_added = false;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return;
}
}
@@ -2454,14 +2454,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
void intel_hdcp_component_fini(struct drm_i915_private *dev_priv)
{
- mutex_lock(&dev_priv->hdcp_comp_mutex);
- if (!dev_priv->hdcp_comp_added) {
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ mutex_lock(&dev_priv->display.hdcp.comp_mutex);
+ if (!dev_priv->display.hdcp.comp_added) {
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
return;
}
- dev_priv->hdcp_comp_added = false;
- mutex_unlock(&dev_priv->hdcp_comp_mutex);
+ dev_priv->display.hdcp.comp_added = false;
+ mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
}
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f6841c1e5f0f..8841ec398b07 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -338,7 +338,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->display.audio.mutex);
mutex_init(&dev_priv->display.wm.wm_mutex);
mutex_init(&dev_priv->display.pps.mutex);
- mutex_init(&dev_priv->hdcp_comp_mutex);
+ mutex_init(&dev_priv->display.hdcp.comp_mutex);
i915_memcpy_init_early(dev_priv);
intel_runtime_pm_init_early(&dev_priv->runtime_pm);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9ee08e80f0aa..a0af8190ed87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -588,12 +588,6 @@ struct drm_i915_private {
struct i915_drm_clients clients;
- struct i915_hdcp_comp_master *hdcp_master;
- bool hdcp_comp_added;
-
- /* Mutex to protect the above hdcp component related values. */
- struct mutex hdcp_comp_mutex;
-
/* The TTM device structure. */
struct ttm_device bdev;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp
2022-08-11 15:07 ` [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp Jani Nikula
@ 2022-08-22 4:02 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-22 4:02 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under
> display.hdcp
>
> Move display related members under drm_i915_private display sub-struct.
I hope the previous comments as to update of the patch description will be taken care!
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
With the above said updates included
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> .../gpu/drm/i915/display/intel_display_core.h | 9 ++
> drivers/gpu/drm/i915/display/intel_hdcp.c | 134 +++++++++---------
> drivers/gpu/drm/i915/i915_driver.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 6 -
> 4 files changed, 77 insertions(+), 74 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index c2a79e487ee9..8ac63352b27b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -19,6 +19,7 @@
>
> struct drm_i915_private;
> struct i915_audio_component;
> +struct i915_hdcp_comp_master;
> struct intel_atomic_state;
> struct intel_audio_funcs;
> struct intel_cdclk_funcs;
> @@ -193,6 +194,14 @@ struct intel_display {
> wait_queue_head_t wait_queue;
> } gmbus;
>
> + struct {
> + struct i915_hdcp_comp_master *master;
> + bool comp_added;
> +
> + /* Mutex to protect the above hdcp component related
> values. */
> + struct mutex comp_mutex;
> + } hdcp;
> +
> struct {
> u32 mmio_base;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index c5e9e86bb4cb..6f04dd69087e 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -188,12 +188,12 @@ bool intel_hdcp2_capable(struct intel_connector
> *connector)
> return false;
>
> /* MEI interface is solid */
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - if (!dev_priv->hdcp_comp_added || !dev_priv->hdcp_master) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + if (!dev_priv->display.hdcp.comp_added || !dev_priv-
> >display.hdcp.master) {
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return false;
> }
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> /* Sink's capability for HDCP2.2 */
> hdcp->shim->hdcp_2_2_capable(dig_port, &capable); @@ -1124,11
> +1124,11 @@ hdcp2_prepare_ake_init(struct intel_connector *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1136,7 +1136,7 @@ hdcp2_prepare_ake_init(struct intel_connector
> *connector,
> if (ret)
> drm_dbg_kms(&dev_priv->drm, "Prepare_ake_init failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1154,11 +1154,11 @@ hdcp2_verify_rx_cert_prepare_km(struct
> intel_connector *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1168,7 +1168,7 @@ hdcp2_verify_rx_cert_prepare_km(struct
> intel_connector *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Verify rx_cert failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1182,18 +1182,18 @@ static int hdcp2_verify_hprime(struct
> intel_connector *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> ret = comp->ops->verify_hprime(comp->mei_dev, data, rx_hprime);
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Verify hprime failed.
> %d\n", ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1208,11 +1208,11 @@ hdcp2_store_pairing_info(struct intel_connector
> *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1220,7 +1220,7 @@ hdcp2_store_pairing_info(struct intel_connector
> *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Store pairing info failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1235,11 +1235,11 @@ hdcp2_prepare_lc_init(struct intel_connector
> *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1247,7 +1247,7 @@ hdcp2_prepare_lc_init(struct intel_connector
> *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Prepare lc_init failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1262,11 +1262,11 @@ hdcp2_verify_lprime(struct intel_connector
> *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1274,7 +1274,7 @@ hdcp2_verify_lprime(struct intel_connector
> *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Verify L_Prime failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1288,11 +1288,11 @@ static int hdcp2_prepare_skey(struct
> intel_connector *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1300,7 +1300,7 @@ static int hdcp2_prepare_skey(struct
> intel_connector *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Get session key failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1317,11 +1317,11 @@ hdcp2_verify_rep_topology_prepare_ack(struct
> intel_connector *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1331,7 +1331,7 @@ hdcp2_verify_rep_topology_prepare_ack(struct
> intel_connector *connector,
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm,
> "Verify rep topology failed. %d\n", ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1346,18 +1346,18 @@ hdcp2_verify_mprime(struct intel_connector
> *connector,
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> ret = comp->ops->verify_mprime(comp->mei_dev, data,
> stream_ready);
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Verify mprime failed.
> %d\n", ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1370,11 +1370,11 @@ static int hdcp2_authenticate_port(struct
> intel_connector *connector)
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> @@ -1382,7 +1382,7 @@ static int hdcp2_authenticate_port(struct
> intel_connector *connector)
> if (ret < 0)
> drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed.
> %d\n",
> ret);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -1394,17 +1394,17 @@ static int hdcp2_close_mei_session(struct
> intel_connector *connector)
> struct i915_hdcp_comp_master *comp;
> int ret;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - comp = dev_priv->hdcp_master;
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + comp = dev_priv->display.hdcp.master;
>
> if (!comp || !comp->ops) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return -EINVAL;
> }
>
> ret = comp->ops->close_hdcp_session(comp->mei_dev,
> &dig_port->hdcp_port_data);
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return ret;
> }
> @@ -2122,10 +2122,10 @@ static int i915_hdcp_component_bind(struct
> device *i915_kdev,
> struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
>
> drm_dbg(&dev_priv->drm, "I915 HDCP comp bind\n");
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - dev_priv->hdcp_master = (struct i915_hdcp_comp_master *)data;
> - dev_priv->hdcp_master->mei_dev = mei_kdev;
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + dev_priv->display.hdcp.master = (struct i915_hdcp_comp_master
> *)data;
> + dev_priv->display.hdcp.master->mei_dev = mei_kdev;
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> return 0;
> }
> @@ -2136,9 +2136,9 @@ static void i915_hdcp_component_unbind(struct
> device *i915_kdev,
> struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
>
> drm_dbg(&dev_priv->drm, "I915 HDCP comp unbind\n");
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - dev_priv->hdcp_master = NULL;
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + dev_priv->display.hdcp.master = NULL;
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> }
>
> static const struct component_ops i915_hdcp_component_ops = { @@ -
> 2229,19 +2229,19 @@ void intel_hdcp_component_init(struct
> drm_i915_private *dev_priv)
> if (!is_hdcp2_supported(dev_priv))
> return;
>
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - drm_WARN_ON(&dev_priv->drm, dev_priv->hdcp_comp_added);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + drm_WARN_ON(&dev_priv->drm, dev_priv-
> >display.hdcp.comp_added);
>
> - dev_priv->hdcp_comp_added = true;
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + dev_priv->display.hdcp.comp_added = true;
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> ret = component_add_typed(dev_priv->drm.dev,
> &i915_hdcp_component_ops,
> I915_COMPONENT_HDCP);
> if (ret < 0) {
> drm_dbg_kms(&dev_priv->drm, "Failed at component
> add(%d)\n",
> ret);
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - dev_priv->hdcp_comp_added = false;
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + dev_priv->display.hdcp.comp_added = false;
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return;
> }
> }
> @@ -2454,14 +2454,14 @@ void intel_hdcp_update_pipe(struct
> intel_atomic_state *state,
>
> void intel_hdcp_component_fini(struct drm_i915_private *dev_priv) {
> - mutex_lock(&dev_priv->hdcp_comp_mutex);
> - if (!dev_priv->hdcp_comp_added) {
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + mutex_lock(&dev_priv->display.hdcp.comp_mutex);
> + if (!dev_priv->display.hdcp.comp_added) {
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
> return;
> }
>
> - dev_priv->hdcp_comp_added = false;
> - mutex_unlock(&dev_priv->hdcp_comp_mutex);
> + dev_priv->display.hdcp.comp_added = false;
> + mutex_unlock(&dev_priv->display.hdcp.comp_mutex);
>
> component_del(dev_priv->drm.dev, &i915_hdcp_component_ops);
> } diff --git a/drivers/gpu/drm/i915/i915_driver.c
> b/drivers/gpu/drm/i915/i915_driver.c
> index f6841c1e5f0f..8841ec398b07 100644
> --- a/drivers/gpu/drm/i915/i915_driver.c
> +++ b/drivers/gpu/drm/i915/i915_driver.c
> @@ -338,7 +338,7 @@ static int i915_driver_early_probe(struct
> drm_i915_private *dev_priv)
> mutex_init(&dev_priv->display.audio.mutex);
> mutex_init(&dev_priv->display.wm.wm_mutex);
> mutex_init(&dev_priv->display.pps.mutex);
> - mutex_init(&dev_priv->hdcp_comp_mutex);
> + mutex_init(&dev_priv->display.hdcp.comp_mutex);
>
> i915_memcpy_init_early(dev_priv);
> intel_runtime_pm_init_early(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index 9ee08e80f0aa..a0af8190ed87
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -588,12 +588,6 @@ struct drm_i915_private {
>
> struct i915_drm_clients clients;
>
> - struct i915_hdcp_comp_master *hdcp_master;
> - bool hdcp_comp_added;
> -
> - /* Mutex to protect the above hdcp component related values. */
> - struct mutex hdcp_comp_mutex;
> -
> /* The TTM device structure. */
> struct ttm_device bdev;
>
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (15 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 16/39] drm/i915: move and group hdcp under display.hdcp Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:24 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay Jani Nikula
` (27 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
.../gpu/drm/i915/display/intel_display_core.h | 40 ++++++
.../drm/i915/display/intel_display_debugfs.c | 16 +--
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_hotplug.c | 116 +++++++++---------
drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
drivers/gpu/drm/i915/i915_driver.c | 6 +-
drivers/gpu/drm/i915/i915_drv.h | 40 ------
drivers/gpu/drm/i915/i915_irq.c | 52 ++++----
10 files changed, 144 insertions(+), 144 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 82ad8fe7440c..e3e3d27ffb53 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -1169,7 +1169,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
static bool ibx_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -1223,7 +1223,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder)
static bool ilk_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 23c8287b0262..320304809ed6 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4032,7 +4032,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
static bool lpt_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, SDEISR) & bit;
}
@@ -4040,7 +4040,7 @@ static bool lpt_digital_port_connected(struct intel_encoder *encoder)
static bool hsw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, DEISR) & bit;
}
@@ -4048,7 +4048,7 @@ static bool hsw_digital_port_connected(struct intel_encoder *encoder)
static bool bdw_digital_port_connected(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 8ac63352b27b..cf31ad0c9593 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -102,6 +102,45 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_hotplug {
+ struct delayed_work hotplug_work;
+
+ const u32 *hpd, *pch_hpd;
+
+ struct {
+ unsigned long last_jiffies;
+ int count;
+ enum {
+ HPD_ENABLED = 0,
+ HPD_DISABLED = 1,
+ HPD_MARK_DISABLED = 2
+ } state;
+ } stats[HPD_NUM_PINS];
+ u32 event_bits;
+ u32 retry_bits;
+ struct delayed_work reenable_work;
+
+ u32 long_port_mask;
+ u32 short_port_mask;
+ struct work_struct dig_port_work;
+
+ struct work_struct poll_init_work;
+ bool poll_enabled;
+
+ unsigned int hpd_storm_threshold;
+ /* Whether or not to count short HPD IRQs in HPD storms */
+ u8 hpd_short_storm_enabled;
+
+ /*
+ * if we get a HPD irq from DP and a HPD irq from non-DP
+ * the non-DP HPD could block the workqueue on a mode config
+ * mutex getting, that userspace may have taken. However
+ * userspace is waiting on the DP workqueue to run which is
+ * blocked behind the non-DP one.
+ */
+ struct workqueue_struct *dp_wq;
+};
+
struct intel_wm {
/*
* Raw watermark latency values:
@@ -213,6 +252,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_hotplug hotplug;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 395facf6c1aa..13c855b59f7d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -1618,14 +1618,14 @@ static const struct file_operations i915_cur_wm_latency_fops = {
static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
/* Synchronize with everything first in case there's been an HPD
* storm, but we haven't finished handling it in the kernel yet
*/
intel_synchronize_irq(dev_priv);
- flush_work(&dev_priv->hotplug.dig_port_work);
- flush_delayed_work(&dev_priv->hotplug.hotplug_work);
+ flush_work(&dev_priv->display.hotplug.dig_port_work);
+ flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
seq_printf(m, "Detected: %s\n",
@@ -1640,7 +1640,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
unsigned int new_threshold;
int i;
char *newline;
@@ -1679,7 +1679,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->hotplug.reenable_work);
+ flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
return len;
}
@@ -1703,7 +1703,7 @@ static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = m->private;
seq_printf(m, "Enabled: %s\n",
- str_yes_no(dev_priv->hotplug.hpd_short_storm_enabled));
+ str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled));
return 0;
}
@@ -1721,7 +1721,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
{
struct seq_file *m = file->private_data;
struct drm_i915_private *dev_priv = m->private;
- struct i915_hotplug *hotplug = &dev_priv->hotplug;
+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
char *newline;
char tmp[16];
int i;
@@ -1757,7 +1757,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
spin_unlock_irq(&dev_priv->irq_lock);
/* Re-enable hpd immediately if we were in an irq storm */
- flush_delayed_work(&dev_priv->hotplug.reenable_work);
+ flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
return len;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 32292c0be2bd..8d9c3af8443d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5023,9 +5023,9 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
struct drm_i915_private *i915 = to_i915(connector->dev);
spin_lock_irq(&i915->irq_lock);
- i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
+ i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
spin_unlock_irq(&i915->irq_lock);
- queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
+ queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
}
static const struct drm_connector_funcs intel_dp_connector_funcs = {
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 5f8b4f481cff..f7a2f485b177 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -119,13 +119,13 @@ intel_connector_hpd_pin(struct intel_connector *connector)
* responsible for further action.
*
* The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
- * stored in @dev_priv->hotplug.hpd_storm_threshold which defaults to
+ * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
* @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
* short IRQs count as +1. If this threshold is exceeded, it's considered an
* IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
*
* By default, most systems will only count long IRQs towards
- * &dev_priv->hotplug.hpd_storm_threshold. However, some older systems also
+ * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
* suffer from short IRQ storms and must also track these. Because short IRQ
* storms are naturally caused by sideband interactions with DP MST devices,
* short IRQ detection is only enabled for systems without DP MST support.
@@ -140,7 +140,7 @@ intel_connector_hpd_pin(struct intel_connector *connector)
static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
enum hpd_pin pin, bool long_hpd)
{
- struct i915_hotplug *hpd = &dev_priv->hotplug;
+ struct intel_hotplug *hpd = &dev_priv->display.hotplug;
unsigned long start = hpd->stats[pin].last_jiffies;
unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
const int increment = long_hpd ? 10 : 1;
@@ -148,7 +148,7 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
bool storm = false;
if (!threshold ||
- (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled))
+ (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
return false;
if (!time_in_range(jiffies, start, end)) {
@@ -191,7 +191,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
+ dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
continue;
drm_info(&dev_priv->drm,
@@ -199,7 +199,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
"switching from hotplug detection to polling\n",
connector->base.name);
- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
+ dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
DRM_CONNECTOR_POLL_DISCONNECT;
hpd_disabled = true;
@@ -209,7 +209,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
/* Enable polling and queue hotplug re-enabling. */
if (hpd_disabled) {
drm_kms_helper_poll_enable(dev);
- mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
+ mod_delayed_work(system_wq, &dev_priv->display.hotplug.reenable_work,
msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
}
}
@@ -218,7 +218,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, typeof(*dev_priv),
- hotplug.reenable_work.work);
+ display.hotplug.reenable_work.work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -233,7 +233,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
for_each_intel_connector_iter(connector, &conn_iter) {
pin = intel_connector_hpd_pin(connector);
if (pin == HPD_NONE ||
- dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
+ dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
continue;
if (connector->base.polled != connector->polled)
@@ -245,8 +245,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
drm_connector_list_iter_end(&conn_iter);
for_each_hpd_pin(pin) {
- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
+ if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
+ dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
}
intel_hpd_irq_setup(dev_priv);
@@ -297,16 +297,16 @@ static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
static void i915_digport_work_func(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, struct drm_i915_private, hotplug.dig_port_work);
+ container_of(work, struct drm_i915_private, display.hotplug.dig_port_work);
u32 long_port_mask, short_port_mask;
struct intel_encoder *encoder;
u32 old_bits = 0;
spin_lock_irq(&dev_priv->irq_lock);
- long_port_mask = dev_priv->hotplug.long_port_mask;
- dev_priv->hotplug.long_port_mask = 0;
- short_port_mask = dev_priv->hotplug.short_port_mask;
- dev_priv->hotplug.short_port_mask = 0;
+ long_port_mask = dev_priv->display.hotplug.long_port_mask;
+ dev_priv->display.hotplug.long_port_mask = 0;
+ short_port_mask = dev_priv->display.hotplug.short_port_mask;
+ dev_priv->display.hotplug.short_port_mask = 0;
spin_unlock_irq(&dev_priv->irq_lock);
for_each_intel_encoder(&dev_priv->drm, encoder) {
@@ -335,9 +335,9 @@ static void i915_digport_work_func(struct work_struct *work)
if (old_bits) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.event_bits |= old_bits;
+ dev_priv->display.hotplug.event_bits |= old_bits;
spin_unlock_irq(&dev_priv->irq_lock);
- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
+ queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
}
}
@@ -353,10 +353,10 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
spin_lock_irq(&i915->irq_lock);
- i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
+ i915->display.hotplug.short_port_mask |= BIT(dig_port->base.port);
spin_unlock_irq(&i915->irq_lock);
- queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work);
+ queue_work(i915->display.hotplug.dp_wq, &i915->display.hotplug.dig_port_work);
}
/*
@@ -366,7 +366,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- hotplug.hotplug_work.work);
+ display.hotplug.hotplug_work.work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -379,10 +379,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
spin_lock_irq(&dev_priv->irq_lock);
- hpd_event_bits = dev_priv->hotplug.event_bits;
- dev_priv->hotplug.event_bits = 0;
- hpd_retry_bits = dev_priv->hotplug.retry_bits;
- dev_priv->hotplug.retry_bits = 0;
+ hpd_event_bits = dev_priv->display.hotplug.event_bits;
+ dev_priv->display.hotplug.event_bits = 0;
+ hpd_retry_bits = dev_priv->display.hotplug.retry_bits;
+ dev_priv->display.hotplug.retry_bits = 0;
/* Enable polling for connectors which had HPD IRQ storms */
intel_hpd_irq_storm_switch_to_polling(dev_priv);
@@ -435,10 +435,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
retry &= ~changed;
if (retry) {
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.retry_bits |= retry;
+ dev_priv->display.hotplug.retry_bits |= retry;
spin_unlock_irq(&dev_priv->irq_lock);
- mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
+ mod_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work,
msecs_to_jiffies(HPD_RETRY_DELAY));
}
}
@@ -502,10 +502,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (long_hpd) {
long_hpd_pulse_mask |= BIT(pin);
- dev_priv->hotplug.long_port_mask |= BIT(port);
+ dev_priv->display.hotplug.long_port_mask |= BIT(port);
} else {
short_hpd_pulse_mask |= BIT(pin);
- dev_priv->hotplug.short_port_mask |= BIT(port);
+ dev_priv->display.hotplug.short_port_mask |= BIT(port);
}
}
@@ -516,7 +516,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (!(BIT(pin) & pin_mask))
continue;
- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
+ if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED) {
/*
* On GMCH platforms the interrupt mask bits only
* prevent irq generation, not the setting of the
@@ -529,7 +529,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
continue;
}
- if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
+ if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
continue;
/*
@@ -540,13 +540,13 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
long_hpd = long_hpd_pulse_mask & BIT(pin);
} else {
- dev_priv->hotplug.event_bits |= BIT(pin);
+ dev_priv->display.hotplug.event_bits |= BIT(pin);
long_hpd = true;
queue_hp = true;
}
if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
- dev_priv->hotplug.event_bits &= ~BIT(pin);
+ dev_priv->display.hotplug.event_bits &= ~BIT(pin);
storm_detected = true;
queue_hp = true;
}
@@ -567,9 +567,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
* deadlock.
*/
if (queue_dig)
- queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
+ queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
if (queue_hp)
- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
+ queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
}
/**
@@ -594,8 +594,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
return;
for_each_hpd_pin(i) {
- dev_priv->hotplug.stats[i].count = 0;
- dev_priv->hotplug.stats[i].state = HPD_ENABLED;
+ dev_priv->display.hotplug.stats[i].count = 0;
+ dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
}
/*
@@ -611,7 +611,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- hotplug.poll_init_work);
+ display.hotplug.poll_init_work);
struct drm_device *dev = &dev_priv->drm;
struct drm_connector_list_iter conn_iter;
struct intel_connector *connector;
@@ -619,7 +619,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
mutex_lock(&dev->mode_config.mutex);
- enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
+ enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
drm_connector_list_iter_begin(dev, &conn_iter);
for_each_intel_connector_iter(connector, &conn_iter) {
@@ -672,7 +672,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
!INTEL_DISPLAY_ENABLED(dev_priv))
return;
- WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
+ WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
/*
* We might already be holding dev->mode_config.mutex, so do this in a
@@ -680,7 +680,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
* As well, there's no issue if we race here since we always reschedule
* this worker anyway
*/
- schedule_work(&dev_priv->hotplug.poll_init_work);
+ schedule_work(&dev_priv->display.hotplug.poll_init_work);
}
/**
@@ -707,17 +707,17 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
if (!HAS_DISPLAY(dev_priv))
return;
- WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
- schedule_work(&dev_priv->hotplug.poll_init_work);
+ WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
+ schedule_work(&dev_priv->display.hotplug.poll_init_work);
}
void intel_hpd_init_work(struct drm_i915_private *dev_priv)
{
- INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
+ INIT_DELAYED_WORK(&dev_priv->display.hotplug.hotplug_work,
i915_hotplug_work_func);
- INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
- INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
- INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
+ INIT_WORK(&dev_priv->display.hotplug.dig_port_work, i915_digport_work_func);
+ INIT_WORK(&dev_priv->display.hotplug.poll_init_work, i915_hpd_poll_init_work);
+ INIT_DELAYED_WORK(&dev_priv->display.hotplug.reenable_work,
intel_hpd_irq_storm_reenable_work);
}
@@ -728,17 +728,17 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.long_port_mask = 0;
- dev_priv->hotplug.short_port_mask = 0;
- dev_priv->hotplug.event_bits = 0;
- dev_priv->hotplug.retry_bits = 0;
+ dev_priv->display.hotplug.long_port_mask = 0;
+ dev_priv->display.hotplug.short_port_mask = 0;
+ dev_priv->display.hotplug.event_bits = 0;
+ dev_priv->display.hotplug.retry_bits = 0;
spin_unlock_irq(&dev_priv->irq_lock);
- cancel_work_sync(&dev_priv->hotplug.dig_port_work);
- cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
- cancel_work_sync(&dev_priv->hotplug.poll_init_work);
- cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
+ cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
+ cancel_delayed_work_sync(&dev_priv->display.hotplug.hotplug_work);
+ cancel_work_sync(&dev_priv->display.hotplug.poll_init_work);
+ cancel_delayed_work_sync(&dev_priv->display.hotplug.reenable_work);
}
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
@@ -749,8 +749,8 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
return false;
spin_lock_irq(&dev_priv->irq_lock);
- if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
+ if (dev_priv->display.hotplug.stats[pin].state == HPD_ENABLED) {
+ dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
ret = true;
}
spin_unlock_irq(&dev_priv->irq_lock);
@@ -764,6 +764,6 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
return;
spin_lock_irq(&dev_priv->irq_lock);
- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
+ dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
spin_unlock_irq(&dev_priv->irq_lock);
}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 6773840f6cc7..e5af955b5600 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -246,7 +246,7 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct intel_uncore *uncore = &i915->uncore;
- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
u32 mask = 0;
u32 val;
@@ -279,7 +279,7 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+ u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
struct intel_uncore *uncore = &i915->uncore;
u32 val, mask = 0;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 8841ec398b07..6607ed250531 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -252,8 +252,8 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
if (dev_priv->wq == NULL)
goto out_err;
- dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
- if (dev_priv->hotplug.dp_wq == NULL)
+ dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
+ if (dev_priv->display.hotplug.dp_wq == NULL)
goto out_free_wq;
return 0;
@@ -268,7 +268,7 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
{
- destroy_workqueue(dev_priv->hotplug.dp_wq);
+ destroy_workqueue(dev_priv->display.hotplug.dp_wq);
destroy_workqueue(dev_priv->wq);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a0af8190ed87..ef67a5322c2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,45 +89,6 @@ struct vlv_s0ix_state;
/* Threshold == 5 for long IRQs, 50 for short */
#define HPD_STORM_DEFAULT_THRESHOLD 50
-struct i915_hotplug {
- struct delayed_work hotplug_work;
-
- const u32 *hpd, *pch_hpd;
-
- struct {
- unsigned long last_jiffies;
- int count;
- enum {
- HPD_ENABLED = 0,
- HPD_DISABLED = 1,
- HPD_MARK_DISABLED = 2
- } state;
- } stats[HPD_NUM_PINS];
- u32 event_bits;
- u32 retry_bits;
- struct delayed_work reenable_work;
-
- u32 long_port_mask;
- u32 short_port_mask;
- struct work_struct dig_port_work;
-
- struct work_struct poll_init_work;
- bool poll_enabled;
-
- unsigned int hpd_storm_threshold;
- /* Whether or not to count short HPD IRQs in HPD storms */
- u8 hpd_short_storm_enabled;
-
- /*
- * if we get a HPD irq from DP and a HPD irq from non-DP
- * the non-DP HPD could block the workqueue on a mode config
- * mutex getting, that userspace may have taken. However
- * userspace is waiting on the DP workqueue to run which is
- * blocked behind the non-DP one.
- */
- struct workqueue_struct *dp_wq;
-};
-
#define I915_GEM_GPU_DOMAINS \
(I915_GEM_DOMAIN_RENDER | \
I915_GEM_DOMAIN_SAMPLER | \
@@ -375,7 +336,6 @@ struct drm_i915_private {
};
u32 pipestat_irq_mask[I915_MAX_PIPES];
- struct i915_hotplug hotplug;
struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_opregion opregion;
struct intel_vbt_data vbt;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b0095b289a79..c2f2d7b8d964 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -185,7 +185,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
{
- struct i915_hotplug *hpd = &dev_priv->hotplug;
+ struct intel_hotplug *hpd = &dev_priv->display.hotplug;
if (HAS_GMCH(dev_priv)) {
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
@@ -1272,7 +1272,7 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
u32 enabled_irqs = 0;
for_each_intel_encoder(&dev_priv->drm, encoder)
- if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
+ if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
enabled_irqs |= hpd[encoder->hpd_pin];
return enabled_irqs;
@@ -1637,7 +1637,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, hotplug_trigger,
- dev_priv->hotplug.hpd,
+ dev_priv->display.hotplug.hpd,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1841,7 +1841,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display.hotplug.pch_hpd,
pch_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -1986,7 +1986,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
ddi_hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display.hotplug.pch_hpd,
icp_ddi_port_hotplug_long_detect);
}
@@ -1998,7 +1998,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
tc_hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display.hotplug.pch_hpd,
icp_tc_port_hotplug_long_detect);
}
@@ -2024,7 +2024,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display.hotplug.pch_hpd,
spt_port_hotplug_long_detect);
}
@@ -2036,7 +2036,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug2_trigger, dig_hotplug_reg,
- dev_priv->hotplug.pch_hpd,
+ dev_priv->display.hotplug.pch_hpd,
spt_port_hotplug2_long_detect);
}
@@ -2057,7 +2057,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display.hotplug.hpd,
ilk_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2237,7 +2237,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
hotplug_trigger, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display.hotplug.hpd,
bxt_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2257,7 +2257,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tc, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display.hotplug.hpd,
gen11_port_hotplug_long_detect);
}
@@ -2269,7 +2269,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
trigger_tbt, dig_hotplug_reg,
- dev_priv->hotplug.hpd,
+ dev_priv->display.hotplug.hpd,
gen11_port_hotplug_long_detect);
}
@@ -3313,8 +3313,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3383,8 +3383,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
@@ -3460,8 +3460,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
u32 hotplug_irqs, enabled_irqs;
u32 val;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
val &= ~hotplug_irqs;
@@ -3538,8 +3538,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3578,8 +3578,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
if (DISPLAY_VER(dev_priv) >= 8)
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -3636,8 +3636,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
{
u32 hotplug_irqs, enabled_irqs;
- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
@@ -4413,14 +4413,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->display_irqs_enabled = false;
- dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
+ dev_priv->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
/* If we have MST support, we want to avoid doing short HPD IRQ storm
* detection, as short HPD storms will occur as a natural part of
* sideband messaging with MST.
* On older platforms however, IRQ storms can occur with both long and
* short pulses, as seen on some G4x systems.
*/
- dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
+ dev_priv->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug
2022-08-11 15:07 ` [Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug Jani Nikula
@ 2022-08-17 4:24 ` Lucas De Marchi
0 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:24 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:28PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
missed the mention that i915_hotplug is now intel_hotplug.
For this and all previous patches (except patch 5, for
clock_gating_funcs):
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/g4x_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
> .../gpu/drm/i915/display/intel_display_core.h | 40 ++++++
> .../drm/i915/display/intel_display_debugfs.c | 16 +--
> drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/display/intel_hotplug.c | 116 +++++++++---------
> drivers/gpu/drm/i915/display/intel_tc.c | 4 +-
> drivers/gpu/drm/i915/i915_driver.c | 6 +-
> drivers/gpu/drm/i915/i915_drv.h | 40 ------
> drivers/gpu/drm/i915/i915_irq.c | 52 ++++----
> 10 files changed, 144 insertions(+), 144 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
>index 82ad8fe7440c..e3e3d27ffb53 100644
>--- a/drivers/gpu/drm/i915/display/g4x_dp.c
>+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
>@@ -1169,7 +1169,7 @@ intel_dp_hotplug(struct intel_encoder *encoder,
> static bool ibx_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
>+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
>
> return intel_de_read(dev_priv, SDEISR) & bit;
> }
>@@ -1223,7 +1223,7 @@ static bool gm45_digital_port_connected(struct intel_encoder *encoder)
> static bool ilk_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
>+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
>
> return intel_de_read(dev_priv, DEISR) & bit;
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>index 23c8287b0262..320304809ed6 100644
>--- a/drivers/gpu/drm/i915/display/intel_ddi.c
>+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>@@ -4032,7 +4032,7 @@ intel_ddi_hotplug(struct intel_encoder *encoder,
> static bool lpt_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
>+ u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin];
>
> return intel_de_read(dev_priv, SDEISR) & bit;
> }
>@@ -4040,7 +4040,7 @@ static bool lpt_digital_port_connected(struct intel_encoder *encoder)
> static bool hsw_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
>+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
>
> return intel_de_read(dev_priv, DEISR) & bit;
> }
>@@ -4048,7 +4048,7 @@ static bool hsw_digital_port_connected(struct intel_encoder *encoder)
> static bool bdw_digital_port_connected(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>- u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
>+ u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin];
>
> return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 8ac63352b27b..cf31ad0c9593 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -102,6 +102,45 @@ struct intel_dpll {
> } ref_clks;
> };
>
>+struct intel_hotplug {
>+ struct delayed_work hotplug_work;
>+
>+ const u32 *hpd, *pch_hpd;
>+
>+ struct {
>+ unsigned long last_jiffies;
>+ int count;
>+ enum {
>+ HPD_ENABLED = 0,
>+ HPD_DISABLED = 1,
>+ HPD_MARK_DISABLED = 2
>+ } state;
>+ } stats[HPD_NUM_PINS];
>+ u32 event_bits;
>+ u32 retry_bits;
>+ struct delayed_work reenable_work;
>+
>+ u32 long_port_mask;
>+ u32 short_port_mask;
>+ struct work_struct dig_port_work;
>+
>+ struct work_struct poll_init_work;
>+ bool poll_enabled;
>+
>+ unsigned int hpd_storm_threshold;
>+ /* Whether or not to count short HPD IRQs in HPD storms */
>+ u8 hpd_short_storm_enabled;
>+
>+ /*
>+ * if we get a HPD irq from DP and a HPD irq from non-DP
>+ * the non-DP HPD could block the workqueue on a mode config
>+ * mutex getting, that userspace may have taken. However
>+ * userspace is waiting on the DP workqueue to run which is
>+ * blocked behind the non-DP one.
>+ */
>+ struct workqueue_struct *dp_wq;
>+};
>+
> struct intel_wm {
> /*
> * Raw watermark latency values:
>@@ -213,6 +252,7 @@ struct intel_display {
> struct intel_audio audio;
> struct intel_dmc dmc;
> struct intel_dpll dpll;
>+ struct intel_hotplug hotplug;
> struct intel_wm wm;
> };
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>index 395facf6c1aa..13c855b59f7d 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
>@@ -1618,14 +1618,14 @@ static const struct file_operations i915_cur_wm_latency_fops = {
> static int i915_hpd_storm_ctl_show(struct seq_file *m, void *data)
> {
> struct drm_i915_private *dev_priv = m->private;
>- struct i915_hotplug *hotplug = &dev_priv->hotplug;
>+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
>
> /* Synchronize with everything first in case there's been an HPD
> * storm, but we haven't finished handling it in the kernel yet
> */
> intel_synchronize_irq(dev_priv);
>- flush_work(&dev_priv->hotplug.dig_port_work);
>- flush_delayed_work(&dev_priv->hotplug.hotplug_work);
>+ flush_work(&dev_priv->display.hotplug.dig_port_work);
>+ flush_delayed_work(&dev_priv->display.hotplug.hotplug_work);
>
> seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold);
> seq_printf(m, "Detected: %s\n",
>@@ -1640,7 +1640,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
>- struct i915_hotplug *hotplug = &dev_priv->hotplug;
>+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
> unsigned int new_threshold;
> int i;
> char *newline;
>@@ -1679,7 +1679,7 @@ static ssize_t i915_hpd_storm_ctl_write(struct file *file,
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* Re-enable hpd immediately if we were in an irq storm */
>- flush_delayed_work(&dev_priv->hotplug.reenable_work);
>+ flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
>
> return len;
> }
>@@ -1703,7 +1703,7 @@ static int i915_hpd_short_storm_ctl_show(struct seq_file *m, void *data)
> struct drm_i915_private *dev_priv = m->private;
>
> seq_printf(m, "Enabled: %s\n",
>- str_yes_no(dev_priv->hotplug.hpd_short_storm_enabled));
>+ str_yes_no(dev_priv->display.hotplug.hpd_short_storm_enabled));
>
> return 0;
> }
>@@ -1721,7 +1721,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
> {
> struct seq_file *m = file->private_data;
> struct drm_i915_private *dev_priv = m->private;
>- struct i915_hotplug *hotplug = &dev_priv->hotplug;
>+ struct intel_hotplug *hotplug = &dev_priv->display.hotplug;
> char *newline;
> char tmp[16];
> int i;
>@@ -1757,7 +1757,7 @@ static ssize_t i915_hpd_short_storm_ctl_write(struct file *file,
> spin_unlock_irq(&dev_priv->irq_lock);
>
> /* Re-enable hpd immediately if we were in an irq storm */
>- flush_delayed_work(&dev_priv->hotplug.reenable_work);
>+ flush_delayed_work(&dev_priv->display.hotplug.reenable_work);
>
> return len;
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>index 32292c0be2bd..8d9c3af8443d 100644
>--- a/drivers/gpu/drm/i915/display/intel_dp.c
>+++ b/drivers/gpu/drm/i915/display/intel_dp.c
>@@ -5023,9 +5023,9 @@ static void intel_dp_oob_hotplug_event(struct drm_connector *connector)
> struct drm_i915_private *i915 = to_i915(connector->dev);
>
> spin_lock_irq(&i915->irq_lock);
>- i915->hotplug.event_bits |= BIT(encoder->hpd_pin);
>+ i915->display.hotplug.event_bits |= BIT(encoder->hpd_pin);
> spin_unlock_irq(&i915->irq_lock);
>- queue_delayed_work(system_wq, &i915->hotplug.hotplug_work, 0);
>+ queue_delayed_work(system_wq, &i915->display.hotplug.hotplug_work, 0);
> }
>
> static const struct drm_connector_funcs intel_dp_connector_funcs = {
>diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c b/drivers/gpu/drm/i915/display/intel_hotplug.c
>index 5f8b4f481cff..f7a2f485b177 100644
>--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
>+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
>@@ -119,13 +119,13 @@ intel_connector_hpd_pin(struct intel_connector *connector)
> * responsible for further action.
> *
> * The number of IRQs that are allowed within @HPD_STORM_DETECT_PERIOD is
>- * stored in @dev_priv->hotplug.hpd_storm_threshold which defaults to
>+ * stored in @dev_priv->display.hotplug.hpd_storm_threshold which defaults to
> * @HPD_STORM_DEFAULT_THRESHOLD. Long IRQs count as +10 to this threshold, and
> * short IRQs count as +1. If this threshold is exceeded, it's considered an
> * IRQ storm and the IRQ state is set to @HPD_MARK_DISABLED.
> *
> * By default, most systems will only count long IRQs towards
>- * &dev_priv->hotplug.hpd_storm_threshold. However, some older systems also
>+ * &dev_priv->display.hotplug.hpd_storm_threshold. However, some older systems also
> * suffer from short IRQ storms and must also track these. Because short IRQ
> * storms are naturally caused by sideband interactions with DP MST devices,
> * short IRQ detection is only enabled for systems without DP MST support.
>@@ -140,7 +140,7 @@ intel_connector_hpd_pin(struct intel_connector *connector)
> static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
> enum hpd_pin pin, bool long_hpd)
> {
>- struct i915_hotplug *hpd = &dev_priv->hotplug;
>+ struct intel_hotplug *hpd = &dev_priv->display.hotplug;
> unsigned long start = hpd->stats[pin].last_jiffies;
> unsigned long end = start + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD);
> const int increment = long_hpd ? 10 : 1;
>@@ -148,7 +148,7 @@ static bool intel_hpd_irq_storm_detect(struct drm_i915_private *dev_priv,
> bool storm = false;
>
> if (!threshold ||
>- (!long_hpd && !dev_priv->hotplug.hpd_short_storm_enabled))
>+ (!long_hpd && !dev_priv->display.hotplug.hpd_short_storm_enabled))
> return false;
>
> if (!time_in_range(jiffies, start, end)) {
>@@ -191,7 +191,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
>
> pin = intel_connector_hpd_pin(connector);
> if (pin == HPD_NONE ||
>- dev_priv->hotplug.stats[pin].state != HPD_MARK_DISABLED)
>+ dev_priv->display.hotplug.stats[pin].state != HPD_MARK_DISABLED)
> continue;
>
> drm_info(&dev_priv->drm,
>@@ -199,7 +199,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
> "switching from hotplug detection to polling\n",
> connector->base.name);
>
>- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
>+ dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
> connector->base.polled = DRM_CONNECTOR_POLL_CONNECT |
> DRM_CONNECTOR_POLL_DISCONNECT;
> hpd_disabled = true;
>@@ -209,7 +209,7 @@ intel_hpd_irq_storm_switch_to_polling(struct drm_i915_private *dev_priv)
> /* Enable polling and queue hotplug re-enabling. */
> if (hpd_disabled) {
> drm_kms_helper_poll_enable(dev);
>- mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work,
>+ mod_delayed_work(system_wq, &dev_priv->display.hotplug.reenable_work,
> msecs_to_jiffies(HPD_STORM_REENABLE_DELAY));
> }
> }
>@@ -218,7 +218,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> container_of(work, typeof(*dev_priv),
>- hotplug.reenable_work.work);
>+ display.hotplug.reenable_work.work);
> struct drm_device *dev = &dev_priv->drm;
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
>@@ -233,7 +233,7 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> for_each_intel_connector_iter(connector, &conn_iter) {
> pin = intel_connector_hpd_pin(connector);
> if (pin == HPD_NONE ||
>- dev_priv->hotplug.stats[pin].state != HPD_DISABLED)
>+ dev_priv->display.hotplug.stats[pin].state != HPD_DISABLED)
> continue;
>
> if (connector->base.polled != connector->polled)
>@@ -245,8 +245,8 @@ static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
> drm_connector_list_iter_end(&conn_iter);
>
> for_each_hpd_pin(pin) {
>- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED)
>- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
>+ if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED)
>+ dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
> }
>
> intel_hpd_irq_setup(dev_priv);
>@@ -297,16 +297,16 @@ static bool intel_encoder_has_hpd_pulse(struct intel_encoder *encoder)
> static void i915_digport_work_func(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
>- container_of(work, struct drm_i915_private, hotplug.dig_port_work);
>+ container_of(work, struct drm_i915_private, display.hotplug.dig_port_work);
> u32 long_port_mask, short_port_mask;
> struct intel_encoder *encoder;
> u32 old_bits = 0;
>
> spin_lock_irq(&dev_priv->irq_lock);
>- long_port_mask = dev_priv->hotplug.long_port_mask;
>- dev_priv->hotplug.long_port_mask = 0;
>- short_port_mask = dev_priv->hotplug.short_port_mask;
>- dev_priv->hotplug.short_port_mask = 0;
>+ long_port_mask = dev_priv->display.hotplug.long_port_mask;
>+ dev_priv->display.hotplug.long_port_mask = 0;
>+ short_port_mask = dev_priv->display.hotplug.short_port_mask;
>+ dev_priv->display.hotplug.short_port_mask = 0;
> spin_unlock_irq(&dev_priv->irq_lock);
>
> for_each_intel_encoder(&dev_priv->drm, encoder) {
>@@ -335,9 +335,9 @@ static void i915_digport_work_func(struct work_struct *work)
>
> if (old_bits) {
> spin_lock_irq(&dev_priv->irq_lock);
>- dev_priv->hotplug.event_bits |= old_bits;
>+ dev_priv->display.hotplug.event_bits |= old_bits;
> spin_unlock_irq(&dev_priv->irq_lock);
>- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
>+ queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
> }
> }
>
>@@ -353,10 +353,10 @@ void intel_hpd_trigger_irq(struct intel_digital_port *dig_port)
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>
> spin_lock_irq(&i915->irq_lock);
>- i915->hotplug.short_port_mask |= BIT(dig_port->base.port);
>+ i915->display.hotplug.short_port_mask |= BIT(dig_port->base.port);
> spin_unlock_irq(&i915->irq_lock);
>
>- queue_work(i915->hotplug.dp_wq, &i915->hotplug.dig_port_work);
>+ queue_work(i915->display.hotplug.dp_wq, &i915->display.hotplug.dig_port_work);
> }
>
> /*
>@@ -366,7 +366,7 @@ static void i915_hotplug_work_func(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> container_of(work, struct drm_i915_private,
>- hotplug.hotplug_work.work);
>+ display.hotplug.hotplug_work.work);
> struct drm_device *dev = &dev_priv->drm;
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
>@@ -379,10 +379,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
>
> spin_lock_irq(&dev_priv->irq_lock);
>
>- hpd_event_bits = dev_priv->hotplug.event_bits;
>- dev_priv->hotplug.event_bits = 0;
>- hpd_retry_bits = dev_priv->hotplug.retry_bits;
>- dev_priv->hotplug.retry_bits = 0;
>+ hpd_event_bits = dev_priv->display.hotplug.event_bits;
>+ dev_priv->display.hotplug.event_bits = 0;
>+ hpd_retry_bits = dev_priv->display.hotplug.retry_bits;
>+ dev_priv->display.hotplug.retry_bits = 0;
>
> /* Enable polling for connectors which had HPD IRQ storms */
> intel_hpd_irq_storm_switch_to_polling(dev_priv);
>@@ -435,10 +435,10 @@ static void i915_hotplug_work_func(struct work_struct *work)
> retry &= ~changed;
> if (retry) {
> spin_lock_irq(&dev_priv->irq_lock);
>- dev_priv->hotplug.retry_bits |= retry;
>+ dev_priv->display.hotplug.retry_bits |= retry;
> spin_unlock_irq(&dev_priv->irq_lock);
>
>- mod_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work,
>+ mod_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work,
> msecs_to_jiffies(HPD_RETRY_DELAY));
> }
> }
>@@ -502,10 +502,10 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
>
> if (long_hpd) {
> long_hpd_pulse_mask |= BIT(pin);
>- dev_priv->hotplug.long_port_mask |= BIT(port);
>+ dev_priv->display.hotplug.long_port_mask |= BIT(port);
> } else {
> short_hpd_pulse_mask |= BIT(pin);
>- dev_priv->hotplug.short_port_mask |= BIT(port);
>+ dev_priv->display.hotplug.short_port_mask |= BIT(port);
> }
> }
>
>@@ -516,7 +516,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (!(BIT(pin) & pin_mask))
> continue;
>
>- if (dev_priv->hotplug.stats[pin].state == HPD_DISABLED) {
>+ if (dev_priv->display.hotplug.stats[pin].state == HPD_DISABLED) {
> /*
> * On GMCH platforms the interrupt mask bits only
> * prevent irq generation, not the setting of the
>@@ -529,7 +529,7 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> continue;
> }
>
>- if (dev_priv->hotplug.stats[pin].state != HPD_ENABLED)
>+ if (dev_priv->display.hotplug.stats[pin].state != HPD_ENABLED)
> continue;
>
> /*
>@@ -540,13 +540,13 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (((short_hpd_pulse_mask | long_hpd_pulse_mask) & BIT(pin))) {
> long_hpd = long_hpd_pulse_mask & BIT(pin);
> } else {
>- dev_priv->hotplug.event_bits |= BIT(pin);
>+ dev_priv->display.hotplug.event_bits |= BIT(pin);
> long_hpd = true;
> queue_hp = true;
> }
>
> if (intel_hpd_irq_storm_detect(dev_priv, pin, long_hpd)) {
>- dev_priv->hotplug.event_bits &= ~BIT(pin);
>+ dev_priv->display.hotplug.event_bits &= ~BIT(pin);
> storm_detected = true;
> queue_hp = true;
> }
>@@ -567,9 +567,9 @@ void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
> * deadlock.
> */
> if (queue_dig)
>- queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work);
>+ queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
> if (queue_hp)
>- queue_delayed_work(system_wq, &dev_priv->hotplug.hotplug_work, 0);
>+ queue_delayed_work(system_wq, &dev_priv->display.hotplug.hotplug_work, 0);
> }
>
> /**
>@@ -594,8 +594,8 @@ void intel_hpd_init(struct drm_i915_private *dev_priv)
> return;
>
> for_each_hpd_pin(i) {
>- dev_priv->hotplug.stats[i].count = 0;
>- dev_priv->hotplug.stats[i].state = HPD_ENABLED;
>+ dev_priv->display.hotplug.stats[i].count = 0;
>+ dev_priv->display.hotplug.stats[i].state = HPD_ENABLED;
> }
>
> /*
>@@ -611,7 +611,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
> {
> struct drm_i915_private *dev_priv =
> container_of(work, struct drm_i915_private,
>- hotplug.poll_init_work);
>+ display.hotplug.poll_init_work);
> struct drm_device *dev = &dev_priv->drm;
> struct drm_connector_list_iter conn_iter;
> struct intel_connector *connector;
>@@ -619,7 +619,7 @@ static void i915_hpd_poll_init_work(struct work_struct *work)
>
> mutex_lock(&dev->mode_config.mutex);
>
>- enabled = READ_ONCE(dev_priv->hotplug.poll_enabled);
>+ enabled = READ_ONCE(dev_priv->display.hotplug.poll_enabled);
>
> drm_connector_list_iter_begin(dev, &conn_iter);
> for_each_intel_connector_iter(connector, &conn_iter) {
>@@ -672,7 +672,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
> !INTEL_DISPLAY_ENABLED(dev_priv))
> return;
>
>- WRITE_ONCE(dev_priv->hotplug.poll_enabled, true);
>+ WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, true);
>
> /*
> * We might already be holding dev->mode_config.mutex, so do this in a
>@@ -680,7 +680,7 @@ void intel_hpd_poll_enable(struct drm_i915_private *dev_priv)
> * As well, there's no issue if we race here since we always reschedule
> * this worker anyway
> */
>- schedule_work(&dev_priv->hotplug.poll_init_work);
>+ schedule_work(&dev_priv->display.hotplug.poll_init_work);
> }
>
> /**
>@@ -707,17 +707,17 @@ void intel_hpd_poll_disable(struct drm_i915_private *dev_priv)
> if (!HAS_DISPLAY(dev_priv))
> return;
>
>- WRITE_ONCE(dev_priv->hotplug.poll_enabled, false);
>- schedule_work(&dev_priv->hotplug.poll_init_work);
>+ WRITE_ONCE(dev_priv->display.hotplug.poll_enabled, false);
>+ schedule_work(&dev_priv->display.hotplug.poll_init_work);
> }
>
> void intel_hpd_init_work(struct drm_i915_private *dev_priv)
> {
>- INIT_DELAYED_WORK(&dev_priv->hotplug.hotplug_work,
>+ INIT_DELAYED_WORK(&dev_priv->display.hotplug.hotplug_work,
> i915_hotplug_work_func);
>- INIT_WORK(&dev_priv->hotplug.dig_port_work, i915_digport_work_func);
>- INIT_WORK(&dev_priv->hotplug.poll_init_work, i915_hpd_poll_init_work);
>- INIT_DELAYED_WORK(&dev_priv->hotplug.reenable_work,
>+ INIT_WORK(&dev_priv->display.hotplug.dig_port_work, i915_digport_work_func);
>+ INIT_WORK(&dev_priv->display.hotplug.poll_init_work, i915_hpd_poll_init_work);
>+ INIT_DELAYED_WORK(&dev_priv->display.hotplug.reenable_work,
> intel_hpd_irq_storm_reenable_work);
> }
>
>@@ -728,17 +728,17 @@ void intel_hpd_cancel_work(struct drm_i915_private *dev_priv)
>
> spin_lock_irq(&dev_priv->irq_lock);
>
>- dev_priv->hotplug.long_port_mask = 0;
>- dev_priv->hotplug.short_port_mask = 0;
>- dev_priv->hotplug.event_bits = 0;
>- dev_priv->hotplug.retry_bits = 0;
>+ dev_priv->display.hotplug.long_port_mask = 0;
>+ dev_priv->display.hotplug.short_port_mask = 0;
>+ dev_priv->display.hotplug.event_bits = 0;
>+ dev_priv->display.hotplug.retry_bits = 0;
>
> spin_unlock_irq(&dev_priv->irq_lock);
>
>- cancel_work_sync(&dev_priv->hotplug.dig_port_work);
>- cancel_delayed_work_sync(&dev_priv->hotplug.hotplug_work);
>- cancel_work_sync(&dev_priv->hotplug.poll_init_work);
>- cancel_delayed_work_sync(&dev_priv->hotplug.reenable_work);
>+ cancel_work_sync(&dev_priv->display.hotplug.dig_port_work);
>+ cancel_delayed_work_sync(&dev_priv->display.hotplug.hotplug_work);
>+ cancel_work_sync(&dev_priv->display.hotplug.poll_init_work);
>+ cancel_delayed_work_sync(&dev_priv->display.hotplug.reenable_work);
> }
>
> bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
>@@ -749,8 +749,8 @@ bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
> return false;
>
> spin_lock_irq(&dev_priv->irq_lock);
>- if (dev_priv->hotplug.stats[pin].state == HPD_ENABLED) {
>- dev_priv->hotplug.stats[pin].state = HPD_DISABLED;
>+ if (dev_priv->display.hotplug.stats[pin].state == HPD_ENABLED) {
>+ dev_priv->display.hotplug.stats[pin].state = HPD_DISABLED;
> ret = true;
> }
> spin_unlock_irq(&dev_priv->irq_lock);
>@@ -764,6 +764,6 @@ void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin)
> return;
>
> spin_lock_irq(&dev_priv->irq_lock);
>- dev_priv->hotplug.stats[pin].state = HPD_ENABLED;
>+ dev_priv->display.hotplug.stats[pin].state = HPD_ENABLED;
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
>index 6773840f6cc7..e5af955b5600 100644
>--- a/drivers/gpu/drm/i915/display/intel_tc.c
>+++ b/drivers/gpu/drm/i915/display/intel_tc.c
>@@ -246,7 +246,7 @@ static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct intel_uncore *uncore = &i915->uncore;
>- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
>+ u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
> u32 mask = 0;
> u32 val;
>
>@@ -279,7 +279,7 @@ static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
>- u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
>+ u32 isr_bit = i915->display.hotplug.pch_hpd[dig_port->base.hpd_pin];
> struct intel_uncore *uncore = &i915->uncore;
> u32 val, mask = 0;
>
>diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
>index 8841ec398b07..6607ed250531 100644
>--- a/drivers/gpu/drm/i915/i915_driver.c
>+++ b/drivers/gpu/drm/i915/i915_driver.c
>@@ -252,8 +252,8 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
> if (dev_priv->wq == NULL)
> goto out_err;
>
>- dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
>- if (dev_priv->hotplug.dp_wq == NULL)
>+ dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
>+ if (dev_priv->display.hotplug.dp_wq == NULL)
> goto out_free_wq;
>
> return 0;
>@@ -268,7 +268,7 @@ static int i915_workqueues_init(struct drm_i915_private *dev_priv)
>
> static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
> {
>- destroy_workqueue(dev_priv->hotplug.dp_wq);
>+ destroy_workqueue(dev_priv->display.hotplug.dp_wq);
> destroy_workqueue(dev_priv->wq);
> }
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index a0af8190ed87..ef67a5322c2d 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -89,45 +89,6 @@ struct vlv_s0ix_state;
> /* Threshold == 5 for long IRQs, 50 for short */
> #define HPD_STORM_DEFAULT_THRESHOLD 50
>
>-struct i915_hotplug {
>- struct delayed_work hotplug_work;
>-
>- const u32 *hpd, *pch_hpd;
>-
>- struct {
>- unsigned long last_jiffies;
>- int count;
>- enum {
>- HPD_ENABLED = 0,
>- HPD_DISABLED = 1,
>- HPD_MARK_DISABLED = 2
>- } state;
>- } stats[HPD_NUM_PINS];
>- u32 event_bits;
>- u32 retry_bits;
>- struct delayed_work reenable_work;
>-
>- u32 long_port_mask;
>- u32 short_port_mask;
>- struct work_struct dig_port_work;
>-
>- struct work_struct poll_init_work;
>- bool poll_enabled;
>-
>- unsigned int hpd_storm_threshold;
>- /* Whether or not to count short HPD IRQs in HPD storms */
>- u8 hpd_short_storm_enabled;
>-
>- /*
>- * if we get a HPD irq from DP and a HPD irq from non-DP
>- * the non-DP HPD could block the workqueue on a mode config
>- * mutex getting, that userspace may have taken. However
>- * userspace is waiting on the DP workqueue to run which is
>- * blocked behind the non-DP one.
>- */
>- struct workqueue_struct *dp_wq;
>-};
>-
> #define I915_GEM_GPU_DOMAINS \
> (I915_GEM_DOMAIN_RENDER | \
> I915_GEM_DOMAIN_SAMPLER | \
>@@ -375,7 +336,6 @@ struct drm_i915_private {
> };
> u32 pipestat_irq_mask[I915_MAX_PIPES];
>
>- struct i915_hotplug hotplug;
> struct intel_fbc *fbc[I915_MAX_FBCS];
> struct intel_opregion opregion;
> struct intel_vbt_data vbt;
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index b0095b289a79..c2f2d7b8d964 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -185,7 +185,7 @@ static const u32 hpd_sde_dg1[HPD_NUM_PINS] = {
>
> static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
> {
>- struct i915_hotplug *hpd = &dev_priv->hotplug;
>+ struct intel_hotplug *hpd = &dev_priv->display.hotplug;
>
> if (HAS_GMCH(dev_priv)) {
> if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
>@@ -1272,7 +1272,7 @@ static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
> u32 enabled_irqs = 0;
>
> for_each_intel_encoder(&dev_priv->drm, encoder)
>- if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
>+ if (dev_priv->display.hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
> enabled_irqs |= hpd[encoder->hpd_pin];
>
> return enabled_irqs;
>@@ -1637,7 +1637,7 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
> if (hotplug_trigger) {
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, hotplug_trigger,
>- dev_priv->hotplug.hpd,
>+ dev_priv->display.hotplug.hpd,
> i9xx_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>@@ -1841,7 +1841,7 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.pch_hpd,
>+ dev_priv->display.hotplug.pch_hpd,
> pch_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>@@ -1986,7 +1986,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> ddi_hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.pch_hpd,
>+ dev_priv->display.hotplug.pch_hpd,
> icp_ddi_port_hotplug_long_detect);
> }
>
>@@ -1998,7 +1998,7 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> tc_hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.pch_hpd,
>+ dev_priv->display.hotplug.pch_hpd,
> icp_tc_port_hotplug_long_detect);
> }
>
>@@ -2024,7 +2024,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.pch_hpd,
>+ dev_priv->display.hotplug.pch_hpd,
> spt_port_hotplug_long_detect);
> }
>
>@@ -2036,7 +2036,7 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug2_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.pch_hpd,
>+ dev_priv->display.hotplug.pch_hpd,
> spt_port_hotplug2_long_detect);
> }
>
>@@ -2057,7 +2057,7 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.hpd,
>+ dev_priv->display.hotplug.hpd,
> ilk_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>@@ -2237,7 +2237,7 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> hotplug_trigger, dig_hotplug_reg,
>- dev_priv->hotplug.hpd,
>+ dev_priv->display.hotplug.hpd,
> bxt_port_hotplug_long_detect);
>
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>@@ -2257,7 +2257,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> trigger_tc, dig_hotplug_reg,
>- dev_priv->hotplug.hpd,
>+ dev_priv->display.hotplug.hpd,
> gen11_port_hotplug_long_detect);
> }
>
>@@ -2269,7 +2269,7 @@ static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
>
> intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
> trigger_tbt, dig_hotplug_reg,
>- dev_priv->hotplug.hpd,
>+ dev_priv->display.hotplug.hpd,
> gen11_port_hotplug_long_detect);
> }
>
>@@ -3313,8 +3313,8 @@ static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug_irqs, enabled_irqs;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
>@@ -3383,8 +3383,8 @@ static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug_irqs, enabled_irqs;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>
> if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
> intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
>@@ -3460,8 +3460,8 @@ static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
> u32 hotplug_irqs, enabled_irqs;
> u32 val;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>
> val = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IMR);
> val &= ~hotplug_irqs;
>@@ -3538,8 +3538,8 @@ static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
> intel_uncore_write(&dev_priv->uncore, SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.pch_hpd);
>
> ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
>
>@@ -3578,8 +3578,8 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug_irqs, enabled_irqs;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>
> if (DISPLAY_VER(dev_priv) >= 8)
> bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>@@ -3636,8 +3636,8 @@ static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
> {
> u32 hotplug_irqs, enabled_irqs;
>
>- enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
>- hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->hotplug.hpd);
>+ enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>+ hotplug_irqs = intel_hpd_hotplug_irqs(dev_priv, dev_priv->display.hotplug.hpd);
>
> bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
>
>@@ -4413,14 +4413,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->display_irqs_enabled = false;
>
>- dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
>+ dev_priv->display.hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
> /* If we have MST support, we want to avoid doing short HPD IRQ storm
> * detection, as short HPD storms will occur as a natural part of
> * sideband messaging with MST.
> * On older platforms however, IRQ storms can occur with both long and
> * short pulses, as seen on some G4x systems.
> */
>- dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
>+ dev_priv->display.hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
>
> if (HAS_GMCH(dev_priv)) {
> if (I915_HAS_HOTPLUG(dev_priv))
>--
>2.34.1
>
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (16 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 17/39] drm/i915: move hotplug to display.hotplug Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-22 4:10 ` Murthy, Arun R
2022-08-11 15:07 ` [Intel-gfx] [PATCH 19/39] drm/i915: move and group sagv under display.sagv Jani Nikula
` (26 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
drivers/gpu/drm/i915/display/intel_overlay.c | 12 ++++++------
drivers/gpu/drm/i915/i915_drv.h | 4 ----
drivers/gpu/drm/i915/i915_getparam.c | 2 +-
4 files changed, 9 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index cf31ad0c9593..a5cd3a3d440e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -33,6 +33,7 @@ struct intel_fbdev;
struct intel_fdi_funcs;
struct intel_hotplug_funcs;
struct intel_initial_plane_config;
+struct intel_overlay;
struct intel_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
@@ -253,6 +254,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_hotplug hotplug;
+ struct intel_overlay *overlay;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 79ed8bd04a07..6f26f7f91925 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -487,7 +487,7 @@ static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
void intel_overlay_reset(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display.overlay;
if (!overlay)
return;
@@ -1113,7 +1113,7 @@ int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
struct drm_i915_gem_object *new_bo;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display.overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1273,7 +1273,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
struct intel_overlay *overlay;
int ret;
- overlay = dev_priv->overlay;
+ overlay = dev_priv->display.overlay;
if (!overlay) {
drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
return -ENODEV;
@@ -1416,7 +1416,7 @@ void intel_overlay_setup(struct drm_i915_private *dev_priv)
update_polyphase_filter(overlay->regs);
update_reg_attrs(overlay, overlay->regs);
- dev_priv->overlay = overlay;
+ dev_priv->display.overlay = overlay;
drm_info(&dev_priv->drm, "Initialized overlay support.\n");
return;
@@ -1428,7 +1428,7 @@ void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
{
struct intel_overlay *overlay;
- overlay = fetch_and_zero(&dev_priv->overlay);
+ overlay = fetch_and_zero(&dev_priv->display.overlay);
if (!overlay)
return;
@@ -1457,7 +1457,7 @@ struct intel_overlay_error_state {
struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
{
- struct intel_overlay *overlay = dev_priv->overlay;
+ struct intel_overlay *overlay = dev_priv->display.overlay;
struct intel_overlay_error_state *error;
if (!overlay || !overlay->active)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ef67a5322c2d..3637ee4ca088 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -82,7 +82,6 @@ struct intel_connector;
struct intel_dp;
struct intel_encoder;
struct intel_limit;
-struct intel_overlay;
struct intel_overlay_error_state;
struct vlv_s0ix_state;
@@ -342,9 +341,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* overlay */
- struct intel_overlay *overlay;
-
/* backlight registers and fields in struct intel_panel */
struct mutex backlight_lock;
diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c
index 6fd15b39570c..342c8ca6414e 100644
--- a/drivers/gpu/drm/i915/i915_getparam.c
+++ b/drivers/gpu/drm/i915/i915_getparam.c
@@ -36,7 +36,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
value = to_gt(i915)->ggtt->num_fences;
break;
case I915_PARAM_HAS_OVERLAY:
- value = !!i915->overlay;
+ value = !!i915->display.overlay;
break;
case I915_PARAM_HAS_BSD:
value = !!intel_engine_lookup_user(i915,
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay
2022-08-11 15:07 ` [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay Jani Nikula
@ 2022-08-22 4:10 ` Murthy, Arun R
0 siblings, 0 replies; 110+ messages in thread
From: Murthy, Arun R @ 2022-08-22 4:10 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx; +Cc: Nikula, Jani, De Marchi, Lucas
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Thursday, August 11, 2022 8:37 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; De Marchi, Lucas
> <lucas.demarchi@intel.com>
> Subject: [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay
>
> Move display related members under drm_i915_private display sub-struct.
Please update the patch description!
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
Upon adding the above said updates
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Thanks and Regards,
Arun R Murthy
--------------------
> drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
> drivers/gpu/drm/i915/display/intel_overlay.c | 12 ++++++------
> drivers/gpu/drm/i915/i915_drv.h | 4 ----
> drivers/gpu/drm/i915/i915_getparam.c | 2 +-
> 4 files changed, 9 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index cf31ad0c9593..a5cd3a3d440e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -33,6 +33,7 @@ struct intel_fbdev;
> struct intel_fdi_funcs;
> struct intel_hotplug_funcs;
> struct intel_initial_plane_config;
> +struct intel_overlay;
>
> struct intel_display_funcs {
> /* Returns the active state of the crtc, and if the crtc is active, @@ -
> 253,6 +254,7 @@ struct intel_display {
> struct intel_dmc dmc;
> struct intel_dpll dpll;
> struct intel_hotplug hotplug;
> + struct intel_overlay *overlay;
> struct intel_wm wm;
> };
>
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
> b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 79ed8bd04a07..6f26f7f91925 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -487,7 +487,7 @@ static int intel_overlay_release_old_vid(struct
> intel_overlay *overlay)
>
> void intel_overlay_reset(struct drm_i915_private *dev_priv) {
> - struct intel_overlay *overlay = dev_priv->overlay;
> + struct intel_overlay *overlay = dev_priv->display.overlay;
>
> if (!overlay)
> return;
> @@ -1113,7 +1113,7 @@ int intel_overlay_put_image_ioctl(struct
> drm_device *dev, void *data,
> struct drm_i915_gem_object *new_bo;
> int ret;
>
> - overlay = dev_priv->overlay;
> + overlay = dev_priv->display.overlay;
> if (!overlay) {
> drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
> return -ENODEV;
> @@ -1273,7 +1273,7 @@ int intel_overlay_attrs_ioctl(struct drm_device
> *dev, void *data,
> struct intel_overlay *overlay;
> int ret;
>
> - overlay = dev_priv->overlay;
> + overlay = dev_priv->display.overlay;
> if (!overlay) {
> drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
> return -ENODEV;
> @@ -1416,7 +1416,7 @@ void intel_overlay_setup(struct drm_i915_private
> *dev_priv)
> update_polyphase_filter(overlay->regs);
> update_reg_attrs(overlay, overlay->regs);
>
> - dev_priv->overlay = overlay;
> + dev_priv->display.overlay = overlay;
> drm_info(&dev_priv->drm, "Initialized overlay support.\n");
> return;
>
> @@ -1428,7 +1428,7 @@ void intel_overlay_cleanup(struct
> drm_i915_private *dev_priv) {
> struct intel_overlay *overlay;
>
> - overlay = fetch_and_zero(&dev_priv->overlay);
> + overlay = fetch_and_zero(&dev_priv->display.overlay);
> if (!overlay)
> return;
>
> @@ -1457,7 +1457,7 @@ struct intel_overlay_error_state { struct
> intel_overlay_error_state * intel_overlay_capture_error_state(struct
> drm_i915_private *dev_priv) {
> - struct intel_overlay *overlay = dev_priv->overlay;
> + struct intel_overlay *overlay = dev_priv->display.overlay;
> struct intel_overlay_error_state *error;
>
> if (!overlay || !overlay->active)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h index ef67a5322c2d..3637ee4ca088
> 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -82,7 +82,6 @@ struct intel_connector; struct intel_dp; struct
> intel_encoder; struct intel_limit; -struct intel_overlay; struct
> intel_overlay_error_state; struct vlv_s0ix_state;
>
> @@ -342,9 +341,6 @@ struct drm_i915_private {
>
> bool preserve_bios_swizzle;
>
> - /* overlay */
> - struct intel_overlay *overlay;
> -
> /* backlight registers and fields in struct intel_panel */
> struct mutex backlight_lock;
>
> diff --git a/drivers/gpu/drm/i915/i915_getparam.c
> b/drivers/gpu/drm/i915/i915_getparam.c
> index 6fd15b39570c..342c8ca6414e 100644
> --- a/drivers/gpu/drm/i915/i915_getparam.c
> +++ b/drivers/gpu/drm/i915/i915_getparam.c
> @@ -36,7 +36,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void
> *data,
> value = to_gt(i915)->ggtt->num_fences;
> break;
> case I915_PARAM_HAS_OVERLAY:
> - value = !!i915->overlay;
> + value = !!i915->display.overlay;
> break;
> case I915_PARAM_HAS_BSD:
> value = !!intel_engine_lookup_user(i915,
> --
> 2.34.1
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 19/39] drm/i915: move and group sagv under display.sagv
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (17 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 18/39] drm/i915: move overlay to display.overlay Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 20/39] drm/i915: move and group max_bw and bw_obj under display.bw Jani Nikula
` (25 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 10 ++---
.../gpu/drm/i915/display/intel_display_core.h | 11 ++++++
drivers/gpu/drm/i915/i915_drv.h | 9 -----
drivers/gpu/drm/i915/intel_pm.c | 38 +++++++++----------
4 files changed, 35 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 79269d2c476b..4e60ad847eb0 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -346,9 +346,9 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
* as it will fail and pointless anyway.
*/
if (qi.num_points == 1)
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
else
- dev_priv->sagv_status = I915_SAGV_ENABLED;
+ dev_priv->display.sagv.status = I915_SAGV_ENABLED;
return 0;
}
@@ -456,9 +456,9 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
* as it will fail and pointless anyway.
*/
if (qi.num_points == 1)
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
else
- dev_priv->sagv_status = I915_SAGV_ENABLED;
+ dev_priv->display.sagv.status = I915_SAGV_ENABLED;
return 0;
}
@@ -485,7 +485,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
bi->deratedbw[0] = deratedbw;
}
- i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
}
static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index a5cd3a3d440e..ab68c8799d1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -249,6 +249,17 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ enum {
+ I915_SAGV_UNKNOWN = 0,
+ I915_SAGV_DISABLED,
+ I915_SAGV_ENABLED,
+ I915_SAGV_NOT_CONTROLLED
+ } status;
+
+ u32 block_time_us;
+ } sagv;
+
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3637ee4ca088..daa6266ef127 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -447,15 +447,6 @@ struct drm_i915_private {
struct i915_suspend_saved_registers regfile;
struct vlv_s0ix_state *vlv_s0ix_state;
- enum {
- I915_SAGV_UNKNOWN = 0,
- I915_SAGV_DISABLED,
- I915_SAGV_ENABLED,
- I915_SAGV_NOT_CONTROLLED
- } sagv_status;
-
- u32 sagv_block_time_us;
-
struct dram_info {
bool wm_lv_0_adjust_needed;
u8 num_channels;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 14134e57034e..f72481e85ebd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3669,7 +3669,7 @@ static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
return DISPLAY_VER(dev_priv) >= 9 && !IS_LP(dev_priv) &&
- dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status != I915_SAGV_NOT_CONTROLLED;
}
static u32
@@ -3700,7 +3700,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
static void intel_sagv_init(struct drm_i915_private *i915)
{
if (!intel_has_sagv(i915))
- i915->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
/*
* Probe to see if we have working SAGV control.
@@ -3709,21 +3709,21 @@ static void intel_sagv_init(struct drm_i915_private *i915)
if (DISPLAY_VER(i915) < 11)
skl_sagv_disable(i915);
- drm_WARN_ON(&i915->drm, i915->sagv_status == I915_SAGV_UNKNOWN);
+ drm_WARN_ON(&i915->drm, i915->display.sagv.status == I915_SAGV_UNKNOWN);
- i915->sagv_block_time_us = intel_sagv_block_time(i915);
+ i915->display.sagv.block_time_us = intel_sagv_block_time(i915);
drm_dbg_kms(&i915->drm, "SAGV supported: %s, original SAGV block time: %u us\n",
- str_yes_no(intel_has_sagv(i915)), i915->sagv_block_time_us);
+ str_yes_no(intel_has_sagv(i915)), i915->display.sagv.block_time_us);
/* avoid overflow when adding with wm0 latency/etc. */
- if (drm_WARN(&i915->drm, i915->sagv_block_time_us > U16_MAX,
+ if (drm_WARN(&i915->drm, i915->display.sagv.block_time_us > U16_MAX,
"Excessive SAGV block time %u, ignoring\n",
- i915->sagv_block_time_us))
- i915->sagv_block_time_us = 0;
+ i915->display.sagv.block_time_us))
+ i915->display.sagv.block_time_us = 0;
if (!intel_has_sagv(i915))
- i915->sagv_block_time_us = 0;
+ i915->display.sagv.block_time_us = 0;
}
/*
@@ -3744,7 +3744,7 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
if (!intel_has_sagv(dev_priv))
return;
- if (dev_priv->sagv_status == I915_SAGV_ENABLED)
+ if (dev_priv->display.sagv.status == I915_SAGV_ENABLED)
return;
drm_dbg_kms(&dev_priv->drm, "Enabling SAGV\n");
@@ -3759,14 +3759,14 @@ static void skl_sagv_enable(struct drm_i915_private *dev_priv)
*/
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
return;
} else if (ret < 0) {
drm_err(&dev_priv->drm, "Failed to enable SAGV\n");
return;
}
- dev_priv->sagv_status = I915_SAGV_ENABLED;
+ dev_priv->display.sagv.status = I915_SAGV_ENABLED;
}
static void skl_sagv_disable(struct drm_i915_private *dev_priv)
@@ -3776,7 +3776,7 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
if (!intel_has_sagv(dev_priv))
return;
- if (dev_priv->sagv_status == I915_SAGV_DISABLED)
+ if (dev_priv->display.sagv.status == I915_SAGV_DISABLED)
return;
drm_dbg_kms(&dev_priv->drm, "Disabling SAGV\n");
@@ -3791,14 +3791,14 @@ static void skl_sagv_disable(struct drm_i915_private *dev_priv)
*/
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
drm_dbg(&dev_priv->drm, "No SAGV found on system, ignoring\n");
- dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
return;
} else if (ret < 0) {
drm_err(&dev_priv->drm, "Failed to disable SAGV (%d)\n", ret);
return;
}
- dev_priv->sagv_status = I915_SAGV_DISABLED;
+ dev_priv->display.sagv.status = I915_SAGV_DISABLED;
}
static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
@@ -5560,8 +5560,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
result->enable = true;
- if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)
- result->can_sagv = latency >= dev_priv->sagv_block_time_us;
+ if (DISPLAY_VER(dev_priv) < 12 && dev_priv->display.sagv.block_time_us)
+ result->can_sagv = latency >= dev_priv->display.sagv.block_time_us;
}
static void
@@ -5595,8 +5595,8 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
struct skl_wm_level *levels = plane_wm->wm;
unsigned int latency = 0;
- if (dev_priv->sagv_block_time_us)
- latency = dev_priv->sagv_block_time_us + dev_priv->display.wm.skl_latency[0];
+ if (dev_priv->display.sagv.block_time_us)
+ latency = dev_priv->display.sagv.block_time_us + dev_priv->display.wm.skl_latency[0];
skl_compute_plane_wm(crtc_state, plane, 0, latency,
wm_params, &levels[0],
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 20/39] drm/i915: move and group max_bw and bw_obj under display.bw
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (18 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 19/39] drm/i915: move and group sagv under display.sagv Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 21/39] drm/i915: move opregion to display.opregion Jani Nikula
` (24 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 42 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 21 ++++++++++
.../drm/i915/display/intel_modeset_setup.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 19 ---------
4 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4e60ad847eb0..3eb281f2cd5e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -292,7 +292,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
int ipqdepth, ipqdepthpch = 16;
int dclk_max;
int maxdebw;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -308,7 +308,7 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
int clpchgroup;
int j;
@@ -363,7 +363,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
int dclk_max;
int maxdebw, peakbw;
int clperchgroup;
- int num_groups = ARRAY_SIZE(dev_priv->max_bw);
+ int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
int i, ret;
ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
@@ -399,13 +399,13 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &dev_priv->max_bw[i];
+ struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
struct intel_bw_info *bi_next;
int clpchgroup;
int j;
if (i < num_groups - 1)
- bi_next = &dev_priv->max_bw[i + 1];
+ bi_next = &dev_priv->display.bw.max[i + 1];
clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
@@ -466,7 +466,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
static void dg2_get_bw_info(struct drm_i915_private *i915)
{
unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
- int num_groups = ARRAY_SIZE(i915->max_bw);
+ int num_groups = ARRAY_SIZE(i915->display.bw.max);
int i;
/*
@@ -477,7 +477,7 @@ static void dg2_get_bw_info(struct drm_i915_private *i915)
* whereas DG2-G11 platforms have 38 GB/s.
*/
for (i = 0; i < num_groups; i++) {
- struct intel_bw_info *bi = &i915->max_bw[i];
+ struct intel_bw_info *bi = &i915->display.bw.max[i];
bi->num_planes = 1;
/* Need only one dummy QGV point per group */
@@ -498,9 +498,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
+ for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -526,9 +526,9 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
*/
num_planes = max(1, num_planes);
- for (i = ARRAY_SIZE(dev_priv->max_bw) - 1; i >= 0; i--) {
+ for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
const struct intel_bw_info *bi =
- &dev_priv->max_bw[i];
+ &dev_priv->display.bw.max[i];
/*
* Pcode will not expose all QGV points when
@@ -541,14 +541,14 @@ static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
return bi->deratedbw[qgv_point];
}
- return dev_priv->max_bw[0].deratedbw[qgv_point];
+ return dev_priv->display.bw.max[0].deratedbw[qgv_point];
}
static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
int psf_gv_point)
{
const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
+ &dev_priv->display.bw.max[0];
return bi->psf_bw[psf_gv_point];
}
@@ -667,7 +667,7 @@ intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
return to_intel_bw_state(bw_state);
}
@@ -678,7 +678,7 @@ intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
return to_intel_bw_state(bw_state);
}
@@ -689,7 +689,7 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *bw_state;
- bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->bw_obj);
+ bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
if (IS_ERR(bw_state))
return ERR_CAST(bw_state);
@@ -896,8 +896,8 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
{
- unsigned int num_psf_gv_points = i915->max_bw[0].num_psf_gv_points;
- unsigned int num_qgv_points = i915->max_bw[0].num_qgv_points;
+ unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
+ unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
u16 qgv_points = 0, psf_points = 0;
/*
@@ -970,8 +970,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
int i, ret;
u16 qgv_points = 0, psf_points = 0;
unsigned int max_bw_point = 0, max_bw = 0;
- unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
- unsigned int num_psf_gv_points = dev_priv->max_bw[0].num_psf_gv_points;
+ unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
+ unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
bool changed = false;
/* FIXME earlier gens need some checks too */
@@ -1126,7 +1126,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv)
if (!state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->bw_obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
&state->base, &intel_bw_funcs);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index ab68c8799d1c..65c3394d2e7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -14,6 +14,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
+#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_pm_types.h"
@@ -35,6 +36,12 @@ struct intel_hotplug_funcs;
struct intel_initial_plane_config;
struct intel_overlay;
+/* Amount of SAGV/QGV points, BSpec precisely defines this */
+#define I915_NUM_QGV_POINTS 8
+
+/* Amount of PSF GV points, BSpec precisely defines this */
+#define I915_NUM_PSF_GV_POINTS 3
+
struct intel_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -210,6 +217,20 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ struct intel_global_obj obj;
+
+ struct intel_bw_info {
+ /* for each QGV point */
+ unsigned int deratedbw[I915_NUM_QGV_POINTS];
+ /* for each PSF GV point */
+ unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
+ u8 num_qgv_points;
+ u8 num_psf_gv_points;
+ u8 num_planes;
+ } max[6];
+ } bw;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index e0d5c58c2037..e0a6ea61227e 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -30,7 +30,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_encoder *encoder;
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_bw_state *bw_state =
- to_intel_bw_state(i915->bw_obj.state);
+ to_intel_bw_state(i915->display.bw.obj.state);
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
@@ -535,7 +535,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
for_each_intel_crtc(&i915->drm, crtc) {
struct intel_bw_state *bw_state =
- to_intel_bw_state(i915->bw_obj.state);
+ to_intel_bw_state(i915->display.bw.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index daa6266ef127..645eafa53a8f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -44,7 +44,6 @@
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
-#include "display/intel_global_state.h"
#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
@@ -202,14 +201,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
return i915_fence_context_timeout(i915, U64_MAX);
}
-/* Amount of SAGV/QGV points, BSpec precisely defines this */
-#define I915_NUM_QGV_POINTS 8
-
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-/* Amount of PSF GV points, BSpec precisely defines this */
-#define I915_NUM_PSF_GV_POINTS 3
-
struct intel_vbt_data {
/* bdb version */
u16 version;
@@ -464,18 +457,6 @@ struct drm_i915_private {
u8 num_psf_gv_points;
} dram_info;
- struct intel_bw_info {
- /* for each QGV point */
- unsigned int deratedbw[I915_NUM_QGV_POINTS];
- /* for each PSF GV point */
- unsigned int psf_bw[I915_NUM_PSF_GV_POINTS];
- u8 num_qgv_points;
- u8 num_psf_gv_points;
- u8 num_planes;
- } max_bw[6];
-
- struct intel_global_obj bw_obj;
-
struct intel_runtime_pm runtime_pm;
struct i915_perf perf;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 21/39] drm/i915: move opregion to display.opregion
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (19 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 20/39] drm/i915: move and group max_bw and bw_obj under display.bw Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 22/39] drm/i915: move and group cdclk under display.cdclk Jani Nikula
` (23 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
.../gpu/drm/i915/display/intel_display_core.h | 2 +
.../drm/i915/display/intel_display_debugfs.c | 6 ++-
drivers/gpu/drm/i915/display/intel_opregion.c | 42 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 2 -
drivers/gpu/drm/i915/i915_irq.c | 2 +-
6 files changed, 30 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 51dde5bfd956..5923cce94c11 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -3078,7 +3078,7 @@ static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915)
*/
void intel_bios_init(struct drm_i915_private *i915)
{
- const struct vbt_header *vbt = i915->opregion.vbt;
+ const struct vbt_header *vbt = i915->display.opregion.vbt;
struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
@@ -3285,7 +3285,7 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
* additional data. Trust that if the VBT was written into
* the OpRegion then they have validated the LVDS's existence.
*/
- if (i915->opregion.vbt)
+ if (i915->display.opregion.vbt)
return true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 65c3394d2e7f..948415e1a64e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_dpll_mgr.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
+#include "intel_opregion.h"
#include "intel_pm_types.h"
struct drm_i915_private;
@@ -286,6 +287,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_hotplug hotplug;
+ struct intel_opregion opregion;
struct intel_overlay *overlay;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 13c855b59f7d..619523f85a18 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -103,7 +103,8 @@ static int i915_sr_status(struct seq_file *m, void *unused)
static int i915_opregion(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->header)
seq_write(m, opregion->header, OPREGION_SIZE);
@@ -113,7 +114,8 @@ static int i915_opregion(struct seq_file *m, void *unused)
static int i915_vbt(struct seq_file *m, void *unused)
{
- struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_opregion *opregion = &i915->display.opregion;
if (opregion->vbt)
seq_write(m, opregion->vbt, opregion->vbt_size);
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 1c0c745c142d..caa07ef34f21 100644
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -252,7 +252,7 @@ struct opregion_asle_ext {
static int check_swsci_function(struct drm_i915_private *i915, u32 function)
{
- struct opregion_swsci *swsci = i915->opregion.swsci;
+ struct opregion_swsci *swsci = i915->display.opregion.swsci;
u32 main_function, sub_function;
if (!swsci)
@@ -265,11 +265,11 @@ static int check_swsci_function(struct drm_i915_private *i915, u32 function)
/* Check if we can call the function. See swsci_setup for details. */
if (main_function == SWSCI_SBCB) {
- if ((i915->opregion.swsci_sbcb_sub_functions &
+ if ((i915->display.opregion.swsci_sbcb_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
} else if (main_function == SWSCI_GBDA) {
- if ((i915->opregion.swsci_gbda_sub_functions &
+ if ((i915->display.opregion.swsci_gbda_sub_functions &
(1 << sub_function)) == 0)
return -EINVAL;
}
@@ -280,7 +280,7 @@ static int check_swsci_function(struct drm_i915_private *i915, u32 function)
static int swsci(struct drm_i915_private *dev_priv,
u32 function, u32 parm, u32 *parm_out)
{
- struct opregion_swsci *swsci = dev_priv->opregion.swsci;
+ struct opregion_swsci *swsci = dev_priv->display.opregion.swsci;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
u32 scic, dslp;
u16 swsci_val;
@@ -462,7 +462,7 @@ static u32 asle_set_backlight(struct drm_i915_private *dev_priv, u32 bclp)
{
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
- struct opregion_asle *asle = dev_priv->opregion.asle;
+ struct opregion_asle *asle = dev_priv->display.opregion.asle;
struct drm_device *dev = &dev_priv->drm;
drm_dbg(&dev_priv->drm, "bclp = 0x%08x\n", bclp);
@@ -586,8 +586,8 @@ static void asle_work(struct work_struct *work)
struct intel_opregion *opregion =
container_of(work, struct intel_opregion, asle_work);
struct drm_i915_private *dev_priv =
- container_of(opregion, struct drm_i915_private, opregion);
- struct opregion_asle *asle = dev_priv->opregion.asle;
+ container_of(opregion, struct drm_i915_private, display.opregion);
+ struct opregion_asle *asle = dev_priv->display.opregion.asle;
u32 aslc_stat = 0;
u32 aslc_req;
@@ -635,8 +635,8 @@ static void asle_work(struct work_struct *work)
void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
- if (dev_priv->opregion.asle)
- schedule_work(&dev_priv->opregion.asle_work);
+ if (dev_priv->display.opregion.asle)
+ schedule_work(&dev_priv->display.opregion.asle_work);
}
#define ACPI_EV_DISPLAY_SWITCH (1<<0)
@@ -692,7 +692,7 @@ static void set_did(struct intel_opregion *opregion, int i, u32 val)
static void intel_didl_outputs(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0, max_outputs;
@@ -731,7 +731,7 @@ static void intel_didl_outputs(struct drm_i915_private *dev_priv)
static void intel_setup_cadls(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct intel_connector *connector;
struct drm_connector_list_iter conn_iter;
int i = 0;
@@ -761,7 +761,7 @@ static void intel_setup_cadls(struct drm_i915_private *dev_priv)
static void swsci_setup(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
bool requested_callbacks = false;
u32 tmp;
@@ -839,7 +839,7 @@ static const struct dmi_system_id intel_no_opregion_vbt[] = {
static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
const struct firmware *fw = NULL;
const char *name = dev_priv->params.vbt_firmware;
int ret;
@@ -879,7 +879,7 @@ static int intel_load_vbt_firmware(struct drm_i915_private *dev_priv)
int intel_opregion_setup(struct drm_i915_private *dev_priv)
{
- struct intel_opregion *opregion = &dev_priv->opregion;
+ struct intel_opregion *opregion = &dev_priv->display.opregion;
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
u32 asls, mboxes;
char buf[sizeof(OPREGION_SIGNATURE)];
@@ -1106,7 +1106,7 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
{
struct drm_connector *connector = &intel_connector->base;
struct drm_i915_private *i915 = to_i915(connector->dev);
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
const void *in_edid;
const struct edid *edid;
struct edid *new_edid;
@@ -1141,7 +1141,7 @@ struct edid *intel_opregion_get_edid(struct intel_connector *intel_connector)
bool intel_opregion_headless_sku(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
struct opregion_header *header = opregion->header;
if (!header || header->over.major < 2 ||
@@ -1153,7 +1153,7 @@ bool intel_opregion_headless_sku(struct drm_i915_private *i915)
void intel_opregion_register(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1169,7 +1169,7 @@ void intel_opregion_register(struct drm_i915_private *i915)
void intel_opregion_resume(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1200,7 +1200,7 @@ void intel_opregion_resume(struct drm_i915_private *i915)
void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
if (!opregion->header)
return;
@@ -1210,7 +1210,7 @@ void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
if (opregion->asle)
opregion->asle->ardy = ASLE_ARDY_NOT_READY;
- cancel_work_sync(&i915->opregion.asle_work);
+ cancel_work_sync(&i915->display.opregion.asle_work);
if (opregion->acpi)
opregion->acpi->drdy = 0;
@@ -1218,7 +1218,7 @@ void intel_opregion_suspend(struct drm_i915_private *i915, pci_power_t state)
void intel_opregion_unregister(struct drm_i915_private *i915)
{
- struct intel_opregion *opregion = &i915->opregion;
+ struct intel_opregion *opregion = &i915->display.opregion;
intel_opregion_suspend(i915, PCI_D1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 645eafa53a8f..bd2f1e9f3679 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -44,7 +44,6 @@
#include "display/intel_dsb.h"
#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
-#include "display/intel_opregion.h"
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_lmem.h"
@@ -329,7 +328,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct intel_fbc *fbc[I915_MAX_FBCS];
- struct intel_opregion opregion;
struct intel_vbt_data vbt;
bool preserve_bios_swizzle;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c2f2d7b8d964..515648cd1233 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -595,7 +595,7 @@ void i915_disable_pipestat(struct drm_i915_private *dev_priv,
static bool i915_has_asle(struct drm_i915_private *dev_priv)
{
- if (!dev_priv->opregion.asle)
+ if (!dev_priv->display.opregion.asle)
return false;
return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 22/39] drm/i915: move and group cdclk under display.cdclk
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (20 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 21/39] drm/i915: move opregion to display.opregion Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 23/39] drm/i915: move backlight to display.backlight Jani Nikula
` (22 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 6 +-
.../gpu/drm/i915/display/intel_backlight.c | 4 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 206 +++++++++---------
drivers/gpu/drm/i915/display/intel_cdclk.h | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
.../gpu/drm/i915/display/intel_display_core.h | 14 ++
.../drm/i915/display/intel_display_power.c | 2 +-
.../i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_dp.c | 4 +-
drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 4 +-
.../drm/i915/display/intel_modeset_setup.c | 4 +-
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 4 +-
drivers/gpu/drm/i915/i915_drv.h | 15 --
15 files changed, 141 insertions(+), 142 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 861dcd2eb890..a5be4af792cb 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -202,7 +202,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(i915) &&
- crtc_state->pixel_rate > i915->max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index a74fc79b7910..aacbc6da84ef 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -532,7 +532,7 @@ static unsigned int calc_hblank_early_prog(struct intel_encoder *encoder,
h_total = crtc_state->hw.adjusted_mode.crtc_htotal;
pixel_clk = crtc_state->hw.adjusted_mode.crtc_clock;
vdsc_bpp = crtc_state->dsc.compressed_bpp;
- cdclk = i915->cdclk.hw.cdclk;
+ cdclk = i915->display.cdclk.hw.cdclk;
/* fec= 0.972261, using rounding multiplier of 1000000 */
fec_coeff = 972261;
link_clk = crtc_state->port_clock;
@@ -971,7 +971,7 @@ void intel_audio_cdclk_change_post(struct drm_i915_private *i915)
struct aud_ts_cdclk_m_n aud_ts;
if (DISPLAY_VER(i915) >= 13) {
- get_aud_ts_cdclk_m_n(i915->cdclk.hw.ref, i915->cdclk.hw.cdclk, &aud_ts);
+ get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
intel_de_write(i915, AUD_TS_CDCLK_N, aud_ts.n);
intel_de_write(i915, AUD_TS_CDCLK_M, aud_ts.m | AUD_TS_CDCLK_M_EN);
@@ -1119,7 +1119,7 @@ static int i915_audio_component_get_cdclk_freq(struct device *kdev)
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_DDI(dev_priv)))
return -ENODEV;
- return dev_priv->cdclk.hw.cdclk;
+ return dev_priv->display.cdclk.hw.cdclk;
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 110fc98ec280..fbe87ec458be 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1113,7 +1113,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_PINEVIEW(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
}
@@ -1131,7 +1131,7 @@ static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
if (IS_G4X(dev_priv))
clock = KHz(RUNTIME_INFO(dev_priv)->rawclk_freq);
else
- clock = KHz(dev_priv->cdclk.hw.cdclk);
+ clock = KHz(dev_priv->display.cdclk.hw.cdclk);
return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ea40c75c2986..9f8bbf9ddfa1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -548,7 +548,7 @@ static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
else
default_credits = PFI_CREDIT(8);
- if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
+ if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
/* CHV suggested value is 31 or 63 */
if (IS_CHERRYVIEW(dev_priv))
credits = PFI_CREDIT_63;
@@ -1026,7 +1026,7 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
drm_err(&dev_priv->drm, "DPLL0 not locked\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
/* We'll want to keep using the current vco from now on. */
skl_set_preferred_cdclk_vco(dev_priv, vco);
@@ -1040,7 +1040,7 @@ static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
@@ -1049,7 +1049,7 @@ static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
switch (cdclk) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 308571:
@@ -1098,13 +1098,13 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_disable(dev_priv);
cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco) {
+ if (dev_priv->display.cdclk.hw.vco != vco) {
/* Wa Display #1183: skl,kbl,cfl */
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
@@ -1116,7 +1116,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
intel_de_posting_read(dev_priv, CDCLK_CTL);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
skl_dpll0_enable(dev_priv, vco);
/* Wa Display #1183: skl,kbl,cfl */
@@ -1151,11 +1151,11 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
goto sanitize;
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
/* Is PLL enabled and locked ? */
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1166,7 +1166,7 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
*/
cdctl = intel_de_read(dev_priv, CDCLK_CTL);
expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
- skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
+ skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
if (cdctl == expected)
/* All well; nothing to sanitize */
return;
@@ -1175,9 +1175,9 @@ static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1186,19 +1186,19 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
skl_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0) {
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0) {
/*
* Use the current vco as our initial
* guess as to what the preferred vco is.
*/
if (dev_priv->skl_preferred_vco_freq == 0)
skl_set_preferred_cdclk_vco(dev_priv,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.vco);
return;
}
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
if (cdclk_config.vco == 0)
@@ -1211,7 +1211,7 @@ static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1352,35 +1352,35 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = {
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk >= min_cdclk)
return table[i].cdclk;
drm_WARN(&dev_priv->drm, 1,
"Cannot satisfy minimum cdclk %d with refclk %u\n",
- min_cdclk, dev_priv->cdclk.hw.ref);
+ min_cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display.cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk == cdclk)
- return dev_priv->cdclk.hw.ref * table[i].ratio;
+ return dev_priv->display.cdclk.hw.ref * table[i].ratio;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display.cdclk.hw.ref);
return 0;
}
@@ -1554,12 +1554,12 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
@@ -1571,7 +1571,7 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
@@ -1583,12 +1583,12 @@ static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
- dev_priv->cdclk.hw.vco = 0;
+ dev_priv->display.cdclk.hw.vco = 0;
}
static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
val = ICL_CDCLK_PLL_RATIO(ratio);
@@ -1601,12 +1601,12 @@ static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
{
- int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
+ int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
u32 val;
/* Write PLL ratio without disabling */
@@ -1625,7 +1625,7 @@ static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
val &= ~BXT_DE_PLL_FREQ_REQ;
intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
- dev_priv->cdclk.hw.vco = vco;
+ dev_priv->display.cdclk.hw.vco = vco;
}
static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
@@ -1655,7 +1655,7 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
default:
drm_WARN_ON(&dev_priv->drm,
- cdclk != dev_priv->cdclk.hw.bypass);
+ cdclk != dev_priv->display.cdclk.hw.bypass);
drm_WARN_ON(&dev_priv->drm, vco != 0);
fallthrough;
case 2:
@@ -1672,19 +1672,19 @@ static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
int cdclk)
{
- const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
+ const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
int i;
- if (cdclk == dev_priv->cdclk.hw.bypass)
+ if (cdclk == dev_priv->display.cdclk.hw.bypass)
return 0;
for (i = 0; table[i].refclk; i++)
- if (table[i].refclk == dev_priv->cdclk.hw.ref &&
+ if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
table[i].cdclk == cdclk)
return table[i].waveform;
drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
- cdclk, dev_priv->cdclk.hw.ref);
+ cdclk, dev_priv->display.cdclk.hw.ref);
return 0xffff;
}
@@ -1721,22 +1721,22 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
return;
}
- if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
- if (dev_priv->cdclk.hw.vco != vco)
+ if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0) {
+ if (dev_priv->display.cdclk.hw.vco != vco)
adlp_cdclk_pll_crawl(dev_priv, vco);
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
icl_cdclk_pll_enable(dev_priv, vco);
} else {
- if (dev_priv->cdclk.hw.vco != 0 &&
- dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != 0 &&
+ dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_disable(dev_priv);
- if (dev_priv->cdclk.hw.vco != vco)
+ if (dev_priv->display.cdclk.hw.vco != vco)
bxt_de_pll_enable(dev_priv, vco);
}
@@ -1803,7 +1803,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* Can't read out the voltage level :(
* Let's just assume everything is as expected.
*/
- dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
+ dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
}
static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
@@ -1812,10 +1812,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
int cdclk, clock, vco;
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
- if (dev_priv->cdclk.hw.vco == 0 ||
- dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
+ if (dev_priv->display.cdclk.hw.vco == 0 ||
+ dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
goto sanitize;
/* DPLL okay; verify the cdclock
@@ -1833,32 +1833,32 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
/* Make sure this is a legal cdclk value for the platform */
- cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
- if (cdclk != dev_priv->cdclk.hw.cdclk)
+ cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
+ if (cdclk != dev_priv->display.cdclk.hw.cdclk)
goto sanitize;
/* Make sure the VCO is correct for the cdclk */
vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
- if (vco != dev_priv->cdclk.hw.vco)
+ if (vco != dev_priv->display.cdclk.hw.vco)
goto sanitize;
expected = skl_cdclk_decimal(cdclk);
/* Figure out what CD2X divider we should be using for this cdclk */
if (has_cdclk_squasher(dev_priv))
- clock = dev_priv->cdclk.hw.vco / 2;
+ clock = dev_priv->display.cdclk.hw.vco / 2;
else
- clock = dev_priv->cdclk.hw.cdclk;
+ clock = dev_priv->display.cdclk.hw.cdclk;
expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock,
- dev_priv->cdclk.hw.vco);
+ dev_priv->display.cdclk.hw.vco);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
* enable otherwise.
*/
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
- dev_priv->cdclk.hw.cdclk >= 500000)
+ dev_priv->display.cdclk.hw.cdclk >= 500000)
expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
if (cdctl == expected)
@@ -1869,10 +1869,10 @@ static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
/* force cdclk programming */
- dev_priv->cdclk.hw.cdclk = 0;
+ dev_priv->display.cdclk.hw.cdclk = 0;
/* force full PLL disable + enable */
- dev_priv->cdclk.hw.vco = -1;
+ dev_priv->display.cdclk.hw.vco = -1;
}
static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
@@ -1881,11 +1881,11 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
bxt_sanitize_cdclk(dev_priv);
- if (dev_priv->cdclk.hw.cdclk != 0 &&
- dev_priv->cdclk.hw.vco != 0)
+ if (dev_priv->display.cdclk.hw.cdclk != 0 &&
+ dev_priv->display.cdclk.hw.vco != 0)
return;
- cdclk_config = dev_priv->cdclk.hw;
+ cdclk_config = dev_priv->display.cdclk.hw;
/*
* FIXME:
@@ -1902,7 +1902,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
{
- struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
+ struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
@@ -1916,7 +1916,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
* intel_cdclk_init_hw - Initialize CDCLK hardware
* @i915: i915 device
*
- * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
+ * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
* sanitizing the state of the hardware if needed. This is generally done only
* during the display core initialization sequence, after which the DMC will
* take care of turning CDCLK off/on as needed.
@@ -2077,7 +2077,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
{
struct intel_encoder *encoder;
- if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
+ if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
return;
if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
@@ -2124,9 +2124,9 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv,
intel_audio_cdclk_change_post(dev_priv);
if (drm_WARN(&dev_priv->drm,
- intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
+ intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
"cdclk state doesn't match!\n")) {
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "[hw state]");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
}
}
@@ -2315,7 +2315,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
*/
min_cdclk = max_t(int, min_cdclk,
min_t(int, crtc_state->pixel_rate,
- dev_priv->max_cdclk_freq));
+ dev_priv->display.cdclk.max_cdclk_freq));
}
return min_cdclk;
@@ -2368,10 +2368,10 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
for_each_pipe(dev_priv, pipe)
min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
- if (min_cdclk > dev_priv->max_cdclk_freq) {
+ if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
drm_dbg_kms(&dev_priv->drm,
"required cdclk (%d kHz) exceeds max (%d kHz)\n",
- min_cdclk, dev_priv->max_cdclk_freq);
+ min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
return -EINVAL;
}
@@ -2643,7 +2643,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *cdclk_state;
- cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
+ cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
if (IS_ERR(cdclk_state))
return ERR_CAST(cdclk_state);
@@ -2693,7 +2693,7 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
if (!cdclk_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
&cdclk_state->base, &intel_cdclk_funcs);
return 0;
@@ -2799,7 +2799,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
{
- int max_cdclk_freq = dev_priv->max_cdclk_freq;
+ int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
if (DISPLAY_VER(dev_priv) >= 10)
return 2 * max_cdclk_freq;
@@ -2825,19 +2825,19 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
{
if (IS_JSL_EHL(dev_priv)) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 552000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.cdclk.max_cdclk_freq = 552000;
else
- dev_priv->max_cdclk_freq = 556800;
+ dev_priv->display.cdclk.max_cdclk_freq = 556800;
} else if (DISPLAY_VER(dev_priv) >= 11) {
- if (dev_priv->cdclk.hw.ref == 24000)
- dev_priv->max_cdclk_freq = 648000;
+ if (dev_priv->display.cdclk.hw.ref == 24000)
+ dev_priv->display.cdclk.max_cdclk_freq = 648000;
else
- dev_priv->max_cdclk_freq = 652800;
+ dev_priv->display.cdclk.max_cdclk_freq = 652800;
} else if (IS_GEMINILAKE(dev_priv)) {
- dev_priv->max_cdclk_freq = 316800;
+ dev_priv->display.cdclk.max_cdclk_freq = 316800;
} else if (IS_BROXTON(dev_priv)) {
- dev_priv->max_cdclk_freq = 624000;
+ dev_priv->display.cdclk.max_cdclk_freq = 624000;
} else if (DISPLAY_VER(dev_priv) == 9) {
u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
int max_cdclk, vco;
@@ -2859,7 +2859,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
else
max_cdclk = 308571;
- dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
+ dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
} else if (IS_BROADWELL(dev_priv)) {
/*
* FIXME with extra cooling we can allow
@@ -2868,26 +2868,26 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
* available? PCI ID, VTB, something else?
*/
if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.cdclk.max_cdclk_freq = 450000;
else if (IS_BDW_ULX(dev_priv))
- dev_priv->max_cdclk_freq = 450000;
+ dev_priv->display.cdclk.max_cdclk_freq = 450000;
else if (IS_BDW_ULT(dev_priv))
- dev_priv->max_cdclk_freq = 540000;
+ dev_priv->display.cdclk.max_cdclk_freq = 540000;
else
- dev_priv->max_cdclk_freq = 675000;
+ dev_priv->display.cdclk.max_cdclk_freq = 675000;
} else if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 320000;
+ dev_priv->display.cdclk.max_cdclk_freq = 320000;
} else if (IS_VALLEYVIEW(dev_priv)) {
- dev_priv->max_cdclk_freq = 400000;
+ dev_priv->display.cdclk.max_cdclk_freq = 400000;
} else {
/* otherwise assume cdclk is fixed */
- dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
+ dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
}
dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
- dev_priv->max_cdclk_freq);
+ dev_priv->display.cdclk.max_cdclk_freq);
drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
dev_priv->max_dotclk_freq);
@@ -2901,7 +2901,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
*/
void intel_update_cdclk(struct drm_i915_private *dev_priv)
{
- intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw);
+ intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
/*
* 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
@@ -2911,7 +2911,7 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv)
*/
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
intel_de_write(dev_priv, GMBUSFREQ_VLV,
- DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
+ DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
}
static int dg1_rawclk(struct drm_i915_private *dev_priv)
@@ -3188,32 +3188,32 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = dg2_cdclk_table;
+ dev_priv->display.cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
else
- dev_priv->cdclk.table = adlp_cdclk_table;
+ dev_priv->display.cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = rkl_cdclk_table;
+ dev_priv->display.cdclk.table = rkl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 12) {
dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_JSL_EHL(dev_priv)) {
dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (DISPLAY_VER(dev_priv) >= 11) {
dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
- dev_priv->cdclk.table = icl_cdclk_table;
+ dev_priv->display.cdclk.table = icl_cdclk_table;
} else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
if (IS_GEMINILAKE(dev_priv))
- dev_priv->cdclk.table = glk_cdclk_table;
+ dev_priv->display.cdclk.table = glk_cdclk_table;
else
- dev_priv->cdclk.table = bxt_cdclk_table;
+ dev_priv->display.cdclk.table = bxt_cdclk_table;
} else if (DISPLAY_VER(dev_priv) == 9) {
dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
} else if (IS_BROADWELL(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index b535cf6a7d9e..c674879a84a5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -77,9 +77,9 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
#define intel_atomic_get_old_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
#define intel_atomic_get_new_cdclk_state(state) \
- to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
int intel_cdclk_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index efc0fa648736..6c352db1f7aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2659,7 +2659,7 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
if (DISPLAY_VER(i915) < 4) {
- clock_limit = i915->max_cdclk_freq * 9 / 10;
+ clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
/*
* Enable double wide mode when the dot clock
@@ -8394,11 +8394,11 @@ void intel_modeset_init_hw(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- cdclk_state = to_intel_cdclk_state(i915->cdclk.obj.state);
+ cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
intel_update_cdclk(i915);
- intel_cdclk_dump_config(i915, &i915->cdclk.hw, "Current CDCLK");
- cdclk_state->logical = cdclk_state->actual = i915->cdclk.hw;
+ intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
}
static int sanitize_watermarks_add_affected(struct drm_atomic_state *state)
@@ -8762,7 +8762,7 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
intel_hdcp_component_init(i915);
- if (i915->max_cdclk_freq == 0)
+ if (i915->display.cdclk.max_cdclk_freq == 0)
intel_update_max_cdclk(i915);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 948415e1a64e..d5069c4d3e3d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -11,6 +11,7 @@
#include <linux/wait.h>
#include <linux/workqueue.h>
+#include "intel_cdclk.h"
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
@@ -25,6 +26,7 @@ struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
struct intel_cdclk_funcs;
+struct intel_cdclk_vals;
struct intel_clock_gating_funcs;
struct intel_color_funcs;
struct intel_crtc;
@@ -232,6 +234,18 @@ struct intel_display {
} max[6];
} bw;
+ struct {
+ /* The current hardware cdclk configuration */
+ struct intel_cdclk_config hw;
+
+ /* cdclk, divider, and ratio table from bspec */
+ const struct intel_cdclk_vals *table;
+
+ struct intel_global_obj obj;
+
+ unsigned int max_cdclk_freq;
+ } cdclk;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 07d083e95e37..a25e632c726f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1309,7 +1309,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_update_cdclk(dev_priv);
- intel_cdclk_dump_config(dev_priv, &dev_priv->cdclk.hw, "Current CDCLK");
+ intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 119e6134b789..efeee2d47849 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -971,7 +971,7 @@ void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
+ intel_cdclk_needs_modeset(&dev_priv->display.cdclk.hw,
&cdclk_config));
gen9_assert_dbuf_enabled(dev_priv);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 8d9c3af8443d..9b5d96ce3aa0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -720,7 +720,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
if (bigjoiner) {
u32 max_bpp_bigjoiner =
- i915->max_cdclk_freq * 48 /
+ i915->display.cdclk.max_cdclk_freq * 48 /
intel_dp_mode_to_fec_clock(mode_clock);
bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
@@ -1536,7 +1536,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
* is greater than the maximum Cdclock and if slice count is even
* then we need to use 2 VDSC instances.
*/
- if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
+ if (adjusted_mode->crtc_clock > dev_priv->display.cdclk.max_cdclk_freq ||
pipe_config->bigjoiner_pipes) {
if (pipe_config->dsc.slice_count < 2) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 227fbee88b89..f2ad1d09ab43 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -86,7 +86,7 @@ static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
* divide by 2000 and use that
*/
if (dig_port->aux_ch == AUX_CH_A)
- freq = dev_priv->cdclk.hw.cdclk;
+ freq = dev_priv->display.cdclk.hw.cdclk;
else
freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
return DIV_ROUND_CLOSEST(freq, 2000);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index bbe142056c7c..d324bc8b5ef0 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -1858,7 +1858,7 @@ static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
@@ -3967,7 +3967,7 @@ static void mg_pll_disable(struct drm_i915_private *dev_priv,
static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
{
/* No SSC ref */
- i915->display.dpll.ref_clks.nssc = i915->cdclk.hw.ref;
+ i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
}
static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index e0a6ea61227e..6efbbb85c8ed 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -32,7 +32,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_bw_state *bw_state =
to_intel_bw_state(i915->display.bw.obj.state);
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(i915->cdclk.obj.state);
+ to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->dbuf.obj.state);
struct intel_crtc_state *crtc_state =
@@ -415,7 +415,7 @@ static void readout_plane_state(struct drm_i915_private *i915)
static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
{
struct intel_cdclk_state *cdclk_state =
- to_intel_cdclk_state(i915->cdclk.obj.state);
+ to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
to_intel_dbuf_state(i915->dbuf.obj.state);
enum pipe pipe;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
index 40bdd4cb629f..108b9e76c32e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -504,8 +504,8 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p)
drm_puts(p, "no P-state info available\n");
}
- drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
- drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
+ drm_printf(p, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
+ drm_printf(p, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
drm_printf(p, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
intel_runtime_pm_put(uncore->rpm, wakeref);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd2f1e9f3679..a28d0bcb07ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -37,7 +37,6 @@
#include <drm/drm_connector.h>
#include <drm/ttm/ttm_device.h>
-#include "display/intel_cdclk.h"
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
@@ -73,9 +72,6 @@
struct drm_i915_gem_object;
struct drm_i915_private;
-struct intel_cdclk_config;
-struct intel_cdclk_state;
-struct intel_cdclk_vals;
struct intel_connector;
struct intel_dp;
struct intel_encoder;
@@ -337,23 +333,12 @@ struct drm_i915_private {
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
- unsigned int max_cdclk_freq;
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
unsigned int fdi_pll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware cdclk configuration */
- struct intel_cdclk_config hw;
-
- /* cdclk, divider, and ratio table from bspec */
- const struct intel_cdclk_vals *table;
-
- struct intel_global_obj obj;
- } cdclk;
-
struct {
/* The current hardware dbuf configuration */
u8 enabled_slices;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 23/39] drm/i915: move backlight to display.backlight
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (21 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 22/39] drm/i915: move and group cdclk under display.cdclk Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:30 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi Jani Nikula
` (21 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_backlight.c | 28 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 5 ++++
drivers/gpu/drm/i915/i915_driver.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 --
4 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index fbe87ec458be..67ecad0f9ef1 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -303,7 +303,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (!panel->backlight.present || !conn_state->crtc)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -319,7 +319,7 @@ void intel_backlight_set_acpi(const struct drm_connector_state *conn_state,
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state, u32 level)
@@ -463,14 +463,14 @@ void intel_backlight_disable(const struct drm_connector_state *old_conn_state)
return;
}
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (panel->backlight.device)
panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
panel->backlight.enabled = false;
panel->backlight.funcs->disable(old_conn_state, 0);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
@@ -813,11 +813,11 @@ void intel_backlight_enable(const struct intel_crtc_state *crtc_state,
drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(pipe));
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
@@ -827,12 +827,12 @@ static u32 intel_panel_get_backlight(struct intel_connector *connector)
struct intel_panel *panel = &connector->panel;
u32 val = 0;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (panel->backlight.enabled)
val = panel->backlight.funcs->get(connector, intel_connector_get_pipe(connector));
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
drm_dbg_kms(&dev_priv->drm, "get backlight PWM = %d\n", val);
return val;
@@ -860,7 +860,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
drm_WARN_ON(&dev_priv->drm, panel->backlight.max == 0);
@@ -870,7 +870,7 @@ static void intel_panel_set_backlight(const struct drm_connector_state *conn_sta
if (panel->backlight.enabled)
intel_panel_actually_set_backlight(conn_state, hw_level);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
static int intel_backlight_device_update_status(struct backlight_device *bd)
@@ -1591,11 +1591,11 @@ void intel_backlight_update(struct intel_atomic_state *state,
if (!panel->backlight.present)
return;
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
if (!panel->backlight.enabled)
__intel_backlight_enable(crtc_state, conn_state);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
}
int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
@@ -1620,9 +1620,9 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
return -ENODEV;
/* set level and max in panel struct */
- mutex_lock(&dev_priv->backlight_lock);
+ mutex_lock(&dev_priv->display.backlight.lock);
ret = panel->backlight.funcs->setup(connector, pipe);
- mutex_unlock(&dev_priv->backlight_lock);
+ mutex_unlock(&dev_priv->display.backlight.lock);
if (ret) {
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index d5069c4d3e3d..533c2e3a6685 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -220,6 +220,11 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct {
+ /* backlight registers and fields in struct intel_panel */
+ struct mutex lock;
+ } backlight;
+
struct {
struct intel_global_obj obj;
diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index 6607ed250531..5d272d2d450e 100644
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -330,7 +330,7 @@ static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->gpu_error.lock);
- mutex_init(&dev_priv->backlight_lock);
+ mutex_init(&dev_priv->display.backlight.lock);
mutex_init(&dev_priv->sb_lock);
cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a28d0bcb07ca..29d7dcdf89af 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -328,9 +328,6 @@ struct drm_i915_private {
bool preserve_bios_swizzle;
- /* backlight registers and fields in struct intel_panel */
- struct mutex backlight_lock;
-
unsigned int fsb_freq, mem_freq, is_ddr3;
unsigned int skl_preferred_vco_freq;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (22 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 23/39] drm/i915: move backlight to display.backlight Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:32 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 25/39] drm/i915: move vbt to display.vbt Jani Nikula
` (20 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Abstract mmio base member access in register definitions in a macro.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 5 +
drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 3 -
4 files changed, 102 insertions(+), 98 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 533c2e3a6685..db1ba379797e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -251,6 +251,11 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
+ u32 mmio_base;
+ } dsi;
+
struct {
/* list of fbdev register on this device */
struct intel_fbdev *fbdev;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index b9b1fed99874..9651a1f00587 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
return;
if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
else
- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
if (!intel_dsi)
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
index 356e51515346..e065b8f2ee08 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
@@ -11,6 +11,8 @@
#define VLV_MIPI_BASE VLV_DISPLAY_BASE
#define BXT_MIPI_BASE 0x60000
+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
+
#define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
#define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
@@ -96,8 +98,8 @@
/* MIPI DSI Controller and D-PHY registers */
-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
+#define _MIPIC_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb800)
#define MIPI_DEVICE_READY(port) _MMIO_MIPI(port, _MIPIA_DEVICE_READY, _MIPIC_DEVICE_READY)
#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
#define ULPS_STATE_MASK (3 << 1)
@@ -106,11 +108,11 @@
#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
#define DEVICE_READY (1 << 0)
-#define _MIPIA_INTR_STAT (dev_priv->mipi_mmio_base + 0xb004)
-#define _MIPIC_INTR_STAT (dev_priv->mipi_mmio_base + 0xb804)
+#define _MIPIA_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb004)
+#define _MIPIC_INTR_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb804)
#define MIPI_INTR_STAT(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT, _MIPIC_INTR_STAT)
-#define _MIPIA_INTR_EN (dev_priv->mipi_mmio_base + 0xb008)
-#define _MIPIC_INTR_EN (dev_priv->mipi_mmio_base + 0xb808)
+#define _MIPIA_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb008)
+#define _MIPIC_INTR_EN (_MIPI_MMIO_BASE(dev_priv) + 0xb808)
#define MIPI_INTR_EN(port) _MMIO_MIPI(port, _MIPIA_INTR_EN, _MIPIC_INTR_EN)
#define TEARING_EFFECT (1 << 31)
#define SPL_PKT_SENT_INTERRUPT (1 << 30)
@@ -145,8 +147,8 @@
#define RXSOT_SYNC_ERROR (1 << 1)
#define RXSOT_ERROR (1 << 0)
-#define _MIPIA_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb00c)
-#define _MIPIC_DSI_FUNC_PRG (dev_priv->mipi_mmio_base + 0xb80c)
+#define _MIPIA_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb00c)
+#define _MIPIC_DSI_FUNC_PRG (_MIPI_MMIO_BASE(dev_priv) + 0xb80c)
#define MIPI_DSI_FUNC_PRG(port) _MMIO_MIPI(port, _MIPIA_DSI_FUNC_PRG, _MIPIC_DSI_FUNC_PRG)
#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
#define CMD_MODE_NOT_SUPPORTED (0 << 13)
@@ -168,76 +170,76 @@
#define DATA_LANES_PRG_REG_SHIFT 0
#define DATA_LANES_PRG_REG_MASK (7 << 0)
-#define _MIPIA_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb010)
-#define _MIPIC_HS_TX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb810)
+#define _MIPIA_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb010)
+#define _MIPIC_HS_TX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb810)
#define MIPI_HS_TX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_HS_TX_TIMEOUT, _MIPIC_HS_TX_TIMEOUT)
#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb014)
-#define _MIPIC_LP_RX_TIMEOUT (dev_priv->mipi_mmio_base + 0xb814)
+#define _MIPIA_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb014)
+#define _MIPIC_LP_RX_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb814)
#define MIPI_LP_RX_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_LP_RX_TIMEOUT, _MIPIC_LP_RX_TIMEOUT)
#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
-#define _MIPIA_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb018)
-#define _MIPIC_TURN_AROUND_TIMEOUT (dev_priv->mipi_mmio_base + 0xb818)
+#define _MIPIA_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb018)
+#define _MIPIC_TURN_AROUND_TIMEOUT (_MIPI_MMIO_BASE(dev_priv) + 0xb818)
#define MIPI_TURN_AROUND_TIMEOUT(port) _MMIO_MIPI(port, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIC_TURN_AROUND_TIMEOUT)
#define TURN_AROUND_TIMEOUT_MASK 0x3f
-#define _MIPIA_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb01c)
-#define _MIPIC_DEVICE_RESET_TIMER (dev_priv->mipi_mmio_base + 0xb81c)
+#define _MIPIA_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb01c)
+#define _MIPIC_DEVICE_RESET_TIMER (_MIPI_MMIO_BASE(dev_priv) + 0xb81c)
#define MIPI_DEVICE_RESET_TIMER(port) _MMIO_MIPI(port, _MIPIA_DEVICE_RESET_TIMER, _MIPIC_DEVICE_RESET_TIMER)
#define DEVICE_RESET_TIMER_MASK 0xffff
-#define _MIPIA_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb020)
-#define _MIPIC_DPI_RESOLUTION (dev_priv->mipi_mmio_base + 0xb820)
+#define _MIPIA_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb020)
+#define _MIPIC_DPI_RESOLUTION (_MIPI_MMIO_BASE(dev_priv) + 0xb820)
#define MIPI_DPI_RESOLUTION(port) _MMIO_MIPI(port, _MIPIA_DPI_RESOLUTION, _MIPIC_DPI_RESOLUTION)
#define VERTICAL_ADDRESS_SHIFT 16
#define VERTICAL_ADDRESS_MASK (0xffff << 16)
#define HORIZONTAL_ADDRESS_SHIFT 0
#define HORIZONTAL_ADDRESS_MASK 0xffff
-#define _MIPIA_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb024)
-#define _MIPIC_DBI_FIFO_THROTTLE (dev_priv->mipi_mmio_base + 0xb824)
+#define _MIPIA_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb024)
+#define _MIPIC_DBI_FIFO_THROTTLE (_MIPI_MMIO_BASE(dev_priv) + 0xb824)
#define MIPI_DBI_FIFO_THROTTLE(port) _MMIO_MIPI(port, _MIPIA_DBI_FIFO_THROTTLE, _MIPIC_DBI_FIFO_THROTTLE)
#define DBI_FIFO_EMPTY_HALF (0 << 0)
#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
/* regs below are bits 15:0 */
-#define _MIPIA_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb028)
-#define _MIPIC_HSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb828)
+#define _MIPIA_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb028)
+#define _MIPIC_HSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb828)
#define MIPI_HSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_HSYNC_PADDING_COUNT, _MIPIC_HSYNC_PADDING_COUNT)
-#define _MIPIA_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb02c)
-#define _MIPIC_HBP_COUNT (dev_priv->mipi_mmio_base + 0xb82c)
+#define _MIPIA_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb02c)
+#define _MIPIC_HBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb82c)
#define MIPI_HBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HBP_COUNT, _MIPIC_HBP_COUNT)
-#define _MIPIA_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb030)
-#define _MIPIC_HFP_COUNT (dev_priv->mipi_mmio_base + 0xb830)
+#define _MIPIA_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb030)
+#define _MIPIC_HFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb830)
#define MIPI_HFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_HFP_COUNT, _MIPIC_HFP_COUNT)
-#define _MIPIA_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb034)
-#define _MIPIC_HACTIVE_AREA_COUNT (dev_priv->mipi_mmio_base + 0xb834)
+#define _MIPIA_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb034)
+#define _MIPIC_HACTIVE_AREA_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb834)
#define MIPI_HACTIVE_AREA_COUNT(port) _MMIO_MIPI(port, _MIPIA_HACTIVE_AREA_COUNT, _MIPIC_HACTIVE_AREA_COUNT)
-#define _MIPIA_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb038)
-#define _MIPIC_VSYNC_PADDING_COUNT (dev_priv->mipi_mmio_base + 0xb838)
+#define _MIPIA_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb038)
+#define _MIPIC_VSYNC_PADDING_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb838)
#define MIPI_VSYNC_PADDING_COUNT(port) _MMIO_MIPI(port, _MIPIA_VSYNC_PADDING_COUNT, _MIPIC_VSYNC_PADDING_COUNT)
-#define _MIPIA_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb03c)
-#define _MIPIC_VBP_COUNT (dev_priv->mipi_mmio_base + 0xb83c)
+#define _MIPIA_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb03c)
+#define _MIPIC_VBP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb83c)
#define MIPI_VBP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VBP_COUNT, _MIPIC_VBP_COUNT)
-#define _MIPIA_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb040)
-#define _MIPIC_VFP_COUNT (dev_priv->mipi_mmio_base + 0xb840)
+#define _MIPIA_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb040)
+#define _MIPIC_VFP_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb840)
#define MIPI_VFP_COUNT(port) _MMIO_MIPI(port, _MIPIA_VFP_COUNT, _MIPIC_VFP_COUNT)
-#define _MIPIA_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb044)
-#define _MIPIC_HIGH_LOW_SWITCH_COUNT (dev_priv->mipi_mmio_base + 0xb844)
+#define _MIPIA_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb044)
+#define _MIPIC_HIGH_LOW_SWITCH_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb844)
#define MIPI_HIGH_LOW_SWITCH_COUNT(port) _MMIO_MIPI(port, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIC_HIGH_LOW_SWITCH_COUNT)
-#define _MIPIA_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb048)
-#define _MIPIC_DPI_CONTROL (dev_priv->mipi_mmio_base + 0xb848)
+#define _MIPIA_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb048)
+#define _MIPIC_DPI_CONTROL (_MIPI_MMIO_BASE(dev_priv) + 0xb848)
#define MIPI_DPI_CONTROL(port) _MMIO_MIPI(port, _MIPIA_DPI_CONTROL, _MIPIC_DPI_CONTROL)
#define DPI_LP_MODE (1 << 6)
#define BACKLIGHT_OFF (1 << 5)
@@ -247,27 +249,27 @@
#define TURN_ON (1 << 1)
#define SHUTDOWN (1 << 0)
-#define _MIPIA_DPI_DATA (dev_priv->mipi_mmio_base + 0xb04c)
-#define _MIPIC_DPI_DATA (dev_priv->mipi_mmio_base + 0xb84c)
+#define _MIPIA_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb04c)
+#define _MIPIC_DPI_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb84c)
#define MIPI_DPI_DATA(port) _MMIO_MIPI(port, _MIPIA_DPI_DATA, _MIPIC_DPI_DATA)
#define COMMAND_BYTE_SHIFT 0
#define COMMAND_BYTE_MASK (0x3f << 0)
-#define _MIPIA_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb050)
-#define _MIPIC_INIT_COUNT (dev_priv->mipi_mmio_base + 0xb850)
+#define _MIPIA_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb050)
+#define _MIPIC_INIT_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb850)
#define MIPI_INIT_COUNT(port) _MMIO_MIPI(port, _MIPIA_INIT_COUNT, _MIPIC_INIT_COUNT)
#define MASTER_INIT_TIMER_SHIFT 0
#define MASTER_INIT_TIMER_MASK (0xffff << 0)
-#define _MIPIA_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb054)
-#define _MIPIC_MAX_RETURN_PKT_SIZE (dev_priv->mipi_mmio_base + 0xb854)
+#define _MIPIA_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb054)
+#define _MIPIC_MAX_RETURN_PKT_SIZE (_MIPI_MMIO_BASE(dev_priv) + 0xb854)
#define MIPI_MAX_RETURN_PKT_SIZE(port) _MMIO_MIPI(port, \
_MIPIA_MAX_RETURN_PKT_SIZE, _MIPIC_MAX_RETURN_PKT_SIZE)
#define MAX_RETURN_PKT_SIZE_SHIFT 0
#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
-#define _MIPIA_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb058)
-#define _MIPIC_VIDEO_MODE_FORMAT (dev_priv->mipi_mmio_base + 0xb858)
+#define _MIPIA_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb058)
+#define _MIPIC_VIDEO_MODE_FORMAT (_MIPI_MMIO_BASE(dev_priv) + 0xb858)
#define MIPI_VIDEO_MODE_FORMAT(port) _MMIO_MIPI(port, _MIPIA_VIDEO_MODE_FORMAT, _MIPIC_VIDEO_MODE_FORMAT)
#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
#define DISABLE_VIDEO_BTA (1 << 3)
@@ -276,8 +278,8 @@
#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
#define VIDEO_MODE_BURST (3 << 0)
-#define _MIPIA_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb05c)
-#define _MIPIC_EOT_DISABLE (dev_priv->mipi_mmio_base + 0xb85c)
+#define _MIPIA_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb05c)
+#define _MIPIC_EOT_DISABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb85c)
#define MIPI_EOT_DISABLE(port) _MMIO_MIPI(port, _MIPIA_EOT_DISABLE, _MIPIC_EOT_DISABLE)
#define BXT_DEFEATURE_DPI_FIFO_CTR (1 << 9)
#define BXT_DPHY_DEFEATURE_EN (1 << 8)
@@ -290,35 +292,35 @@
#define CLOCKSTOP (1 << 1)
#define EOT_DISABLE (1 << 0)
-#define _MIPIA_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb060)
-#define _MIPIC_LP_BYTECLK (dev_priv->mipi_mmio_base + 0xb860)
+#define _MIPIA_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb060)
+#define _MIPIC_LP_BYTECLK (_MIPI_MMIO_BASE(dev_priv) + 0xb860)
#define MIPI_LP_BYTECLK(port) _MMIO_MIPI(port, _MIPIA_LP_BYTECLK, _MIPIC_LP_BYTECLK)
#define LP_BYTECLK_SHIFT 0
#define LP_BYTECLK_MASK (0xffff << 0)
-#define _MIPIA_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb0a4)
-#define _MIPIC_TLPX_TIME_COUNT (dev_priv->mipi_mmio_base + 0xb8a4)
+#define _MIPIA_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb0a4)
+#define _MIPIC_TLPX_TIME_COUNT (_MIPI_MMIO_BASE(dev_priv) + 0xb8a4)
#define MIPI_TLPX_TIME_COUNT(port) _MMIO_MIPI(port, _MIPIA_TLPX_TIME_COUNT, _MIPIC_TLPX_TIME_COUNT)
-#define _MIPIA_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb098)
-#define _MIPIC_CLK_LANE_TIMING (dev_priv->mipi_mmio_base + 0xb898)
+#define _MIPIA_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb098)
+#define _MIPIC_CLK_LANE_TIMING (_MIPI_MMIO_BASE(dev_priv) + 0xb898)
#define MIPI_CLK_LANE_TIMING(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_TIMING, _MIPIC_CLK_LANE_TIMING)
/* bits 31:0 */
-#define _MIPIA_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb064)
-#define _MIPIC_LP_GEN_DATA (dev_priv->mipi_mmio_base + 0xb864)
+#define _MIPIA_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb064)
+#define _MIPIC_LP_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb864)
#define MIPI_LP_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_DATA, _MIPIC_LP_GEN_DATA)
/* bits 31:0 */
-#define _MIPIA_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb068)
-#define _MIPIC_HS_GEN_DATA (dev_priv->mipi_mmio_base + 0xb868)
+#define _MIPIA_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb068)
+#define _MIPIC_HS_GEN_DATA (_MIPI_MMIO_BASE(dev_priv) + 0xb868)
#define MIPI_HS_GEN_DATA(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_DATA, _MIPIC_HS_GEN_DATA)
-#define _MIPIA_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb06c)
-#define _MIPIC_LP_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb86c)
+#define _MIPIA_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb06c)
+#define _MIPIC_LP_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb86c)
#define MIPI_LP_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_LP_GEN_CTRL, _MIPIC_LP_GEN_CTRL)
-#define _MIPIA_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb070)
-#define _MIPIC_HS_GEN_CTRL (dev_priv->mipi_mmio_base + 0xb870)
+#define _MIPIA_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb070)
+#define _MIPIC_HS_GEN_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb870)
#define MIPI_HS_GEN_CTRL(port) _MMIO_MIPI(port, _MIPIA_HS_GEN_CTRL, _MIPIC_HS_GEN_CTRL)
#define LONG_PACKET_WORD_COUNT_SHIFT 8
#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
@@ -330,8 +332,8 @@
#define DATA_TYPE_MASK (0x3f << 0)
/* data type values, see include/video/mipi_display.h */
-#define _MIPIA_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb074)
-#define _MIPIC_GEN_FIFO_STAT (dev_priv->mipi_mmio_base + 0xb874)
+#define _MIPIA_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb074)
+#define _MIPIC_GEN_FIFO_STAT (_MIPI_MMIO_BASE(dev_priv) + 0xb874)
#define MIPI_GEN_FIFO_STAT(port) _MMIO_MIPI(port, _MIPIA_GEN_FIFO_STAT, _MIPIC_GEN_FIFO_STAT)
#define DPI_FIFO_EMPTY (1 << 28)
#define DBI_FIFO_EMPTY (1 << 27)
@@ -348,15 +350,15 @@
#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
#define HS_DATA_FIFO_FULL (1 << 0)
-#define _MIPIA_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb078)
-#define _MIPIC_HS_LS_DBI_ENABLE (dev_priv->mipi_mmio_base + 0xb878)
+#define _MIPIA_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb078)
+#define _MIPIC_HS_LS_DBI_ENABLE (_MIPI_MMIO_BASE(dev_priv) + 0xb878)
#define MIPI_HS_LP_DBI_ENABLE(port) _MMIO_MIPI(port, _MIPIA_HS_LS_DBI_ENABLE, _MIPIC_HS_LS_DBI_ENABLE)
#define DBI_HS_LP_MODE_MASK (1 << 0)
#define DBI_LP_MODE (1 << 0)
#define DBI_HS_MODE (0 << 0)
-#define _MIPIA_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb080)
-#define _MIPIC_DPHY_PARAM (dev_priv->mipi_mmio_base + 0xb880)
+#define _MIPIA_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb080)
+#define _MIPIC_DPHY_PARAM (_MIPI_MMIO_BASE(dev_priv) + 0xb880)
#define MIPI_DPHY_PARAM(port) _MMIO_MIPI(port, _MIPIA_DPHY_PARAM, _MIPIC_DPHY_PARAM)
#define EXIT_ZERO_COUNT_SHIFT 24
#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
@@ -367,34 +369,34 @@
#define PREPARE_COUNT_SHIFT 0
#define PREPARE_COUNT_MASK (0x3f << 0)
-#define _MIPIA_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb084)
-#define _MIPIC_DBI_BW_CTRL (dev_priv->mipi_mmio_base + 0xb884)
+#define _MIPIA_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb084)
+#define _MIPIC_DBI_BW_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb884)
#define MIPI_DBI_BW_CTRL(port) _MMIO_MIPI(port, _MIPIA_DBI_BW_CTRL, _MIPIC_DBI_BW_CTRL)
-#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb088)
-#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (dev_priv->mipi_mmio_base + 0xb888)
+#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb088)
+#define _MIPIC_CLK_LANE_SWITCH_TIME_CNT (_MIPI_MMIO_BASE(dev_priv) + 0xb888)
#define MIPI_CLK_LANE_SWITCH_TIME_CNT(port) _MMIO_MIPI(port, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIC_CLK_LANE_SWITCH_TIME_CNT)
#define LP_HS_SSW_CNT_SHIFT 16
#define LP_HS_SSW_CNT_MASK (0xffff << 16)
#define HS_LP_PWR_SW_CNT_SHIFT 0
#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
-#define _MIPIA_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb08c)
-#define _MIPIC_STOP_STATE_STALL (dev_priv->mipi_mmio_base + 0xb88c)
+#define _MIPIA_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb08c)
+#define _MIPIC_STOP_STATE_STALL (_MIPI_MMIO_BASE(dev_priv) + 0xb88c)
#define MIPI_STOP_STATE_STALL(port) _MMIO_MIPI(port, _MIPIA_STOP_STATE_STALL, _MIPIC_STOP_STATE_STALL)
#define STOP_STATE_STALL_COUNTER_SHIFT 0
#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
-#define _MIPIA_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb090)
-#define _MIPIC_INTR_STAT_REG_1 (dev_priv->mipi_mmio_base + 0xb890)
+#define _MIPIA_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb090)
+#define _MIPIC_INTR_STAT_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb890)
#define MIPI_INTR_STAT_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_STAT_REG_1, _MIPIC_INTR_STAT_REG_1)
-#define _MIPIA_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb094)
-#define _MIPIC_INTR_EN_REG_1 (dev_priv->mipi_mmio_base + 0xb894)
+#define _MIPIA_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb094)
+#define _MIPIC_INTR_EN_REG_1 (_MIPI_MMIO_BASE(dev_priv) + 0xb894)
#define MIPI_INTR_EN_REG_1(port) _MMIO_MIPI(port, _MIPIA_INTR_EN_REG_1, _MIPIC_INTR_EN_REG_1)
#define RX_CONTENTION_DETECTED (1 << 0)
/* XXX: only pipe A ?!? */
-#define MIPIA_DBI_TYPEC_CTRL (dev_priv->mipi_mmio_base + 0xb100)
+#define MIPIA_DBI_TYPEC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb100)
#define DBI_TYPEC_ENABLE (1 << 31)
#define DBI_TYPEC_WIP (1 << 30)
#define DBI_TYPEC_OPTION_SHIFT 28
@@ -407,8 +409,8 @@
/* MIPI adapter registers */
-#define _MIPIA_CTRL (dev_priv->mipi_mmio_base + 0xb104)
-#define _MIPIC_CTRL (dev_priv->mipi_mmio_base + 0xb904)
+#define _MIPIA_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb104)
+#define _MIPIC_CTRL (_MIPI_MMIO_BASE(dev_priv) + 0xb904)
#define MIPI_CTRL(port) _MMIO_MIPI(port, _MIPIA_CTRL, _MIPIC_CTRL)
#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
@@ -440,21 +442,21 @@
#define GLK_MIPIIO_PORT_POWERED (1 << 1) /* RO */
#define GLK_MIPIIO_ENABLE (1 << 0)
-#define _MIPIA_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb108)
-#define _MIPIC_DATA_ADDRESS (dev_priv->mipi_mmio_base + 0xb908)
+#define _MIPIA_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb108)
+#define _MIPIC_DATA_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb908)
#define MIPI_DATA_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_DATA_ADDRESS, _MIPIC_DATA_ADDRESS)
#define DATA_MEM_ADDRESS_SHIFT 5
#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
#define DATA_VALID (1 << 0)
-#define _MIPIA_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb10c)
-#define _MIPIC_DATA_LENGTH (dev_priv->mipi_mmio_base + 0xb90c)
+#define _MIPIA_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb10c)
+#define _MIPIC_DATA_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb90c)
#define MIPI_DATA_LENGTH(port) _MMIO_MIPI(port, _MIPIA_DATA_LENGTH, _MIPIC_DATA_LENGTH)
#define DATA_LENGTH_SHIFT 0
#define DATA_LENGTH_MASK (0xfffff << 0)
-#define _MIPIA_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb110)
-#define _MIPIC_COMMAND_ADDRESS (dev_priv->mipi_mmio_base + 0xb910)
+#define _MIPIA_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb110)
+#define _MIPIC_COMMAND_ADDRESS (_MIPI_MMIO_BASE(dev_priv) + 0xb910)
#define MIPI_COMMAND_ADDRESS(port) _MMIO_MIPI(port, _MIPIA_COMMAND_ADDRESS, _MIPIC_COMMAND_ADDRESS)
#define COMMAND_MEM_ADDRESS_SHIFT 5
#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
@@ -462,18 +464,18 @@
#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
#define COMMAND_VALID (1 << 0)
-#define _MIPIA_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb114)
-#define _MIPIC_COMMAND_LENGTH (dev_priv->mipi_mmio_base + 0xb914)
+#define _MIPIA_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb114)
+#define _MIPIC_COMMAND_LENGTH (_MIPI_MMIO_BASE(dev_priv) + 0xb914)
#define MIPI_COMMAND_LENGTH(port) _MMIO_MIPI(port, _MIPIA_COMMAND_LENGTH, _MIPIC_COMMAND_LENGTH)
#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
-#define _MIPIA_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb118)
-#define _MIPIC_READ_DATA_RETURN0 (dev_priv->mipi_mmio_base + 0xb918)
+#define _MIPIA_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb118)
+#define _MIPIC_READ_DATA_RETURN0 (_MIPI_MMIO_BASE(dev_priv) + 0xb918)
#define MIPI_READ_DATA_RETURN(port, n) _MMIO(_MIPI(port, _MIPIA_READ_DATA_RETURN0, _MIPIC_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
-#define _MIPIA_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb138)
-#define _MIPIC_READ_DATA_VALID (dev_priv->mipi_mmio_base + 0xb938)
+#define _MIPIA_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb138)
+#define _MIPIC_READ_DATA_VALID (_MIPI_MMIO_BASE(dev_priv) + 0xb938)
#define MIPI_READ_DATA_VALID(port) _MMIO_MIPI(port, _MIPIA_READ_DATA_VALID, _MIPIC_READ_DATA_VALID)
#define READ_DATA_VALID(n) (1 << (n))
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 29d7dcdf89af..2f22f27cb038 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -297,9 +297,6 @@ struct drm_i915_private {
struct intel_wopcm wopcm;
- /* MMIO base address for MIPI regs */
- u32 mipi_mmio_base;
-
struct pci_dev *bridge_dev;
struct rb_root uabi_engines;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi Jani Nikula
@ 2022-08-17 4:32 ` Lucas De Marchi
2022-08-17 7:00 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:35PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Prefer adding anonymous sub-structs even for single members that aren't
>our own structs.
>
>Abstract mmio base member access in register definitions in a macro.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> .../gpu/drm/i915/display/intel_display_core.h | 5 +
> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++++---------
> drivers/gpu/drm/i915/i915_drv.h | 3 -
> 4 files changed, 102 insertions(+), 98 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 533c2e3a6685..db1ba379797e 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -251,6 +251,11 @@ struct intel_display {
> unsigned int max_cdclk_freq;
> } cdclk;
>
>+ struct {
>+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
this is already outdated, so maybe remove the platforms from the
comment?
>+ u32 mmio_base;
>+ } dsi;
>+
> struct {
> /* list of fbdev register on this device */
> struct intel_fbdev *fbdev;
>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>index b9b1fed99874..9651a1f00587 100644
>--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
> return;
>
> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
> else
>- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
>
> intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
> if (!intel_dsi)
>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>index 356e51515346..e065b8f2ee08 100644
>--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>@@ -11,6 +11,8 @@
> #define VLV_MIPI_BASE VLV_DISPLAY_BASE
> #define BXT_MIPI_BASE 0x60000
>
>+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
>+
> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
> #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>
>@@ -96,8 +98,8 @@
>
> /* MIPI DSI Controller and D-PHY registers */
>
>-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
>-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
>+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
ugh, and I thought we wouldn't have so many implicit params anymore.
Mind adding a "TODO: remove implicit dev_priv parameter" ?
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
2022-08-17 4:32 ` Lucas De Marchi
@ 2022-08-17 7:00 ` Jani Nikula
2022-08-17 7:21 ` Lucas De Marchi
0 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-17 7:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Thu, Aug 11, 2022 at 06:07:35PM +0300, Jani Nikula wrote:
>>Move display related members under drm_i915_private display sub-struct.
>>
>>Prefer adding anonymous sub-structs even for single members that aren't
>>our own structs.
>>
>>Abstract mmio base member access in register definitions in a macro.
>>
>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>---
>> .../gpu/drm/i915/display/intel_display_core.h | 5 +
>> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
>> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++++---------
>> drivers/gpu/drm/i915/i915_drv.h | 3 -
>> 4 files changed, 102 insertions(+), 98 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>index 533c2e3a6685..db1ba379797e 100644
>>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>@@ -251,6 +251,11 @@ struct intel_display {
>> unsigned int max_cdclk_freq;
>> } cdclk;
>>
>>+ struct {
>>+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
>
> this is already outdated, so maybe remove the platforms from the
> comment?
What did I miss? It's only used for vlv_dsi, not icl_dsi which is the
newer thing.
>
>
>>+ u32 mmio_base;
>>+ } dsi;
>>+
>> struct {
>> /* list of fbdev register on this device */
>> struct intel_fbdev *fbdev;
>>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>>index b9b1fed99874..9651a1f00587 100644
>>--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>>+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>>@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>> return;
>>
>> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>>- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>>+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
>> else
>>- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>>+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
>>
>> intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
>> if (!intel_dsi)
>>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>index 356e51515346..e065b8f2ee08 100644
>>--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>@@ -11,6 +11,8 @@
>> #define VLV_MIPI_BASE VLV_DISPLAY_BASE
>> #define BXT_MIPI_BASE 0x60000
>>
>>+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
>>+
>> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
>> #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>>
>>@@ -96,8 +98,8 @@
>>
>> /* MIPI DSI Controller and D-PHY registers */
>>
>>-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
>>-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
>>+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
>
> ugh, and I thought we wouldn't have so many implicit params anymore.
> Mind adding a "TODO: remove implicit dev_priv parameter" ?
It's been on my private todo list like 10 years. :(
BR,
Jani.
>
>
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>
> Lucas De Marchi
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
2022-08-17 7:00 ` Jani Nikula
@ 2022-08-17 7:21 ` Lucas De Marchi
2022-08-17 7:54 ` Jani Nikula
0 siblings, 1 reply; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 7:21 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Wed, Aug 17, 2022 at 10:00:01AM +0300, Jani Nikula wrote:
>On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>> On Thu, Aug 11, 2022 at 06:07:35PM +0300, Jani Nikula wrote:
>>>Move display related members under drm_i915_private display sub-struct.
>>>
>>>Prefer adding anonymous sub-structs even for single members that aren't
>>>our own structs.
>>>
>>>Abstract mmio base member access in register definitions in a macro.
>>>
>>>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>>>---
>>> .../gpu/drm/i915/display/intel_display_core.h | 5 +
>>> drivers/gpu/drm/i915/display/vlv_dsi.c | 4 +-
>>> drivers/gpu/drm/i915/display/vlv_dsi_regs.h | 188 +++++++++---------
>>> drivers/gpu/drm/i915/i915_drv.h | 3 -
>>> 4 files changed, 102 insertions(+), 98 deletions(-)
>>>
>>>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>>>index 533c2e3a6685..db1ba379797e 100644
>>>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>>>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>>>@@ -251,6 +251,11 @@ struct intel_display {
>>> unsigned int max_cdclk_freq;
>>> } cdclk;
>>>
>>>+ struct {
>>>+ /* VLV/CHV/BXT/GLK DSI MMIO register base address */
>>
>> this is already outdated, so maybe remove the platforms from the
>> comment?
>
>What did I miss? It's only used for vlv_dsi, not icl_dsi which is the
>newer thing.
you missed that I misread this part. It's the icl_dsi that is used
later.
>
>>
>>
>>>+ u32 mmio_base;
>>>+ } dsi;
>>>+
>>> struct {
>>> /* list of fbdev register on this device */
>>> struct intel_fbdev *fbdev;
>>>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
>>>index b9b1fed99874..9651a1f00587 100644
>>>--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
>>>+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
>>>@@ -1872,9 +1872,9 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv)
>>> return;
>>>
>>> if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
>>>- dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
>>>+ dev_priv->display.dsi.mmio_base = BXT_MIPI_BASE;
>>> else
>>>- dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
>>>+ dev_priv->display.dsi.mmio_base = VLV_MIPI_BASE;
>>>
>>> intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
>>> if (!intel_dsi)
>>>diff --git a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>>index 356e51515346..e065b8f2ee08 100644
>>>--- a/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>>+++ b/drivers/gpu/drm/i915/display/vlv_dsi_regs.h
>>>@@ -11,6 +11,8 @@
>>> #define VLV_MIPI_BASE VLV_DISPLAY_BASE
>>> #define BXT_MIPI_BASE 0x60000
>>>
>>>+#define _MIPI_MMIO_BASE(__i915) ((__i915)->display.dsi.mmio_base)
>>>+
>>> #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
>>> #define _MMIO_MIPI(port, a, c) _MMIO(_MIPI_PORT(port, a, c))
>>>
>>>@@ -96,8 +98,8 @@
>>>
>>> /* MIPI DSI Controller and D-PHY registers */
>>>
>>>-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
>>>-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
>>>+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
>>
>> ugh, and I thought we wouldn't have so many implicit params anymore.
>> Mind adding a "TODO: remove implicit dev_priv parameter" ?
>
>It's been on my private todo list like 10 years. :(
and we are finally removing that from the todo list soon. right? :)
Lucas De Marchi
>
>BR,
>Jani.
>
>
>>
>>
>> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>
>>
>> Lucas De Marchi
>
>--
>Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi
2022-08-17 7:21 ` Lucas De Marchi
@ 2022-08-17 7:54 ` Jani Nikula
0 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-17 7:54 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
On Wed, 17 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> On Wed, Aug 17, 2022 at 10:00:01AM +0300, Jani Nikula wrote:
>>On Tue, 16 Aug 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote:
>>> On Thu, Aug 11, 2022 at 06:07:35PM +0300, Jani Nikula wrote:
>>>>-#define _MIPIA_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb000)
>>>>-#define _MIPIC_DEVICE_READY (dev_priv->mipi_mmio_base + 0xb800)
>>>>+#define _MIPIA_DEVICE_READY (_MIPI_MMIO_BASE(dev_priv) + 0xb000)
>>>
>>> ugh, and I thought we wouldn't have so many implicit params anymore.
>>> Mind adding a "TODO: remove implicit dev_priv parameter" ?
>>
>>It's been on my private todo list like 10 years. :(
>
> and we are finally removing that from the todo list soon. right? :)
Maybe the perfect has been the enemy of the good here, too.
The simple thing to do is to just pass i915 to all register macros that
need it, and be done with it. It's a little bit of churn here and there,
not too bad.
But then some register macros need it, some don't, and it's all case by
case. What if we passed i915 to *all* register macros instead? Some
wouldn't need it and it would be all the same. But some could
benefit. See e.g. how HDCP_CONF() in intel_hdcp_regs.h adapts to
platforms. It's not really a style we use anywhere else, but should we
do that more instead of having it inline in code?
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 25/39] drm/i915: move vbt to display.vbt
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (23 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 24/39] drm/i915: move mipi_mmio_base to display.dsi Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 26/39] drm/i915: move fbc to display.fbc Jani Nikula
` (19 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 210 +++++++++---------
drivers/gpu/drm/i915/display/intel_crt.c | 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_display_core.h | 38 ++++
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 14 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 18 +-
drivers/gpu/drm/i915/display/intel_dsi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 4 +-
drivers/gpu/drm/i915/display/intel_panel.c | 2 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 18 +-
drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 37 ---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
15 files changed, 187 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 5923cce94c11..e06c38cbeea0 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -159,7 +159,7 @@ find_section(struct drm_i915_private *i915,
{
struct bdb_block_entry *entry;
- list_for_each_entry(entry, &i915->vbt.bdb_blocks, node) {
+ list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) {
if (entry->section_id == section_id)
return entry->data + 3;
}
@@ -501,7 +501,7 @@ init_bdb_block(struct drm_i915_private *i915,
return;
}
- list_add_tail(&entry->node, &i915->vbt.bdb_blocks);
+ list_add_tail(&entry->node, &i915->display.vbt.bdb_blocks);
}
static void init_bdb_blocks(struct drm_i915_private *i915,
@@ -878,7 +878,7 @@ parse_lfp_data(struct drm_i915_private *i915,
if (!tail)
return;
- if (i915->vbt.version >= 188) {
+ if (i915->display.vbt.version >= 188) {
panel->vbt.seamless_drrs_min_refresh_rate =
tail->seamless_drrs_min_refresh_rate[panel_type];
drm_dbg_kms(&i915->drm,
@@ -904,7 +904,7 @@ parse_generic_dtd(struct drm_i915_private *i915,
* first on VBT >= 229, but still fall back to trying the old LFP
* block if that fails.
*/
- if (i915->vbt.version < 229)
+ if (i915->display.vbt.version < 229)
return;
generic_dtd = find_section(i915, BDB_GENERIC_DTD);
@@ -1008,12 +1008,12 @@ parse_lfp_backlight(struct drm_i915_private *i915,
}
panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI;
- if (i915->vbt.version >= 191) {
+ if (i915->display.vbt.version >= 191) {
size_t exp_size;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
exp_size = sizeof(struct bdb_lfp_backlight_data);
- else if (i915->vbt.version >= 234)
+ else if (i915->display.vbt.version >= 234)
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234;
else
exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191;
@@ -1030,14 +1030,14 @@ parse_lfp_backlight(struct drm_i915_private *i915,
panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz;
panel->vbt.backlight.active_low_pwm = entry->active_low_pwm;
- if (i915->vbt.version >= 234) {
+ if (i915->display.vbt.version >= 234) {
u16 min_level;
bool scale;
level = backlight_data->brightness_level[panel_type].level;
min_level = backlight_data->brightness_min_level[panel_type].level;
- if (i915->vbt.version >= 236)
+ if (i915->display.vbt.version >= 236)
scale = backlight_data->brightness_precision_bits[panel_type] == 16;
else
scale = level > 255;
@@ -1134,37 +1134,37 @@ parse_general_features(struct drm_i915_private *i915)
if (!general)
return;
- i915->vbt.int_tv_support = general->int_tv_support;
+ i915->display.vbt.int_tv_support = general->int_tv_support;
/* int_crt_support can't be trusted on earlier platforms */
- if (i915->vbt.version >= 155 &&
+ if (i915->display.vbt.version >= 155 &&
(HAS_DDI(i915) || IS_VALLEYVIEW(i915)))
- i915->vbt.int_crt_support = general->int_crt_support;
- i915->vbt.lvds_use_ssc = general->enable_ssc;
- i915->vbt.lvds_ssc_freq =
+ i915->display.vbt.int_crt_support = general->int_crt_support;
+ i915->display.vbt.lvds_use_ssc = general->enable_ssc;
+ i915->display.vbt.lvds_ssc_freq =
intel_bios_ssc_frequency(i915, general->ssc_freq);
- i915->vbt.display_clock_mode = general->display_clock_mode;
- i915->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
- if (i915->vbt.version >= 181) {
- i915->vbt.orientation = general->rotate_180 ?
+ i915->display.vbt.display_clock_mode = general->display_clock_mode;
+ i915->display.vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
+ if (i915->display.vbt.version >= 181) {
+ i915->display.vbt.orientation = general->rotate_180 ?
DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP :
DRM_MODE_PANEL_ORIENTATION_NORMAL;
} else {
- i915->vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
+ i915->display.vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN;
}
- if (i915->vbt.version >= 249 && general->afc_startup_config) {
- i915->vbt.override_afc_startup = true;
- i915->vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
+ if (i915->display.vbt.version >= 249 && general->afc_startup_config) {
+ i915->display.vbt.override_afc_startup = true;
+ i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
}
drm_dbg_kms(&i915->drm,
"BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
- i915->vbt.int_tv_support,
- i915->vbt.int_crt_support,
- i915->vbt.lvds_use_ssc,
- i915->vbt.lvds_ssc_freq,
- i915->vbt.display_clock_mode,
- i915->vbt.fdi_rx_polarity_inverted);
+ i915->display.vbt.int_tv_support,
+ i915->display.vbt.int_crt_support,
+ i915->display.vbt.lvds_use_ssc,
+ i915->display.vbt.lvds_ssc_freq,
+ i915->display.vbt.display_clock_mode,
+ i915->display.vbt.fdi_rx_polarity_inverted);
}
static const struct child_device_config *
@@ -1190,7 +1190,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
return;
}
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (child->slave_addr != SLAVE_ADDR1 &&
@@ -1214,7 +1214,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *i915)
child->slave_addr,
(child->dvo_port == DEVICE_PORT_DVOB) ?
"SDVOB" : "SDVOC");
- mapping = &i915->vbt.sdvo_mappings[child->dvo_port - 1];
+ mapping = &i915->display.vbt.sdvo_mappings[child->dvo_port - 1];
if (!mapping->initialized) {
mapping->dvo_port = child->dvo_port;
mapping->slave_addr = child->slave_addr;
@@ -1265,7 +1265,7 @@ parse_driver_features(struct drm_i915_private *i915)
* interpretation, but real world VBTs seem to.
*/
if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS)
- i915->vbt.int_lvds_support = 0;
+ i915->display.vbt.int_lvds_support = 0;
} else {
/*
* FIXME it's not clear which BDB version has the LVDS config
@@ -1278,10 +1278,10 @@ parse_driver_features(struct drm_i915_private *i915)
* in the wild with the bits correctly populated. Version
* 108 (on i85x) does not have the bits correctly populated.
*/
- if (i915->vbt.version >= 134 &&
+ if (i915->display.vbt.version >= 134 &&
driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS &&
driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS)
- i915->vbt.int_lvds_support = 0;
+ i915->display.vbt.int_lvds_support = 0;
}
}
@@ -1295,7 +1295,7 @@ parse_panel_driver_features(struct drm_i915_private *i915,
if (!driver)
return;
- if (i915->vbt.version < 228) {
+ if (i915->display.vbt.version < 228) {
drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n",
driver->drrs_enabled);
/*
@@ -1328,7 +1328,7 @@ parse_power_conservation_features(struct drm_i915_private *i915,
panel->vbt.vrr = true; /* matches Windows behaviour */
- if (i915->vbt.version < 228)
+ if (i915->display.vbt.version < 228)
return;
power = find_section(i915, BDB_LFP_POWER);
@@ -1354,10 +1354,10 @@ parse_power_conservation_features(struct drm_i915_private *i915,
panel->vbt.drrs_type = DRRS_TYPE_NONE;
}
- if (i915->vbt.version >= 232)
+ if (i915->display.vbt.version >= 232)
panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type);
- if (i915->vbt.version >= 233)
+ if (i915->display.vbt.version >= 233)
panel->vbt.vrr = panel_bool(power->vrr_feature_enabled,
panel_type);
}
@@ -1393,7 +1393,7 @@ parse_edp(struct drm_i915_private *i915,
panel->vbt.edp.pps = *edp_pps;
- if (i915->vbt.version >= 224) {
+ if (i915->display.vbt.version >= 224) {
panel->vbt.edp.rate =
edp->edp_fast_link_training_rate[panel_type] * 20;
} else {
@@ -1472,7 +1472,7 @@ parse_edp(struct drm_i915_private *i915,
break;
}
- if (i915->vbt.version >= 173) {
+ if (i915->display.vbt.version >= 173) {
u8 vswing;
/* Don't read from VBT if module parameter has valid value*/
@@ -1488,7 +1488,7 @@ parse_edp(struct drm_i915_private *i915,
panel->vbt.edp.drrs_msa_timing_delay =
panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2);
- if (i915->vbt.version >= 244)
+ if (i915->display.vbt.version >= 244)
panel->vbt.edp.max_link_rate =
edp->edp_max_port_link_rate[panel_type] * 20;
}
@@ -1520,7 +1520,7 @@ parse_psr(struct drm_i915_private *i915,
* New psr options 0=500us, 1=100us, 2=2500us, 3=0us
* Old decimal value is wake up time in multiples of 100 us.
*/
- if (i915->vbt.version >= 205 &&
+ if (i915->display.vbt.version >= 205 &&
(DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) {
switch (psr_table->tp1_wakeup_time) {
case 0:
@@ -1566,7 +1566,7 @@ parse_psr(struct drm_i915_private *i915,
panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100;
}
- if (i915->vbt.version >= 226) {
+ if (i915->display.vbt.version >= 226) {
u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time;
wakeup_time = panel_bits(wakeup_time, panel_type, 2);
@@ -1596,7 +1596,7 @@ static void parse_dsi_backlight_ports(struct drm_i915_private *i915,
struct intel_panel *panel,
enum port port)
{
- if (!panel->vbt.dsi.config->dual_link || i915->vbt.version < 197) {
+ if (!panel->vbt.dsi.config->dual_link || i915->display.vbt.version < 197) {
panel->vbt.dsi.bl_ports = BIT(port);
if (panel->vbt.dsi.config->cabc_supported)
panel->vbt.dsi.cabc_ports = BIT(port);
@@ -2051,7 +2051,7 @@ parse_compression_parameters(struct drm_i915_private *i915)
u16 block_size;
int index;
- if (i915->vbt.version < 198)
+ if (i915->display.vbt.version < 198)
return;
params = find_section(i915, BDB_COMPRESSION_PARAMETERS);
@@ -2071,7 +2071,7 @@ parse_compression_parameters(struct drm_i915_private *i915)
}
}
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!child->compression_enable)
@@ -2205,7 +2205,7 @@ static enum port get_port_by_ddc_pin(struct drm_i915_private *i915, u8 ddc_pin)
return PORT_NONE;
for_each_port(port) {
- devdata = i915->vbt.ports[port];
+ devdata = i915->display.vbt.ports[port];
if (devdata && ddc_pin == devdata->child.ddc_pin)
return port;
@@ -2254,7 +2254,7 @@ static void sanitize_ddc_pin(struct intel_bios_encoder_data *devdata,
* there are real machines (eg. Asrock B250M-HDV) where VBT has both
* port A and port E with the same AUX ch and we must pick port E :(
*/
- child = &i915->vbt.ports[p]->child;
+ child = &i915->display.vbt.ports[p]->child;
child->device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING;
child->device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT;
@@ -2271,7 +2271,7 @@ static enum port get_port_by_aux_ch(struct drm_i915_private *i915, u8 aux_ch)
return PORT_NONE;
for_each_port(port) {
- devdata = i915->vbt.ports[port];
+ devdata = i915->display.vbt.ports[port];
if (devdata && aux_ch == devdata->child.aux_channel)
return port;
@@ -2306,7 +2306,7 @@ static void sanitize_aux_ch(struct intel_bios_encoder_data *devdata,
* there are real machines (eg. Asrock B250M-HDV) where VBT has both
* port A and port E with the same AUX ch and we must pick port E :(
*/
- child = &i915->vbt.ports[p]->child;
+ child = &i915->display.vbt.ports[p]->child;
child->device_type &= ~DEVICE_TYPE_DISPLAYPORT_OUTPUT;
child->aux_channel = 0;
@@ -2480,10 +2480,10 @@ static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate)
static int _intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 216)
+ if (!devdata || devdata->i915->display.vbt.version < 216)
return 0;
- if (devdata->i915->vbt.version >= 230)
+ if (devdata->i915->display.vbt.version >= 230)
return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate);
else
return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate);
@@ -2544,7 +2544,7 @@ intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata)
static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 158)
+ if (!devdata || devdata->i915->display.vbt.version < 158)
return -1;
return devdata->child.hdmi_level_shifter_value;
@@ -2552,7 +2552,7 @@ static int _intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *de
static int _intel_bios_max_tmds_clock(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 204)
+ if (!devdata || devdata->i915->display.vbt.version < 204)
return 0;
switch (devdata->child.hdmi_max_data_rate) {
@@ -2661,7 +2661,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
return;
}
- if (i915->vbt.ports[port]) {
+ if (i915->display.vbt.ports[port]) {
drm_dbg_kms(&i915->drm,
"More than one child device for port %c in VBT, using the first.\n",
port_name(port));
@@ -2676,7 +2676,7 @@ static void parse_ddi_port(struct intel_bios_encoder_data *devdata)
if (intel_bios_encoder_supports_dp(devdata))
sanitize_aux_ch(devdata, port);
- i915->vbt.ports[port] = devdata;
+ i915->display.vbt.ports[port] = devdata;
}
static bool has_ddi_port_info(struct drm_i915_private *i915)
@@ -2692,12 +2692,12 @@ static void parse_ddi_ports(struct drm_i915_private *i915)
if (!has_ddi_port_info(i915))
return;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node)
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node)
parse_ddi_port(devdata);
for_each_port(port) {
- if (i915->vbt.ports[port])
- print_ddi_port(i915->vbt.ports[port], port);
+ if (i915->display.vbt.ports[port])
+ print_ddi_port(i915->display.vbt.ports[port], port);
}
}
@@ -2730,33 +2730,33 @@ parse_general_definitions(struct drm_i915_private *i915)
bus_pin = defs->crt_ddc_gmbus_pin;
drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
if (intel_gmbus_is_valid_pin(i915, bus_pin))
- i915->vbt.crt_ddc_pin = bus_pin;
+ i915->display.vbt.crt_ddc_pin = bus_pin;
- if (i915->vbt.version < 106) {
+ if (i915->display.vbt.version < 106) {
expected_size = 22;
- } else if (i915->vbt.version < 111) {
+ } else if (i915->display.vbt.version < 111) {
expected_size = 27;
- } else if (i915->vbt.version < 195) {
+ } else if (i915->display.vbt.version < 195) {
expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE;
- } else if (i915->vbt.version == 195) {
+ } else if (i915->display.vbt.version == 195) {
expected_size = 37;
- } else if (i915->vbt.version <= 215) {
+ } else if (i915->display.vbt.version <= 215) {
expected_size = 38;
- } else if (i915->vbt.version <= 237) {
+ } else if (i915->display.vbt.version <= 237) {
expected_size = 39;
} else {
expected_size = sizeof(*child);
BUILD_BUG_ON(sizeof(*child) < 39);
drm_dbg(&i915->drm,
"Expected child device config size for VBT version %u not known; assuming %u\n",
- i915->vbt.version, expected_size);
+ i915->display.vbt.version, expected_size);
}
/* Flag an error for unexpected size, but continue anyway. */
if (defs->child_dev_size != expected_size)
drm_err(&i915->drm,
"Unexpected child device config size %u (expected %u for VBT version %u)\n",
- defs->child_dev_size, expected_size, i915->vbt.version);
+ defs->child_dev_size, expected_size, i915->display.vbt.version);
/* The legacy sized child device config is the minimum we need. */
if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) {
@@ -2792,10 +2792,10 @@ parse_general_definitions(struct drm_i915_private *i915)
memcpy(&devdata->child, child,
min_t(size_t, defs->child_dev_size, sizeof(*child)));
- list_add_tail(&devdata->node, &i915->vbt.display_devices);
+ list_add_tail(&devdata->node, &i915->display.vbt.display_devices);
}
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
drm_dbg_kms(&i915->drm,
"no child dev is parsed from VBT\n");
}
@@ -2804,25 +2804,25 @@ parse_general_definitions(struct drm_i915_private *i915)
static void
init_vbt_defaults(struct drm_i915_private *i915)
{
- i915->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
+ i915->display.vbt.crt_ddc_pin = GMBUS_PIN_VGADDC;
/* general features */
- i915->vbt.int_tv_support = 1;
- i915->vbt.int_crt_support = 1;
+ i915->display.vbt.int_tv_support = 1;
+ i915->display.vbt.int_crt_support = 1;
/* driver features */
- i915->vbt.int_lvds_support = 1;
+ i915->display.vbt.int_lvds_support = 1;
/* Default to using SSC */
- i915->vbt.lvds_use_ssc = 1;
+ i915->display.vbt.lvds_use_ssc = 1;
/*
* Core/SandyBridge/IvyBridge use alternative (120MHz) reference
* clock for LVDS.
*/
- i915->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
+ i915->display.vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
!HAS_PCH_SPLIT(i915));
drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n",
- i915->vbt.lvds_ssc_freq);
+ i915->display.vbt.lvds_ssc_freq);
}
/* Common defaults which may be overridden by VBT. */
@@ -2883,7 +2883,7 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
if (port == PORT_A)
child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR;
- list_add_tail(&devdata->node, &i915->vbt.display_devices);
+ list_add_tail(&devdata->node, &i915->display.vbt.display_devices);
drm_dbg_kms(&i915->drm,
"Generating default VBT child device with type 0x04%x on port %c\n",
@@ -2891,7 +2891,7 @@ init_vbt_missing_defaults(struct drm_i915_private *i915)
}
/* Bypass some minimum baseline VBT version checks */
- i915->vbt.version = 155;
+ i915->display.vbt.version = 155;
}
static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt)
@@ -3082,8 +3082,8 @@ void intel_bios_init(struct drm_i915_private *i915)
struct vbt_header *oprom_vbt = NULL;
const struct bdb_header *bdb;
- INIT_LIST_HEAD(&i915->vbt.display_devices);
- INIT_LIST_HEAD(&i915->vbt.bdb_blocks);
+ INIT_LIST_HEAD(&i915->display.vbt.display_devices);
+ INIT_LIST_HEAD(&i915->display.vbt.bdb_blocks);
if (!HAS_DISPLAY(i915)) {
drm_dbg_kms(&i915->drm,
@@ -3111,11 +3111,11 @@ void intel_bios_init(struct drm_i915_private *i915)
goto out;
bdb = get_bdb_header(vbt);
- i915->vbt.version = bdb->version;
+ i915->display.vbt.version = bdb->version;
drm_dbg_kms(&i915->drm,
"VBT signature \"%.*s\", BDB version %d\n",
- (int)sizeof(vbt->signature), vbt->signature, i915->vbt.version);
+ (int)sizeof(vbt->signature), vbt->signature, i915->display.vbt.version);
init_bdb_blocks(i915, bdb);
@@ -3172,13 +3172,13 @@ void intel_bios_driver_remove(struct drm_i915_private *i915)
struct intel_bios_encoder_data *devdata, *nd;
struct bdb_block_entry *entry, *ne;
- list_for_each_entry_safe(devdata, nd, &i915->vbt.display_devices, node) {
+ list_for_each_entry_safe(devdata, nd, &i915->display.vbt.display_devices, node) {
list_del(&devdata->node);
kfree(devdata->dsc);
kfree(devdata);
}
- list_for_each_entry_safe(entry, ne, &i915->vbt.bdb_blocks, node) {
+ list_for_each_entry_safe(entry, ne, &i915->display.vbt.bdb_blocks, node) {
list_del(&entry->node);
kfree(entry);
}
@@ -3212,13 +3212,13 @@ bool intel_bios_is_tv_present(struct drm_i915_private *i915)
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- if (!i915->vbt.int_tv_support)
+ if (!i915->display.vbt.int_tv_support)
return false;
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
return true;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
/*
@@ -3255,10 +3255,10 @@ bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin)
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- if (list_empty(&i915->vbt.display_devices))
+ if (list_empty(&i915->display.vbt.display_devices))
return true;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
/* If the device type is not LFP, continue.
@@ -3304,7 +3304,7 @@ bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port)
if (WARN_ON(!has_ddi_port_info(i915)))
return true;
- return i915->vbt.ports[port];
+ return i915->display.vbt.ports[port];
}
/**
@@ -3364,7 +3364,7 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *i915,
const struct child_device_config *child;
u8 dvo_port;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
@@ -3463,7 +3463,7 @@ bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
const struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
- list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+ list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) {
child = &devdata->child;
if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
@@ -3494,7 +3494,7 @@ bool
intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
if (drm_WARN_ON_ONCE(&i915->drm,
!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)))
@@ -3514,7 +3514,7 @@ bool
intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
return HAS_LSPCON(i915) && devdata && devdata->child.lspcon;
}
@@ -3530,7 +3530,7 @@ bool
intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
return devdata && devdata->child.lane_reversal;
}
@@ -3538,7 +3538,7 @@ intel_bios_is_lane_reversal_needed(const struct drm_i915_private *i915,
enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
enum port port)
{
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[port];
enum aux_ch aux_ch;
if (!devdata || !devdata->child.aux_channel) {
@@ -3632,7 +3632,7 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_max_tmds_clock(devdata);
}
@@ -3641,14 +3641,14 @@ int intel_bios_max_tmds_clock(struct intel_encoder *encoder)
int intel_bios_hdmi_level_shift(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_hdmi_level_shift(devdata);
}
int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
+ if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
return translate_iboost(devdata->child.dp_iboost_level);
@@ -3656,7 +3656,7 @@ int intel_bios_encoder_dp_boost_level(const struct intel_bios_encoder_data *devd
int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *devdata)
{
- if (!devdata || devdata->i915->vbt.version < 196 || !devdata->child.iboost)
+ if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost)
return 0;
return translate_iboost(devdata->child.hdmi_iboost_level);
@@ -3665,7 +3665,7 @@ int intel_bios_encoder_hdmi_boost_level(const struct intel_bios_encoder_data *de
int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
return _intel_bios_dp_max_link_rate(devdata);
}
@@ -3673,7 +3673,7 @@ int intel_bios_dp_max_link_rate(struct intel_encoder *encoder)
int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- const struct intel_bios_encoder_data *devdata = i915->vbt.ports[encoder->port];
+ const struct intel_bios_encoder_data *devdata = i915->display.vbt.ports[encoder->port];
if (!devdata || !devdata->child.ddc_pin)
return 0;
@@ -3683,16 +3683,16 @@ int intel_bios_alternate_ddc_pin(struct intel_encoder *encoder)
bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
{
- return devdata->i915->vbt.version >= 195 && devdata->child.dp_usb_type_c;
+ return devdata->i915->display.vbt.version >= 195 && devdata->child.dp_usb_type_c;
}
bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
{
- return devdata->i915->vbt.version >= 209 && devdata->child.tbt;
+ return devdata->i915->display.vbt.version >= 209 && devdata->child.tbt;
}
const struct intel_bios_encoder_data *
intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port)
{
- return i915->vbt.ports[port];
+ return i915->display.vbt.ports[port];
}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 6a3893c8ff22..760b5788eb43 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -645,7 +645,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
- i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
+ i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
edid = intel_crt_get_edid(connector, i2c);
if (edid) {
@@ -931,7 +931,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
- i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin);
+ i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->display.vbt.crt_ddc_pin);
ret = intel_crt_ddc_get_modes(connector, i2c);
if (ret || !IS_G4X(dev_priv))
goto out;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6c352db1f7aa..f98ca4debcbe 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2772,12 +2772,12 @@ static void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
PCH_DREF_CONTROL) &
DREF_SSC1_ENABLE;
- if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
+ if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
drm_dbg_kms(&dev_priv->drm,
"SSC %s by BIOS, overriding VBT which says %s\n",
str_enabled_disabled(bios_lvds_use_ssc),
- str_enabled_disabled(dev_priv->vbt.lvds_use_ssc));
- dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
+ str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
+ dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
}
}
}
@@ -4373,7 +4373,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
u32 dpll = pipe_config->dpll_hw_state.dpll;
if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
- return dev_priv->vbt.lvds_ssc_freq;
+ return dev_priv->display.vbt.lvds_ssc_freq;
else if (HAS_PCH_SPLIT(dev_priv))
return 120000;
else if (DISPLAY_VER(dev_priv) != 2)
@@ -7923,7 +7923,7 @@ static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
return false;
- if (!dev_priv->vbt.int_crt_support)
+ if (!dev_priv->display.vbt.int_crt_support)
return false;
return true;
@@ -8058,7 +8058,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bool has_edp, has_port;
- if (IS_VALLEYVIEW(dev_priv) && dev_priv->vbt.int_crt_support)
+ if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
intel_crt_init(dev_priv);
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index db1ba379797e..861178f969bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -6,11 +6,14 @@
#ifndef __INTEL_DISPLAY_CORE_H__
#define __INTEL_DISPLAY_CORE_H__
+#include <linux/list.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
+#include <drm/drm_connector.h>
+
#include "intel_cdclk.h"
#include "intel_display.h"
#include "intel_dmc.h"
@@ -25,6 +28,7 @@ struct i915_audio_component;
struct i915_hdcp_comp_master;
struct intel_atomic_state;
struct intel_audio_funcs;
+struct intel_bios_encoder_data;
struct intel_cdclk_funcs;
struct intel_cdclk_vals;
struct intel_clock_gating_funcs;
@@ -152,6 +156,39 @@ struct intel_hotplug {
struct workqueue_struct *dp_wq;
};
+struct intel_vbt_data {
+ /* bdb version */
+ u16 version;
+
+ /* Feature bits */
+ unsigned int int_tv_support:1;
+ unsigned int int_crt_support:1;
+ unsigned int lvds_use_ssc:1;
+ unsigned int int_lvds_support:1;
+ unsigned int display_clock_mode:1;
+ unsigned int fdi_rx_polarity_inverted:1;
+ int lvds_ssc_freq;
+ enum drm_panel_orientation orientation;
+
+ bool override_afc_startup;
+ u8 override_afc_startup_val;
+
+ int crt_ddc_pin;
+
+ struct list_head display_devices;
+ struct list_head bdb_blocks;
+
+ struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
+ struct sdvo_device_mapping {
+ u8 initialized;
+ u8 dvo_port;
+ u8 slave_addr;
+ u8 dvo_wiring;
+ u8 i2c_pin;
+ u8 ddc_pin;
+ } sdvo_mappings[2];
+};
+
struct intel_wm {
/*
* Raw watermark latency values:
@@ -313,6 +350,7 @@ struct intel_display {
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
+ struct intel_vbt_data vbt;
struct intel_wm wm;
};
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9b5d96ce3aa0..935ec3661aa2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5183,7 +5183,7 @@ intel_edp_add_properties(struct intel_dp *intel_dp)
return;
drm_connector_set_panel_orientation_with_quirk(&connector->base,
- i915->vbt.orientation,
+ i915->display.vbt.orientation,
fixed_mode->hdisplay,
fixed_mode->vdisplay);
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 87899702a522..81655fdf2c89 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -991,7 +991,7 @@ static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state,
factor = 21;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if ((intel_panel_use_ssc(dev_priv) &&
- dev_priv->vbt.lvds_ssc_freq == 100000) ||
+ dev_priv->display.vbt.lvds_ssc_freq == 100000) ||
(HAS_PCH_IBX(dev_priv) &&
intel_is_dual_link_lvds(dev_priv)))
factor = 25;
@@ -1105,8 +1105,8 @@ static int ilk_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_panel_use_ssc(dev_priv)) {
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
- dev_priv->vbt.lvds_ssc_freq);
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ dev_priv->display.vbt.lvds_ssc_freq);
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
}
if (intel_is_dual_link_lvds(dev_priv)) {
@@ -1231,7 +1231,7 @@ static int g4x_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1273,7 +1273,7 @@ static int pnv_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1306,7 +1306,7 @@ static int i9xx_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
@@ -1339,7 +1339,7 @@ static int i8xx_crtc_compute_clock(struct intel_atomic_state *state,
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
if (intel_panel_use_ssc(dev_priv)) {
- refclk = dev_priv->vbt.lvds_ssc_freq;
+ refclk = dev_priv->display.vbt.lvds_ssc_freq;
drm_dbg_kms(&dev_priv->drm,
"using SSC reference clock of %d kHz\n",
refclk);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index d324bc8b5ef0..4c79e15d156d 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2769,8 +2769,8 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
else
pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
- if (i915->vbt.override_afc_startup)
- pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->vbt.override_afc_startup_val);
+ if (i915->display.vbt.override_afc_startup)
+ pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
}
static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
@@ -2965,8 +2965,8 @@ static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
DKL_PLL_DIV0_FBPREDIV(m1div) |
DKL_PLL_DIV0_FBDIV_INT(m2div_int);
- if (dev_priv->vbt.override_afc_startup) {
- u8 val = dev_priv->vbt.override_afc_startup_val;
+ if (dev_priv->display.vbt.override_afc_startup) {
+ u8 val = dev_priv->display.vbt.override_afc_startup_val;
pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
}
@@ -3502,7 +3502,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
hw_state->mg_pll_div0 = intel_de_read(dev_priv, DKL_PLL_DIV0(tc_port));
val = DKL_PLL_DIV0_MASK;
- if (dev_priv->vbt.override_afc_startup)
+ if (dev_priv->display.vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
hw_state->mg_pll_div0 &= val;
@@ -3566,7 +3566,7 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
TGL_DPLL_CFGCR0(id));
hw_state->cfgcr1 = intel_de_read(dev_priv,
TGL_DPLL_CFGCR1(id));
- if (dev_priv->vbt.override_afc_startup) {
+ if (dev_priv->display.vbt.override_afc_startup) {
hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id));
hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
}
@@ -3638,9 +3638,9 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
- drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->vbt.override_afc_startup &&
+ drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->display.vbt.override_afc_startup &&
!i915_mmio_reg_valid(div0_reg));
- if (dev_priv->vbt.override_afc_startup &&
+ if (dev_priv->display.vbt.override_afc_startup &&
i915_mmio_reg_valid(div0_reg))
intel_de_rmw(dev_priv, div0_reg, TGL_DPLL0_DIV0_AFC_STARTUP_MASK,
hw_state->div0);
@@ -3732,7 +3732,7 @@ static void dkl_pll_write(struct drm_i915_private *dev_priv,
intel_de_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
val = DKL_PLL_DIV0_MASK;
- if (dev_priv->vbt.override_afc_startup)
+ if (dev_priv->display.vbt.override_afc_startup)
val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
intel_de_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val,
hw_state->mg_pll_div0);
diff --git a/drivers/gpu/drm/i915/display/intel_dsi.c b/drivers/gpu/drm/i915/display/intel_dsi.c
index 35e121cd226c..5efdd471ac2b 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi.c
@@ -106,7 +106,7 @@ intel_dsi_get_panel_orientation(struct intel_connector *connector)
if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return orientation;
- orientation = dev_priv->vbt.orientation;
+ orientation = dev_priv->display.vbt.orientation;
if (orientation != DRM_MODE_PANEL_ORIENTATION_UNKNOWN)
return orientation;
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 730480ac3300..9aa38e8141b5 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -837,12 +837,12 @@ void intel_lvds_init(struct drm_i915_private *dev_priv)
/* Skip init on machines we know falsely report LVDS */
if (dmi_check_system(intel_no_lvds)) {
- drm_WARN(dev, !dev_priv->vbt.int_lvds_support,
+ drm_WARN(dev, !dev_priv->display.vbt.int_lvds_support,
"Useless DMI match. Internal LVDS support disabled by VBT\n");
return;
}
- if (!dev_priv->vbt.int_lvds_support) {
+ if (!dev_priv->display.vbt.int_lvds_support) {
drm_dbg_kms(&dev_priv->drm,
"Internal LVDS support disabled by VBT\n");
return;
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 237a40623dd7..43dbc5a3ec37 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -42,7 +42,7 @@ bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
if (i915->params.panel_use_ssc >= 0)
return i915->params.panel_use_ssc != 0;
- return i915->vbt.lvds_use_ssc
+ return i915->display.vbt.lvds_use_ssc
&& !(i915->quirks & QUIRK_LVDS_SSC_DISABLE);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index ee72400759a3..33bd4d7df465 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -514,7 +514,7 @@ static void ilk_init_pch_refclk(struct drm_i915_private *dev_priv)
}
if (HAS_PCH_IBX(dev_priv)) {
- has_ck505 = dev_priv->vbt.display_clock_mode;
+ has_ck505 = dev_priv->display.vbt.display_clock_mode;
can_ssc = has_ck505;
} else {
has_ck505 = false;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 19122bc6d2ab..f5b744bef18f 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2016,7 +2016,7 @@ intel_sdvo_get_analog_edid(struct drm_connector *connector)
return drm_get_edid(connector,
intel_gmbus_get_adapter(dev_priv,
- dev_priv->vbt.crt_ddc_pin));
+ dev_priv->display.vbt.crt_ddc_pin));
}
static enum drm_connector_status
@@ -2581,9 +2581,9 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
struct sdvo_device_mapping *mapping;
if (sdvo->port == PORT_B)
- mapping = &dev_priv->vbt.sdvo_mappings[0];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[0];
else
- mapping = &dev_priv->vbt.sdvo_mappings[1];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized)
sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
@@ -2599,9 +2599,9 @@ intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
u8 pin;
if (sdvo->port == PORT_B)
- mapping = &dev_priv->vbt.sdvo_mappings[0];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[0];
else
- mapping = &dev_priv->vbt.sdvo_mappings[1];
+ mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized &&
intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
@@ -2639,11 +2639,11 @@ intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
struct sdvo_device_mapping *my_mapping, *other_mapping;
if (sdvo->port == PORT_B) {
- my_mapping = &dev_priv->vbt.sdvo_mappings[0];
- other_mapping = &dev_priv->vbt.sdvo_mappings[1];
+ my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
+ other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
} else {
- my_mapping = &dev_priv->vbt.sdvo_mappings[1];
- other_mapping = &dev_priv->vbt.sdvo_mappings[0];
+ my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
+ other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
}
/* If the BIOS described our SDVO device, take advantage of it. */
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 509b0a419c20..d474f5130aea 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -362,10 +362,10 @@ enum vbt_gmbus_ddi {
* basically any of the fields to ensure the correct interpretation for the BDB
* version in question.
*
- * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve
- * space for the full structure below, and initialize the tail not actually
- * present in VBT to zeros. Accessing those fields is fine, as long as the
- * default zero is taken into account, again according to the BDB version.
+ * When we copy the child device configs to dev_priv->display.vbt.child_dev, we
+ * reserve space for the full structure below, and initialize the tail not
+ * actually present in VBT to zeros. Accessing those fields is fine, as long as
+ * the default zero is taken into account, again according to the BDB version.
*
* BDB versions 155 and below are considered legacy, and version 155 seems to be
* a baseline for some of the VBT documentation. When adding new fields, please
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f22f27cb038..0dc3983eba84 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -34,7 +34,6 @@
#include <linux/pm_qos.h>
-#include <drm/drm_connector.h>
#include <drm/ttm/ttm_device.h>
#include "display/intel_display.h"
@@ -89,15 +88,6 @@ struct vlv_s0ix_state;
I915_GEM_DOMAIN_INSTRUCTION | \
I915_GEM_DOMAIN_VERTEX)
-struct sdvo_device_mapping {
- u8 initialized;
- u8 dvo_port;
- u8 slave_addr;
- u8 dvo_wiring;
- u8 i2c_pin;
- u8 ddc_pin;
-};
-
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
@@ -198,32 +188,6 @@ i915_fence_timeout(const struct drm_i915_private *i915)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-struct intel_vbt_data {
- /* bdb version */
- u16 version;
-
- /* Feature bits */
- unsigned int int_tv_support:1;
- unsigned int int_crt_support:1;
- unsigned int lvds_use_ssc:1;
- unsigned int int_lvds_support:1;
- unsigned int display_clock_mode:1;
- unsigned int fdi_rx_polarity_inverted:1;
- int lvds_ssc_freq;
- enum drm_panel_orientation orientation;
-
- bool override_afc_startup;
- u8 override_afc_startup_val;
-
- int crt_ddc_pin;
-
- struct list_head display_devices;
- struct list_head bdb_blocks;
-
- struct intel_bios_encoder_data *ports[I915_MAX_PORTS]; /* Non-NULL if port present. */
- struct sdvo_device_mapping sdvo_mappings[2];
-};
-
struct i915_frontbuffer_tracking {
spinlock_t lock;
@@ -321,7 +285,6 @@ struct drm_i915_private {
u32 pipestat_irq_mask[I915_MAX_PIPES];
struct intel_fbc *fbc[I915_MAX_FBCS];
- struct intel_vbt_data vbt;
bool preserve_bios_swizzle;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f72481e85ebd..89eea3f9dd72 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7435,7 +7435,7 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
val = intel_uncore_read(&dev_priv->uncore, TRANS_CHICKEN2(pipe));
val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
- if (dev_priv->vbt.fdi_rx_polarity_inverted)
+ if (dev_priv->display.vbt.fdi_rx_polarity_inverted)
val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 26/39] drm/i915: move fbc to display.fbc
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (24 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 25/39] drm/i915: move vbt to display.vbt Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 27/39] drm/i915/vrr: drop window2_delay member from i915 Jani Nikula
` (18 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Pointers and arrays of pointers to structs that we defined are fine
without a sub-struct wrapping.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 2 ++
drivers/gpu/drm/i915/display/intel_fbc.c | 6 +++---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ---
5 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 0f35f2facdfc..5afbe3e98ee8 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -125,7 +125,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct drm_i915_private *dev_priv,
enum i9xx_plane_id i9xx_plane)
{
if (i9xx_plane_has_fbc(dev_priv, i9xx_plane))
- return dev_priv->fbc[INTEL_FBC_A];
+ return dev_priv->display.fbc[INTEL_FBC_A];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 861178f969bd..066e7ee0b8df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -18,6 +18,7 @@
#include "intel_display.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
+#include "intel_fbc.h"
#include "intel_global_state.h"
#include "intel_gmbus.h"
#include "intel_opregion.h"
@@ -347,6 +348,7 @@ struct intel_display {
struct intel_audio audio;
struct intel_dmc dmc;
struct intel_dpll dpll;
+ struct intel_fbc *fbc[I915_MAX_FBCS];
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 7436b35f7ea0..5e8e29a4559f 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -59,7 +59,7 @@
#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \
for_each_fbc_id((__dev_priv), (__fbc_id)) \
- for_each_if((__fbc) = (__dev_priv)->fbc[(__fbc_id)])
+ for_each_if((__fbc) = (__dev_priv)->display.fbc[(__fbc_id)])
struct intel_fbc_funcs {
void (*activate)(struct intel_fbc *fbc);
@@ -1720,7 +1720,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
i915->params.enable_fbc);
for_each_fbc_id(i915, fbc_id)
- i915->fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
+ i915->display.fbc[fbc_id] = intel_fbc_create(i915, fbc_id);
}
/**
@@ -1840,7 +1840,7 @@ void intel_fbc_debugfs_register(struct drm_i915_private *i915)
struct drm_minor *minor = i915->drm.primary;
struct intel_fbc *fbc;
- fbc = i915->fbc[INTEL_FBC_A];
+ fbc = i915->display.fbc[INTEL_FBC_A];
if (fbc)
intel_fbc_debugfs_add(fbc, minor->debugfs_root);
}
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 4d6a27757065..594cda11382d 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1940,7 +1940,7 @@ static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
- return dev_priv->fbc[fbc_id];
+ return dev_priv->display.fbc[fbc_id];
else
return NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0dc3983eba84..752eeccb94eb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -40,7 +40,6 @@
#include "display/intel_display_core.h"
#include "display/intel_display_power.h"
#include "display/intel_dsb.h"
-#include "display/intel_fbc.h"
#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_context_types.h"
@@ -284,8 +283,6 @@ struct drm_i915_private {
};
u32 pipestat_irq_mask[I915_MAX_PIPES];
- struct intel_fbc *fbc[I915_MAX_FBCS];
-
bool preserve_bios_swizzle;
unsigned int fsb_freq, mem_freq, is_ddr3;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 27/39] drm/i915/vrr: drop window2_delay member from i915
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (25 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 26/39] drm/i915: move fbc to display.fbc Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power Jani Nikula
` (17 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
The window2_delay member has been functionally unused (always set to 0)
since it was added in commit bb265dbdf38d ("drm/i915/xelpd: Add VRR
guardband for VRR CTL"). Replace it with a FIXME comment.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 2 --
drivers/gpu/drm/i915/display/intel_vrr.c | 14 ++++++++++----
drivers/gpu/drm/i915/i915_drv.h | 3 ---
3 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f98ca4debcbe..5bf062adf9ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8685,8 +8685,6 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
- i915->window2_delay = 0; /* No DSB so no window2 delay */
-
intel_mode_config_init(i915);
ret = intel_cdclk_init(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 04250a0fec3c..291374689ee7 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -142,11 +142,16 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
* For XE_LPD+, we use guardband and pipeline override
* is deprecated.
*/
- if (DISPLAY_VER(i915) >= 13)
+ if (DISPLAY_VER(i915) >= 13) {
+ /*
+ * FIXME: Substract Window2 delay from below value.
+ *
+ * Window2 specifies time required to program DSB (Window2) in
+ * number of scan lines. Assuming 0 for no DSB.
+ */
crtc_state->vrr.guardband =
- crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
- i915->window2_delay;
- else
+ crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay;
+ } else {
/*
* FIXME: s/4/framestart_delay/ to get consistent
* earliest/latest points for register latching regardless
@@ -159,6 +164,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
*/
crtc_state->vrr.pipeline_full =
min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+ }
crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 752eeccb94eb..6fa5ab1f173f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -426,9 +426,6 @@ struct drm_i915_private {
struct file *mmap_singleton;
} gem;
- /* Window2 specifies time required to program DSB (Window2) in number of scan lines */
- u8 window2_delay;
-
u8 pch_ssc_use;
/* For i915gm/i945gm vblank irq workaround */
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (26 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 27/39] drm/i915/vrr: drop window2_delay member from i915 Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:41 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 29/39] drm/i915: move and group fdi members under display.fdi Jani Nikula
` (16 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Arguably chv_phy_control and chv_phy_assert could be placed in a phy
substruct, but they are only used in the power code.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 11 ++
.../drm/i915/display/intel_display_power.c | 112 +++++++++---------
.../i915/display/intel_display_power_map.c | 4 +-
.../i915/display/intel_display_power_well.c | 56 ++++-----
.../i915/display/intel_display_power_well.h | 12 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 20 +---
8 files changed, 110 insertions(+), 109 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 066e7ee0b8df..19abdd05d413 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -16,6 +16,7 @@
#include "intel_cdclk.h"
#include "intel_display.h"
+#include "intel_display_power.h"
#include "intel_dmc.h"
#include "intel_dpll_mgr.h"
#include "intel_fbc.h"
@@ -326,6 +327,16 @@ struct intel_display {
struct mutex comp_mutex;
} hdcp;
+ struct {
+ struct i915_power_domains domains;
+
+ /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
+ u32 chv_phy_control;
+
+ /* perform PHY state sanity checks? */
+ bool chv_phy_assert[2];
+ } power;
+
struct {
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index a25e632c726f..9960b7f59146 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -243,7 +243,7 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains;
bool ret;
- power_domains = &dev_priv->power_domains;
+ power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
ret = __intel_display_power_is_enabled(dev_priv, domain);
@@ -291,7 +291,7 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
{
struct i915_power_well *power_well;
bool dc_off_enabled;
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
@@ -339,7 +339,7 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
return !drm_WARN_ON(&i915->drm,
bitmap_intersects(power_domains->async_put_domains[0].bits,
@@ -352,7 +352,7 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
struct intel_power_domain_mask async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
@@ -375,7 +375,7 @@ static void print_power_domains(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
enum intel_display_power_domain domain;
drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
@@ -390,7 +390,7 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
drm_dbg(&i915->drm, "async_put_wakeref %u\n",
power_domains->async_put_wakeref);
@@ -445,7 +445,7 @@ static bool
intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct intel_power_domain_mask async_put_mask;
bool ret = false;
@@ -474,7 +474,7 @@ static void
__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
@@ -501,7 +501,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
intel_wakeref_t wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
mutex_lock(&power_domains->lock);
@@ -527,7 +527,7 @@ intel_wakeref_t
intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
intel_wakeref_t wakeref;
bool is_enabled;
@@ -563,7 +563,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
const char *name = intel_display_power_domain_str(domain);
struct intel_power_domain_mask async_put_mask;
- power_domains = &dev_priv->power_domains;
+ power_domains = &dev_priv->display.power.domains;
drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
"Use count on domain %s is already zero\n",
@@ -583,7 +583,7 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
static void __intel_display_power_put(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
mutex_lock(&power_domains->lock);
__intel_display_power_put_domain(dev_priv, domain);
@@ -596,7 +596,7 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
drm_WARN_ON(&i915->drm, power_domains->async_put_wakeref);
power_domains->async_put_wakeref = wakeref;
drm_WARN_ON(&i915->drm, !queue_delayed_work(system_unbound_wq,
@@ -610,7 +610,7 @@ release_async_put_domains(struct i915_power_domains *power_domains,
{
struct drm_i915_private *dev_priv =
container_of(power_domains, struct drm_i915_private,
- power_domains);
+ display.power.domains);
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
enum intel_display_power_domain domain;
intel_wakeref_t wakeref;
@@ -637,8 +637,8 @@ intel_display_power_put_async_work(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private,
- power_domains.async_put_work.work);
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ display.power.domains.async_put_work.work);
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
intel_wakeref_t new_work_wakeref = intel_runtime_pm_get_raw(rpm);
intel_wakeref_t old_work_wakeref = 0;
@@ -698,7 +698,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
enum intel_display_power_domain domain,
intel_wakeref_t wakeref)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct intel_runtime_pm *rpm = &i915->runtime_pm;
intel_wakeref_t work_wakeref = intel_runtime_pm_get_raw(rpm);
@@ -746,7 +746,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
*/
void intel_display_power_flush_work(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct intel_power_domain_mask async_put_mask;
intel_wakeref_t work_wakeref;
@@ -779,7 +779,7 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
static void
intel_display_power_flush_work_sync(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
intel_display_power_flush_work(i915);
cancel_delayed_work_sync(&power_domains->async_put_work);
@@ -976,7 +976,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
*/
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
@@ -1003,12 +1003,12 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
{
- intel_display_power_map_cleanup(&dev_priv->power_domains);
+ intel_display_power_map_cleanup(&dev_priv->display.power.domains);
}
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -1037,7 +1037,7 @@ static void gen9_dbuf_slice_set(struct drm_i915_private *dev_priv,
void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
enum dbuf_slice slice;
@@ -1394,7 +1394,7 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
static void skl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1426,7 +1426,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1460,7 +1460,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
@@ -1494,7 +1494,7 @@ static void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume
static void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1603,7 +1603,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
static void icl_display_core_init(struct drm_i915_private *dev_priv,
bool resume)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
u32 val;
@@ -1678,7 +1678,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
struct i915_power_well *well;
if (!HAS_DISPLAY(dev_priv))
@@ -1723,7 +1723,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* power well state and lane status to reconstruct the
* expected initial value.
*/
- dev_priv->chv_phy_control =
+ dev_priv->display.power.chv_phy_control =
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
@@ -1745,27 +1745,27 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
mask = (status & DPLL_PORTC_READY_MASK) >> 4;
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
- dev_priv->chv_phy_assert[DPIO_PHY0] = false;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY0] = true;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY0] = true;
}
if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
@@ -1777,21 +1777,21 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
if (mask == 0xf)
mask = 0x0;
else
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |=
+ dev_priv->display.power.chv_phy_control |=
PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
- dev_priv->chv_phy_assert[DPIO_PHY1] = false;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = false;
} else {
- dev_priv->chv_phy_assert[DPIO_PHY1] = true;
+ dev_priv->display.power.chv_phy_assert[DPIO_PHY1] = true;
}
drm_dbg_kms(&dev_priv->drm, "Initial PHY_CONTROL=0x%08x\n",
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
/* Defer application of initial phy_control to enabling the powerwell */
}
@@ -1875,7 +1875,7 @@ static void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
*/
void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
power_domains->initializing = true;
@@ -1916,7 +1916,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
/* Disable power support if the user asked so. */
if (!i915->params.disable_power_well) {
drm_WARN_ON(&i915->drm, power_domains->disable_wakeref);
- i915->power_domains.disable_wakeref = intel_display_power_get(i915,
+ i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
POWER_DOMAIN_INIT);
}
intel_power_domains_sync_hw(i915);
@@ -1938,12 +1938,12 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume)
void intel_power_domains_driver_remove(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->power_domains.init_wakeref);
+ fetch_and_zero(&i915->display.power.domains.init_wakeref);
/* Remove the refcount we took to keep power well support disabled. */
if (!i915->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->power_domains.disable_wakeref));
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
intel_display_power_flush_work_sync(i915);
@@ -1965,7 +1965,7 @@ void intel_power_domains_driver_remove(struct drm_i915_private *i915)
*/
void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
mutex_lock(&power_domains->lock);
@@ -1999,7 +1999,7 @@ void intel_power_domains_sanitize_state(struct drm_i915_private *i915)
void intel_power_domains_enable(struct drm_i915_private *i915)
{
intel_wakeref_t wakeref __maybe_unused =
- fetch_and_zero(&i915->power_domains.init_wakeref);
+ fetch_and_zero(&i915->display.power.domains.init_wakeref);
intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
intel_power_domains_verify_state(i915);
@@ -2014,7 +2014,7 @@ void intel_power_domains_enable(struct drm_i915_private *i915)
*/
void intel_power_domains_disable(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
drm_WARN_ON(&i915->drm, power_domains->init_wakeref);
power_domains->init_wakeref =
@@ -2037,7 +2037,7 @@ void intel_power_domains_disable(struct drm_i915_private *i915)
void intel_power_domains_suspend(struct drm_i915_private *i915,
enum i915_drm_suspend_mode suspend_mode)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
intel_wakeref_t wakeref __maybe_unused =
fetch_and_zero(&power_domains->init_wakeref);
@@ -2064,7 +2064,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
if (!i915->params.disable_power_well)
intel_display_power_put(i915, POWER_DOMAIN_INIT,
- fetch_and_zero(&i915->power_domains.disable_wakeref));
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
intel_display_power_flush_work(i915);
intel_power_domains_verify_state(i915);
@@ -2091,7 +2091,7 @@ void intel_power_domains_suspend(struct drm_i915_private *i915,
*/
void intel_power_domains_resume(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
if (power_domains->display_core_suspended) {
intel_power_domains_init_hw(i915, true);
@@ -2109,7 +2109,7 @@ void intel_power_domains_resume(struct drm_i915_private *i915)
static void intel_power_domains_dump_info(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
for_each_power_well(i915, power_well) {
@@ -2137,7 +2137,7 @@ static void intel_power_domains_dump_info(struct drm_i915_private *i915)
*/
static void intel_power_domains_verify_state(struct drm_i915_private *i915)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
struct i915_power_well *power_well;
bool dump_domain_info;
@@ -2263,7 +2263,7 @@ void intel_display_power_resume(struct drm_i915_private *i915)
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m)
{
- struct i915_power_domains *power_domains = &i915->power_domains;
+ struct i915_power_domains *power_domains = &i915->display.power.domains;
int i;
mutex_lock(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97b367f39f35..5ddd1b93751c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1388,7 +1388,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
u64 power_well_ids = 0;
const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
@@ -1447,7 +1447,7 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
- power_domains);
+ display.power.domains);
/*
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index efeee2d47849..bc8cf0ae623b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -84,7 +84,7 @@ lookup_power_well(struct drm_i915_private *i915,
drm_WARN(&i915->drm, 1,
"Power well %d not defined for this platform\n",
power_well_id);
- return &i915->power_domains.power_wells[0];
+ return &i915->display.power.domains.power_wells[0];
}
void intel_power_well_enable(struct drm_i915_private *i915,
@@ -1207,7 +1207,7 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
* During driver initialization/resume we can avoid restoring the
* part of the HW/SW state that will be inited anyway explicitly.
*/
- if (dev_priv->power_domains.initializing)
+ if (dev_priv->display.power.domains.initializing)
return;
intel_hpd_init(dev_priv);
@@ -1302,7 +1302,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->chv_phy_control;
+ u32 phy_control = dev_priv->display.power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1313,7 +1313,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[DPIO_PHY0])
+ if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
@@ -1321,7 +1321,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
- if (!dev_priv->chv_phy_assert[DPIO_PHY1])
+ if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1397,7 +1397,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
drm_err(&dev_priv->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->chv_phy_control);
+ phy_status, dev_priv->display.power.chv_phy_control);
}
#undef BITS_SET
@@ -1457,13 +1457,13 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_put(dev_priv);
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
}
@@ -1487,18 +1487,18 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
vlv_set_power_well(dev_priv, power_well, false);
drm_dbg_kms(&dev_priv->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
+ phy, dev_priv->display.power.chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->chv_phy_assert[phy] = true;
+ dev_priv->display.power.chv_phy_assert[phy] = true;
assert_chv_phy_status(dev_priv);
}
@@ -1516,7 +1516,7 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->chv_phy_assert[phy])
+ if (!dev_priv->display.power.chv_phy_assert[phy])
return;
if (ch == DPIO_CH0)
@@ -1570,27 +1570,27 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override)
{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
bool was_override;
mutex_lock(&power_domains->lock);
- was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
if (override == was_override)
goto out;
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->chv_phy_control);
+ phy, ch, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1604,26 +1604,26 @@ void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
mutex_lock(&power_domains->lock);
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
drm_dbg_kms(&dev_priv->drm,
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->chv_phy_control);
+ phy, ch, mask, dev_priv->display.power.chv_phy_control);
assert_chv_phy_status(dev_priv);
@@ -1701,7 +1701,7 @@ static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
+ dev_priv->display.power.chv_phy_control);
}
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index d0624642dcb6..31a898176ebb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -14,15 +14,15 @@ struct drm_i915_private;
struct i915_power_well;
#define for_each_power_well(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
- (__power_well) - (__dev_priv)->power_domains.power_wells < \
- (__dev_priv)->power_domains.power_well_count; \
+ for ((__power_well) = (__dev_priv)->display.power.domains.power_wells; \
+ (__power_well) - (__dev_priv)->display.power.domains.power_wells < \
+ (__dev_priv)->display.power.domains.power_well_count; \
(__power_well)++)
#define for_each_power_well_reverse(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
- (__dev_priv)->power_domains.power_well_count - 1; \
- (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ for ((__power_well) = (__dev_priv)->display.power.domains.power_wells + \
+ (__dev_priv)->display.power.domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->display.power.domains.power_wells >= 0; \
(__power_well)--)
/*
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index cc6abe761f5e..8732b8722ed7 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -484,7 +484,7 @@ void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
bool was_enabled;
- lockdep_assert_held(&dev_priv->power_domains.lock);
+ lockdep_assert_held(&dev_priv->display.power.domains.lock);
was_enabled = true;
if (rcomp_phy != -1)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 94e5c29d2ee3..f5c6a0714d79 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -493,7 +493,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
seq_puts(m, "Runtime power management not supported\n");
seq_printf(m, "Runtime power status: %s\n",
- str_enabled_disabled(!dev_priv->power_domains.init_wakeref));
+ str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref));
seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
seq_printf(m, "IRQs disabled: %s\n",
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6fa5ab1f173f..bd15bb1efac5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -38,7 +38,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
-#include "display/intel_display_power.h"
#include "display/intel_dsb.h"
#include "display/intel_frontbuffer.h"
@@ -354,8 +353,6 @@ struct drm_i915_private {
*/
u32 edram_size_mb;
- struct i915_power_domains power_domains;
-
struct i915_gpu_error gpu_error;
struct drm_property *broadcast_rgb_property;
@@ -363,8 +360,6 @@ struct drm_i915_private {
u32 fdi_rx_config;
- /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
- u32 chv_phy_control;
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
@@ -433,16 +428,11 @@ struct drm_i915_private {
bool irq_enabled;
- union {
- /* perform PHY state sanity checks? */
- bool chv_phy_assert[2];
-
- /*
- * DG2: Mask of PHYs that were not calibrated by the firmware
- * and should not be used.
- */
- u8 snps_phy_failed_calibration;
- };
+ /*
+ * DG2: Mask of PHYs that were not calibrated by the firmware
+ * and should not be used.
+ */
+ u8 snps_phy_failed_calibration;
bool ipc_enabled;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power
2022-08-11 15:07 ` [Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power Jani Nikula
@ 2022-08-17 4:41 ` Lucas De Marchi
0 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:41 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:39PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Arguably chv_phy_control and chv_phy_assert could be placed in a phy
>substruct, but they are only used in the power code.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> .../gpu/drm/i915/display/intel_display_core.h | 11 ++
> .../drm/i915/display/intel_display_power.c | 112 +++++++++---------
> .../i915/display/intel_display_power_map.c | 4 +-
> .../i915/display/intel_display_power_well.c | 56 ++++-----
> .../i915/display/intel_display_power_well.h | 12 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 2 +-
> drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 20 +---
> 8 files changed, 110 insertions(+), 109 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index 066e7ee0b8df..19abdd05d413 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -16,6 +16,7 @@
>
> #include "intel_cdclk.h"
> #include "intel_display.h"
>+#include "intel_display_power.h"
> #include "intel_dmc.h"
> #include "intel_dpll_mgr.h"
> #include "intel_fbc.h"
>@@ -326,6 +327,16 @@ struct intel_display {
> struct mutex comp_mutex;
> } hdcp;
>
>+ struct {
>+ struct i915_power_domains domains;
rename the struct to display_power_domains?
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
for all patches til this, expect patch 5
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 29/39] drm/i915: move and group fdi members under display.fdi
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (27 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 28/39] drm/i915: move and group power related members under display.power Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 30/39] drm/i915: move fb_tracking under display sub-struct Jani Nikula
` (15 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_core.h | 5 +++++
drivers/gpu/drm/i915/display/intel_fdi.c | 10 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 760b5788eb43..85c2fa632c7a 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -1110,7 +1110,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->fdi_rx_config = intel_de_read(dev_priv,
+ dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
FDI_RX_CTL(PIPE_A)) & fdi_config;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 19abdd05d413..714fb1a6bda3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -301,6 +301,11 @@ struct intel_display {
struct work_struct suspend_work;
} fbdev;
+ struct {
+ unsigned int pll_freq;
+ u32 rx_config;
+ } fdi;
+
struct {
/*
* Base address of where the gmbus and gpio blocks are located
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 03ad5f5c8417..f67dd4f05bab 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -210,14 +210,14 @@ void intel_fdi_pll_freq_update(struct drm_i915_private *i915)
u32 fdi_pll_clk =
intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK;
- i915->fdi_pll_freq = (fdi_pll_clk + 2) * 10000;
+ i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000;
} else if (IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) {
- i915->fdi_pll_freq = 270000;
+ i915->display.fdi.pll_freq = 270000;
} else {
return;
}
- drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->fdi_pll_freq);
+ drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq);
}
int intel_fdi_link_freq(struct drm_i915_private *i915,
@@ -226,7 +226,7 @@ int intel_fdi_link_freq(struct drm_i915_private *i915,
if (HAS_DDI(i915))
return pipe_config->port_clock; /* SPLL */
else
- return i915->fdi_pll_freq;
+ return i915->display.fdi.pll_freq;
}
int ilk_fdi_compute_config(struct intel_crtc *crtc,
@@ -789,7 +789,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
/* Enable the PCH Receiver FDI PLL */
- rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
+ rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
FDI_RX_PLL_ENABLE |
FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bd15bb1efac5..5833affe263d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -289,7 +289,6 @@ struct drm_i915_private {
unsigned int max_dotclk_freq;
unsigned int hpll_freq;
- unsigned int fdi_pll_freq;
unsigned int czclk_freq;
struct {
@@ -358,8 +357,6 @@ struct drm_i915_private {
struct drm_property *broadcast_rgb_property;
struct drm_property *force_audio_property;
- u32 fdi_rx_config;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 30/39] drm/i915: move fb_tracking under display sub-struct
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (28 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 29/39] drm/i915: move and group fdi members under display.fdi Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 31/39] drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h Jani Nikula
` (14 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Rename struct i915_frontbuffer_tracking to intel_frontbuffer_tracking
while at it.
FIXME: fb_tracking.lock mutex init should be moved away from
i915_gem_init_early().
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_display_core.h | 12 +++++
.../drm/i915/display/intel_display_debugfs.c | 4 +-
.../gpu/drm/i915/display/intel_frontbuffer.c | 54 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 14 -----
drivers/gpu/drm/i915/i915_gem.c | 2 +-
5 files changed, 42 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 714fb1a6bda3..f3fc69d4b7e0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -119,6 +119,17 @@ struct intel_dpll {
} ref_clks;
};
+struct intel_frontbuffer_tracking {
+ spinlock_t lock;
+
+ /*
+ * Tracking bits for delayed frontbuffer flushing du to gpu activity or
+ * scheduled flips.
+ */
+ unsigned busy_bits;
+ unsigned flip_bits;
+};
+
struct intel_hotplug {
struct delayed_work hotplug_work;
@@ -365,6 +376,7 @@ struct intel_display {
struct intel_dmc dmc;
struct intel_dpll dpll;
struct intel_fbc *fbc[I915_MAX_FBCS];
+ struct intel_frontbuffer_tracking fb_tracking;
struct intel_hotplug hotplug;
struct intel_opregion opregion;
struct intel_overlay *overlay;
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 619523f85a18..5dc364e9db49 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -37,10 +37,10 @@ static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
seq_printf(m, "FB tracking busy bits: 0x%08x\n",
- dev_priv->fb_tracking.busy_bits);
+ dev_priv->display.fb_tracking.busy_bits);
seq_printf(m, "FB tracking flip bits: 0x%08x\n",
- dev_priv->fb_tracking.flip_bits);
+ dev_priv->display.fb_tracking.flip_bits);
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 791248f812aa..0d4cfbd8403e 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -81,9 +81,9 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
enum fb_op_origin origin)
{
/* Delay flushing when rings are still busy.*/
- spin_lock(&i915->fb_tracking.lock);
- frontbuffer_bits &= ~i915->fb_tracking.busy_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
+ frontbuffer_bits &= ~i915->display.fb_tracking.busy_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (!frontbuffer_bits)
return;
@@ -111,11 +111,11 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.flip_bits |= frontbuffer_bits;
+ spin_lock(&i915->display.fb_tracking.lock);
+ i915->display.fb_tracking.flip_bits |= frontbuffer_bits;
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
/**
@@ -131,11 +131,11 @@ void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Mask any cancelled flips. */
- frontbuffer_bits &= i915->fb_tracking.flip_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display.fb_tracking.flip_bits;
+ i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
if (frontbuffer_bits)
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
@@ -155,10 +155,10 @@ void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
void intel_frontbuffer_flip(struct drm_i915_private *i915,
unsigned frontbuffer_bits)
{
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Remove stale busy bits due to the old buffer. */
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
frontbuffer_flush(i915, frontbuffer_bits, ORIGIN_FLIP);
}
@@ -170,10 +170,10 @@ void __intel_fb_invalidate(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
- i915->fb_tracking.busy_bits |= frontbuffer_bits;
- i915->fb_tracking.flip_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
+ i915->display.fb_tracking.busy_bits |= frontbuffer_bits;
+ i915->display.fb_tracking.flip_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
trace_intel_frontbuffer_invalidate(frontbuffer_bits, origin);
@@ -191,11 +191,11 @@ void __intel_fb_flush(struct intel_frontbuffer *front,
struct drm_i915_private *i915 = to_i915(front->obj->base.dev);
if (origin == ORIGIN_CS) {
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
/* Filter out new bits since rendering started. */
- frontbuffer_bits &= i915->fb_tracking.busy_bits;
- i915->fb_tracking.busy_bits &= ~frontbuffer_bits;
- spin_unlock(&i915->fb_tracking.lock);
+ frontbuffer_bits &= i915->display.fb_tracking.busy_bits;
+ i915->display.fb_tracking.busy_bits &= ~frontbuffer_bits;
+ spin_unlock(&i915->display.fb_tracking.lock);
}
if (frontbuffer_bits)
@@ -221,7 +221,7 @@ static void frontbuffer_retire(struct i915_active *ref)
}
static void frontbuffer_release(struct kref *ref)
- __releases(&to_i915(front->obj->base.dev)->fb_tracking.lock)
+ __releases(&to_i915(front->obj->base.dev)->display.fb_tracking.lock)
{
struct intel_frontbuffer *front =
container_of(ref, typeof(*front), ref);
@@ -238,7 +238,7 @@ static void frontbuffer_release(struct kref *ref)
spin_unlock(&obj->vma.lock);
RCU_INIT_POINTER(obj->frontbuffer, NULL);
- spin_unlock(&to_i915(obj->base.dev)->fb_tracking.lock);
+ spin_unlock(&to_i915(obj->base.dev)->display.fb_tracking.lock);
i915_active_fini(&front->write);
@@ -268,7 +268,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
frontbuffer_retire,
I915_ACTIVE_RETIRE_SLEEPS);
- spin_lock(&i915->fb_tracking.lock);
+ spin_lock(&i915->display.fb_tracking.lock);
if (rcu_access_pointer(obj->frontbuffer)) {
kfree(front);
front = rcu_dereference_protected(obj->frontbuffer, true);
@@ -277,7 +277,7 @@ intel_frontbuffer_get(struct drm_i915_gem_object *obj)
i915_gem_object_get(obj);
rcu_assign_pointer(obj->frontbuffer, front);
}
- spin_unlock(&i915->fb_tracking.lock);
+ spin_unlock(&i915->display.fb_tracking.lock);
return front;
}
@@ -286,7 +286,7 @@ void intel_frontbuffer_put(struct intel_frontbuffer *front)
{
kref_put_lock(&front->ref,
frontbuffer_release,
- &to_i915(front->obj->base.dev)->fb_tracking.lock);
+ &to_i915(front->obj->base.dev)->display.fb_tracking.lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5833affe263d..19f41526c70a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -39,7 +39,6 @@
#include "display/intel_display.h"
#include "display/intel_display_core.h"
#include "display/intel_dsb.h"
-#include "display/intel_frontbuffer.h"
#include "gem/i915_gem_context_types.h"
#include "gem/i915_gem_lmem.h"
@@ -186,17 +185,6 @@ i915_fence_timeout(const struct drm_i915_private *i915)
#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
-struct i915_frontbuffer_tracking {
- spinlock_t lock;
-
- /*
- * Tracking bits for delayed frontbuffer flushing du to gpu activity or
- * scheduled flips.
- */
- unsigned busy_bits;
- unsigned flip_bits;
-};
-
struct i915_virtual_gpu {
struct mutex lock; /* serialises sending of g2v_notify command pkts */
bool active;
@@ -327,8 +315,6 @@ struct drm_i915_private {
struct list_head global_obj_list;
- struct i915_frontbuffer_tracking fb_tracking;
-
struct intel_atomic_helper {
struct llist_head free_list;
struct work_struct free_work;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 702e5b89be22..0639ec7e5455 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1213,7 +1213,7 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
i915_gem_init__mm(dev_priv);
i915_gem_init__contexts(dev_priv);
- spin_lock_init(&dev_priv->fb_tracking.lock);
+ spin_lock_init(&dev_priv->display.fb_tracking.lock);
}
void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 31/39] drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (29 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 30/39] drm/i915: move fb_tracking under display sub-struct Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 32/39] drm/i915: move dbuf under display sub-struct Jani Nikula
` (13 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
The macros clearly don't belong in i915_drv.h. Move to
intel_frontbuffer.h.
Also split the BUILD_BUG_ON()s to intel_frontbuffer_track() to avoid
depending on some other macros in the header.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../gpu/drm/i915/display/intel_frontbuffer.c | 2 ++
.../gpu/drm/i915/display/intel_frontbuffer.h | 18 +++++++++++++++++
drivers/gpu/drm/i915/i915_drv.h | 20 -------------------
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index 0d4cfbd8403e..d80e3e8a9b01 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -311,6 +311,8 @@ void intel_frontbuffer_track(struct intel_frontbuffer *old,
*/
BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES >
BITS_PER_TYPE(atomic_t));
+ BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32);
+ BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE);
if (old) {
drm_WARN_ON(old->obj->base.dev,
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.h b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
index ff0c37b079aa..3c474ed937fb 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.h
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.h
@@ -25,6 +25,7 @@
#define __INTEL_FRONTBUFFER_H__
#include <linux/atomic.h>
+#include <linux/bits.h>
#include <linux/kref.h>
#include "gem/i915_gem_object_types.h"
@@ -48,6 +49,23 @@ struct intel_frontbuffer {
struct rcu_head rcu;
};
+/*
+ * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
+ * considered to be the frontbuffer for the given plane interface-wise. This
+ * doesn't mean that the hw necessarily already scans it out, but that any
+ * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
+ *
+ * We have one bit per pipe and per scanout plane type.
+ */
+#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
+#define INTEL_FRONTBUFFER(pipe, plane_id) \
+ BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
+#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
+ BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
+#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
+ GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
+ INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
+
void intel_frontbuffer_flip_prepare(struct drm_i915_private *i915,
unsigned frontbuffer_bits);
void intel_frontbuffer_flip_complete(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 19f41526c70a..acc04bf58be9 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -483,26 +483,6 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
#define I915_GTT_OFFSET_NONE ((u32)-1)
-/*
- * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
- * considered to be the frontbuffer for the given plane interface-wise. This
- * doesn't mean that the hw necessarily already scans it out, but that any
- * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
- *
- * We have one bit per pipe and per scanout plane type.
- */
-#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
-#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
- BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
- BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
- BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
-})
-#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
- BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
-#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
- GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
- INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
-
#define INTEL_INFO(dev_priv) (&(dev_priv)->__info)
#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 32/39] drm/i915: move dbuf under display sub-struct
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (30 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 31/39] drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 33/39] drm/i915: move and group modeset_wq and flip_wq under display.wq Jani Nikula
` (12 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 7 +++++++
drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++---
.../drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 7 -------
drivers/gpu/drm/i915/intel_pm.c | 14 +++++++-------
drivers/gpu/drm/i915/intel_pm.h | 4 ++--
7 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index f3fc69d4b7e0..f942d156026a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -301,6 +301,13 @@ struct intel_display {
unsigned int max_cdclk_freq;
} cdclk;
+ struct {
+ /* The current hardware dbuf configuration */
+ u8 enabled_slices;
+
+ struct intel_global_obj obj;
+ } dbuf;
+
struct {
/* VLV/CHV/BXT/GLK DSI MMIO register base address */
u32 mmio_base;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9960b7f59146..3e2f4a3d03a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1060,14 +1060,14 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
for_each_dbuf_slice(dev_priv, slice)
gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice));
- dev_priv->dbuf.enabled_slices = req_slices;
+ dev_priv->display.dbuf.enabled_slices = req_slices;
mutex_unlock(&power_domains->lock);
}
static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
{
- dev_priv->dbuf.enabled_slices =
+ dev_priv->display.dbuf.enabled_slices =
intel_enabled_dbuf_slices_mask(dev_priv);
/*
@@ -1075,7 +1075,7 @@ static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
* figure out later which slices we have and what we need.
*/
gen9_dbuf_slices_update(dev_priv, BIT(DBUF_S1) |
- dev_priv->dbuf.enabled_slices);
+ dev_priv->display.dbuf.enabled_slices);
}
static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index bc8cf0ae623b..06569fc31493 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -945,7 +945,7 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
{
u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
+ u8 enabled_dbuf_slices = dev_priv->display.dbuf.enabled_slices;
drm_WARN(&dev_priv->drm,
hw_enabled_dbuf_slices != enabled_dbuf_slices,
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index 6efbbb85c8ed..7c75ad1b88a0 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -34,7 +34,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
struct intel_plane *plane;
@@ -417,7 +417,7 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
struct intel_cdclk_state *cdclk_state =
to_intel_cdclk_state(i915->display.cdclk.obj.state);
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
enum pipe pipe;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index acc04bf58be9..71ed89e91e88 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -279,13 +279,6 @@ struct drm_i915_private {
unsigned int hpll_freq;
unsigned int czclk_freq;
- struct {
- /* The current hardware dbuf configuration */
- u8 enabled_slices;
-
- struct intel_global_obj obj;
- } dbuf;
-
/**
* wq - Driver workqueue for GEM.
*
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 89eea3f9dd72..5b78147081b9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6546,7 +6546,7 @@ static void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(dev_priv->dbuf.obj.state);
+ to_intel_dbuf_state(dev_priv->display.dbuf.obj.state);
struct intel_crtc *crtc;
if (HAS_MBUS_JOINING(dev_priv))
@@ -6602,13 +6602,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
str_yes_no(dbuf_state->joined_mbus));
}
- dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
+ dbuf_state->enabled_slices = dev_priv->display.dbuf.enabled_slices;
}
static bool skl_dbuf_is_misconfigured(struct drm_i915_private *i915)
{
const struct intel_dbuf_state *dbuf_state =
- to_intel_dbuf_state(i915->dbuf.obj.state);
+ to_intel_dbuf_state(i915->display.dbuf.obj.state);
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
struct intel_crtc *crtc;
@@ -7194,10 +7194,10 @@ void intel_wm_state_verify(struct intel_crtc *crtc,
hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
if (DISPLAY_VER(dev_priv) >= 11 &&
- hw_enabled_slices != dev_priv->dbuf.enabled_slices)
+ hw_enabled_slices != dev_priv->display.dbuf.enabled_slices)
drm_err(&dev_priv->drm,
"mismatch in DBUF Slices (expected 0x%x, got 0x%x)\n",
- dev_priv->dbuf.enabled_slices,
+ dev_priv->display.dbuf.enabled_slices,
hw_enabled_slices);
for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
@@ -8314,7 +8314,7 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_global_state *dbuf_state;
- dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->dbuf.obj);
+ dbuf_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.dbuf.obj);
if (IS_ERR(dbuf_state))
return ERR_CAST(dbuf_state);
@@ -8329,7 +8329,7 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
if (!dbuf_state)
return -ENOMEM;
- intel_atomic_global_obj_init(dev_priv, &dev_priv->dbuf.obj,
+ intel_atomic_global_obj_init(dev_priv, &dev_priv->display.dbuf.obj,
&dbuf_state->base, &intel_dbuf_funcs);
return 0;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 945503ae493e..3ee71831d1a4 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -77,9 +77,9 @@ intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
#define to_intel_dbuf_state(x) container_of((x), struct intel_dbuf_state, base)
#define intel_atomic_get_old_dbuf_state(state) \
- to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
#define intel_atomic_get_new_dbuf_state(state) \
- to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->dbuf.obj))
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
int intel_dbuf_init(struct drm_i915_private *dev_priv);
void intel_dbuf_pre_plane_update(struct intel_atomic_state *state);
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 33/39] drm/i915: move and group modeset_wq and flip_wq under display.wq
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (31 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 32/39] drm/i915: move dbuf under display sub-struct Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 34/39] drm/i915: split gem quirks from display quirks Jani Nikula
` (11 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 20 +++++++++----------
.../gpu/drm/i915/display/intel_display_core.h | 8 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 5 -----
3 files changed, 18 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5bf062adf9ab..f80c7797176d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7812,12 +7812,12 @@ static int intel_atomic_commit(struct drm_device *dev,
i915_sw_fence_commit(&state->commit_ready);
if (nonblock && state->modeset) {
- queue_work(dev_priv->modeset_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
} else if (nonblock) {
- queue_work(dev_priv->flip_wq, &state->base.commit_work);
+ queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
} else {
if (state->modeset)
- flush_workqueue(dev_priv->modeset_wq);
+ flush_workqueue(dev_priv->display.wq.modeset);
intel_atomic_commit_tail(state);
}
@@ -8681,9 +8681,9 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
intel_dmc_ucode_init(i915);
- i915->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
- i915->flip_wq = alloc_workqueue("i915_flip", WQ_HIGHPRI |
- WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
+ i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
+ i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
+ WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
intel_mode_config_init(i915);
@@ -8990,8 +8990,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
if (!HAS_DISPLAY(i915))
return;
- flush_workqueue(i915->flip_wq);
- flush_workqueue(i915->modeset_wq);
+ flush_workqueue(i915->display.wq.flip);
+ flush_workqueue(i915->display.wq.modeset);
flush_work(&i915->atomic_helper.free_work);
drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
@@ -9032,8 +9032,8 @@ void intel_modeset_driver_remove_noirq(struct drm_i915_private *i915)
intel_gmbus_teardown(i915);
- destroy_workqueue(i915->flip_wq);
- destroy_workqueue(i915->modeset_wq);
+ destroy_workqueue(i915->display.wq.flip);
+ destroy_workqueue(i915->display.wq.modeset);
intel_fbc_cleanup(i915);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index f942d156026a..da76b3eecbf5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -378,6 +378,14 @@ struct intel_display {
u32 block_time_us;
} sagv;
+ struct {
+ /* ordered wq for modesets */
+ struct workqueue_struct *modeset;
+
+ /* unbound hipri wq for page flips/plane updates */
+ struct workqueue_struct *flip;
+ } wq;
+
/* Grouping using named structs. Keep sorted. */
struct intel_audio audio;
struct intel_dmc dmc;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71ed89e91e88..f9170b45663f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -288,11 +288,6 @@ struct drm_i915_private {
*/
struct workqueue_struct *wq;
- /* ordered wq for modesets */
- struct workqueue_struct *modeset_wq;
- /* unbound hipri wq for page flips/plane updates */
- struct workqueue_struct *flip_wq;
-
/* PCH chipset type */
enum intel_pch pch_type;
unsigned short pch_id;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 34/39] drm/i915: split gem quirks from display quirks
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (32 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 33/39] drm/i915: move and group modeset_wq and flip_wq under display.wq Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 35/39] drm/i915/quirks: abstract checking for " Jani Nikula
` (10 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
The lone gem quirk is an outlier, not even handled by the common quirk
code. Split it to a separate gem_quirks member.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_pages.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 4 ++--
drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 4 +++-
drivers/gpu/drm/i915/i915_gem.c | 2 +-
8 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 8357dbdcab5c..e0b39463c1b0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -66,7 +66,7 @@ void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
shrinkable = i915_gem_object_is_shrinkable(obj);
if (i915_gem_object_is_tiled(obj) &&
- i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
i915_gem_object_set_tiling_quirk(obj);
GEM_BUG_ON(!list_empty(&obj->mm.link));
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
index 85518b28cd72..fd42b89b7162 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c
@@ -278,7 +278,7 @@ i915_gem_object_set_tiling(struct drm_i915_gem_object *obj,
*/
if (i915_gem_object_has_pages(obj) &&
obj->mm.madv == I915_MADV_WILLNEED &&
- i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
if (tiling == I915_TILING_NONE) {
GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
i915_gem_object_clear_tiling_quirk(obj);
@@ -458,7 +458,7 @@ i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
}
/* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
- if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
else
args->phys_swizzle_mode = args->swizzle_mode;
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index 3cfc621ef363..9a6a6b5b722b 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -711,7 +711,7 @@ static bool bad_swizzling(struct drm_i915_private *i915)
{
struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
return true;
if (has_bit17_swizzle(ggtt->bit_6_swizzle_x) ||
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index 3ced9948a331..25bb3bd4c3fe 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -367,7 +367,7 @@ static int igt_partial_tiling(void *arg)
unsigned int pitch;
struct tile tile;
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
/*
* The swizzling pattern is actually unknown as it
* varies based on physical address of each page.
@@ -464,7 +464,7 @@ static int igt_smoke_tiling(void *arg)
* Remember to look at the st_seed if we see a flip-flop in BAT!
*/
- if (i915->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
return 0;
obj = huge_gem_object(i915,
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
index 6ebda3d65086..cf4a326f5f48 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
@@ -727,7 +727,7 @@ static void detect_bit_6_swizzle(struct i915_ggtt *ggtt)
* bit17 dependent, and so we need to also prevent the pages
* from being moved.
*/
- i915->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
+ i915->gem_quirks |= GEM_QUIRK_PIN_SWIZZLED_PAGES;
swizzle_x = I915_BIT_6_SWIZZLE_NONE;
swizzle_y = I915_BIT_6_SWIZZLE_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f5c6a0714d79..36cc05150249 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -411,7 +411,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
- if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
+ if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
/* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9170b45663f..22571f77dc71 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -87,10 +87,11 @@ struct vlv_s0ix_state;
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */
+#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
+
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
-#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
#define QUIRK_INCREASE_T12_DELAY (1<<6)
#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
@@ -292,6 +293,7 @@ struct drm_i915_private {
enum intel_pch pch_type;
unsigned short pch_id;
+ unsigned long gem_quirks;
unsigned long quirks;
struct drm_atomic_state *modeset_restore_state;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 0639ec7e5455..ccf8291a00e7 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1035,7 +1035,7 @@ i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
if (i915_gem_object_has_pages(obj) &&
i915_gem_object_is_tiled(obj) &&
- i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
+ i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
if (obj->mm.madv == I915_MADV_WILLNEED) {
GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
i915_gem_object_clear_tiling_quirk(obj);
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 35/39] drm/i915/quirks: abstract checking for display quirks
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (33 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 34/39] drm/i915: split gem quirks from display quirks Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 36/39] drm/i915/quirks: abstract quirks further by making quirk ids an enum Jani Nikula
` (9 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Add intel_has_quirk() for checking if a display quirk is present. Avoid
accessing i915->quirks all over the place.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_backlight.c | 7 ++++---
drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++-
drivers/gpu/drm/i915/display/intel_dp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_panel.c | 5 +++--
drivers/gpu/drm/i915/display/intel_pps.c | 3 ++-
drivers/gpu/drm/i915/display/intel_quirks.c | 5 +++++
drivers/gpu/drm/i915/display/intel_quirks.h | 5 ++++-
7 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 67ecad0f9ef1..e2bbb6fc4331 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -16,6 +16,7 @@
#include "intel_dsi_dcs_backlight.h"
#include "intel_panel.h"
#include "intel_pci_config.h"
+#include "intel_quirks.h"
/**
* scale - scale values from one range to another
@@ -86,7 +87,7 @@ u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 val)
return val;
if (dev_priv->params.invert_brightness > 0 ||
- dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
+ intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val + panel->backlight.pwm_level_min;
}
@@ -126,7 +127,7 @@ u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)
panel->backlight.max == 0 || panel->backlight.pwm_level_max == 0);
if (dev_priv->params.invert_brightness > 0 ||
- (dev_priv->params.invert_brightness == 0 && dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS))
+ (dev_priv->params.invert_brightness == 0 && intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val - panel->backlight.pwm_level_min);
return scale(val, panel->backlight.pwm_level_min, panel->backlight.pwm_level_max,
@@ -1605,7 +1606,7 @@ int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
int ret;
if (!connector->panel.vbt.backlight.present) {
- if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
+ if (intel_has_quirk(dev_priv, QUIRK_BACKLIGHT_PRESENT)) {
drm_dbg_kms(&dev_priv->drm,
"no backlight present per VBT, but present per quirk\n");
} else {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 320304809ed6..de04528938dc 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -57,6 +57,7 @@
#include "intel_lspcon.h"
#include "intel_pps.h"
#include "intel_psr.h"
+#include "intel_quirks.h"
#include "intel_snps_phy.h"
#include "intel_sprite.h"
#include "intel_tc.h"
@@ -631,7 +632,7 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
- if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
+ if (intel_has_quirk(dev_priv, QUIRK_INCREASE_DDI_DISABLED_TIME) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
drm_dbg_kms(&dev_priv->drm,
"Quirk Increase DDI disabled time\n");
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 935ec3661aa2..2503920903a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -72,6 +72,7 @@
#include "intel_pch_display.h"
#include "intel_pps.h"
#include "intel_psr.h"
+#include "intel_quirks.h"
#include "intel_tc.h"
#include "intel_vdsc.h"
#include "intel_vrr.h"
@@ -5293,7 +5294,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
intel_panel_init(intel_connector);
- if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
+ if (!intel_has_quirk(dev_priv, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK))
intel_connector->panel.backlight.power = intel_pps_backlight_power;
intel_backlight_setup(intel_connector, pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c
index 43dbc5a3ec37..a1b4ef1ad917 100644
--- a/drivers/gpu/drm/i915/display/intel_panel.c
+++ b/drivers/gpu/drm/i915/display/intel_panel.c
@@ -37,13 +37,14 @@
#include "intel_display_types.h"
#include "intel_drrs.h"
#include "intel_panel.h"
+#include "intel_quirks.h"
bool intel_panel_use_ssc(struct drm_i915_private *i915)
{
if (i915->params.panel_use_ssc >= 0)
return i915->params.panel_use_ssc != 0;
- return i915->display.vbt.lvds_use_ssc
- && !(i915->quirks & QUIRK_LVDS_SSC_DISABLE);
+ return i915->display.vbt.lvds_use_ssc &&
+ !intel_has_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
}
const struct drm_display_mode *
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 9a66e03aa2d6..21944f5bf3a8 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -12,6 +12,7 @@
#include "intel_dpll.h"
#include "intel_lvds.h"
#include "intel_pps.h"
+#include "intel_quirks.h"
static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
enum pipe pipe);
@@ -1202,7 +1203,7 @@ static void pps_init_delays_vbt(struct intel_dp *intel_dp,
* just fails to power back on. Increasing the delay to 800ms
* seems sufficient to avoid this problem.
*/
- if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
+ if (intel_has_quirk(dev_priv, QUIRK_INCREASE_T12_DELAY)) {
vbt->t11_t12 = max_t(u16, vbt->t11_t12, 1300 * 10);
drm_dbg_kms(&dev_priv->drm,
"Increasing T12 panel delay as per the quirk to %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index c8488f5ebd04..9b5db1193a00 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -213,3 +213,8 @@ void intel_init_quirks(struct drm_i915_private *i915)
intel_dmi_quirks[i].hook(i915);
}
}
+
+bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk)
+{
+ return i915->quirks & quirk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
index b0fcff142a56..f5e399a6e7d3 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -6,8 +6,11 @@
#ifndef __INTEL_QUIRKS_H__
#define __INTEL_QUIRKS_H__
+#include <linux/types.h>
+
struct drm_i915_private;
-void intel_init_quirks(struct drm_i915_private *dev_priv);
+void intel_init_quirks(struct drm_i915_private *i915);
+bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk);
#endif /* __INTEL_QUIRKS_H__ */
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 36/39] drm/i915/quirks: abstract quirks further by making quirk ids an enum
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (34 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 35/39] drm/i915/quirks: abstract checking for " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct Jani Nikula
` (8 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Turn the quirk ids to enums instead of bits, and hide the masking inside
intel_quirks.c. Define the enums in intel_quirks.h to declutter
i915_drv.h while at it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_quirks.c | 21 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_quirks.h | 11 ++++++++++-
drivers/gpu/drm/i915/i915_drv.h | 7 -------
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 9b5db1193a00..22e0df9d9dba 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -9,12 +9,17 @@
#include "intel_display_types.h"
#include "intel_quirks.h"
+static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
+{
+ i915->quirks |= BIT(quirk);
+}
+
/*
* Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
*/
static void quirk_ssc_force_disable(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_LVDS_SSC_DISABLE;
+ intel_set_quirk(i915, QUIRK_LVDS_SSC_DISABLE);
drm_info(&i915->drm, "applying lvds SSC disable quirk\n");
}
@@ -24,14 +29,14 @@ static void quirk_ssc_force_disable(struct drm_i915_private *i915)
*/
static void quirk_invert_brightness(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INVERT_BRIGHTNESS;
+ intel_set_quirk(i915, QUIRK_INVERT_BRIGHTNESS);
drm_info(&i915->drm, "applying inverted panel brightness quirk\n");
}
/* Some VBT's incorrectly indicate no backlight is present */
static void quirk_backlight_present(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_BACKLIGHT_PRESENT;
+ intel_set_quirk(i915, QUIRK_BACKLIGHT_PRESENT);
drm_info(&i915->drm, "applying backlight present quirk\n");
}
@@ -40,7 +45,7 @@ static void quirk_backlight_present(struct drm_i915_private *i915)
*/
static void quirk_increase_t12_delay(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_T12_DELAY;
+ intel_set_quirk(i915, QUIRK_INCREASE_T12_DELAY);
drm_info(&i915->drm, "Applying T12 delay quirk\n");
}
@@ -50,13 +55,13 @@ static void quirk_increase_t12_delay(struct drm_i915_private *i915)
*/
static void quirk_increase_ddi_disabled_time(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_INCREASE_DDI_DISABLED_TIME;
+ intel_set_quirk(i915, QUIRK_INCREASE_DDI_DISABLED_TIME);
drm_info(&i915->drm, "Applying Increase DDI Disabled quirk\n");
}
static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915)
{
- i915->quirks |= QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK;
+ intel_set_quirk(i915, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK);
drm_info(&i915->drm, "Applying no pps backlight power quirk\n");
}
@@ -214,7 +219,7 @@ void intel_init_quirks(struct drm_i915_private *i915)
}
}
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk)
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & quirk;
+ return i915->quirks & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h
index f5e399a6e7d3..10a4d163149f 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.h
+++ b/drivers/gpu/drm/i915/display/intel_quirks.h
@@ -10,7 +10,16 @@
struct drm_i915_private;
+enum intel_quirk_id {
+ QUIRK_BACKLIGHT_PRESENT,
+ QUIRK_INCREASE_DDI_DISABLED_TIME,
+ QUIRK_INCREASE_T12_DELAY,
+ QUIRK_INVERT_BRIGHTNESS,
+ QUIRK_LVDS_SSC_DISABLE,
+ QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK,
+};
+
void intel_init_quirks(struct drm_i915_private *i915);
-bool intel_has_quirk(struct drm_i915_private *i915, unsigned long quirk);
+bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk);
#endif /* __INTEL_QUIRKS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 22571f77dc71..60f654db7819 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,13 +89,6 @@ struct vlv_s0ix_state;
#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
-#define QUIRK_LVDS_SSC_DISABLE (1<<1)
-#define QUIRK_INVERT_BRIGHTNESS (1<<2)
-#define QUIRK_BACKLIGHT_PRESENT (1<<3)
-#define QUIRK_INCREASE_T12_DELAY (1<<6)
-#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
-#define QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK (1<<8)
-
struct i915_suspend_saved_registers {
u32 saveDSPARB;
u32 saveSWF0[16];
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (35 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 36/39] drm/i915/quirks: abstract quirks further by making quirk ids an enum Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-17 4:49 ` Lucas De Marchi
2022-08-11 15:07 ` [Intel-gfx] [PATCH 38/39] drm/i915: move atomic_helper " Jani Nikula
` (7 subsequent siblings)
44 siblings, 1 reply; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Prefer adding anonymous sub-structs even for single members that aren't
our own structs.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++++
drivers/gpu/drm/i915/display/intel_quirks.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 1 -
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index da76b3eecbf5..252da61f2c6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -367,6 +367,10 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ unsigned long mask;
+ } quirks;
+
struct {
enum {
I915_SAGV_UNKNOWN = 0,
diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
index 22e0df9d9dba..e74ff042a9da 100644
--- a/drivers/gpu/drm/i915/display/intel_quirks.c
+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
@@ -11,7 +11,7 @@
static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- i915->quirks |= BIT(quirk);
+ i915->display.quirks.mask |= BIT(quirk);
}
/*
@@ -221,5 +221,5 @@ void intel_init_quirks(struct drm_i915_private *i915)
bool intel_has_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
{
- return i915->quirks & BIT(quirk);
+ return i915->display.quirks.mask & BIT(quirk);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 60f654db7819..e529a9575a66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -287,7 +287,6 @@ struct drm_i915_private {
unsigned short pch_id;
unsigned long gem_quirks;
- unsigned long quirks;
struct drm_atomic_state *modeset_restore_state;
struct drm_modeset_acquire_ctx reset_ctx;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct
2022-08-11 15:07 ` [Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct Jani Nikula
@ 2022-08-17 4:49 ` Lucas De Marchi
0 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:48PM +0300, Jani Nikula wrote:
>Move display related members under drm_i915_private display sub-struct.
>
>Prefer adding anonymous sub-structs even for single members that aren't
>our own structs.
>
>Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>---
> drivers/gpu/drm/i915/display/intel_display_core.h | 4 ++++
> drivers/gpu/drm/i915/display/intel_quirks.c | 4 ++--
> drivers/gpu/drm/i915/i915_drv.h | 1 -
> 3 files changed, 6 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>index da76b3eecbf5..252da61f2c6a 100644
>--- a/drivers/gpu/drm/i915/display/intel_display_core.h
>+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>@@ -367,6 +367,10 @@ struct intel_display {
> struct mutex mutex;
> } pps;
>
>+ struct {
>+ unsigned long mask;
>+ } quirks;
>+
> struct {
> enum {
> I915_SAGV_UNKNOWN = 0,
>diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c
>index 22e0df9d9dba..e74ff042a9da 100644
>--- a/drivers/gpu/drm/i915/display/intel_quirks.c
>+++ b/drivers/gpu/drm/i915/display/intel_quirks.c
>@@ -11,7 +11,7 @@
>
> static void intel_set_quirk(struct drm_i915_private *i915, enum intel_quirk_id quirk)
> {
>- i915->quirks |= BIT(quirk);
>+ i915->display.quirks.mask |= BIT(quirk);
you started splitting gem from the display, so maybe this could be
intel_display_set_quirk()? similar for other functions
anyway:
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
until this patch, except patch 5
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread
* [Intel-gfx] [PATCH 38/39] drm/i915: move atomic_helper under display sub-struct
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (36 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 37/39] drm/i915: move quirks under display sub-struct Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:07 ` [Intel-gfx] [PATCH 39/39] drm/i915: move and group properties under display.properties Jani Nikula
` (6 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Move display related members under drm_i915_private display sub-struct.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 +++++++-------
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 5 -----
3 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f80c7797176d..818f8ea52156 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7409,7 +7409,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
struct intel_atomic_state *state, *next;
struct llist_node *freed;
- freed = llist_del_all(&dev_priv->atomic_helper.free_list);
+ freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
llist_for_each_entry_safe(state, next, freed, freed)
drm_atomic_state_put(&state->base);
}
@@ -7417,7 +7417,7 @@ static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
static void intel_atomic_helper_free_state_worker(struct work_struct *work)
{
struct drm_i915_private *dev_priv =
- container_of(work, typeof(*dev_priv), atomic_helper.free_work);
+ container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
intel_atomic_helper_free_state(dev_priv);
}
@@ -7709,7 +7709,7 @@ intel_atomic_commit_ready(struct i915_sw_fence *fence,
case FENCE_FREE:
{
struct intel_atomic_helper *helper =
- &to_i915(state->base.dev)->atomic_helper;
+ &to_i915(state->base.dev)->display.atomic_helper;
if (llist_add(&state->freed, &helper->free_list))
schedule_work(&helper->free_work);
@@ -8699,8 +8699,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
if (ret)
goto cleanup_vga_client_pw_domain_dmc;
- init_llist_head(&i915->atomic_helper.free_list);
- INIT_WORK(&i915->atomic_helper.free_work,
+ init_llist_head(&i915->display.atomic_helper.free_list);
+ INIT_WORK(&i915->display.atomic_helper.free_work,
intel_atomic_helper_free_state_worker);
intel_init_quirks(i915);
@@ -8993,8 +8993,8 @@ void intel_modeset_driver_remove(struct drm_i915_private *i915)
flush_workqueue(i915->display.wq.flip);
flush_workqueue(i915->display.wq.modeset);
- flush_work(&i915->atomic_helper.free_work);
- drm_WARN_ON(&i915->drm, !llist_empty(&i915->atomic_helper.free_list));
+ flush_work(&i915->display.atomic_helper.free_work);
+ drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
}
/* part #2: call after irq uninstall */
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 252da61f2c6a..a753f6d66714 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -7,6 +7,7 @@
#define __INTEL_DISPLAY_CORE_H__
#include <linux/list.h>
+#include <linux/llist.h>
#include <linux/mutex.h>
#include <linux/types.h>
#include <linux/wait.h>
@@ -270,6 +271,11 @@ struct intel_display {
} funcs;
/* Grouping using anonymous structs. Keep sorted. */
+ struct intel_atomic_helper {
+ struct llist_head free_list;
+ struct work_struct free_work;
+ } atomic_helper;
+
struct {
/* backlight registers and fields in struct intel_panel */
struct mutex lock;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e529a9575a66..1bf7b13fdeda 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -297,11 +297,6 @@ struct drm_i915_private {
struct list_head global_obj_list;
- struct intel_atomic_helper {
- struct llist_head free_list;
- struct work_struct free_work;
- } atomic_helper;
-
bool mchbar_need_disable;
struct intel_l3_parity l3_parity;
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* [Intel-gfx] [PATCH 39/39] drm/i915: move and group properties under display.properties
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (37 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 38/39] drm/i915: move atomic_helper " Jani Nikula
@ 2022-08-11 15:07 ` Jani Nikula
2022-08-11 15:15 ` [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (5 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, lucas.demarchi
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_connector.c | 8 ++++----
drivers/gpu/drm/i915/display/intel_display_core.h | 6 ++++++
drivers/gpu/drm/i915/i915_drv.h | 3 ---
4 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index b94973b5633f..18f0a5ae3bac 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -62,9 +62,9 @@ int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property)
+ if (property == dev_priv->display.properties.force_audio)
*val = intel_conn_state->force_audio;
- else if (property == dev_priv->broadcast_rgb_property)
+ else if (property == dev_priv->display.properties.broadcast_rgb)
*val = intel_conn_state->broadcast_rgb;
else {
drm_dbg_atomic(&dev_priv->drm,
@@ -95,12 +95,12 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
struct intel_digital_connector_state *intel_conn_state =
to_intel_digital_connector_state(state);
- if (property == dev_priv->force_audio_property) {
+ if (property == dev_priv->display.properties.force_audio) {
intel_conn_state->force_audio = val;
return 0;
}
- if (property == dev_priv->broadcast_rgb_property) {
+ if (property == dev_priv->display.properties.broadcast_rgb) {
intel_conn_state->broadcast_rgb = val;
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c
index 1dcc268927a2..6d5cbeb8df4d 100644
--- a/drivers/gpu/drm/i915/display/intel_connector.c
+++ b/drivers/gpu/drm/i915/display/intel_connector.c
@@ -229,7 +229,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->force_audio_property;
+ prop = dev_priv->display.properties.force_audio;
if (prop == NULL) {
prop = drm_property_create_enum(dev, 0,
"audio",
@@ -238,7 +238,7 @@ intel_attach_force_audio_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->force_audio_property = prop;
+ dev_priv->display.properties.force_audio = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
}
@@ -256,7 +256,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_property *prop;
- prop = dev_priv->broadcast_rgb_property;
+ prop = dev_priv->display.properties.broadcast_rgb;
if (prop == NULL) {
prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM,
"Broadcast RGB",
@@ -265,7 +265,7 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector)
if (prop == NULL)
return;
- dev_priv->broadcast_rgb_property = prop;
+ dev_priv->display.properties.broadcast_rgb = prop;
}
drm_object_attach_property(&connector->base, prop, 0);
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index a753f6d66714..41ebdbd741c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -27,6 +27,7 @@
#include "intel_pm_types.h"
struct drm_i915_private;
+struct drm_property;
struct i915_audio_component;
struct i915_hdcp_comp_master;
struct intel_atomic_state;
@@ -373,6 +374,11 @@ struct intel_display {
struct mutex mutex;
} pps;
+ struct {
+ struct drm_property *broadcast_rgb;
+ struct drm_property *force_audio;
+ } properties;
+
struct {
unsigned long mask;
} quirks;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1bf7b13fdeda..ca97437f0e44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -317,9 +317,6 @@ struct drm_i915_private {
struct i915_gpu_error gpu_error;
- struct drm_property *broadcast_rgb_property;
- struct drm_property *force_audio_property;
-
/*
* Shadows for CHV DPLL_MD regs to keep the state
* checker somewhat working in the presence hardware
--
2.34.1
^ permalink raw reply related [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (38 preceding siblings ...)
2022-08-11 15:07 ` [Intel-gfx] [PATCH 39/39] drm/i915: move and group properties under display.properties Jani Nikula
@ 2022-08-11 15:15 ` Jani Nikula
2022-08-11 15:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (4 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Jani Nikula @ 2022-08-11 15:15 UTC (permalink / raw)
To: intel-gfx; +Cc: lucas.demarchi
On Thu, 11 Aug 2022, Jani Nikula <jani.nikula@intel.com> wrote:
> Add display sub-struct to drm_i915_private, and start moving display
> related members there.
>
> This doesn't help with build dependencies yet, but adds a lot of clarity
> in organizing the display data, and who accesses display data and where.
>
> This is a beginning, there are still stragglers, but need to start
> sending the patches instead of accumulating tons more.
Also pushed the lot to
https://cgit.freedesktop.org/~jani/drm/log/?h=display-substruct
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 110+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (39 preceding siblings ...)
2022-08-11 15:15 ` [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
@ 2022-08-11 15:38 ` Patchwork
2022-08-11 15:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Patchwork @ 2022-08-11 15:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private
URL : https://patchwork.freedesktop.org/series/107170/
State : warning
== Summary ==
Error: dim checkpatch failed
81a599e0acc6 drm/i915: add display sub-struct to drm_i915_private
Traceback (most recent call last):
File "scripts/spdxcheck.py", line 11, in <module>
import git
ModuleNotFoundError: No module named 'git'
-:125: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#125:
new file mode 100644
-:147: WARNING:BLOCK_COMMENT_STYLE: Block comments use a trailing */ on a separate line
#147: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:18:
+ * fills out the pipe-config with the hw state. */
-:148: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc *' should also have an identifier name
#148: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:19:
+ bool (*get_pipe_config)(struct intel_crtc *,
-:148: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc_state *' should also have an identifier name
#148: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:19:
+ bool (*get_pipe_config)(struct intel_crtc *,
-:150: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_crtc *' should also have an identifier name
#150: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:21:
+ void (*get_initial_plane_config)(struct intel_crtc *,
-:150: WARNING:FUNCTION_ARGUMENTS: function definition argument 'struct intel_initial_plane_config *' should also have an identifier name
#150: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:21:
+ void (*get_initial_plane_config)(struct intel_crtc *,
total: 0 errors, 6 warnings, 0 checks, 198 lines checked
98eec48f505c drm/i915: move cdclk_funcs to display.funcs
699528783267 drm/i915: move dpll_funcs to display.funcs
22eeabd10546 drm/i915: move hotplug_funcs to display.funcs
af7f4c94cba1 drm/i915: move clock_gating_funcs to display.funcs
5902bf135e5f drm/i915: move wm_disp funcs to display.funcs
763b41870eb1 drm/i915: move fdi_funcs to display.funcs
d4e25a89ea42 drm/i915: move color_funcs to display.funcs
97a1a55d792b drm/i915: move and group gmbus members under display.gmbus
-:347: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns
#347: FILE: drivers/gpu/drm/i915/i915_reg.h:1485:
+#define GMBUS0 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5100) /* clock/port select */
-:356: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#356: FILE: drivers/gpu/drm/i915/i915_reg.h:1494:
+#define GMBUS1 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5104) /* command/status */
-:375: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#375: FILE: drivers/gpu/drm/i915/i915_reg.h:1517:
+#define GMBUS3 _MMIO(dev_priv->display.gmbus.mmio_base + 0x510c) /* data buffer bytes 3-0 */
-:376: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#376: FILE: drivers/gpu/drm/i915/i915_reg.h:1518:
+#define GMBUS4 _MMIO(dev_priv->display.gmbus.mmio_base + 0x5110) /* interrupt mask (Pineview+) */
total: 0 errors, 4 warnings, 0 checks, 320 lines checked
c81231bd7491 drm/i915: move and group pps members under display.pps
9691040cd55f drm/i915: move dmc to display.dmc
-:210: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#210: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:455:
+ !intel_de_read(i915, DMC_PROGRAM(i915->display.dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
total: 0 errors, 1 warnings, 0 checks, 339 lines checked
cb5448c3b8e0 drm/i915: move and split audio under display.audio and display.funcs
-:318: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "dev_priv->display.audio.lpe.platdev"
#318: FILE: drivers/gpu/drm/i915/display/intel_audio.c:1406:
+ if (dev_priv->display.audio.lpe.platdev != NULL)
-:394: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "display.audio.lpe.platdev"
#394: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:78:
+#define HAS_LPE_AUDIO(dev_priv) ((dev_priv)->display.audio.lpe.platdev != NULL)
-:403: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#403: FILE: drivers/gpu/drm/i915/display/intel_lpe_audio.c:100:
+ rsc[0].start = rsc[0].end = dev_priv->display.audio.lpe.irq;
total: 0 errors, 0 warnings, 3 checks, 501 lines checked
45cea2c0cb3f drm/i915: move dpll under display.dpll
-:213: CHECK:UNCOMMENTED_DEFINITION: struct mutex definition without comment
#213: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:89:
+ struct mutex lock;
-:562: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON & recovery code rather than BUG() or BUG_ON()
#562: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:4210:
+ BUG_ON(dev_priv->display.dpll.num_shared_dpll > I915_NUM_PLLS);
total: 0 errors, 1 warnings, 1 checks, 628 lines checked
911a4d8416a9 drm/i915: move and group fbdev under display.fbdev
44d269d91c7f drm/i915: move wm to display.wm
a73009c01d23 drm/i915: move and group hdcp under display.hdcp
2a6c083eab3a drm/i915: move hotplug to display.hotplug
-:434: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#434: FILE: drivers/gpu/drm/i915/display/intel_hotplug.c:570:
+ queue_work(dev_priv->display.hotplug.dp_wq, &dev_priv->display.hotplug.dig_port_work);
-:590: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!dev_priv->display.hotplug.dp_wq"
#590: FILE: drivers/gpu/drm/i915/i915_driver.c:256:
+ if (dev_priv->display.hotplug.dp_wq == NULL)
total: 0 errors, 1 warnings, 1 checks, 738 lines checked
b6f4b60b07d8 drm/i915: move overlay to display.overlay
05330effbd89 drm/i915: move and group sagv under display.sagv
-:210: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#210: FILE: drivers/gpu/drm/i915/intel_pm.c:5599:
+ latency = dev_priv->display.sagv.block_time_us + dev_priv->display.wm.skl_latency[0];
total: 0 errors, 1 warnings, 0 checks, 174 lines checked
1527cbe5e360 drm/i915: move and group max_bw and bw_obj under display.bw
5f212c8cffc9 drm/i915: move opregion to display.opregion
e193c1b4ed89 drm/i915: move and group cdclk under display.cdclk
-:41: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/intel_audio.c:974:
+ get_aud_ts_cdclk_m_n(i915->display.cdclk.hw.ref, i915->display.cdclk.hw.cdclk, &aud_ts);
-:702: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#702: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:80:
+ to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:705: WARNING:LONG_LINE: line length of 120 exceeds 100 columns
#705: FILE: drivers/gpu/drm/i915/display/intel_cdclk.h:82:
+ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj))
-:733: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#733: FILE: drivers/gpu/drm/i915/display/intel_display.c:8401:
+ cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
total: 0 errors, 3 warnings, 1 checks, 815 lines checked
1cd4ceb70c16 drm/i915: move backlight to display.backlight
1da9f25eea3a drm/i915: move mipi_mmio_base to display.dsi
8a9779b4fd6f drm/i915: move vbt to display.vbt
-:120: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#120: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1157:
+ i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7;
-:466: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#466: FILE: drivers/gpu/drm/i915/display/intel_bios.c:2823:
+ i915->display.vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915,
!HAS_PCH_SPLIT(i915));
-:926: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#926: FILE: drivers/gpu/drm/i915/display/intel_dpll_mgr.c:2773:
+ pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
total: 0 errors, 2 warnings, 1 checks, 1030 lines checked
715d5e56ca5b drm/i915: move fbc to display.fbc
5fad180f909e drm/i915/vrr: drop window2_delay member from i915
-:36: WARNING:TYPO_SPELLING: 'Substract' may be misspelled - perhaps 'Subtract'?
#36: FILE: drivers/gpu/drm/i915/display/intel_vrr.c:147:
+ * FIXME: Substract Window2 delay from below value.
^^^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 44 lines checked
cf5121f27e5e drm/i915: move and group power related members under display.power
-:385: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#385: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:1920:
+ i915->display.power.domains.disable_wakeref = intel_display_power_get(i915,
POWER_DOMAIN_INIT);
-:399: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#399: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:1946:
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
-:444: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#444: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:2067:
+ fetch_and_zero(&i915->display.power.domains.disable_wakeref));
total: 0 errors, 2 warnings, 1 checks, 683 lines checked
7dbf3b63780b drm/i915: move and group fdi members under display.fdi
-:20: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#20: FILE: drivers/gpu/drm/i915/display/intel_crt.c:1114:
+ dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
FDI_RX_CTL(PIPE_A)) & fdi_config;
total: 0 errors, 0 warnings, 1 checks, 67 lines checked
7761e27c8757 drm/i915: move fb_tracking under display sub-struct
-:25: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#25: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:123:
+ spinlock_t lock;
-:31: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#31: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:129:
+ unsigned busy_bits;
-:32: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#32: FILE: drivers/gpu/drm/i915/display/intel_display_core.h:130:
+ unsigned flip_bits;
total: 0 errors, 2 warnings, 1 checks, 200 lines checked
ada2d6104385 drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h
-:53: WARNING:TRAILING_SEMICOLON: macros should not use a trailing semicolon
#53: FILE: drivers/gpu/drm/i915/display/intel_frontbuffer.h:61:
+#define INTEL_FRONTBUFFER(pipe, plane_id) \
+ BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe));
-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#57: FILE: drivers/gpu/drm/i915/display/intel_frontbuffer.h:65:
+#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
+ GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
+ INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
total: 0 errors, 1 warnings, 1 checks, 64 lines checked
6e09cf9e9a8d drm/i915: move dbuf under display sub-struct
-:180: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#180: FILE: drivers/gpu/drm/i915/intel_pm.h:80:
+ to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
-:183: WARNING:LONG_LINE: line length of 118 exceeds 100 columns
#183: FILE: drivers/gpu/drm/i915/intel_pm.h:82:
+ to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.dbuf.obj))
total: 0 errors, 2 warnings, 0 checks, 136 lines checked
b4bb59b99188 drm/i915: move and group modeset_wq and flip_wq under display.wq
309e0c8e99e6 drm/i915: split gem quirks from display quirks
7d72fe97d832 drm/i915/quirks: abstract checking for display quirks
-:37: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#37: FILE: drivers/gpu/drm/i915/display/intel_backlight.c:130:
+ (dev_priv->params.invert_brightness == 0 && intel_has_quirk(dev_priv, QUIRK_INVERT_BRIGHTNESS)))
total: 0 errors, 1 warnings, 0 checks, 112 lines checked
1261c09ec71b drm/i915/quirks: abstract quirks further by making quirk ids an enum
856c7041cdfc drm/i915: move quirks under display sub-struct
b87932c1ae0e drm/i915: move atomic_helper under display sub-struct
dfb37a2ed796 drm/i915: move and group properties under display.properties
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 84 lines checked
^ permalink raw reply [flat|nested] 110+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (40 preceding siblings ...)
2022-08-11 15:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-08-11 15:38 ` Patchwork
2022-08-11 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
44 siblings, 0 replies; 110+ messages in thread
From: Patchwork @ 2022-08-11 15:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private
URL : https://patchwork.freedesktop.org/series/107170/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 110+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (41 preceding siblings ...)
2022-08-11 15:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-08-11 15:58 ` Patchwork
2022-08-12 0:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-08-17 4:52 ` [Intel-gfx] [PATCH 00/39] " Lucas De Marchi
44 siblings, 0 replies; 110+ messages in thread
From: Patchwork @ 2022-08-11 15:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 22150 bytes --]
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private
URL : https://patchwork.freedesktop.org/series/107170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11983 -> Patchwork_107170v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/index.html
Participating hosts (29 -> 38)
------------------------------
Additional (13): bat-dg1-6 bat-dg1-5 bat-dg2-8 bat-adlm-1 bat-dg2-9 bat-adlp-6 bat-adlp-4 bat-adln-1 fi-cfl-8109u bat-rplp-1 bat-rpls-1 bat-rpls-2 bat-jsl-1
Missing (4): fi-ctg-p8600 fi-rkl-11600 fi-hsw-4200u fi-snb-2600
Known issues
------------
Here are the changes found in Patchwork_107170v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@nullptr:
- bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@fbdev@nullptr.html
* igt@fbdev@read:
- bat-adlp-4: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@fbdev@read.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-apl-guc/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlp-4: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][7] ([i915#4083])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4083])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4077]) +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][12] ([i915#4079]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@gem_tiled_pread_basic.html
- bat-adlp-4: NOTRUN -> [SKIP][13] ([i915#3282])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#1155])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
- bat-adlp-4: NOTRUN -> [SKIP][15] ([i915#1155])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#1155])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][17] -> [INCOMPLETE][18] ([i915#5847])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-skl-6700k2: [PASS][19] -> [DMESG-FAIL][20] ([i915#5334])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-skl-6700k2/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][21] ([i915#4957])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
- bat-dg1-6: NOTRUN -> [DMESG-FAIL][22] ([i915#4494] / [i915#4957])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][23] -> [DMESG-FAIL][24] ([i915#4528])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-blb-e6850/igt@i915_selftest@live@requests.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][25] ([i915#6011])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@i915_suspend@basic-s2idle-without-i915.html
- bat-dg1-5: NOTRUN -> [INCOMPLETE][26] ([i915#6011])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][27] ([i915#4212]) +7 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][28] ([i915#4215])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-6: NOTRUN -> [SKIP][29] ([i915#4215])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-6: NOTRUN -> [SKIP][30] ([i915#4212]) +7 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#1845] / [i915#4303])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_busy@basic.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-apl-guc: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-apl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][33] ([fdo#111827]) +8 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html
- bat-dg1-5: NOTRUN -> [SKIP][34] ([fdo#111827]) +7 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- bat-dg1-6: NOTRUN -> [SKIP][35] ([fdo#111827]) +7 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-cfl-8109u: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +8 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor:
- bat-dg1-6: NOTRUN -> [SKIP][37] ([i915#4103] / [i915#4213])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
- fi-bsw-kefka: [PASS][38] -> [FAIL][39] ([i915#6298])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlp-4: NOTRUN -> [SKIP][40] ([i915#3637]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlp-4: NOTRUN -> [SKIP][41] ([i915#4093]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][42] ([fdo#109285])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-6: NOTRUN -> [SKIP][43] ([fdo#109285])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-4: NOTRUN -> [SKIP][44] ([i915#4342])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@nonblocking-crc:
- bat-dg1-5: NOTRUN -> [SKIP][45] ([i915#4078]) +13 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_pipe_crc_basic@nonblocking-crc.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence:
- bat-adlp-4: NOTRUN -> [SKIP][46] ([i915#3546]) +10 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html
* igt@kms_psr@primary_page_flip:
- bat-dg1-5: NOTRUN -> [SKIP][47] ([i915#1072] / [i915#4078]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- bat-dg1-6: NOTRUN -> [SKIP][48] ([i915#1072] / [i915#4078]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_psr@sprite_plane_onoff.html
- bat-adlp-4: NOTRUN -> [SKIP][49] ([i915#1072]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_psr@sprite_plane_onoff.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-5: NOTRUN -> [SKIP][50] ([i915#3555])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg1-6: NOTRUN -> [SKIP][51] ([i915#3555])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlp-4: NOTRUN -> [SKIP][52] ([i915#3555] / [i915#4579])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlp-4: NOTRUN -> [SKIP][53] ([fdo#109295] / [i915#3546] / [i915#3708])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@prime_vgem@basic-fence-flip.html
- bat-dg1-5: NOTRUN -> [SKIP][54] ([i915#1845] / [i915#3708])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- bat-dg1-5: NOTRUN -> [SKIP][55] ([i915#3708]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][56] ([i915#3708] / [i915#4077]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html
- bat-dg1-5: NOTRUN -> [SKIP][57] ([i915#3708] / [i915#4077]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- fi-cfl-8109u: NOTRUN -> [SKIP][58] ([fdo#109271]) +10 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-cfl-8109u/igt@prime_vgem@basic-userptr.html
- bat-dg1-6: NOTRUN -> [SKIP][59] ([i915#3708] / [i915#4873])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html
- bat-adlp-4: NOTRUN -> [SKIP][60] ([fdo#109295] / [i915#3301] / [i915#3708])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@prime_vgem@basic-userptr.html
- bat-dg1-5: NOTRUN -> [SKIP][61] ([i915#3708] / [i915#4873])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- bat-dg1-6: NOTRUN -> [SKIP][62] ([i915#3708]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@prime_vgem@basic-write.html
- bat-adlp-4: NOTRUN -> [SKIP][63] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-adlp-4/igt@prime_vgem@basic-write.html
* igt@runner@aborted:
- bat-dg1-5: NOTRUN -> [FAIL][64] ([i915#4312] / [i915#5257])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-5/igt@runner@aborted.html
- bat-dg1-6: NOTRUN -> [FAIL][65] ([i915#4312] / [i915#5257])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/bat-dg1-6/igt@runner@aborted.html
- fi-bsw-nick: NOTRUN -> [FAIL][66] ([fdo#109271] / [i915#4312])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-bsw-nick/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [INCOMPLETE][67] ([i915#6533]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4342]: https://gitlab.freedesktop.org/drm/intel/issues/4342
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#5153]: https://gitlab.freedesktop.org/drm/intel/issues/5153
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537
[i915#5847]: https://gitlab.freedesktop.org/drm/intel/issues/5847
[i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950
[i915#6011]: https://gitlab.freedesktop.org/drm/intel/issues/6011
[i915#6297]: https://gitlab.freedesktop.org/drm/intel/issues/6297
[i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6531]: https://gitlab.freedesktop.org/drm/intel/issues/6531
[i915#6533]: https://gitlab.freedesktop.org/drm/intel/issues/6533
Build changes
-------------
* Linux: CI_DRM_11983 -> Patchwork_107170v1
CI-20190529: 20190529
CI_DRM_11983: be61f160096902ab2f402179c81f6de59b016d82 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6621: 62685978a0c00bb4b874935129b9761ae10d5ca1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107170v1: be61f160096902ab2f402179c81f6de59b016d82 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
13c1b8e7e6b5 drm/i915: move and group properties under display.properties
b9e74f9c3726 drm/i915: move atomic_helper under display sub-struct
c21adb4e612d drm/i915: move quirks under display sub-struct
70427ae20e4a drm/i915/quirks: abstract quirks further by making quirk ids an enum
749d9ac037ac drm/i915/quirks: abstract checking for display quirks
b28e422dbcc1 drm/i915: split gem quirks from display quirks
dacf3a3beb21 drm/i915: move and group modeset_wq and flip_wq under display.wq
6a1fda99b6ec drm/i915: move dbuf under display sub-struct
15c5601052bb drm/i915: move INTEL_FRONTBUFFER_* macros to intel_frontbuffer.h
f8c6d650f22e drm/i915: move fb_tracking under display sub-struct
d08ab9f2db6c drm/i915: move and group fdi members under display.fdi
ac9771b0eda8 drm/i915: move and group power related members under display.power
52e709f45d4b drm/i915/vrr: drop window2_delay member from i915
d845d1e8c9a8 drm/i915: move fbc to display.fbc
61995fd9949f drm/i915: move vbt to display.vbt
0246de41833c drm/i915: move mipi_mmio_base to display.dsi
4b6d84fd1029 drm/i915: move backlight to display.backlight
b4d66dac6ec0 drm/i915: move and group cdclk under display.cdclk
efe269abf8ef drm/i915: move opregion to display.opregion
34282f2273d4 drm/i915: move and group max_bw and bw_obj under display.bw
42f39a0a4e80 drm/i915: move and group sagv under display.sagv
213afa4afcfc drm/i915: move overlay to display.overlay
12901d325160 drm/i915: move hotplug to display.hotplug
1f3d6e226eb5 drm/i915: move and group hdcp under display.hdcp
e9f4ec8f74c7 drm/i915: move wm to display.wm
3f35c02a408b drm/i915: move and group fbdev under display.fbdev
95135ba8ee1f drm/i915: move dpll under display.dpll
e5223855144b drm/i915: move and split audio under display.audio and display.funcs
16d3a0f999ac drm/i915: move dmc to display.dmc
086157a50dd0 drm/i915: move and group pps members under display.pps
f22526ad0c49 drm/i915: move and group gmbus members under display.gmbus
a083842cd0ec drm/i915: move color_funcs to display.funcs
9c47c12b7b77 drm/i915: move fdi_funcs to display.funcs
ad9f3ff1080c drm/i915: move wm_disp funcs to display.funcs
df2233ea0e1b drm/i915: move clock_gating_funcs to display.funcs
36dcc4ad40bf drm/i915: move hotplug_funcs to display.funcs
58132a37a737 drm/i915: move dpll_funcs to display.funcs
49cc074d7acb drm/i915: move cdclk_funcs to display.funcs
e2f30b144cf7 drm/i915: add display sub-struct to drm_i915_private
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/index.html
[-- Attachment #2: Type: text/html, Size: 26725 bytes --]
^ permalink raw reply [flat|nested] 110+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (42 preceding siblings ...)
2022-08-11 15:58 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-08-12 0:40 ` Patchwork
2022-08-17 4:52 ` [Intel-gfx] [PATCH 00/39] " Lucas De Marchi
44 siblings, 0 replies; 110+ messages in thread
From: Patchwork @ 2022-08-12 0:40 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 53112 bytes --]
== Series Details ==
Series: drm/i915: add display sub-struct to drm_i915_private
URL : https://patchwork.freedesktop.org/series/107170/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11983_full -> Patchwork_107170v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_107170v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- {shard-rkl}: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
Known issues
------------
Here are the changes found in Patchwork_107170v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [FAIL][50], [PASS][51]) ([i915#4392])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk1/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk2/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk3/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk7/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk7/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk8/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk1/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk9/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk8/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk8/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk7/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk7/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk7/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk3/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk3/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk2/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk2/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk2/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk2/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@preservation-s3@rcs0:
- shard-apl: [PASS][52] -> [DMESG-WARN][53] ([i915#180]) +2 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-apl7/igt@gem_ctx_isolation@preservation-s3@rcs0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl2/igt@gem_ctx_isolation@preservation-s3@rcs0.html
* igt@gem_ctx_persistence@engines-hang:
- shard-snb: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#1099])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-snb5/igt@gem_ctx_persistence@engines-hang.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [PASS][55] -> [SKIP][56] ([i915#4525]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb8/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [PASS][57] -> [FAIL][58] ([i915#2842])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-tglb7/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][59] -> [FAIL][60] ([i915#2851])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-pace@rcs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][61] -> [FAIL][62] ([i915#2842])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][63] -> [FAIL][64] ([i915#2842])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_lmem_swapping@smem-oom:
- shard-apl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#4613]) +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl1/igt@gem_lmem_swapping@smem-oom.html
* igt@gem_lmem_swapping@verify-random:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#4613]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@gem_lmem_swapping@verify-random.html
* igt@gem_spin_batch@spin-each:
- shard-apl: [PASS][67] -> [FAIL][68] ([i915#2898])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-apl1/igt@gem_spin_batch@spin-each.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl8/igt@gem_spin_batch@spin-each.html
* igt@gen7_exec_parse@oacontrol-tracking:
- shard-snb: NOTRUN -> [SKIP][69] ([fdo#109271]) +63 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-snb5/igt@gen7_exec_parse@oacontrol-tracking.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-kbl: NOTRUN -> [SKIP][70] ([fdo#109271]) +102 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][71] -> [INCOMPLETE][72] ([i915#3921])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-snb2/igt@i915_selftest@live@hangcheck.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-snb2/igt@i915_selftest@live@hangcheck.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1:
- shard-skl: [PASS][73] -> [FAIL][74] ([i915#2521]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-c-edp-1.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][75] ([i915#3743])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl10/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#3886]) +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl4/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +16 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl1/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][80] ([fdo#109271]) +82 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl1/igt@kms_ccs@pipe-d-bad-pixel-format-y_tiled_gen12_mc_ccs.html
* igt@kms_chamelium@dp-hpd-storm:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [fdo#111827]) +3 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@kms_chamelium@dp-hpd-storm.html
* igt@kms_chamelium@hdmi-audio:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [fdo#111827]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl1/igt@kms_chamelium@hdmi-audio.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-glk: NOTRUN -> [SKIP][83] ([fdo#109271] / [fdo#111827])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-snb: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-snb5/igt@kms_chamelium@hdmi-hpd-storm.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions:
- shard-iclb: [PASS][85] -> [FAIL][86] ([i915#5072])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions.html
* igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size:
- shard-skl: NOTRUN -> [INCOMPLETE][87] ([i915#6528])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl1/igt@kms_cursor_legacy@cursor-vs-flip@atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][88] -> [FAIL][89] ([i915#4767])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl6/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][90] -> [FAIL][91] ([i915#2122])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][92] -> [FAIL][93] ([i915#79])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@c-dp1:
- shard-kbl: [PASS][94] -> [FAIL][95] ([i915#79])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl4/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@kms_flip@flip-vs-expired-vblank@c-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-kbl: [PASS][96] -> [DMESG-WARN][97] ([i915#180]) +6 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][98] ([i915#2672]) +5 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode:
- shard-iclb: [PASS][99] -> [SKIP][100] ([i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#3555])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-downscaling@pipe-a-default-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#2672] / [i915#3555])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite:
- shard-glk: NOTRUN -> [SKIP][103] ([fdo#109271]) +26 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html
* igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1:
- shard-kbl: NOTRUN -> [DMESG-WARN][104] ([i915#180])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-kbl: NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-glk: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [PASS][107] -> [FAIL][108] ([fdo#108145] / [i915#265])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-glk: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#658])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@overlay-plane-update-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#658])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl4/igt@kms_psr2_sf@overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [i915#658]) +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [PASS][112] -> [SKIP][113] ([fdo#109642] / [fdo#111068] / [i915#658])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb1/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: [PASS][114] -> [SKIP][115] ([fdo#109441]) +1 similar issue
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_gtt.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2437])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@kms_writeback@writeback-check-output.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][117] -> [FAIL][118] ([i915#5639])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl1/igt@perf@polling-parameterized.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl6/igt@perf@polling-parameterized.html
* igt@sysfs_clients@fair-3:
- shard-kbl: NOTRUN -> [SKIP][119] ([fdo#109271] / [i915#2994])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@fair-7:
- shard-apl: NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#2994]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl1/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@split-10:
- shard-glk: NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#2994])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@device_reset@unbind-reset-rebind:
- {shard-rkl}: [FAIL][122] ([i915#4778]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@device_reset@unbind-reset-rebind.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@device_reset@unbind-reset-rebind.html
* igt@fbdev@pan:
- {shard-rkl}: [SKIP][124] ([i915#2582]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@fbdev@pan.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@fbdev@pan.html
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][126] ([i915#658]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb6/igt@feature_discovery@psr2.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_ctx_exec@basic-nohangcheck:
- {shard-tglu}: [FAIL][128] ([i915#6268]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglu-1/igt@gem_ctx_exec@basic-nohangcheck.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-tglu-1/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@engines-hang@vcs0:
- {shard-dg1}: [FAIL][130] ([i915#4883]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-dg1-17/igt@gem_ctx_persistence@engines-hang@vcs0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-dg1-16/igt@gem_ctx_persistence@engines-hang@vcs0.html
* igt@gem_eio@hibernate:
- shard-snb: [INCOMPLETE][132] -> [PASS][133]
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-snb5/igt@gem_eio@hibernate.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-snb5/igt@gem_eio@hibernate.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- {shard-tglu}: [FAIL][134] ([i915#2842]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglu-5/igt@gem_exec_fair@basic-none-share@rcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-tglu-2/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [FAIL][136] ([i915#2842]) -> [PASS][137]
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][138] ([i915#2842]) -> [PASS][139] +1 similar issue
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk6/igt@gem_exec_fair@basic-none@vcs0.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk3/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- {shard-rkl}: [SKIP][140] ([i915#3281]) -> [PASS][141] +4 similar issues
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-noreloc.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_fence_thrash@bo-write-verify-none:
- {shard-rkl}: [SKIP][142] ([fdo#109315]) -> [PASS][143] +25 similar issues
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@gem_fence_thrash@bo-write-verify-none.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@gem_fence_thrash@bo-write-verify-none.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- {shard-rkl}: [SKIP][144] ([i915#3282]) -> [PASS][145] +3 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@gem_partial_pwrite_pread@reads-uncached.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- {shard-rkl}: [INCOMPLETE][146] ([i915#3692]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@gem_ppgtt@blt-vs-render-ctxn.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][148] ([i915#180]) -> [PASS][149] +3 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
* igt@gen9_exec_parse@allowed-single:
- shard-kbl: [DMESG-WARN][150] ([i915#5566] / [i915#716]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gen9_exec_parse@allowed-single.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@basic-rejected:
- {shard-rkl}: [SKIP][152] ([i915#2527]) -> [PASS][153] +1 similar issue
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@gen9_exec_parse@basic-rejected.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- {shard-dg1}: [SKIP][154] ([i915#1397]) -> [PASS][155]
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-dg1-15/igt@i915_pm_rpm@modeset-lpsp-stress.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-dg1-19/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@system-suspend-devices:
- {shard-rkl}: [SKIP][156] ([i915#5174]) -> [PASS][157]
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@i915_pm_rpm@system-suspend-devices.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@i915_pm_rpm@system-suspend-devices.html
* igt@i915_pm_sseu@full-enable:
- {shard-rkl}: [SKIP][158] ([i915#4387]) -> [PASS][159]
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@i915_pm_sseu@full-enable.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@gt_pm:
- {shard-tglu}: [DMESG-FAIL][160] ([i915#3987]) -> [PASS][161]
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglu-8/igt@i915_selftest@live@gt_pm.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-tglu-4/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@fence-restore-untiled:
- shard-skl: [INCOMPLETE][162] ([i915#4817] / [i915#4939]) -> [PASS][163]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl9/igt@i915_suspend@fence-restore-untiled.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1:
- shard-skl: [FAIL][164] ([i915#2521]) -> [PASS][165]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl10/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl6/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-edp-1.html
* igt@kms_atomic@atomic_plane_damage:
- {shard-rkl}: [SKIP][166] ([i915#4098]) -> [PASS][167]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@kms_atomic@atomic_plane_damage.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_atomic@atomic_plane_damage.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- {shard-rkl}: [SKIP][168] ([i915#1845] / [i915#4098]) -> [PASS][169] +21 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled:
- {shard-rkl}: [SKIP][170] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][171] +7 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-ytiled.html
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-skl: [FAIL][172] ([i915#79]) -> [PASS][173] +1 similar issue
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* igt@kms_flip@plain-flip-ts-check@a-edp1:
- shard-skl: [FAIL][174] ([i915#2122]) -> [PASS][175]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl6/igt@kms_flip@plain-flip-ts-check@a-edp1.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl10/igt@kms_flip@plain-flip-ts-check@a-edp1.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt:
- {shard-rkl}: [SKIP][176] ([i915#1849] / [i915#4098]) -> [PASS][177] +12 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_plane@plane-position-hole@pipe-b-planes:
- {shard-rkl}: [SKIP][178] ([i915#1849] / [i915#3558]) -> [PASS][179] +4 similar issues
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@kms_plane@plane-position-hole@pipe-b-planes.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_plane@plane-position-hole@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- {shard-rkl}: [SKIP][180] ([i915#2575]) -> [PASS][181] +7 similar issues
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- {shard-rkl}: [SKIP][182] ([i915#1849] / [i915#3546] / [i915#4070] / [i915#4098]) -> [PASS][183] +1 similar issue
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- {shard-rkl}: [SKIP][184] ([i915#1849] / [i915#3546] / [i915#4098]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1:
- shard-iclb: [SKIP][186] ([i915#5235]) -> [PASS][187] +2 similar issues
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-b-edp-1.html
* igt@kms_psr@primary_render:
- {shard-rkl}: [SKIP][188] ([i915#1072]) -> [PASS][189] +1 similar issue
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@kms_psr@primary_render.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_psr@primary_render.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][190] ([fdo#109441]) -> [PASS][191] +2 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- {shard-rkl}: [SKIP][192] ([i915#5461]) -> [PASS][193]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-b:
- {shard-rkl}: [SKIP][194] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][195]
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@kms_universal_plane@disable-primary-vs-flip-pipe-b.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-b.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][196] ([i915#180]) -> [PASS][197] +4 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-apl3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl1/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@perf@polling:
- shard-skl: [FAIL][198] ([i915#1542]) -> [PASS][199]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-skl7/igt@perf@polling.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-skl4/igt@perf@polling.html
* igt@perf@polling-parameterized:
- {shard-rkl}: [FAIL][200] ([i915#5639]) -> [PASS][201]
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-2/igt@perf@polling-parameterized.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-2/igt@perf@polling-parameterized.html
* igt@perf@short-reads:
- {shard-rkl}: [SKIP][202] ([i915#5608]) -> [PASS][203]
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-rkl-5/igt@perf@short-reads.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-rkl-6/igt@perf@short-reads.html
* igt@perf@stress-open-close:
- shard-glk: [INCOMPLETE][204] ([i915#5213]) -> [PASS][205]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-glk7/igt@perf@stress-open-close.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-glk5/igt@perf@stress-open-close.html
#### Warnings ####
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][206] ([i915#3063]) -> [FAIL][207] ([i915#5784])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-tglb7/igt@gem_eio@unwedge-stress.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-tglb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][208] ([i915#2842]) -> [FAIL][209] ([i915#2852])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb4/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [FAIL][210] ([i915#2842]) -> [SKIP][211] ([fdo#109271])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][212] ([i915#588]) -> [SKIP][213] ([i915#658])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][214] ([i915#4767]) -> [INCOMPLETE][215] ([i915#180] / [i915#1982] / [i915#4939])
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf:
- shard-iclb: [SKIP][216] ([i915#2920]) -> [SKIP][217] ([i915#658]) +1 similar issue
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb8/igt@kms_psr2_sf@overlay-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: [FAIL][218] ([i915#5939]) -> [SKIP][219] ([fdo#109642] / [fdo#111068] / [i915#658])
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-iclb2/igt@kms_psr2_su@page_flip-nv12.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-iclb1/igt@kms_psr2_su@page_flip-nv12.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][220], [FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#716] / [i915#92]) -> ([FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232], [FAIL][233], [FAIL][234], [FAIL][235], [FAIL][236], [FAIL][237]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl1/igt@runner@aborted.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl4/igt@runner@aborted.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl1/igt@runner@aborted.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl4/igt@runner@aborted.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl4/igt@runner@aborted.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl1/igt@runner@aborted.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11983/shard-kbl7/igt@runner@aborted.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@runner@aborted.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@runner@aborted.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@runner@aborted.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl4/igt@runner@aborted.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/shard-kbl1/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1850]: https://gitlab.freedesktop.org/drm/intel/issues/1850
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2898]: https://gitlab.freedesktop.org/drm/intel/issues/2898
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3692]: https://gitlab.freedesktop.org/drm/intel/issues/3692
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3987]: https://gitlab.freedesktop.org/drm/intel/issues/3987
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4778]: https://gitlab.freedesktop.org/drm/intel/issues/4778
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4939]: https://gitlab.freedesktop.org/drm/intel/issues/4939
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#5072]: https://gitlab.freedesktop.org/drm/intel/issues/5072
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5775]: https://gitlab.freedesktop.org/drm/intel/issues/5775
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/intel/issues/6344
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6474]: https://gitlab.freedesktop.org/drm/intel/issues/6474
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#6528]: https://gitlab.freedesktop.org/drm/intel/issues/6528
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* Linux: CI_DRM_11983 -> Patchwork_107170v1
CI-20190529: 20190529
CI_DRM_11983: be61f160096902ab2f402179c81f6de59b016d82 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6621: 62685978a0c00bb4b874935129b9761ae10d5ca1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_107170v1: be61f160096902ab2f402179c81f6de59b016d82 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_107170v1/index.html
[-- Attachment #2: Type: text/html, Size: 57294 bytes --]
^ permalink raw reply [flat|nested] 110+ messages in thread* Re: [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private
2022-08-11 15:07 [Intel-gfx] [PATCH 00/39] drm/i915: add display sub-struct to drm_i915_private Jani Nikula
` (43 preceding siblings ...)
2022-08-12 0:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2022-08-17 4:52 ` Lucas De Marchi
44 siblings, 0 replies; 110+ messages in thread
From: Lucas De Marchi @ 2022-08-17 4:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, Aug 11, 2022 at 06:07:11PM +0300, Jani Nikula wrote:
>Add display sub-struct to drm_i915_private, and start moving display
>related members there.
>
>This doesn't help with build dependencies yet, but adds a lot of clarity
>in organizing the display data, and who accesses display data and where.
>
>This is a beginning, there are still stragglers, but need to start
>sending the patches instead of accumulating tons more.
>
>BR,
>Jani.
I was not sure if I would have time to review all the patches, so I
started adding my r-b on each of them. But I made it through the end.
You can add my Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
on all of them, except patch 5.
For patch 5, movingo clock_gating_funcs, I'm not really sure it's what
we want.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 110+ messages in thread