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From: Richard Henderson <richard.henderson@linaro.org>
To: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Cc: ycliang@andestech.com, qemu-riscv@nongnu.org,
	alankao@andestech.com, wangjunqiang@iscas.ac.cn,
	dylan@andestech.com, qemu-devel@nongnu.org, alistair23@gmail.com,
	bmeng.cn@gmail.com
Subject: Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
Date: Fri, 22 Oct 2021 08:59:55 -0700	[thread overview]
Message-ID: <04cab623-4695-097f-28b2-96e80c7a5ad2@linaro.org> (raw)
In-Reply-To: <YXJ3lEChs9bSkqSZ@ruinland-x1c>

On 10/22/21 1:34 AM, Ruinland ChuanTzu Tsai wrote:
>>> +    /* Custom CSR value holder per hart */
>>> +    void *custom_csr_val;
>>>    };
>>
>> Value singular?  Anyhow, I think that it's a mistake trying to hide the
>> value structure in another file.  It complicates allocation of the
>> CPURISCVState, and you have no mechanism by which to migrate the csr values.
> 
> What I'm trying to do here is to provide a hook for CSR value storage and let
> it being set during CPU initilization. We have heterogeneous harts which
> have different sets of CSRs.

I understand that, but the common CPURISCVState should contain the storage for all of the 
CSRs for every possible hart.

I might have made a different call if we had a more object-y language, but we have C.  The 
difference in size (here exactly one word) is not worth the complication of splitting 
structures apart.


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Ruinland ChuanTzu Tsai <ruinland@andestech.com>
Cc: alistair23@gmail.com, wangjunqiang@iscas.ac.cn,
	bmeng.cn@gmail.com, ycliang@andestech.com, alankao@andestech.com,
	dylan@andestech.com, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: Re: [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw()
Date: Fri, 22 Oct 2021 08:59:55 -0700	[thread overview]
Message-ID: <04cab623-4695-097f-28b2-96e80c7a5ad2@linaro.org> (raw)
In-Reply-To: <YXJ3lEChs9bSkqSZ@ruinland-x1c>

On 10/22/21 1:34 AM, Ruinland ChuanTzu Tsai wrote:
>>> +    /* Custom CSR value holder per hart */
>>> +    void *custom_csr_val;
>>>    };
>>
>> Value singular?  Anyhow, I think that it's a mistake trying to hide the
>> value structure in another file.  It complicates allocation of the
>> CPURISCVState, and you have no mechanism by which to migrate the csr values.
> 
> What I'm trying to do here is to provide a hook for CSR value storage and let
> it being set during CPU initilization. We have heterogeneous harts which
> have different sets of CSRs.

I understand that, but the common CPURISCVState should contain the storage for all of the 
CSRs for every possible hart.

I might have made a different call if we had a more object-y language, but we have C.  The 
difference in size (here exactly one word) is not worth the complication of splitting 
structures apart.


r~


  reply	other threads:[~2021-10-22 16:03 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-21 15:09 [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support Ruinland Chuan-Tzu Tsai
2021-10-21 15:09 ` Ruinland Chuan-Tzu Tsai
2021-10-21 15:09 ` [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models Ruinland Chuan-Tzu Tsai
2021-10-21 15:09   ` Ruinland Chuan-Tzu Tsai
2021-10-21 22:33   ` Alistair Francis
2021-10-21 22:33     ` Alistair Francis
2021-10-21 15:09 ` [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw() Ruinland Chuan-Tzu Tsai
2021-10-21 15:09   ` Ruinland Chuan-Tzu Tsai
2021-10-21 22:43   ` Alistair Francis
2021-10-21 22:43     ` Alistair Francis
2021-10-22  8:36     ` Ruinland ChuanTzu Tsai
2021-10-22  8:36       ` Ruinland ChuanTzu Tsai
2021-10-22  0:08   ` Richard Henderson
2021-10-22  0:08     ` Richard Henderson
2021-10-22  8:34     ` Ruinland ChuanTzu Tsai
2021-10-22  8:34       ` Ruinland ChuanTzu Tsai
2021-10-22 15:59       ` Richard Henderson [this message]
2021-10-22 15:59         ` Richard Henderson
2021-10-21 15:09 ` [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs Ruinland Chuan-Tzu Tsai
2021-10-21 15:09   ` Ruinland Chuan-Tzu Tsai
2021-10-21 22:44   ` Alistair Francis
2021-10-21 22:44     ` Alistair Francis
2021-10-22  8:37     ` Ruinland ChuanTzu Tsai
2021-10-22  8:37       ` Ruinland ChuanTzu Tsai
2021-10-22  1:12   ` Richard Henderson
2021-10-22  1:12     ` Richard Henderson
2021-10-21 22:47 ` [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support Alistair Francis
2021-10-21 22:47   ` Alistair Francis

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