From: Alistair Francis <alistair23@gmail.com> To: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> Cc: ycliang@andestech.com, "Alan Quey-Liang Kao\(\(\(\(\(\(\(\(\(\(\)" <alankao@andestech.com>, wangjunqiang <wangjunqiang@iscas.ac.cn>, Dylan Jhong <dylan@andestech.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, Bin Meng <bmeng.cn@gmail.com> Subject: Re: [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models Date: Fri, 22 Oct 2021 08:33:58 +1000 [thread overview] Message-ID: <CAKmqyKOH-vDG59DDC4CLmYo7v4vSyWxXoupNKXPpYyF61E=YPQ@mail.gmail.com> (raw) In-Reply-To: <20211021150921.721630-2-ruinland@andestech.com> On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> wrote: > > Introduce A25 and AX25 CPU model designed by Andes Technology. > > Signed-off-by: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 16 ++++++++++++++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7c626d89cd..0c93b7edd7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -168,6 +168,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -222,6 +229,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > + > +static void a25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -789,8 +803,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5896aca346..3bef0d1265 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -37,6 +37,8 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") > +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > -- > 2.25.1 >
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair23@gmail.com> To: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> Cc: wangjunqiang <wangjunqiang@iscas.ac.cn>, Bin Meng <bmeng.cn@gmail.com>, "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, "open list:RISC-V" <qemu-riscv@nongnu.org>, ycliang@andestech.com, "Alan Quey-Liang Kao(((((((((()" <alankao@andestech.com>, Dylan Jhong <dylan@andestech.com> Subject: Re: [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models Date: Fri, 22 Oct 2021 08:33:58 +1000 [thread overview] Message-ID: <CAKmqyKOH-vDG59DDC4CLmYo7v4vSyWxXoupNKXPpYyF61E=YPQ@mail.gmail.com> (raw) In-Reply-To: <20211021150921.721630-2-ruinland@andestech.com> On Fri, Oct 22, 2021 at 1:13 AM Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> wrote: > > Introduce A25 and AX25 CPU model designed by Andes Technology. > > Signed-off-by: Ruinland Chuan-Tzu Tsai <ruinland@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 16 ++++++++++++++++ > target/riscv/cpu.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7c626d89cd..0c93b7edd7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -168,6 +168,13 @@ static void rv64_base_cpu_init(Object *obj) > set_misa(env, RV64); > } > > +static void ax25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > + > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -222,6 +229,13 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_resetvec(env, DEFAULT_RSTVEC); > qdev_prop_set_bit(DEVICE(obj), "mmu", false); > } > + > +static void a25_cpu_init(Object *obj) > +{ > + CPURISCVState *env = &RISCV_CPU(obj)->env; > + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + set_priv_version(env, PRIV_VERSION_1_10_0); > +} > #endif > > static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) > @@ -789,8 +803,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_A25, a25_cpu_init), > #elif defined(TARGET_RISCV64) > DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_AX25, ax25_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5896aca346..3bef0d1265 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -37,6 +37,8 @@ > #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") > #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") > #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") > +#define TYPE_RISCV_CPU_A25 RISCV_CPU_TYPE_NAME("andes-a25") > +#define TYPE_RISCV_CPU_AX25 RISCV_CPU_TYPE_NAME("andes-ax25") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") > -- > 2.25.1 >
next prev parent reply other threads:[~2021-10-21 22:38 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-21 15:09 [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support Ruinland Chuan-Tzu Tsai 2021-10-21 15:09 ` Ruinland Chuan-Tzu Tsai 2021-10-21 15:09 ` [RFC PATCH v5 1/3] riscv: Adding Andes A25 and AX25 cpu models Ruinland Chuan-Tzu Tsai 2021-10-21 15:09 ` Ruinland Chuan-Tzu Tsai 2021-10-21 22:33 ` Alistair Francis [this message] 2021-10-21 22:33 ` Alistair Francis 2021-10-21 15:09 ` [RFC PATCH v5 2/3] riscv: Introduce custom CSR hooks to riscv_csrrw() Ruinland Chuan-Tzu Tsai 2021-10-21 15:09 ` Ruinland Chuan-Tzu Tsai 2021-10-21 22:43 ` Alistair Francis 2021-10-21 22:43 ` Alistair Francis 2021-10-22 8:36 ` Ruinland ChuanTzu Tsai 2021-10-22 8:36 ` Ruinland ChuanTzu Tsai 2021-10-22 0:08 ` Richard Henderson 2021-10-22 0:08 ` Richard Henderson 2021-10-22 8:34 ` Ruinland ChuanTzu Tsai 2021-10-22 8:34 ` Ruinland ChuanTzu Tsai 2021-10-22 15:59 ` Richard Henderson 2021-10-22 15:59 ` Richard Henderson 2021-10-21 15:09 ` [RFC PATCH v5 3/3] riscv: Enable custom CSR support for Andes AX25 and A25 CPUs Ruinland Chuan-Tzu Tsai 2021-10-21 15:09 ` Ruinland Chuan-Tzu Tsai 2021-10-21 22:44 ` Alistair Francis 2021-10-21 22:44 ` Alistair Francis 2021-10-22 8:37 ` Ruinland ChuanTzu Tsai 2021-10-22 8:37 ` Ruinland ChuanTzu Tsai 2021-10-22 1:12 ` Richard Henderson 2021-10-22 1:12 ` Richard Henderson 2021-10-21 22:47 ` [RFC PATCH v5 0/3] riscv: Add preliminary custom CSR support Alistair Francis 2021-10-21 22:47 ` Alistair Francis
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