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* [PULL 00/15] riscv-to-apply queue
@ 2024-03-22  8:53 Alistair Francis
  2024-03-22  8:53 ` [PULL 01/15] target/riscv: do not enable all named features by default Alistair Francis
                   ` (16 more replies)
  0 siblings, 17 replies; 30+ messages in thread
From: Alistair Francis @ 2024-03-22  8:53 UTC (permalink / raw)
  To: qemu-devel; +Cc: alistair23, Alistair Francis

The following changes since commit fea445e8fe9acea4f775a832815ee22bdf2b0222:

  Merge tag 'pull-maintainer-final-for-real-this-time-200324-1' of https://gitlab.com/stsquad/qemu into staging (2024-03-21 10:31:56 +0000)

are available in the Git repository at:

  https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240322

for you to fetch changes up to 385e575cd5ab2436c123e4b7f8c9b383a64c0dbe:

  target/riscv/kvm: fix timebase-frequency when using KVM acceleration (2024-03-22 15:41:01 +1000)

----------------------------------------------------------------
RISC-V PR for 9.0

* Do not enable all named features by default
* A range of Vector fixes
* Update APLIC IDC after claiming iforce register
* Remove the dependency of Zvfbfmin to Zfbfmin
* Fix mode in riscv_tlb_fill
* Fix timebase-frequency when using KVM acceleration

----------------------------------------------------------------
Daniel Henrique Barboza (10):
      target/riscv: do not enable all named features by default
      target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
      trans_rvv.c.inc: set vstart = 0 in int scalar move insns
      target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess
      target/riscv: always clear vstart in whole vec move insns
      target/riscv: always clear vstart for ldst_whole insns
      target/riscv/vector_helpers: do early exit when vstart >= vl
      target/riscv: remove 'over' brconds from vector trans
      trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
      target/riscv/vector_helper.c: optimize loops in ldst helpers

Frank Chang (1):
      hw/intc: Update APLIC IDC after claiming iforce register

Irina Ryapolova (1):
      target/riscv: Fix mode in riscv_tlb_fill

Ivan Klokov (1):
      target/riscv: enable 'vstart_eq_zero' in the end of insns

Max Chou (1):
      target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin

Yong-Xuan Wang (1):
      target/riscv/kvm: fix timebase-frequency when using KVM acceleration

 target/riscv/cpu_cfg.h                     |   8 +-
 target/riscv/kvm/kvm_riscv.h               |   1 +
 target/riscv/vector_internals.h            |   9 ++
 hw/intc/riscv_aplic.c                      |   1 +
 hw/riscv/virt.c                            |   2 +
 target/riscv/cpu.c                         |  40 ++---
 target/riscv/cpu_helper.c                  |   2 +-
 target/riscv/kvm/kvm-cpu.c                 |   9 ++
 target/riscv/tcg/tcg-cpu.c                 |  19 ++-
 target/riscv/translate.c                   |   6 +
 target/riscv/vcrypto_helper.c              |  32 ++++
 target/riscv/vector_helper.c               |  93 ++++++++++-
 target/riscv/vector_internals.c            |   4 +
 target/riscv/insn_trans/trans_rvbf16.c.inc |  18 +--
 target/riscv/insn_trans/trans_rvv.c.inc    | 244 +++++++++--------------------
 target/riscv/insn_trans/trans_rvvk.c.inc   |  30 +---
 16 files changed, 259 insertions(+), 259 deletions(-)


^ permalink raw reply	[flat|nested] 30+ messages in thread
* [PULL 00/15] riscv-to-apply queue
@ 2020-07-14  0:32 Alistair Francis
  2020-07-14  0:37 ` Alistair Francis
  2020-07-14 18:39 ` Peter Maydell
  0 siblings, 2 replies; 30+ messages in thread
From: Alistair Francis @ 2020-07-14  0:32 UTC (permalink / raw)
  To: qemu-devel; +Cc: Alistair Francis

The following changes since commit 20c1df5476e1e9b5d3f5b94f9f3ce01d21f14c46:

  Merge remote-tracking branch 'remotes/kraxel/tags/fixes-20200713-pull-request' into staging (2020-07-13 16:58:44 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200713

for you to fetch changes up to cfad709bceb629a4ebeb5d8a3acd1871b9a6436b:

  target/riscv: Fix pmp NA4 implementation (2020-07-13 17:25:37 -0700)

----------------------------------------------------------------
This is a colection of bug fixes and small imrprovements for RISC-V.

This includes some vector extensions fixes, a PMP bug fix, OpenTitan
UART bug fix and support for OpenSBI dynamic firmware.

----------------------------------------------------------------
Alexandre Mergnat (1):
      target/riscv: Fix pmp NA4 implementation

Alistair Francis (2):
      hw/char: Convert the Ibex UART to use the qdev Clock model
      hw/char: Convert the Ibex UART to use the registerfields API

Atish Patra (4):
      riscv: Unify Qemu's reset vector code path
      RISC-V: Copy the fdt in dram instead of ROM
      riscv: Add opensbi firmware dynamic support
      RISC-V: Support 64 bit start address

Bin Meng (3):
      MAINTAINERS: Add an entry for OpenSBI firmware
      hw/riscv: virt: Sort the SoC memmap table entries
      hw/riscv: Modify MROM size to end at 0x10000

Frank Chang (4):
      target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion
      target/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
      target/riscv: fix return value of do_opivx_widen()
      target/riscv: fix vill bit index in vtype register

Liao Pingfang (1):
      tcg/riscv: Remove superfluous breaks

 include/hw/char/ibex_uart.h             |  79 ++++++++--------
 include/hw/riscv/boot.h                 |   7 ++
 include/hw/riscv/boot_opensbi.h         |  58 ++++++++++++
 target/riscv/cpu.h                      |   2 +-
 hw/char/ibex_uart.c                     | 158 ++++++++++++++++++--------------
 hw/riscv/boot.c                         | 107 +++++++++++++++++++++
 hw/riscv/sifive_u.c                     |  53 ++++++-----
 hw/riscv/spike.c                        |  59 ++++--------
 hw/riscv/virt.c                         |  63 ++++---------
 target/riscv/insn_trans/trans_rvv.inc.c |   9 +-
 target/riscv/pmp.c                      |   2 +-
 tcg/riscv/tcg-target.inc.c              |   2 -
 MAINTAINERS                             |   7 ++
 13 files changed, 387 insertions(+), 219 deletions(-)
 create mode 100644 include/hw/riscv/boot_opensbi.h


^ permalink raw reply	[flat|nested] 30+ messages in thread
* [PULL 00/15] riscv-to-apply queue
@ 2020-06-03 16:13 Alistair Francis
  2020-06-04 11:40 ` Peter Maydell
  0 siblings, 1 reply; 30+ messages in thread
From: Alistair Francis @ 2020-06-03 16:13 UTC (permalink / raw)
  To: qemu-devel, peter.maydell; +Cc: alistair23, Alistair Francis

The following changes since commit 5cc7a54c2e91d82cb6a52e4921325c511fd90712:

  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into staging (2020-06-02 18:16:38 +0100)

are available in the Git repository at:

  git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200603

for you to fetch changes up to fe0fe4735e798578097758781166cc221319b93d:

  riscv: Initial commit of OpenTitan machine (2020-06-03 09:11:51 -0700)

----------------------------------------------------------------
This is a collection of RISC-V patches for 5.1.

This incldues removing deprecated features and part of the OpenTitan
support series.

----------------------------------------------------------------
Alistair Francis (11):
      hw/riscv: spike: Remove deprecated ISA specific machines
      target/riscv: Remove the deprecated CPUs
      target/riscv: Drop support for ISA spec version 1.09.1
      docs: deprecated: Update the -bios documentation
      riscv: sifive_e: Manually define the machine
      riscv/boot: Add a missing header include
      target/riscv: Don't overwrite the reset vector
      target/riscv: Disable the MMU correctly
      target/riscv: Don't set PMP feature in the cpu init
      target/riscv: Add the lowRISC Ibex CPU
      riscv: Initial commit of OpenTitan machine

Bin Meng (4):
      riscv: Suppress the error report for QEMU testing with riscv_find_firmware()
      riscv: Change the default behavior if no -bios option is specified
      hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions
      hw/riscv: virt: Remove the riscv_ prefix of the machine* functions

 docs/system/deprecated.rst                     |  98 +++++------
 default-configs/riscv32-softmmu.mak            |   1 +
 default-configs/riscv64-softmmu.mak            |  11 +-
 include/hw/riscv/boot.h                        |   1 +
 include/hw/riscv/opentitan.h                   |  68 ++++++++
 include/hw/riscv/sifive_e.h                    |   4 +
 include/hw/riscv/spike.h                       |   6 +-
 target/riscv/cpu.h                             |   9 +-
 hw/riscv/boot.c                                |  45 ++---
 hw/riscv/opentitan.c                           | 184 +++++++++++++++++++++
 hw/riscv/sifive_e.c                            |  41 +++--
 hw/riscv/sifive_u.c                            |  24 +--
 hw/riscv/spike.c                               | 217 -------------------------
 hw/riscv/virt.c                                |  20 +--
 target/riscv/cpu.c                             |  45 ++---
 target/riscv/cpu_helper.c                      |  82 ++++------
 target/riscv/csr.c                             | 138 +++-------------
 target/riscv/insn_trans/trans_privileged.inc.c |  18 +-
 target/riscv/monitor.c                         |   5 -
 target/riscv/op_helper.c                       |  17 +-
 tests/qtest/machine-none-test.c                |   4 +-
 MAINTAINERS                                    |   9 +
 hw/riscv/Kconfig                               |   5 +
 hw/riscv/Makefile.objs                         |   1 +
 24 files changed, 480 insertions(+), 573 deletions(-)
 create mode 100644 include/hw/riscv/opentitan.h
 create mode 100644 hw/riscv/opentitan.c


^ permalink raw reply	[flat|nested] 30+ messages in thread
end of thread, other threads:[~2024-03-27 10:14 UTC | newest]

Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-03-22  8:53 [PULL 00/15] riscv-to-apply queue Alistair Francis
2024-03-22  8:53 ` [PULL 01/15] target/riscv: do not enable all named features by default Alistair Francis
2024-03-22  8:53 ` [PULL 02/15] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Alistair Francis
2024-03-22  8:53 ` [PULL 03/15] trans_rvv.c.inc: set vstart = 0 in int scalar move insns Alistair Francis
2024-03-22  8:53 ` [PULL 04/15] target/riscv/vector_helper.c: fix 'vmvr_v' memcpy endianess Alistair Francis
2024-03-22  8:53 ` [PULL 05/15] target/riscv: always clear vstart in whole vec move insns Alistair Francis
2024-03-22  8:53 ` [PULL 06/15] target/riscv: always clear vstart for ldst_whole insns Alistair Francis
2024-03-22  8:53 ` [PULL 07/15] target/riscv/vector_helpers: do early exit when vstart >= vl Alistair Francis
2024-03-22  8:53 ` [PULL 08/15] target/riscv: remove 'over' brconds from vector trans Alistair Francis
2024-03-22  8:53 ` [PULL 09/15] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Alistair Francis
2024-03-22  8:53 ` [PULL 10/15] target/riscv: enable 'vstart_eq_zero' in the end of insns Alistair Francis
2024-03-22  8:53 ` [PULL 11/15] target/riscv/vector_helper.c: optimize loops in ldst helpers Alistair Francis
2024-03-22  8:53 ` [PULL 12/15] hw/intc: Update APLIC IDC after claiming iforce register Alistair Francis
2024-03-22  8:53 ` [PULL 13/15] target/riscv: rvv: Remove the dependency of Zvfbfmin to Zfbfmin Alistair Francis
2024-03-22  8:53 ` [PULL 14/15] target/riscv: Fix mode in riscv_tlb_fill Alistair Francis
2024-03-22  8:53 ` [PULL 15/15] target/riscv/kvm: fix timebase-frequency when using KVM acceleration Alistair Francis
2024-03-22 12:58 ` [PULL 00/15] riscv-to-apply queue Peter Maydell
2024-03-22 17:16 ` Michael Tokarev
2024-03-22 19:46   ` Daniel Henrique Barboza
2024-03-24 15:07     ` Michael Tokarev
2024-03-24 18:12       ` Daniel Henrique Barboza
2024-03-26  9:53         ` Michael Tokarev
2024-03-26  9:56           ` Alistair Francis
2024-03-26 12:09             ` Daniel Henrique Barboza
2024-03-27 10:13             ` Michael Tokarev
  -- strict thread matches above, loose matches on Subject: below --
2020-07-14  0:32 Alistair Francis
2020-07-14  0:37 ` Alistair Francis
2020-07-14 18:39 ` Peter Maydell
2020-06-03 16:13 Alistair Francis
2020-06-04 11:40 ` Peter Maydell

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