From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU
Date: Tue, 19 Mar 2019 18:21:23 +0000 [thread overview]
Message-ID: <073a79909f5ec317747ff8330744e6d7dabec717.1553019560.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1553019560.git.alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 10 ----------
target/riscv/cpu.h | 1 -
2 files changed, 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b6408e0a83..298413f6f6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -188,15 +188,6 @@ static void riscv_generate_cpu_init(Object *obj)
set_misa(env, rvxlen | target_misa);
}
-
-static void riscv_any_cpu_init(Object *obj)
-{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
- set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
- set_resetvec(env, DEFAULT_RSTVEC);
-}
-
#if defined(TARGET_RISCV32)
static void rv32gcsu_priv1_09_1_cpu_init(Object *obj)
@@ -575,7 +566,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_class_init,
},
- DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_GEN, riscv_generate_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bc877d8107..7d7caa294e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -47,7 +47,6 @@
#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
-#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
--
2.21.0
next prev parent reply other threads:[~2019-03-19 18:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 18:20 [Qemu-riscv] [PATCH for 4.1 v1 0/6] RISC-V: Allow specifying CPU ISA via command line Alistair Francis
2019-03-19 18:20 ` [Qemu-riscv] [PATCH for 4.1 v1 1/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 2/6] target/riscv: Create settable CPU properties Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 3/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
2019-03-19 18:21 ` Alistair Francis [this message]
2019-03-19 19:10 ` [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU Peter Maydell
2019-03-20 21:35 ` Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 6/6] riscv: Add a generic spike machine Alistair Francis
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