From: Alistair Francis <Alistair.Francis@wdc.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "palmer@sifive.com" <palmer@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
"alistair23@gmail.com" <alistair23@gmail.com>
Subject: [Qemu-riscv] [PATCH for 4.1 v1 0/6] RISC-V: Allow specifying CPU ISA via command line
Date: Tue, 19 Mar 2019 18:20:48 +0000 [thread overview]
Message-ID: <cover.1553019560.git.alistair.francis@wdc.com> (raw)
This patch series adds a generic RISC-V CPU that can be generated at run
time based on the ISA string specified to QEMU via the -cpu argument. This
is supported on the virt and spike boards allowing users to specify the
RISC-V extensions as well as the ISA version.
As part of the conversion we have deprecated the version specifi Spike
machines.
Alistair Francis (6):
target/riscv: Fall back to generating a RISC-V CPU
target/riscv: Create settable CPU properties
riscv: virt: Allow specifying a CPU via commandline
target/riscvL Remove the unused any CPU
target/riscv: Remove the generic no MMU CPUs
riscv: Add a generic spike machine
hw/riscv/spike.c | 106 ++++++++++++++++++++++++++++++++-
hw/riscv/virt.c | 3 +-
target/riscv/cpu.c | 143 ++++++++++++++++++++++++++++++++++++++++++---
target/riscv/cpu.h | 13 ++++-
4 files changed, 251 insertions(+), 14 deletions(-)
--
2.21.0
next reply other threads:[~2019-03-19 18:21 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-19 18:20 Alistair Francis [this message]
2019-03-19 18:20 ` [Qemu-riscv] [PATCH for 4.1 v1 1/6] target/riscv: Fall back to generating a RISC-V CPU Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 2/6] target/riscv: Create settable CPU properties Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 3/6] riscv: virt: Allow specifying a CPU via commandline Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 4/6] target/riscvL Remove the unused any CPU Alistair Francis
2019-03-19 19:10 ` [Qemu-riscv] [Qemu-devel] " Peter Maydell
2019-03-20 21:35 ` Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 5/6] target/riscv: Remove the generic no MMU CPUs Alistair Francis
2019-03-19 18:21 ` [Qemu-riscv] [PATCH for 4.1 v1 6/6] riscv: Add a generic spike machine Alistair Francis
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