RE: RFC: detect and manage power cut on MLC NAND

["Jeff Lauruhn (jlauruhn)" <jlauruhn@micron.com>]

Ricard;
I wish I could add some images, they would really help.  But, what you call paired pages we call lower/upper pagers.  Any yes, it's all about the distribution.  I need to look in to other vendors but under program operations for Micron we have a requirement "Within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (i.e. 0, 1, 2, 3, .). Programming pages out of order within a block is prohibited." This ensures that the lower page is programmed, before the upper page and that they are programmed together.  This sequence ensures the best reliability.  When we program the lower page it gets programmed into L0 or L1 state, when we program the upper page we either move L0 or L1 to its final location and we end up with L0, L1, L2, or L3.  Programming takes longer because there are 4 levels on the same gate so tighter distribution is required.  Power loss isn't as big an issue as it was in the past, most vendors are aware and have power loss considerations, but there are still vendors who take the risk.  In the case of a power loss during a upper page program it's always a good idea to check the condition of the lower page. 

Jeff Lauruhn
NAND Application Engineer
Embedded Business Unit


-----Original Message-----
From: Ricard Wanderlof [mailto:ricard.wanderlof@axis.com] 
Sent: Monday, March 16, 2015 2:02 AM
To: Jeff Lauruhn (jlauruhn)
Cc: mtd_mailinglist
Subject: Re: RFC: detect and manage power cut on MLC NAND


Hi Jeff,

I have a question regarding MLC:s, probably not so much something we can do anything about, but I'm curious just the same:

If I understand correctly, page pairing in MLC's means that of the two bits in a cell, one is allocated to one page and another one to a completely different page. This means (among other things) that rewriting one page may impact the other, paired, page.


My question is: why is it done this way? Is it to distribute bit flips more evenly?

An initial trivial allocation would otherwise be to put the paired bits in the same byte, for two reasons a) to avoid page-pairing issues, and b) because it simply would be easier to write both bits in a cell at the same time rather than at different times.

Granted, without page pairing, any sort of failure or disturb in one bit cell would would require twice the amount of ECC as both bits would likely be corrupted, on the other hand, we'd avoid having data in one part of the flash be corrupted by operations in another part of the flash.

/Ricard
-- 
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30