RE: RFC: detect and manage power cut on MLC NAND

[Iwo Mergler <Iwo.Mergler@netcommwireless.com>]

On Fri, 20 Mar 2015 19:26:11 +1100
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:

> I've read many times that MLC pages should be programmed in ascending
> order (0, 1, 2, 3, ..., N), and if you take a look at MLC datasheet
> you'll see that paired pages are not contiguous (here is an example
> [1], page 55-56 describe how pages are paired together).
> 
> My question is: is there a reason for interleaving paired pages with
> other pages (write disturbance mitigation ?) ?
> 
> If there is no specific reason but to annoy software developers :-),


I don't know for sure, but it seems that groups of pages are sharing
some resources. For instance, I've seen a few bit error patterns which
looked like this (256MB SLC, pages in one block):

-------------------------------X-X-X-X-X-X-X-X-X-X-X-X-X-X-X-X-X

The pages marked with 'X' have a single bit error at the same bit
offset in every page.

That is, even on a SLC device, there is some sort of page interleaving
pattern at work. In this case, maybe they share a broken sense amplifier
or similar.

I currently think that the rule about the ascending order is a
generalisation for unknown NAND architecture. In my example, it
may well be slightly better to write (0,2,4,6,8,10,12,14,1,3,5,
7,9,11,13,15,16,18,20,22,24,26,28,30,17,19,21,23,25,27,29,31).

Unless someone tells me otherwise, I guess that the paired pages
probably should be written in sequence anyway (0,4,1,5,etc).
Some of the backup methods appear suggestive of this.


Best regards,

Iwo