Re: [RFC] xen/arm: Handling cache maintenance instructions by set/way

From: Julien Grall <julien.grall@linaro.org>
To: Jan Beulich <JBeulich@suse.com>, Marc Zyngier <marc.zyngier@arm.com>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
	George Dunlap <george.dunlap@eu.citrix.com>,
	Andre Przywara <andre.przywara@arm.com>, Tim Deegan <tim@xen.org>,
	George Dunlap <george.dunlap@citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [RFC] xen/arm: Handling cache maintenance instructions by set/way
Date: Thu, 7 Dec 2017 16:04:47 +0000	[thread overview]
Message-ID: <0c4fbdf8-8f61-a3ad-d24e-401001d396b2@linaro.org> (raw)
In-Reply-To: <5A29702A0200007800195A5E@prv-mh.provo.novell.com>

Hi Jan,

On 07/12/17 15:45, Jan Beulich wrote:
>>>> On 07.12.17 at 15:53, <marc.zyngier@arm.com> wrote:
>> On 07/12/17 13:52, Julien Grall wrote:
>> There is exactly one case where set/way makes sense, and that's when
>> you're the only CPU left in the system, your MMU is off, and you're
>> about to go down.
> 
> With this and ...
> 
>> On top of bypassing the coherency, S/W CMOs do not prevent lines from
>> migrating from one CPU to another. So you could happily be flushing by
>> S/W, and still end up with dirty lines in your cache. Success!
> 
> ... this I wonder what value emulating those insns then has in the first
> place. Can't you as well simply skip and ignore them, with the same
> (bad) result?

The result will be much much worst. Here a concrete example with a Linux 
Arm 32-bit:

	1) Cache enabled
	2) Decompress
	3) Nuke cache (S/W)
	4) Cache off
	5) Access new kernel

If you skip #3, the decompress data may not have reached the memory, so 
you would access stall data.

This would effectively mean we don't support Linux Arm 32-bit.

Cheers,

-- 
Julien Grall

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