Re: [RFC] xen/arm: Handling cache maintenance instructions by set/way

["Jan Beulich" <JBeulich@suse.com>]

>>> On 11.12.17 at 12:11, <andrew.cooper3@citrix.com> wrote:
> On 11/12/17 10:06, Jan Beulich wrote:
>>>>> On 08.12.17 at 15:38, <julien.grall@linaro.org> wrote:
>>> On 08/12/17 08:03, Tim Deegan wrote:
>>>> It should be possible to do something like the misconfigured-entry bit
>>>> trick by _allocating_ the memory up-front and building the p2m entries
>>>> but only making them usable by the {IO}MMUs on first access.  That
>>>> would make these early p2m walks shorter (because they can skip whole
>>>> subtrees that aren't marked present yet) without making major changes
>>>> to domain build or introducing run-time failures.
>>> I am not aware of any way on Arm to misconfigure an entry. We do have 
>>> valid and access bits, although they will affect the IOMMU as well. So 
>>> it will not be possible to get page-table sharing with this "feature" 
>>> enabled.
>> How would you intend to solve the IOMMU part of the problem with
>> PoD? As was pointed out before - IOMMU and PoD are incompatible
>> on x86.
> 
> Not only that.
> 
> The use of an IOMMU is incompatible with any HAP scheme using EPT/NPT
> violations to trigger hypervisor work,

For many forms of "hypervisor work" I agree, but our misconfig
scheme demonstrates that there are exceptions where the IOMMU
continues to work fine.

Jan


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