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From: "Jan Beulich" <JBeulich@suse.com>
To: Julien Grall <julien.grall@linaro.org>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
	George Dunlap <george.dunlap@eu.citrix.com>,
	Andre Przywara <andre.przywara@arm.com>, Tim Deegan <tim@xen.org>,
	George Dunlap <george.dunlap@citrix.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [RFC] xen/arm: Handling cache maintenance instructions by set/way
Date: Mon, 11 Dec 2017 03:06:16 -0700	[thread overview]
Message-ID: <5A2E66A8020000780019650E@prv-mh.provo.novell.com> (raw)
In-Reply-To: <0266554c-fb24-22bf-e4bb-832abffc0ef1@linaro.org>

>>> On 08.12.17 at 15:38, <julien.grall@linaro.org> wrote:
> On 08/12/17 08:03, Tim Deegan wrote:
>> It should be possible to do something like the misconfigured-entry bit
>> trick by _allocating_ the memory up-front and building the p2m entries
>> but only making them usable by the {IO}MMUs on first access.  That
>> would make these early p2m walks shorter (because they can skip whole
>> subtrees that aren't marked present yet) without making major changes
>> to domain build or introducing run-time failures.
> 
> I am not aware of any way on Arm to misconfigure an entry. We do have 
> valid and access bits, although they will affect the IOMMU as well. So 
> it will not be possible to get page-table sharing with this "feature" 
> enabled.

How would you intend to solve the IOMMU part of the problem with
PoD? As was pointed out before - IOMMU and PoD are incompatible
on x86.

Jan


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  parent reply	other threads:[~2017-12-11 10:06 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-05 18:39 [RFC] xen/arm: Handling cache maintenance instructions by set/way Julien Grall
2017-12-05 22:35 ` Stefano Stabellini
2017-12-05 22:54   ` Julien Grall
2017-12-06  9:15 ` Jan Beulich
2017-12-06 12:10   ` Julien Grall
2017-12-06 12:28 ` George Dunlap
2017-12-06 12:58   ` Julien Grall
2017-12-06 13:01     ` Julien Grall
2017-12-06 15:15     ` Jan Beulich
2017-12-06 17:52       ` Julien Grall
2017-12-07  9:39         ` Jan Beulich
2017-12-07 15:22           ` Julien Grall
2017-12-07 15:49             ` Jan Beulich
2017-12-06 17:49     ` George Dunlap
2017-12-07 13:52       ` Julien Grall
2017-12-07 14:25         ` Jan Beulich
2017-12-07 14:53         ` Marc Zyngier
2017-12-07 15:45           ` Jan Beulich
2017-12-07 16:04             ` Marc Zyngier
2017-12-07 16:04             ` Julien Grall
2017-12-07 16:44               ` George Dunlap
2017-12-07 16:58                 ` Marc Zyngier
2017-12-07 18:06                   ` George Dunlap
2017-12-07 19:21                     ` Marc Zyngier
2017-12-08 10:56                       ` George Dunlap
2017-12-11 11:10                         ` Andre Przywara
2017-12-11 12:15                           ` George Dunlap
2017-12-11 21:11                           ` Julien Grall
2017-12-08  8:03     ` Tim Deegan
2017-12-08 14:38       ` Julien Grall
2017-12-10 15:22         ` Tim Deegan
2017-12-11 19:50           ` Julien Grall
2017-12-11 10:06         ` Jan Beulich [this message]
2017-12-11 11:11           ` Andrew Cooper
2017-12-11 11:58             ` Jan Beulich
2017-12-11 20:26           ` Julien Grall
2017-12-12  7:52             ` Jan Beulich
2017-12-06 15:10 ` Konrad Rzeszutek Wilk
2017-12-06 15:19   ` Julien Grall
2017-12-06 15:24     ` George Dunlap
2017-12-06 15:26       ` Julien Grall

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