From: <Tudor.Ambarus@microchip.com>
To: <Kavyasree.Kotagiri@microchip.com>, <broonie@kernel.org>,
<robh+dt@kernel.org>, <krzk+dt@kernel.org>
Cc: <Nicolas.Ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<Claudiu.Beznea@microchip.com>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <UNGLinuxDriver@microchip.com>,
<Manohar.Puri@microchip.com>
Subject: Re: [PATCH] spi: atmel,quadspi: Define lan966x QSPI
Date: Thu, 7 Apr 2022 12:54:49 +0000 [thread overview]
Message-ID: <0d1ad948-278d-4cad-9a20-99cf4fa984b9@microchip.com> (raw)
In-Reply-To: <20220407105420.10765-1-kavyasree.kotagiri@microchip.com>
On 4/7/22 13:54, Kavyasree Kotagiri wrote:
> LAN966x SoC supports 3 QSPI controllers. Each of them support
> data and clock frequency upto 100Mhz DDR and QUAD protocol.
How is this IP different than microchip,sama7g5-qspi? Does this speed
limitation come from the IP itself or from the board that you're using?
Neither of these instances support octal mode?
Cheers,
ta
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
> ---
> Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> index 1d493add4053..100d6e7f2748 100644
> --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> @@ -19,6 +19,7 @@ properties:
> - microchip,sam9x60-qspi
> - microchip,sama7g5-qspi
> - microchip,sama7g5-ospi
> + - microchip,lan966x-qspi
>
> reg:
> items:
WARNING: multiple messages have this Message-ID (diff)
From: <Tudor.Ambarus@microchip.com>
To: <Kavyasree.Kotagiri@microchip.com>, <broonie@kernel.org>,
<robh+dt@kernel.org>, <krzk+dt@kernel.org>
Cc: devicetree@vger.kernel.org, alexandre.belloni@bootlin.com,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
Manohar.Puri@microchip.com, UNGLinuxDriver@microchip.com,
Claudiu.Beznea@microchip.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] spi: atmel,quadspi: Define lan966x QSPI
Date: Thu, 7 Apr 2022 12:54:49 +0000 [thread overview]
Message-ID: <0d1ad948-278d-4cad-9a20-99cf4fa984b9@microchip.com> (raw)
In-Reply-To: <20220407105420.10765-1-kavyasree.kotagiri@microchip.com>
On 4/7/22 13:54, Kavyasree Kotagiri wrote:
> LAN966x SoC supports 3 QSPI controllers. Each of them support
> data and clock frequency upto 100Mhz DDR and QUAD protocol.
How is this IP different than microchip,sama7g5-qspi? Does this speed
limitation come from the IP itself or from the board that you're using?
Neither of these instances support octal mode?
Cheers,
ta
>
> Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
> ---
> Documentation/devicetree/bindings/spi/atmel,quadspi.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> index 1d493add4053..100d6e7f2748 100644
> --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml
> @@ -19,6 +19,7 @@ properties:
> - microchip,sam9x60-qspi
> - microchip,sama7g5-qspi
> - microchip,sama7g5-ospi
> + - microchip,lan966x-qspi
>
> reg:
> items:
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next prev parent reply other threads:[~2022-04-07 12:55 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-07 10:54 [PATCH] spi: atmel,quadspi: Define lan966x QSPI Kavyasree Kotagiri
2022-04-07 10:54 ` Kavyasree Kotagiri
2022-04-07 11:02 ` Mark Brown
2022-04-07 11:02 ` Mark Brown
2022-04-07 11:23 ` Michael Walle
2022-04-07 11:23 ` Michael Walle
2022-04-07 11:31 ` Mark Brown
2022-04-07 11:31 ` Mark Brown
2022-04-07 11:41 ` Michael Walle
2022-04-07 11:41 ` Michael Walle
2022-04-07 12:04 ` Krzysztof Kozlowski
2022-04-07 12:04 ` Krzysztof Kozlowski
2022-04-07 12:05 ` Krzysztof Kozlowski
2022-04-07 12:05 ` Krzysztof Kozlowski
2022-04-07 12:54 ` Tudor.Ambarus [this message]
2022-04-07 12:54 ` Tudor.Ambarus
2022-04-08 11:52 ` Kavyasree.Kotagiri
2022-04-08 11:52 ` Kavyasree.Kotagiri
2022-04-11 14:46 ` Michael Walle
2022-04-11 14:46 ` Michael Walle
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