* Problems with APIC on versions 4.9 and later (4.8 works)
@ 2021-01-18 20:15 Claudemir Todo Bom
2021-01-19 9:07 ` Jan Beulich
0 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-18 20:15 UTC (permalink / raw)
To: xen-users, xen-devel
[-- Attachment #1: Type: text/plain, Size: 1625 bytes --]
Hi,
Sorry for the simultaneous post on xen-users and xen-devel, but as I noted
that the problem appears only for versions of xen that are >= 4.9, I think
that developers may have a look at this.
I recently bought a generic mainboard and a Xeon E5-2926v2 CPU, it is a 12
core, 24 threads cpu.
My system was already running on another machine with xen 4.11 on a debian
10 system and after replacing the mainboard it didn't boot.
After many tries I noticed that downgrading to the previous version of Xen
(4.8, available on Debian 9) works well. I also tried a lot of variations
for the dom0 kernel, all of them with the same results.
All my tests were done with 4.11, but I checked with a live version of
Alpine Linux (3.7.3, with Xen 4.9.4) that the system doesn't boot on that
release also.
With more research I noticed that if I limit dom0 to use only one CPU
(dom0_max_vcpus=1) the system boots up, I didn't check if guest VM worked,
but I suppose that they would not be able to use the other 23 vcpus
available, anyway, a system with one vcpu for dom0 would be very slow I
think.
I've noticed also that if I keep dom0 to use more than one core but disable
acpi on the dom0 kernel, it boots up, unfortunately this is not
sufficient because I cannot use any device attached to the system (not even
the usb keyboard). This only helps to detect that the problem may be in the
ACPI/APIC code.
I tried many variations with parameters related with ACPI and APIC. None of
them was satisfactory, always ended on a halted system or a self rebooting
one.
Can anyone point me to a solution for this?
Best regards,
Claudemir
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-18 20:15 Problems with APIC on versions 4.9 and later (4.8 works) Claudemir Todo Bom
@ 2021-01-19 9:07 ` Jan Beulich
2021-01-19 19:47 ` Claudemir Todo Bom
[not found] ` <CANyqHYcifnCgd5C5vbYoi4CTtoMX5+jzGqHfs6JZ+e=d2Y_dmg@mail.gmail.com>
0 siblings, 2 replies; 26+ messages in thread
From: Jan Beulich @ 2021-01-19 9:07 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 18.01.2021 21:15, Claudemir Todo Bom wrote:
> Sorry for the simultaneous post on xen-users and xen-devel, but as I noted
> that the problem appears only for versions of xen that are >= 4.9, I think
> that developers may have a look at this.
Dropping xen-users.
> I recently bought a generic mainboard and a Xeon E5-2926v2 CPU, it is a 12
> core, 24 threads cpu.
>
> My system was already running on another machine with xen 4.11 on a debian
> 10 system and after replacing the mainboard it didn't boot.
>
> After many tries I noticed that downgrading to the previous version of Xen
> (4.8, available on Debian 9) works well. I also tried a lot of variations
> for the dom0 kernel, all of them with the same results.
>
> All my tests were done with 4.11, but I checked with a live version of
> Alpine Linux (3.7.3, with Xen 4.9.4) that the system doesn't boot on that
> release also.
>
> With more research I noticed that if I limit dom0 to use only one CPU
> (dom0_max_vcpus=1) the system boots up, I didn't check if guest VM worked,
> but I suppose that they would not be able to use the other 23 vcpus
> available, anyway, a system with one vcpu for dom0 would be very slow I
> think.
>
> I've noticed also that if I keep dom0 to use more than one core but disable
> acpi on the dom0 kernel, it boots up, unfortunately this is not
> sufficient because I cannot use any device attached to the system (not even
> the usb keyboard). This only helps to detect that the problem may be in the
> ACPI/APIC code.
>
> I tried many variations with parameters related with ACPI and APIC. None of
> them was satisfactory, always ended on a halted system or a self rebooting
> one.
>
> Can anyone point me to a solution for this?
For this we first of all need details about your problem: A full
boot log ideally, or if this isn't available anything at least
allowing us to see what exactly goes wrong (and with this I mean
the first thing going wrong, not later possible follow-on issues
from earlier problems), like screen shots. And this again ideally
with master / staging Xen, or if that's not feasible with as new
a version as possible.
I don't suppose you'd be up for bisecting the 4.8 ... 4.9 window
to determine when exactly your issue was introduced?
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-19 9:07 ` Jan Beulich
@ 2021-01-19 19:47 ` Claudemir Todo Bom
[not found] ` <CANyqHYcifnCgd5C5vbYoi4CTtoMX5+jzGqHfs6JZ+e=d2Y_dmg@mail.gmail.com>
1 sibling, 0 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-19 19:47 UTC (permalink / raw)
To: Jan Beulich, xen-devel
[-- Attachment #1.1: Type: text/plain, Size: 3691 bytes --]
Hi,
I do not have serial output on this setup, so I recorded a video with
boot_delay=50 in order to be able to get all the kernel messages:
https://youtu.be/y95h6vqoF7Y <https://youtu.be/y95h6vqoF7Y>
This is running 4.14 from debian bullseye (testing).
I'm also attaching the dmesg output when booting xen 4.8 with the same
kernel version and same parameters.
I visually compared all the messages, and the only thing I noticed was
that 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the
kernel with "clocksource=xen" and the problem is happening with that also.
The "start" of the problem is that when the kernel gets to the "Freeing
unused kernel image (initmem) memory: 2380K" it hangs and stays there
for a while. After a few minutes it shows that a process (swapper) is
blocked for sometime (image attached)
About finding what happened on the 4.8 -> 4.9 window, I may be able to
build some code from git to check, I will try to find the build
instructions to look at this.
Best regards,
Claudemir
Em ter., 19 de jan. de 2021 às 06:07, Jan Beulich <jbeulich@suse.com
<mailto:jbeulich@suse.com>> escreveu:
On 18.01.2021 21:15, Claudemir Todo Bom wrote:
> Sorry for the simultaneous post on xen-users and xen-devel, but
as I noted
> that the problem appears only for versions of xen that are >=
4.9, I think
> that developers may have a look at this.
Dropping xen-users.
> I recently bought a generic mainboard and a Xeon E5-2926v2 CPU,
it is a 12
> core, 24 threads cpu.
>
> My system was already running on another machine with xen 4.11 on
a debian
> 10 system and after replacing the mainboard it didn't boot.
>
> After many tries I noticed that downgrading to the previous
version of Xen
> (4.8, available on Debian 9) works well. I also tried a lot of
variations
> for the dom0 kernel, all of them with the same results.
>
> All my tests were done with 4.11, but I checked with a live
version of
> Alpine Linux (3.7.3, with Xen 4.9.4) that the system doesn't boot
on that
> release also.
>
> With more research I noticed that if I limit dom0 to use only one CPU
> (dom0_max_vcpus=1) the system boots up, I didn't check if guest
VM worked,
> but I suppose that they would not be able to use the other 23 vcpus
> available, anyway, a system with one vcpu for dom0 would be very
slow I
> think.
>
> I've noticed also that if I keep dom0 to use more than one core
but disable
> acpi on the dom0 kernel, it boots up, unfortunately this is not
> sufficient because I cannot use any device attached to the system
(not even
> the usb keyboard). This only helps to detect that the problem may
be in the
> ACPI/APIC code.
>
> I tried many variations with parameters related with ACPI and
APIC. None of
> them was satisfactory, always ended on a halted system or a self
rebooting
> one.
>
> Can anyone point me to a solution for this?
For this we first of all need details about your problem: A full
boot log ideally, or if this isn't available anything at least
allowing us to see what exactly goes wrong (and with this I mean
the first thing going wrong, not later possible follow-on issues
from earlier problems), like screen shots. And this again ideally
with master / staging Xen, or if that's not feasible with as new
a version as possible.
I don't suppose you'd be up for bisecting the 4.8 ... 4.9 window
to determine when exactly your issue was introduced?
Jan
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[ 0.000000] Linux version 5.10.0-1-amd64 (debian-kernel@lists.debian.org) (gcc-10 (Debian 10.2.1-3) 10.2.1 20201224, GNU ld (GNU Binutils for Debian) 2.35.1) #1 SMP Debian 5.10.4-1 (2020-12-31)
[ 0.000000] Command line: root=UUID=ee23fbab-8338-46f5-8e96-43827688f501 ro debug loglevel=7 boot_delay=50
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256
[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[ 0.000000] Released 0 page(s)
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable
[ 0.000000] Xen: [mem 0x000000000009e800-0x00000000000fffff] reserved
[ 0.000000] Xen: [mem 0x0000000000100000-0x0000000080061fff] usable
[ 0.000000] Xen: [mem 0x00000000ba952000-0x00000000ba98afff] reserved
[ 0.000000] Xen: [mem 0x00000000babc3000-0x00000000bb1bffff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bb1c0000-0x00000000bb842fff] reserved
[ 0.000000] Xen: [mem 0x00000000bb844000-0x00000000bb8c9fff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bbd0f000-0x00000000bbff3fff] reserved
[ 0.000000] Xen: [mem 0x00000000d0000000-0x00000000dfffffff] reserved
[ 0.000000] Xen: [mem 0x00000000fbffc000-0x00000000fbffcfff] reserved
[ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec01fff] reserved
[ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000feefffff] reserved
[ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] SMBIOS 2.7 present.
[ 0.000000] DMI: To be filled by O.E.M. To be filled by O.E.M./Intel X79, BIOS 4.6.5 07/17/2019
[ 0.000000] Hypervisor detected: Xen PV
[ 0.155748] tsc: Fast TSC calibration using PIT
[ 0.273468] tsc: Detected 2494.432 MHz processor
[ 0.391160] tsc: Detected 2494.358 MHz TSC
[ 0.526144] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 1.154983] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 1.508153] last_pfn = 0x80062 max_arch_pfn = 0x400000000
[ 1.625758] Disabled
[ 1.742984] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[ 1.860672] x86/PAT: Configuration [0-7]: WB WT UC- UC WC WP UC UC
[ 1.993714] Kernel/User page tables isolation: disabled on XEN PV.
[ 2.649981] RAMDISK: [mem 0x04000000-0x05dc8fff]
[ 2.767454] ACPI: Early table checksum verification disabled
[ 2.891105] ACPI: RSDP 0x00000000000F04A0 000024 (v02 ALASKA)
[ 3.253960] ACPI: XSDT 0x00000000BB0DD070 00005C (v01 ALASKA A M I 01072009 AMI 00010013)
[ 3.606987] ACPI: FACP 0x00000000BB0E5728 00010C (v05 ALASKA A M I 01072009 AMI 00010013)
[ 3.970133] ACPI: DSDT 0x00000000BB0DD160 0085C7 (v02 ALASKA A M I 00000020 INTL 20051117)
[ 4.333126] ACPI: FACS 0x00000000BB1B7F80 000040
[ 4.684987] ACPI: APIC 0x00000000BB0E5838 0001A8 (v03 ALASKA A M I 01072009 AMI 00010013)
[ 5.037422] ACPI: FPDT 0x00000000BB0E59E0 000044 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 5.389754] ACPI: MCFG 0x00000000BB0E5A28 00003C (v01 ALASKA OEMMCFG. 01072009 MSFT 00000097)
[ 5.742863] ACPI: HPET 0x00000000BB0E5A68 000038 (v01 ALASKA A M I 01072009 AMI. 00000005)
[ 6.095792] ACPI: SSDT 0x00000000BB0E5AA0 0CD380 (v02 INTEL CpuPm 00004000 INTL 20051117)
[ 6.448670] ACPI: RMAD 0x00000000BB1B2E20 0000EC (v01 A M I OEMDMAR 00000001 INTL 00000001)
[ 6.801480] ACPI: Local APIC address 0xfee00000
[ 6.919012] Setting APIC routing to Xen PV.
[ 7.036279] NUMA turned off
[ 7.153873] Faking a node at [mem 0x0000000000000000-0x0000000080061fff]
[ 7.271149] NODE_DATA(0) allocated [mem 0x3fbf7000-0x3fc20fff]
[ 7.399420] Zone ranges:
[ 7.516680] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 7.751630] DMA32 [mem 0x0000000001000000-0x0000000080061fff]
[ 7.986735] Normal empty
[ 8.222044] Device empty
[ 8.456663] Movable zone start for each node
[ 8.574407] Early memory node ranges
[ 8.691825] node 0: [mem 0x0000000000001000-0x000000000009dfff]
[ 8.809515] node 0: [mem 0x0000000000100000-0x0000000080061fff]
[ 8.927465] Zeroed struct page in unavailable ranges: 32769 pages
[ 9.044667] Initmem setup node 0 [mem 0x0000000000001000-0x0000000080061fff]
[ 9.162315] On node 0 totalpages: 524287
[ 9.279297] DMA zone: 64 pages used for memmap
[ 9.396457] DMA zone: 21 pages reserved
[ 9.513829] DMA zone: 3997 pages, LIFO batch:0
[ 9.631445] DMA32 zone: 8130 pages used for memmap
[ 9.748860] DMA32 zone: 520290 pages, LIFO batch:63
[ 9.867406] p2m virtual area at (____ptrval____), size is 40000000
[ 10.210479] Remapped 98 page(s)
[ 10.329593] ACPI: PM-Timer IO Port: 0x408
[ 10.447444] ACPI: Local APIC address 0xfee00000
[ 10.564733] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[ 10.682281] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
[ 10.799547] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
[ 10.917194] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
[ 11.035024] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
[ 11.152573] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
[ 11.270275] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
[ 11.387657] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
[ 11.505483] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
[ 11.622593] ACPI: LAPIC_NMI (acpi_id[0x12] high edge lint[0x1])
[ 11.739966] ACPI: LAPIC_NMI (acpi_id[0x14] high edge lint[0x1])
[ 11.857589] ACPI: LAPIC_NMI (acpi_id[0x16] high edge lint[0x1])
[ 11.975020] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[ 12.092440] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
[ 12.209727] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
[ 12.327243] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
[ 12.444921] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
[ 12.562617] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
[ 12.680483] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
[ 12.797861] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
[ 12.915513] ACPI: LAPIC_NMI (acpi_id[0x11] high edge lint[0x1])
[ 13.033159] ACPI: LAPIC_NMI (acpi_id[0x13] high edge lint[0x1])
[ 13.150678] ACPI: LAPIC_NMI (acpi_id[0x15] high edge lint[0x1])
[ 13.268602] ACPI: LAPIC_NMI (acpi_id[0x17] high edge lint[0x1])
[ 13.386031] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
[ 13.503665] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
[ 13.631497] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 13.759302] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 13.876235] ACPI: IRQ0 used by override.
[ 13.993793] ACPI: IRQ9 used by override.
[ 14.111247] Using ACPI (MADT) for SMP configuration information
[ 14.228672] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 14.346097] smpboot: Allowing 24 CPUs, 0 hotplug CPUs
[ 14.463755] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 14.581455] PM: hibernation: Registered nosave memory: [mem 0x0009e000-0x0009efff]
[ 14.698760] PM: hibernation: Registered nosave memory: [mem 0x0009f000-0x000fffff]
[ 14.816316] [mem 0x80062000-0xba951fff] available for PCI devices
[ 14.944123] Booting paravirtualized kernel on Xen
[ 15.071833] Xen version: 4.8.5 (preserve-AD)
[ 15.189473] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
[ 15.311546] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:24 nr_cpu_ids:24 nr_node_ids:1
[ 15.429964] percpu: Embedded 54 pages/cpu s183960 r8192 d29032 u262144
[ 15.547375] pcpu-alloc: s183960 r8192 d29032 u262144 alloc=1*2097152
[ 15.782948] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 12 13 14 15
[ 18.135212] pcpu-alloc: [0] 16 17 18 19 20 21 22 23
[ 19.428001] xen: PV spinlocks enabled
[ 19.545785] PV qspinlock hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 19.663507] Built 1 zonelists, mobility grouping on. Total pages: 516072
[ 19.791258] Policy zone: DMA32
[ 19.919067] Kernel command line: root=UUID=ee23fbab-8338-46f5-8e96-43827688f501 ro debug loglevel=7 boot_delay=50
[ 20.036434] printk: log_buf_len individual max cpu contribution: 4096 bytes
[ 20.153962] printk: log_buf_len total cpu_extra contributions: 94208 bytes
[ 20.271758] printk: log_buf_len min size: 131072 bytes
[ 20.389700] printk: log_buf_len: 262144 bytes
[ 20.507253] printk: early log buf free: 122784(93%)
[ 20.624684] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 20.742294] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 20.872428] mem auto-init: stack:off, heap alloc:on, heap free:off
[ 21.039024] software IO TLB: mapped [mem 0x0000000038b00000-0x000000003cb00000] (64MB)
[ 21.176419] Memory: 202080K/2097148K available (12295K kernel code, 2540K rwdata, 4060K rodata, 2380K init, 1692K bss, 1226580K reserved, 0K cma-reserved)
[ 21.294073] random: get_random_u64 called from __kmem_cache_create+0x2e/0x550 with crng_init=0
[ 21.412132] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=24, Nodes=1
[ 21.530599] ftrace: allocating 35988 entries in 141 pages
[ 21.661941] ftrace: allocated 141 pages with 4 groups
[ 21.780239] rcu: Hierarchical RCU implementation.
[ 21.897798] rcu: RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=24.
[ 22.015504] Rude variant of Tasks RCU enabled.
[ 22.132721] Tracing variant of Tasks RCU enabled.
[ 22.250416] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 22.368071] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=24
[ 22.495373] Using NULL legacy PIC
[ 22.613052] NR_IRQS: 524544, nr_irqs: 1024, preallocated irqs: 0
[ 22.731035] xen:events: Using FIFO-based ABI
[ 22.848508] xen: --> pirq=1 -> irq=1 (gsi=1)
[ 22.965668] xen: --> pirq=2 -> irq=2 (gsi=2)
[ 23.083268] xen: --> pirq=3 -> irq=3 (gsi=3)
[ 23.200545] xen: --> pirq=4 -> irq=4 (gsi=4)
[ 23.318489] xen: --> pirq=5 -> irq=5 (gsi=5)
[ 23.435962] xen: --> pirq=6 -> irq=6 (gsi=6)
[ 23.553119] xen: --> pirq=7 -> irq=7 (gsi=7)
[ 23.670867] xen: --> pirq=8 -> irq=8 (gsi=8)
[ 23.787679] xen: --> pirq=9 -> irq=9 (gsi=9)
[ 23.904613] xen: --> pirq=10 -> irq=10 (gsi=10)
[ 24.022630] xen: --> pirq=11 -> irq=11 (gsi=11)
[ 24.140050] xen: --> pirq=12 -> irq=12 (gsi=12)
[ 24.257486] xen: --> pirq=13 -> irq=13 (gsi=13)
[ 24.375039] xen: --> pirq=14 -> irq=14 (gsi=14)
[ 24.492544] xen: --> pirq=15 -> irq=15 (gsi=15)
[ 24.610310] random: crng done (trusting CPU's manufacturer)
[ 24.742994] Console: colour VGA+ 80x25
[ 24.868893] printk: console [tty0] enabled
[ 24.987088] printk: console [hvc0] enabled
[ 25.104720] ACPI: Core revision 20200925
[ 25.312475] clocksource: xen: mask: 0xffffffffffffffff max_cycles: 0x1cd42e4dffb, max_idle_ns: 881590591483 ns
[ 25.440380] Xen: using vcpuop timer interface
[ 25.558129] installing Xen timer for CPU 0
[ 25.614278] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23f467e01fe, max_idle_ns: 440795236622 ns
[ 25.670368] Calibrating delay loop (skipped), value calculated using timer frequency.. 4988.71 BogoMIPS (lpj=9977432)
[ 25.782369] pid_max: default: 32768 minimum: 301
[ 25.838368] LSM: Security Framework initializing
[ 25.894368] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 25.950368] AppArmor: AppArmor initialized
[ 26.006368] TOMOYO Linux initialized
[ 26.062369] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 26.118369] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 26.174369] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8
[ 26.230368] Last level dTLB entries: 4KB 512, 2MB 0, 4MB 0, 1GB 4
[ 26.286369] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[ 26.342369] Spectre V2 : Mitigation: Full generic retpoline
[ 26.398368] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[ 26.454369] Speculative Store Bypass: Vulnerable
[ 26.510368] MDS: Vulnerable: Clear CPU buffers attempted, no microcode
[ 26.566369] Freeing SMP alternatives memory: 32K
[ 26.626369] cpu 0 spinlock event irq 49
[ 26.682368] VPMU disabled by hypervisor.
[ 26.738369] Performance Events: IvyBridge events, PMU not available due to virtualization, using software events only.
[ 26.906368] rcu: Hierarchical SRCU implementation.
[ 26.962368] NMI watchdog: Perf NMI watchdog permanently disabled
[ 27.018368] smp: Bringing up secondary CPUs ...
[ 27.074369] installing Xen timer for CPU 1
[ 27.130113] cpu 1 spinlock event irq 59
[ 27.186370] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.
[ 27.242369] installing Xen timer for CPU 2
[ 27.302191] cpu 2 spinlock event irq 65
[ 27.358369] installing Xen timer for CPU 3
[ 27.414114] cpu 3 spinlock event irq 71
[ 27.470369] installing Xen timer for CPU 4
[ 27.526120] cpu 4 spinlock event irq 77
[ 27.582369] installing Xen timer for CPU 5
[ 27.638120] cpu 5 spinlock event irq 83
[ 27.691661] clocksource: timekeeping watchdog on CPU1: Marking clocksource 'tsc-early' as unstable because the skew is too large:
[ 27.694370] installing Xen timer for CPU 6
[ 27.749879] cpu 6 spinlock event irq 89
[ 27.747706] clocksource: 'xen' wd_now: 7ebeebdcc wd_last: 7cd108633 mask: ffffffffffffffff
[ 27.803707] clocksource: 'tsc-early' cs_now: 4cd939a88e cs_last: 4bc21f9bd6 mask: ffffffffffffffff
[ 27.806369] installing Xen timer for CPU 7
[ 27.862201] cpu 7 spinlock event irq 95
[ 27.859880] tsc: Marking TSC unstable due to clocksource watchdog
[ 27.918369] installing Xen timer for CPU 8
[ 27.974116] cpu 8 spinlock event irq 101
[ 28.030369] installing Xen timer for CPU 9
[ 28.086096] cpu 9 spinlock event irq 107
[ 28.142369] installing Xen timer for CPU 10
[ 28.198097] cpu 10 spinlock event irq 113
[ 28.254369] installing Xen timer for CPU 11
[ 28.310100] cpu 11 spinlock event irq 119
[ 28.366369] installing Xen timer for CPU 12
[ 28.422092] cpu 12 spinlock event irq 125
[ 28.478370] installing Xen timer for CPU 13
[ 28.534107] cpu 13 spinlock event irq 131
[ 28.590370] installing Xen timer for CPU 14
[ 28.646095] cpu 14 spinlock event irq 137
[ 28.702369] installing Xen timer for CPU 15
[ 28.758100] cpu 15 spinlock event irq 143
[ 28.814370] installing Xen timer for CPU 16
[ 28.870114] cpu 16 spinlock event irq 149
[ 28.926370] installing Xen timer for CPU 17
[ 28.982099] cpu 17 spinlock event irq 155
[ 29.038370] installing Xen timer for CPU 18
[ 29.094109] cpu 18 spinlock event irq 161
[ 29.150370] installing Xen timer for CPU 19
[ 29.206090] cpu 19 spinlock event irq 167
[ 29.262369] installing Xen timer for CPU 20
[ 29.318091] cpu 20 spinlock event irq 173
[ 29.374370] installing Xen timer for CPU 21
[ 29.430034] cpu 21 spinlock event irq 179
[ 29.486370] installing Xen timer for CPU 22
[ 29.542088] cpu 22 spinlock event irq 185
[ 29.598370] installing Xen timer for CPU 23
[ 29.654068] cpu 23 spinlock event irq 191
[ 29.710370] smp: Brought up 1 node, 24 CPUs
[ 29.766369] smpboot: Max logical packages: 1
[ 29.818754] node 0 deferred pages initialised in 0ms
[ 29.878369] devtmpfs: initialized
[ 29.934371] x86/mm: Memory block size: 128MB
[ 29.990370] PM: Registering ACPI NVS region [mem 0xbabc3000-0xbb1bffff] (6279168 bytes)
[ 30.046370] PM: Registering ACPI NVS region [mem 0xbb844000-0xbb8c9fff] (548864 bytes)
[ 30.102371] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 30.158370] futex hash table entries: 8192 (order: 7, 524288 bytes, linear)
[ 30.214369] pinctrl core: initialized pinctrl subsystem
[ 30.270369] NET: Registered protocol family 16
[ 30.326371] xen:grant_table: Grant tables using version 1 layout
[ 30.382369] Grant table initialized
[ 30.438371] audit: initializing netlink subsys (disabled)
[ 30.491028] thermal_sys: Registered thermal governor 'fair_share'
[ 30.494054] audit: type=2000 audit(1611077453.743:1): state=initialized audit_enabled=0 res=1
[ 30.547194] thermal_sys: Registered thermal governor 'bang_bang'
[ 30.603361] thermal_sys: Registered thermal governor 'step_wise'
[ 30.659528] thermal_sys: Registered thermal governor 'user_space'
[ 30.715696] ACPI: bus type PCI registered
[ 30.771844] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 30.828013] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xd0000000-0xdfffffff] (base 0xd0000000)
[ 30.884181] PCI: MMCONFIG at [mem 0xd0000000-0xdfffffff] reserved in E820
[ 31.016402] PCI: Using configuration type 1 for base access
[ 31.270351] ACPI: Added _OSI(Module Device)
[ 31.322476] ACPI: Added _OSI(Processor Device)
[ 31.378646] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 31.434812] ACPI: Added _OSI(Processor Aggregator Device)
[ 31.494370] ACPI: Added _OSI(Linux-Dell-Video)
[ 31.550369] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[ 31.606369] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[ 31.850369] ACPI: 2 ACPI AML tables successfully acquired and loaded
[ 32.030371] xen: registering gsi 9 triggering 0 polarity 0
[ 32.094369] ACPI: Interpreter enabled
[ 32.150369] ACPI: (supports S0 S5)
[ 32.206370] ACPI: Using IOAPIC for interrupt routing
[ 32.262371] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 32.266364] ACPI: Enabled 6 GPEs in block 00 to 3F
[ 32.338372] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
[ 32.394370] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 32.450370] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug PME AER LTR]
[ 32.503025] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PCIeCapability]
[ 32.559185] PCI host bridge to bus 0000:00
[ 32.615350] pci_bus 0000:00: root bus resource [io 0x0000-0x03af window]
[ 32.671501] pci_bus 0000:00: root bus resource [io 0x03e0-0x0cf7 window]
[ 32.727625] pci_bus 0000:00: root bus resource [io 0x03b0-0x03df window]
[ 32.783794] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 32.839973] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 32.896160] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 32.952350] pci_bus 0000:00: root bus resource [mem 0xcc000000-0xffffffff window]
[ 33.008533] pci_bus 0000:00: root bus resource [mem 0x840000000-0x3fffffffffff window]
[ 33.064706] pci_bus 0000:00: root bus resource [bus 00-fe]
[ 33.120885] pci 0000:00:00.0: [8086:0e00] type 00 class 0x060000
[ 33.177050] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 33.233215] pci 0000:00:01.0: [8086:0e02] type 01 class 0x060400
[ 33.289382] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 33.345548] pci 0000:00:01.1: [8086:0e03] type 01 class 0x060400
[ 33.401712] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[ 33.457874] pci 0000:00:02.0: [8086:0e04] type 01 class 0x060400
[ 33.514037] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[ 33.570200] pci 0000:00:02.1: [8086:0e05] type 01 class 0x060400
[ 33.626360] pci 0000:00:02.1: PME# supported from D0 D3hot D3cold
[ 33.678463] pci 0000:00:02.2: [8086:0e06] type 01 class 0x060400
[ 33.734631] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[ 33.790798] pci 0000:00:02.3: [8086:0e07] type 01 class 0x060400
[ 33.846963] pci 0000:00:02.3: PME# supported from D0 D3hot D3cold
[ 33.903128] pci 0000:00:03.0: [8086:0e08] type 01 class 0x060400
[ 33.959291] pci 0000:00:03.0: enabling Extended Tags
[ 34.015456] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 34.071620] pci 0000:00:03.1: [8086:0e09] type 01 class 0x060400
[ 34.127782] pci 0000:00:03.1: PME# supported from D0 D3hot D3cold
[ 34.183946] pci 0000:00:03.2: [8086:0e0a] type 01 class 0x060400
[ 34.240107] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[ 34.296270] pci 0000:00:03.3: [8086:0e0b] type 01 class 0x060400
[ 34.352432] pci 0000:00:03.3: PME# supported from D0 D3hot D3cold
[ 34.408591] pci 0000:00:05.0: [8086:0e28] type 00 class 0x088000
[ 34.466371] pci 0000:00:05.2: [8086:0e2a] type 00 class 0x088000
[ 34.522370] pci 0000:00:05.4: [8086:0e2c] type 00 class 0x080020
[ 34.578370] pci 0000:00:05.4: reg 0x10: [mem 0xfb304000-0xfb304fff]
[ 34.634370] pci 0000:00:06.0: [8086:0e10] type 00 class 0x088000
[ 34.690370] pci 0000:00:06.1: [8086:0e11] type 00 class 0x088000
[ 34.746371] pci 0000:00:06.2: [8086:0e12] type 00 class 0x088000
[ 34.802370] pci 0000:00:06.3: [8086:0e13] type 00 class 0x088000
[ 34.858372] pci 0000:00:06.4: [8086:0e14] type 00 class 0x088000
[ 34.914369] pci 0000:00:06.5: [8086:0e15] type 00 class 0x088000
[ 34.970369] pci 0000:00:06.6: [8086:0e16] type 00 class 0x088000
[ 35.026369] pci 0000:00:06.7: [8086:0e17] type 00 class 0x088000
[ 35.082369] pci 0000:00:07.0: [8086:0e18] type 00 class 0x088000
[ 35.138370] pci 0000:00:07.1: [8086:0e19] type 00 class 0x088000
[ 35.194369] pci 0000:00:07.2: [8086:0e1a] type 00 class 0x088000
[ 35.250369] pci 0000:00:07.3: [8086:0e1b] type 00 class 0x088000
[ 35.306369] pci 0000:00:07.4: [8086:0e1c] type 00 class 0x088000
[ 35.362370] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
[ 35.418369] pci 0000:00:1a.0: reg 0x10: [mem 0xfb302000-0xfb3023ff]
[ 35.474031] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 35.530191] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
[ 35.586350] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 35.638462] pci 0000:00:1c.0: Enabling MPC IRBNCE
[ 35.694628] pci 0000:00:1c.0: Intel PCH root port ACS workaround enabled
[ 35.750792] pci 0000:00:1c.1: [8086:1e12] type 01 class 0x060400
[ 35.806955] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[ 35.863119] pci 0000:00:1c.1: Enabling MPC IRBNCE
[ 35.919282] pci 0000:00:1c.1: Intel PCH root port ACS workaround enabled
[ 35.975445] pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400
[ 36.031607] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[ 36.087769] pci 0000:00:1c.4: Enabling MPC IRBNCE
[ 36.143933] pci 0000:00:1c.4: Intel PCH root port ACS workaround enabled
[ 36.200098] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
[ 36.256265] pci 0000:00:1d.0: reg 0x10: [mem 0xfb301000-0xfb3013ff]
[ 36.312430] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 36.368595] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
[ 36.424758] pci 0000:00:1f.0: [8086:1e48] type 00 class 0x060100
[ 36.482370] pci 0000:00:1f.2: [8086:1e02] type 00 class 0x010601
[ 36.538370] pci 0000:00:1f.2: reg 0x10: [io 0xf070-0xf077]
[ 36.594369] pci 0000:00:1f.2: reg 0x14: [io 0xf060-0xf063]
[ 36.650369] pci 0000:00:1f.2: reg 0x18: [io 0xf050-0xf057]
[ 36.706369] pci 0000:00:1f.2: reg 0x1c: [io 0xf040-0xf043]
[ 36.762369] pci 0000:00:1f.2: reg 0x20: [io 0xf020-0xf03f]
[ 36.822369] pci 0000:00:1f.2: reg 0x24: [mem 0xfb300000-0xfb3007ff]
[ 36.878369] pci 0000:00:1f.2: PME# supported from D3hot
[ 36.934372] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
[ 36.990369] pci 0000:00:1f.3: reg 0x10: [mem 0x3ffffff00000-0x3ffffff000ff 64bit]
[ 37.046369] pci 0000:00:1f.3: reg 0x20: [io 0xf000-0xf01f]
[ 37.102369] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 37.158369] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 37.214369] pci 0000:03:00.0: [10de:01d3] type 00 class 0x030000
[ 37.270369] pci 0000:03:00.0: reg 0x10: [mem 0xfa000000-0xfaffffff]
[ 37.326370] pci 0000:03:00.0: reg 0x14: [mem 0xe0000000-0xefffffff 64bit pref]
[ 37.382369] pci 0000:03:00.0: reg 0x1c: [mem 0xf9000000-0xf9ffffff 64bit]
[ 37.438369] pci 0000:03:00.0: reg 0x30: [mem 0xfb000000-0xfb01ffff pref]
[ 37.492077] pci 0000:03:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
[ 37.548242] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 37.604411] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 37.660579] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 37.716744] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 37.772909] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 37.829070] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 37.885232] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 37.941395] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 37.997557] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 38.053719] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 38.109881] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 38.166043] pci 0000:0c:00.0: [1106:3483] type 00 class 0x0c0330
[ 38.222207] pci 0000:0c:00.0: reg 0x10: [mem 0xfb200000-0xfb200fff 64bit]
[ 38.278363] pci 0000:0c:00.0: PME# supported from D0 D3cold
[ 38.330419] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 38.386587] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 38.442755] pci 0000:0d:00.0: [10ec:8168] type 00 class 0x020000
[ 38.498922] pci 0000:0d:00.0: reg 0x10: [io 0xe000-0xe0ff]
[ 38.555088] pci 0000:0d:00.0: reg 0x18: [mem 0xfb104000-0xfb104fff 64bit]
[ 38.611255] pci 0000:0d:00.0: reg 0x20: [mem 0xfb100000-0xfb103fff 64bit]
[ 38.667422] pci 0000:0d:00.0: supports D1 D2
[ 38.723590] pci 0000:0d:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 38.779756] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 38.835923] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 38.892090] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 38.948217] pci_bus 0000:0e: extended config space not accessible
[ 39.004385] pci 0000:00:1e.0: PCI bridge to [bus 0e] (subtractive decode)
[ 39.060549] pci 0000:00:1e.0: bridge window [io 0x0000-0x03af window] (subtractive decode)
[ 39.116713] pci 0000:00:1e.0: bridge window [io 0x03e0-0x0cf7 window] (subtractive decode)
[ 39.174370] pci 0000:00:1e.0: bridge window [io 0x03b0-0x03df window] (subtractive decode)
[ 39.230369] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff window] (subtractive decode)
[ 39.286369] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode)
[ 39.342369] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000dffff window] (subtractive decode)
[ 39.396290] pci 0000:00:1e.0: bridge window [mem 0xcc000000-0xffffffff window] (subtractive decode)
[ 39.454371] pci 0000:00:1e.0: bridge window [mem 0x840000000-0x3fffffffffff window] (subtractive decode)
[ 39.510370] xen: registering gsi 13 triggering 1 polarity 0
[ 39.566370] ACPI: PCI Root Bridge [UNC0] (domain 0000 [bus ff])
[ 39.622369] acpi PNP0A03:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 39.678369] acpi PNP0A03:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR]
[ 39.734368] PCI host bridge to bus 0000:ff
[ 39.790369] pci_bus 0000:ff: root bus resource [bus ff]
[ 39.846371] pci 0000:ff:08.0: [8086:0e80] type 00 class 0x088000
[ 39.902369] pci 0000:ff:08.2: [8086:0e32] type 00 class 0x110100
[ 39.958369] pci 0000:ff:08.3: [8086:0e83] type 00 class 0x088000
[ 40.014369] pci 0000:ff:08.4: [8086:0e84] type 00 class 0x088000
[ 40.070369] pci 0000:ff:08.5: [8086:0e85] type 00 class 0x088000
[ 40.126369] pci 0000:ff:08.6: [8086:0e86] type 00 class 0x088000
[ 40.182369] pci 0000:ff:08.7: [8086:0e87] type 00 class 0x088000
[ 40.238369] pci 0000:ff:09.0: [8086:0e90] type 00 class 0x088000
[ 40.294369] pci 0000:ff:09.2: [8086:0e33] type 00 class 0x110100
[ 40.350369] pci 0000:ff:09.3: [8086:0e93] type 00 class 0x088000
[ 40.406374] pci 0000:ff:09.4: [8086:0e94] type 00 class 0x088000
[ 40.462369] pci 0000:ff:09.5: [8086:0e95] type 00 class 0x088000
[ 40.518369] pci 0000:ff:09.6: [8086:0e96] type 00 class 0x088000
[ 40.574369] pci 0000:ff:0a.0: [8086:0ec0] type 00 class 0x088000
[ 40.630369] pci 0000:ff:0a.1: [8086:0ec1] type 00 class 0x088000
[ 40.686371] pci 0000:ff:0a.2: [8086:0ec2] type 00 class 0x088000
[ 40.742369] pci 0000:ff:0a.3: [8086:0ec3] type 00 class 0x088000
[ 40.798369] pci 0000:ff:0b.0: [8086:0e1e] type 00 class 0x088000
[ 40.854369] pci 0000:ff:0b.3: [8086:0e1f] type 00 class 0x088000
[ 40.910369] pci 0000:ff:0c.0: [8086:0ee0] type 00 class 0x088000
[ 40.966369] pci 0000:ff:0c.1: [8086:0ee2] type 00 class 0x088000
[ 41.022369] pci 0000:ff:0c.2: [8086:0ee4] type 00 class 0x088000
[ 41.078369] pci 0000:ff:0c.3: [8086:0ee6] type 00 class 0x088000
[ 41.134369] pci 0000:ff:0c.4: [8086:0ee8] type 00 class 0x088000
[ 41.190369] pci 0000:ff:0c.5: [8086:0eea] type 00 class 0x088000
[ 41.246369] pci 0000:ff:0d.0: [8086:0ee1] type 00 class 0x088000
[ 41.302373] pci 0000:ff:0d.1: [8086:0ee3] type 00 class 0x088000
[ 41.358369] pci 0000:ff:0d.2: [8086:0ee5] type 00 class 0x088000
[ 41.414369] pci 0000:ff:0d.3: [8086:0ee7] type 00 class 0x088000
[ 41.466945] pci 0000:ff:0d.4: [8086:0ee9] type 00 class 0x088000
[ 41.523113] pci 0000:ff:0d.5: [8086:0eeb] type 00 class 0x088000
[ 41.579282] pci 0000:ff:0e.0: [8086:0ea0] type 00 class 0x088000
[ 41.635448] pci 0000:ff:0e.1: [8086:0e30] type 00 class 0x110100
[ 41.691614] pci 0000:ff:0f.0: [8086:0ea8] type 00 class 0x088000
[ 41.747779] pci 0000:ff:0f.1: [8086:0e71] type 00 class 0x088000
[ 41.803953] pci 0000:ff:0f.2: [8086:0eaa] type 00 class 0x088000
[ 41.860120] pci 0000:ff:0f.3: [8086:0eab] type 00 class 0x088000
[ 41.916287] pci 0000:ff:0f.4: [8086:0eac] type 00 class 0x088000
[ 41.972456] pci 0000:ff:0f.5: [8086:0ead] type 00 class 0x088000
[ 42.028624] pci 0000:ff:10.0: [8086:0eb0] type 00 class 0x088000
[ 42.084795] pci 0000:ff:10.1: [8086:0eb1] type 00 class 0x088000
[ 42.140960] pci 0000:ff:10.2: [8086:0eb2] type 00 class 0x088000
[ 42.197126] pci 0000:ff:10.3: [8086:0eb3] type 00 class 0x088000
[ 42.253293] pci 0000:ff:10.4: [8086:0eb4] type 00 class 0x088000
[ 42.309457] pci 0000:ff:10.5: [8086:0eb5] type 00 class 0x088000
[ 42.365622] pci 0000:ff:10.6: [8086:0eb6] type 00 class 0x088000
[ 42.421785] pci 0000:ff:10.7: [8086:0eb7] type 00 class 0x088000
[ 42.478370] pci 0000:ff:13.0: [8086:0e1d] type 00 class 0x088000
[ 42.534370] pci 0000:ff:13.1: [8086:0e34] type 00 class 0x110100
[ 42.590370] pci 0000:ff:13.4: [8086:0e81] type 00 class 0x088000
[ 42.646369] pci 0000:ff:13.5: [8086:0e36] type 00 class 0x110100
[ 42.702369] pci 0000:ff:16.0: [8086:0ec8] type 00 class 0x088000
[ 42.758369] pci 0000:ff:16.1: [8086:0ec9] type 00 class 0x088000
[ 42.814369] pci 0000:ff:16.2: [8086:0eca] type 00 class 0x088000
[ 42.870371] pci 0000:ff:1c.0: [8086:0e60] type 00 class 0x088000
[ 42.926369] pci 0000:ff:1c.1: [8086:0e38] type 00 class 0x110100
[ 42.982370] pci 0000:ff:1d.0: [8086:0e68] type 00 class 0x088000
[ 43.036429] pci 0000:ff:1d.1: [8086:0e79] type 00 class 0x088000
[ 43.092589] pci 0000:ff:1d.2: [8086:0e6a] type 00 class 0x088000
[ 43.150370] pci 0000:ff:1d.3: [8086:0e6b] type 00 class 0x088000
[ 43.206369] pci 0000:ff:1d.4: [8086:0e6c] type 00 class 0x088000
[ 43.262370] pci 0000:ff:1d.5: [8086:0e6d] type 00 class 0x088000
[ 43.318373] pci 0000:ff:1e.0: [8086:0ef0] type 00 class 0x088000
[ 43.374369] pci 0000:ff:1e.1: [8086:0ef1] type 00 class 0x088000
[ 43.430370] pci 0000:ff:1e.2: [8086:0ef2] type 00 class 0x088000
[ 43.483864] pci 0000:ff:1e.3: [8086:0ef3] type 00 class 0x088000
[ 43.540025] pci 0000:ff:1e.4: [8086:0ef4] type 00 class 0x088000
[ 43.596186] pci 0000:ff:1e.5: [8086:0ef5] type 00 class 0x088000
[ 43.652348] pci 0000:ff:1e.6: [8086:0ef6] type 00 class 0x088000
[ 43.708510] pci 0000:ff:1e.7: [8086:0ef7] type 00 class 0x088000
[ 43.764674] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[ 44.494369] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[ 45.222369] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 45.890418] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 *4 5 6 10 11 12 14 15)
[ 46.564429] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 47.406369] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 48.246369] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 49.086369] ACPI: PCI Interrupt Link [LNKH] (IRQs *3 4 5 6 7 10 11 12 14 15)
[ 49.812449] xen:balloon: Initialising balloon driver
[ 49.868648] iommu: Default domain type: Translated
[ 49.874364] pci 0000:03:00.0: vgaarb: setting as boot VGA device
[ 49.874364] pci 0000:03:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[ 50.034488] pci 0000:03:00.0: vgaarb: bridge control possible
[ 50.090697] vgaarb: loaded
[ 50.146904] EDAC MC: Ver: 3.0.0
[ 50.203110] NetLabel: Initializing
[ 50.259317] NetLabel: domain hash size = 128
[ 50.315522] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO
[ 50.371731] NetLabel: unlabeled traffic allowed by default
[ 50.427943] PCI: Using ACPI for IRQ routing
[ 50.504211] PCI: pci_cache_line_size set to 64 bytes
[ 50.560419] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 50.616625] e820: reserve RAM buffer [mem 0x80062000-0x83ffffff]
[ 50.690404] clocksource: Switched to clocksource xen
[ 50.758373] VFS: Disk quotas dquot_6.6.0
[ 50.814373] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 50.870375] hugetlbfs: disabling because there are no supported hugepage sizes
[ 50.926372] AppArmor: AppArmor Filesystem Enabled
[ 50.982372] pnp: PnP ACPI init
[ 51.038375] system 00:00: [mem 0xfc000000-0xfcffffff] has been reserved
[ 51.094373] system 00:00: [mem 0xfd000000-0xfdffffff] has been reserved
[ 51.150372] system 00:00: [mem 0xfe000000-0xfeafffff] has been reserved
[ 51.206372] system 00:00: [mem 0xfeb00000-0xfebfffff] has been reserved
[ 51.262373] system 00:00: [mem 0xfed00400-0xfed3ffff] could not be reserved
[ 51.318375] system 00:00: [mem 0xfed45000-0xfedfffff] has been reserved
[ 51.374372] system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved
[ 51.374449] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 51.430373] system 00:01: [mem 0xfbffc000-0xfbffdfff] could not be reserved
[ 51.430447] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 51.486375] system 00:02: [io 0x0a00-0x0a1f] has been reserved
[ 51.542374] system 00:02: [io 0x0a20-0x0a2f] has been reserved
[ 51.598372] system 00:02: [io 0x0a30-0x0a3f] has been reserved
[ 51.598449] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 51.654374] xen: registering gsi 1 triggering 1 polarity 0
[ 51.654428] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
[ 51.710372] xen: registering gsi 12 triggering 1 polarity 0
[ 51.710417] pnp 00:04: Plug and Play ACPI device, IDs PNP0f03 PNP0f13 (active)
[ 51.766372] xen: registering gsi 8 triggering 1 polarity 0
[ 51.766412] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 51.822374] system 00:06: [io 0x04d0-0x04d1] has been reserved
[ 51.828320] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 51.882373] system 00:07: [io 0x0400-0x0453] has been reserved
[ 51.938372] system 00:07: [io 0x0458-0x047f] has been reserved
[ 51.994372] system 00:07: [io 0x1180-0x119f] has been reserved
[ 52.050372] system 00:07: [io 0x0500-0x057f] has been reserved
[ 52.106373] system 00:07: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 52.162373] system 00:07: [mem 0xfec00000-0xfecfffff] could not be reserved
[ 52.218372] system 00:07: [mem 0xff000000-0xffffffff] has been reserved
[ 52.218447] system 00:07: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 52.274373] system 00:08: [io 0x0454-0x0457] has been reserved
[ 52.274448] system 00:08: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 52.330373] pnp: PnP ACPI: found 9 devices
[ 52.398373] PM-Timer failed consistency check (0xffffff) - aborting.
[ 52.454372] NET: Registered protocol family 2
[ 52.510407] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[ 52.566382] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 52.622380] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 52.678381] TCP: Hash tables configured (established 16384 bind 16384)
[ 52.734374] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 52.790375] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 52.846373] NET: Registered protocol family 1
[ 52.902372] NET: Registered protocol family 44
[ 52.958378] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 53.014372] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 53.070372] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 53.126373] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 53.182373] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 53.238372] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 53.294373] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 53.350375] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 53.406375] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 53.462375] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 53.518375] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 53.574375] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 53.630375] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 53.686375] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 53.742376] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 53.798376] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 53.854375] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 53.910375] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 53.966375] pci 0000:00:1e.0: PCI bridge to [bus 0e]
[ 54.022375] pci_bus 0000:00: resource 4 [io 0x0000-0x03af window]
[ 54.078375] pci_bus 0000:00: resource 5 [io 0x03e0-0x0cf7 window]
[ 54.134375] pci_bus 0000:00: resource 6 [io 0x03b0-0x03df window]
[ 54.190375] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 54.246375] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 54.302375] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 54.358375] pci_bus 0000:00: resource 10 [mem 0xcc000000-0xffffffff window]
[ 54.414376] pci_bus 0000:00: resource 11 [mem 0x840000000-0x3fffffffffff window]
[ 54.470375] pci_bus 0000:03: resource 1 [mem 0xf9000000-0xfb0fffff]
[ 54.526375] pci_bus 0000:03: resource 2 [mem 0xe0000000-0xefffffff 64bit pref]
[ 54.582375] pci_bus 0000:0c: resource 1 [mem 0xfb200000-0xfb2fffff]
[ 54.638376] pci_bus 0000:0d: resource 0 [io 0xe000-0xefff]
[ 54.694375] pci_bus 0000:0d: resource 1 [mem 0xfb100000-0xfb1fffff]
[ 54.750376] pci_bus 0000:0e: resource 4 [io 0x0000-0x03af window]
[ 54.806375] pci_bus 0000:0e: resource 5 [io 0x03e0-0x0cf7 window]
[ 54.862375] pci_bus 0000:0e: resource 6 [io 0x03b0-0x03df window]
[ 54.918375] pci_bus 0000:0e: resource 7 [io 0x0d00-0xffff window]
[ 54.974375] pci_bus 0000:0e: resource 8 [mem 0x000a0000-0x000bffff window]
[ 55.030375] pci_bus 0000:0e: resource 9 [mem 0x000c0000-0x000dffff window]
[ 55.086375] pci_bus 0000:0e: resource 10 [mem 0xcc000000-0xffffffff window]
[ 55.142375] pci_bus 0000:0e: resource 11 [mem 0x840000000-0x3fffffffffff window]
[ 55.198377] pci 0000:00:05.0: disabled boot interrupts on device [8086:0e28]
[ 55.254382] pci 0000:00:05.0: quirk_disable_intel_boot_interrupt+0x0/0xf0 took 54506 usecs
[ 55.310405] xen: registering gsi 16 triggering 0 polarity 1
[ 55.366375] xen: --> pirq=16 -> irq=16 (gsi=16)
[ 55.422378] pci 0000:00:1a.0: quirk_usb_early_handoff+0x0/0x700 took 109429 usecs
[ 55.478375] xen: registering gsi 23 triggering 0 polarity 1
[ 55.534375] xen: --> pirq=23 -> irq=23 (gsi=23)
[ 55.590418] pci 0000:00:1d.0: quirk_usb_early_handoff+0x0/0x700 took 109422 usecs
[ 55.646374] pci 0000:03:00.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[ 55.702380] pci 0000:03:00.0: pci_fixup_video+0x0/0xe0 took 54604 usecs
[ 55.758373] xen: registering gsi 16 triggering 0 polarity 1
[ 55.814372] Already setup the GSI :16
[ 55.870424] xen: registering gsi 17 triggering 0 polarity 1
[ 55.926373] xen: --> pirq=17 -> irq=17 (gsi=17)
[ 55.982376] pci 0000:0c:00.0: quirk_usb_early_handoff+0x0/0x700 took 218770 usecs
[ 56.038373] PCI: CLS 64 bytes, default 64
[ 56.094373] Trying to unpack rootfs image as initramfs...
[ 56.666379] Freeing initrd memory: 30500K
[ 56.722376] Initialise system trusted keyrings
[ 56.778374] Key type blacklist registered
[ 56.834373] workingset: timestamp_bits=36 max_order=18 bucket_order=0
[ 56.890415] zbud: loaded
[ 56.946372] integrity: Platform Keyring initialized
[ 57.002372] Key type asymmetric registered
[ 57.058374] Asymmetric key parser 'x509' registered
[ 57.114373] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 57.170407] io scheduler mq-deadline registered
[ 57.226374] xen: registering gsi 26 triggering 0 polarity 1
[ 57.282373] xen: --> pirq=26 -> irq=26 (gsi=26)
[ 57.338375] xen: registering gsi 26 triggering 0 polarity 1
[ 57.394378] Already setup the GSI :26
[ 57.450404] xen: registering gsi 32 triggering 0 polarity 1
[ 57.506372] xen: --> pirq=32 -> irq=32 (gsi=32)
[ 57.562375] xen: registering gsi 32 triggering 0 polarity 1
[ 57.618374] Already setup the GSI :32
[ 57.674373] xen: registering gsi 32 triggering 0 polarity 1
[ 57.730414] Already setup the GSI :32
[ 57.786375] xen: registering gsi 32 triggering 0 polarity 1
[ 57.842375] Already setup the GSI :32
[ 57.898373] xen: registering gsi 40 triggering 0 polarity 1
[ 57.954372] xen: --> pirq=40 -> irq=40 (gsi=40)
[ 58.010375] xen: registering gsi 40 triggering 0 polarity 1
[ 58.066375] Already setup the GSI :40
[ 58.122373] xen: registering gsi 40 triggering 0 polarity 1
[ 58.178372] Already setup the GSI :40
[ 58.234375] xen: registering gsi 40 triggering 0 polarity 1
[ 58.290374] Already setup the GSI :40
[ 58.346373] xen: registering gsi 17 triggering 0 polarity 1
[ 58.402374] Already setup the GSI :17
[ 58.458375] xen: registering gsi 17 triggering 0 polarity 1
[ 58.514375] Already setup the GSI :17
[ 58.570404] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 58.626373] intel_idle: MWAIT substates: 0x1120
[ 58.682373] Monitor-Mwait will be used to enter C-1 state
[ 58.738373] Monitor-Mwait will be used to enter C-2 state
[ 58.794375] ACPI: \_SB_.SCK0.C000: Found 2 idle states
[ 58.850415] intel_idle: v0.5.1 model 0x3E
[ 58.906372] intel_idle: intel_idle yielding to none
[ 58.962373] ACPI: \_SB_.SCK0.C000: Found 2 idle states
[ 59.018373] ACPI: \_SB_.SCK0.C002: Found 2 idle states
[ 59.074373] ACPI: \_SB_.SCK0.C004: Found 2 idle states
[ 59.130405] ACPI: \_SB_.SCK0.C006: Found 2 idle states
[ 59.186379] ACPI: \_SB_.SCK0.C008: Found 2 idle states
[ 59.242373] ACPI: \_SB_.SCK0.C00A: Found 2 idle states
[ 59.298373] ACPI: \_SB_.SCK0.C00C: Found 2 idle states
[ 59.354373] ACPI: \_SB_.SCK0.C00E: Found 2 idle states
[ 59.410368] ACPI: \_SB_.SCK0.C010: Found 2 idle states
[ 59.466375] ACPI: \_SB_.SCK0.C012: Found 2 idle states
[ 59.522376] ACPI: \_SB_.SCK0.C014: Found 2 idle states
[ 59.578373] ACPI: \_SB_.SCK0.C016: Found 2 idle states
[ 59.634373] ACPI: \_SB_.SCK0.C001: Found 2 idle states
[ 59.690404] ACPI: \_SB_.SCK0.C003: Found 2 idle states
[ 59.746373] ACPI: \_SB_.SCK0.C005: Found 2 idle states
[ 59.802373] ACPI: \_SB_.SCK0.C007: Found 2 idle states
[ 59.858375] ACPI: \_SB_.SCK0.C009: Found 2 idle states
[ 59.914376] ACPI: \_SB_.SCK0.C00B: Found 2 idle states
[ 59.970407] ACPI: \_SB_.SCK0.C00D: Found 2 idle states
[ 60.026375] ACPI: \_SB_.SCK0.C00F: Found 2 idle states
[ 60.082376] ACPI: \_SB_.SCK0.C011: Found 2 idle states
[ 60.138376] ACPI: \_SB_.SCK0.C013: Found 2 idle states
[ 60.194373] ACPI: \_SB_.SCK0.C015: Found 2 idle states
[ 60.250404] ACPI: \_SB_.SCK0.C017: Found 2 idle states
[ 60.306373] xen_mcelog: /dev/mcelog registered by Xen
[ 60.362374] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 60.418373] hpet_acpi_add: no address or irqs in _CRS
[ 60.474372] Linux agpgart interface v0.103
[ 60.530374] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
[ 60.586372] AMD-Vi: AMD IOMMUv2 functionality not available on this system
[ 60.642374] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
[ 60.698374] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 60.754375] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 60.810405] mousedev: PS/2 mouse device common for all mice
[ 60.866376] rtc_cmos 00:05: RTC can wake from S4
[ 60.922375] rtc_cmos 00:05: registered as rtc0
[ 60.978374] rtc_cmos 00:05: setting system clock to 2021-01-19T17:31:24 UTC (1611077484)
[ 61.034373] rtc_cmos 00:05: alarms up to one month, y3k, 114 bytes nvram
[ 61.090373] intel_pstate: CPU model not supported
[ 61.146372] ledtrig-cpu: registered to indicate activity on CPUs
[ 61.202373] NET: Registered protocol family 10
[ 61.278380] Segment Routing with IPv6
[ 61.334380] mip6: Mobile IPv6
[ 61.390368] NET: Registered protocol family 17
[ 61.446376] mpls_gso: MPLS GSO support
[ 61.502376] IPI shorthand broadcast: enabled
[ 61.558376] sched_clock: Marking stable (60436562241, 1065806413)->(61953278698, -450910044)
[ 61.614372] registered taskstats version 1
[ 61.670418] Loading compiled-in X.509 certificates
[ 61.762380] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1'
[ 61.818379] Loaded X.509 cert 'Debian Secure Boot Signer 2020: 00b55eb3b9'
[ 61.874381] zswap: loaded using pool lzo/zbud
[ 61.930380] Key type ._fscrypt registered
[ 61.986379] Key type .fscrypt registered
[ 62.042379] Key type fscrypt-provisioning registered
[ 62.098381] AppArmor: AppArmor sha1 policy hashing enabled
[ 62.154374] Freeing unused kernel image (initmem) memory: 2380K
[ 62.210374] Write protecting the kernel read-only data: 18432k
[ 62.278372] Freeing unused kernel image (text/rodata gap) memory: 2040K
[ 62.334375] Freeing unused kernel image (rodata/data gap) memory: 36K
[ 62.826376] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[ 62.826509] Run /init as init process
[ 62.826575] with arguments:
[ 62.826576] /init
[ 62.826577] with environment:
[ 62.826577] HOME=/
[ 62.826578] TERM=linux
[ 62.887464] systemd-udevd[233]: Starting version 241
[ 62.896538] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:18: Invalid GROUP operation
[ 62.896635] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:19: Invalid GROUP operation
[ 62.896738] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:20: Invalid GROUP operation
[ 62.896831] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:21: Invalid GROUP operation
[ 62.896925] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:22: Invalid GROUP operation
[ 62.897018] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:23: Invalid GROUP operation
[ 62.897110] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:24: Invalid GROUP operation
[ 62.897204] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:25: Invalid GROUP operation
[ 62.897298] systemd-udevd[234]: /usr/lib/udev/rules.d/50-udev-default.rules:27: Invalid GROUP operation
[ 63.122574] xen: registering gsi 18 triggering 0 polarity 1
[ 63.122612] xen: --> pirq=18 -> irq=18 (gsi=18)
[ 63.122754] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[ 63.123370] i2c i2c-0: 4/4 memory slots populated (from DMI)
[ 63.131767] SCSI subsystem initialized
[ 63.134069] xen: registering gsi 16 triggering 0 polarity 1
[ 63.134078] Already setup the GSI :16
[ 63.134139] ACPI: bus type USB registered
[ 63.134162] usbcore: registered new interface driver usbfs
[ 63.134287] usbcore: registered new interface driver hub
[ 63.134695] usbcore: registered new device driver usb
[ 63.140091] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 63.141465] ehci-pci: EHCI PCI platform driver
[ 63.141635] xen: registering gsi 16 triggering 0 polarity 1
[ 63.141642] Already setup the GSI :16
[ 63.141787] ehci-pci 0000:00:1a.0: EHCI Host Controller
[ 63.141857] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
[ 63.141960] ehci-pci 0000:00:1a.0: debug port 2
[ 63.145972] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
[ 63.146102] ehci-pci 0000:00:1a.0: irq 16, io mem 0xfb302000
[ 63.146964] libata version 3.00 loaded.
[ 63.152104] libphy: r8169: probed
[ 63.152395] r8169 0000:0d:00.0 eth0: RTL8168h/8111h, 00:e0:4c:0a:52:97, XID 541, IRQ 209
[ 63.152484] r8169 0000:0d:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
[ 63.158410] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[ 63.158606] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 63.158694] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 63.158779] usb usb1: Product: EHCI Host Controller
[ 63.158847] usb usb1: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 63.158917] usb usb1: SerialNumber: 0000:00:1a.0
[ 63.159194] hub 1-0:1.0: USB hub found
[ 63.159273] hub 1-0:1.0: 2 ports detected
[ 63.159686] xen: registering gsi 23 triggering 0 polarity 1
[ 63.159693] Already setup the GSI :23
[ 63.159810] ehci-pci 0000:00:1d.0: EHCI Host Controller
[ 63.159879] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
[ 63.159983] ehci-pci 0000:00:1d.0: debug port 2
[ 63.161095] xen: registering gsi 17 triggering 0 polarity 1
[ 63.161102] Already setup the GSI :17
[ 63.161951] ahci 0000:00:1f.2: version 3.0
[ 63.162041] xen: registering gsi 19 triggering 0 polarity 1
[ 63.162068] xen: --> pirq=19 -> irq=19 (gsi=19)
[ 63.162246] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
[ 63.162331] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst
[ 63.163978] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
[ 63.164110] ehci-pci 0000:00:1d.0: irq 23, io mem 0xfb301000
[ 63.164655] r8169 0000:0d:00.0 enp13s0: renamed from eth0
[ 63.175129] scsi host0: ahci
[ 63.175571] scsi host1: ahci
[ 63.175954] scsi host2: ahci
[ 63.176310] scsi host3: ahci
[ 63.176700] scsi host4: ahci
[ 63.177105] scsi host5: ahci
[ 63.177229] ata1: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300100 irq 210
[ 63.177312] ata2: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300180 irq 210
[ 63.177393] ata3: DUMMY
[ 63.177451] ata4: DUMMY
[ 63.177508] ata5: DUMMY
[ 63.177566] ata6: DUMMY
[ 63.182406] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 63.182576] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 63.182659] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 63.182739] usb usb2: Product: EHCI Host Controller
[ 63.182801] usb usb2: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 63.182867] usb usb2: SerialNumber: 0000:00:1d.0
[ 63.183129] hub 2-0:1.0: USB hub found
[ 63.183207] hub 2-0:1.0: 2 ports detected
[ 63.183475] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 63.183559] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 3
[ 63.183747] xhci_hcd 0000:0c:00.0: hcc params 0x002841eb hci version 0x100 quirks 0x0000000000000890
[ 63.184143] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 63.184226] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 63.184306] usb usb3: Product: xHCI Host Controller
[ 63.184368] usb usb3: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 63.184433] usb usb3: SerialNumber: 0000:0c:00.0
[ 63.184691] hub 3-0:1.0: USB hub found
[ 63.184772] hub 3-0:1.0: 1 port detected
[ 63.185006] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 63.185074] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 4
[ 63.185157] xhci_hcd 0000:0c:00.0: Host supports USB 3.0 SuperSpeed
[ 63.185355] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
[ 63.185437] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 63.185517] usb usb4: Product: xHCI Host Controller
[ 63.185579] usb usb4: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 63.185644] usb usb4: SerialNumber: 0000:0c:00.0
[ 63.185901] hub 4-0:1.0: USB hub found
[ 63.185985] hub 4-0:1.0: 4 ports detected
[ 63.494275] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 63.494364] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 63.494406] usb 1-1: new high-speed USB device number 2 using ehci-pci
[ 63.494827] ata1.00: ATA-11: KINGSTON SUV400S37120G, 0C3FD6SD, max UDMA/133
[ 63.494898] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 63.495498] ata1.00: configured for UDMA/133
[ 63.495757] scsi 0:0:0:0: Direct-Access ATA KINGSTON SUV400S D6SD PQ: 0 ANSI: 5
[ 63.512293] ata2.00: ATA-8: KINGSTON SV300S37A120G, 525ABBF0, max UDMA/133
[ 63.512364] ata2.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 63.518455] usb 3-1: new high-speed USB device number 2 using xhci_hcd
[ 63.518460] usb 2-1: new high-speed USB device number 2 using ehci-pci
[ 63.530908] ata2.00: configured for UDMA/133
[ 63.531159] scsi 1:0:0:0: Direct-Access ATA KINGSTON SV300S3 BBF0 PQ: 0 ANSI: 5
[ 63.541460] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 63.541468] sd 1:0:0:0: [sdb] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 63.541546] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 63.541650] sd 1:0:0:0: [sdb] Write Protect is off
[ 63.541711] sd 0:0:0:0: [sda] Write Protect is off
[ 63.541754] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 63.541816] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 63.541853] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 63.541855] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 63.559310] sda: sda1 sda2
[ 63.560122] sd 0:0:0:0: [sda] Attached SCSI disk
[ 63.563787] sd 1:0:0:0: [sdb] Attached SCSI disk
[ 63.648552] process '/usr/bin/fstype' started with executable stack
[ 63.650726] usb 1-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 63.650811] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 63.651130] hub 1-1:1.0: USB hub found
[ 63.651343] hub 1-1:1.0: 6 ports detected
[ 63.663522] PM: Image not found (code -22)
[ 63.672252] usb 3-1: New USB device found, idVendor=2109, idProduct=3431, bcdDevice= 4.20
[ 63.672337] usb 3-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[ 63.672404] usb 3-1: Product: USB2.0 Hub
[ 63.673532] hub 3-1:1.0: USB hub found
[ 63.673868] hub 3-1:1.0: 4 ports detected
[ 63.674722] usb 2-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 63.674806] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 63.675130] hub 2-1:1.0: USB hub found
[ 63.675352] hub 2-1:1.0: 8 ports detected
[ 63.841806] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 63.875899] printk: systemd-udevd: 39 output lines suppressed due to ratelimiting
[ 63.938410] usb 1-1.2: new low-speed USB device number 3 using ehci-pci
[ 63.950006] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist.
[ 63.966407] usb 2-1.4: new high-speed USB device number 3 using ehci-pci
[ 64.042466] systemd[1]: Inserted module 'autofs4'
[ 64.052838] usb 1-1.2: New USB device found, idVendor=099a, idProduct=610c, bcdDevice= 0.01
[ 64.052924] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 64.053003] usb 1-1.2: Product: USB Multimedia Keyboard
[ 64.053066] usb 1-1.2: Manufacturer:
[ 64.085839] usb 2-1.4: New USB device found, idVendor=148f, idProduct=7601, bcdDevice= 0.00
[ 64.085922] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 64.086002] usb 2-1.4: Product: 802.11 n WLAN
[ 64.091935] usb 2-1.4: Manufacturer: MediaTek
[ 64.091936] usb 2-1.4: SerialNumber: 1.0
[ 64.092246] systemd[1]: systemd 241 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD -IDN2 +IDN -PCRE2 default-hierarchy=hybrid)
[ 64.092518] systemd[1]: No virtualization found in DMI
[ 64.092525] systemd[1]: No virtualization found in CPUID
[ 64.092541] systemd[1]: Virtualization XEN found (/proc/xen exists)
[ 64.092588] systemd[1]: Virtualization XEN, found /sys/hypervisor/properties/features with value 000028f0, XENFEAT_dom0 (indicating the 'hardware domain') is set.
[ 64.092612] systemd[1]: Found VM virtualization none
[ 64.092623] systemd[1]: Detected architecture x86-64.
[ 64.092865] systemd[1]: Mounting cgroup to /sys/fs/cgroup/hugetlb of type cgroup with options hugetlb.
[ 64.093001] systemd[1]: Mounting cgroup to /sys/fs/cgroup/cpu,cpuacct of type cgroup with options cpu,cpuacct.
[ 64.093380] systemd[1]: Mounting cgroup to /sys/fs/cgroup/blkio of type cgroup with options blkio.
[ 64.152541] systemd-bless-boot-generator[328]: Skipping generator, not an EFI boot.
[ 64.155034] systemd-fstab-generator[331]: Parsing /etc/fstab
[ 64.155163] systemd-fstab-generator[331]: Found entry what=/dev/disk/by-uuid/ee23fbab-8338-46f5-8e96-43827688f501 where=/ type=ext4 makefs=no nofail=no noauto=no
[ 64.155802] systemd-getty-generator[332]: Automatically adding serial getty for /dev/hvc0.
[ 64.155918] systemd-getty-generator[332]: Automatically adding serial getty for /dev/hvc0.
[ 64.157698] systemd-fstab-generator[331]: Found entry what=/dev/disk/by-uuid/5ce8ab62-3de2-419e-8470-289073e2e55f where=none type=swap makefs=no nofail=no noauto=no
[ 64.161584] systemd-gpt-auto-generator[334]: Failed to chase block device '/', ignoring: No such file or directory
[ 64.161980] systemd-hibernate-resume-generator[336]: Not running in an initrd, quitting.
[ 64.162831] systemd-gpt-auto-generator[334]: sda2: Root device /dev/sda.
[ 64.163001] systemd-rc-local-generator[337]: /etc/rc.local does not exist, skipping.
[ 64.163314] systemd-rc-local-generator[337]: /usr/sbin/halt.local does not exist, skipping.
[ 64.165535] systemd-sysv-generator[340]: Native unit for lvm2.service already exists, skipping.
[ 64.166420] systemd-sysv-generator[340]: Native unit for rsyslog.service already exists, skipping.
[ 64.168812] systemd-sysv-generator[340]: Native unit for procps.service already exists, skipping.
[ 64.169120] systemd-sysv-generator[340]: Cannot find unit exim4.service.
[ 64.170049] systemd-sysv-generator[340]: Native unit for selinux-autorelabel.service already exists, skipping.
[ 64.170132] systemd-sysv-generator[340]: Cannot find unit xen.service.
[ 64.170763] systemd-sysv-generator[340]: Native unit for virtlogd.service already exists, skipping.
[ 64.170827] systemd-sysv-generator[340]: Native unit for dnsmasq.service already exists, skipping.
[ 64.171413] systemd-sysv-generator[340]: Native unit for libvirtd.service already exists, skipping.
[ 64.171998] systemd-sysv-generator[340]: Native unit for dbus.service already exists, skipping.
[ 64.178619] systemd-gpt-auto-generator[334]: No suitable partition table found, ignoring.
[ 64.186008] printk: systemd-sysv-ge: 63 output lines suppressed due to ratelimiting
[ 64.306624] systemd[355]: Operating on architecture: x86
[ 64.306651] systemd[355]: Operating on architecture: x32
[ 64.307519] systemd[355]: Operating on architecture: x86-64
[ 64.307935] systemd[355]: Operating on architecture: x86
[ 64.308208] systemd[355]: Operating on architecture: x32
[ 64.308447] systemd[355]: Operating on architecture: x86-64
[ 64.308666] systemd[355]: Operating on architecture: x86
[ 64.308951] systemd[355]: Operating on architecture: x32
[ 64.309165] systemd[355]: Operating on architecture: x86-64
[ 64.309409] systemd[355]: Restricting namespace to: .
[ 64.309441] systemd[355]: Operating on architecture: x86
[ 64.309473] systemd[355]: Blocking cgroup.
[ 64.309503] systemd[355]: Blocking ipc.
[ 64.309535] systemd[355]: Blocking net.
[ 64.309565] systemd[355]: Blocking mnt.
[ 64.309594] systemd[355]: Blocking pid.
[ 64.309624] systemd[355]: Blocking user.
[ 64.309653] systemd[355]: Blocking uts.
[ 64.309968] systemd[355]: Operating on architecture: x32
[ 64.310002] systemd[355]: Blocking cgroup.
[ 64.310031] systemd[355]: Blocking ipc.
[ 64.310060] systemd[355]: Blocking net.
[ 64.310089] systemd[355]: Blocking mnt.
[ 64.310118] systemd[355]: Blocking pid.
[ 64.310148] systemd[355]: Blocking user.
[ 64.310177] systemd[355]: Blocking uts.
[ 64.310521] systemd[355]: Operating on architecture: x86-64
[ 64.310551] systemd[355]: Blocking cgroup.
[ 64.310577] systemd[355]: Blocking ipc.
[ 64.310603] systemd[355]: Blocking net.
[ 64.310629] systemd[355]: Blocking mnt.
[ 64.310654] systemd[355]: Blocking pid.
[ 64.310680] systemd[355]: Blocking user.
[ 64.310706] systemd[355]: Blocking uts.
[ 64.311719] systemd[355]: Operating on architecture: x86
[ 64.316625] systemd[355]: Operating on architecture: x32
[ 64.318721] systemd[355]: Operating on architecture: x86-64
[ 64.334793] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[ 64.335791] systemd-journald[355]: Found cgroup2 on /sys/fs/cgroup/unified, unified hierarchy for systemd controller
[ 64.339621] systemd-journald[355]: Journal effective settings seal=no compress=yes compress_threshold_bytes=512B
[ 64.339726] systemd-journald[355]: Fixed min_use=1.0M max_use=8.8M max_size=1.1M min_size=512.0K keep_free=13.2M n_max_files=100
[ 64.340220] systemd-journald[355]: Reserving 2047 entries in hash table.
[ 64.340357] systemd-journald[355]: Vacuuming...
[ 64.340413] systemd-journald[355]: Vacuuming done, freed 0B of archived journals from /run/log/journal/213fd1d09b77489086f4d95451358573.
[ 64.340438] systemd-journald[355]: Flushing /dev/kmsg...
[ 64.370979] device-mapper: uevent: version 1.0.3
[ 64.371096] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[ 64.406844] systemd[373]: Operating on architecture: x86
[ 64.406870] systemd[373]: Operating on architecture: x32
[ 64.407687] systemd[373]: Operating on architecture: x86-64
[ 64.408036] systemd[373]: Operating on architecture: x86
[ 64.408261] systemd[373]: Operating on architecture: x32
[ 64.408466] systemd[373]: Operating on architecture: x86-64
[ 64.408672] systemd[373]: Operating on architecture: x86
[ 64.408878] systemd[373]: Operating on architecture: x32
[ 64.409082] systemd[373]: Operating on architecture: x86-64
[ 64.468282] systemd-journald[355]: Data hash table of /run/log/journal/213fd1d09b77489086f4d95451358573/system.journal has a fill level at 75.0 (1536 of 2047 items, 1159168 file size, 754 bytes per hash table item), suggesting rotation.
[ 64.468292] systemd-journald[355]: /run/log/journal/213fd1d09b77489086f4d95451358573/system.journal: Journal header limits reached or header out-of-date, rotating.
[ 64.468301] systemd-journald[355]: Rotating...
[ 64.508261] audit: type=1400 audit(1611077488.080:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe" pid=397 comm="apparmor_parser"
[ 64.508266] audit: type=1400 audit(1611077488.080:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe//kmod" pid=397 comm="apparmor_parser"
[ 64.508773] audit: type=1400 audit(1611077488.080:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=395 comm="apparmor_parser"
[ 64.508777] audit: type=1400 audit(1611077488.080:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=395 comm="apparmor_parser"
[ 64.508779] audit: type=1400 audit(1611077488.080:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=395 comm="apparmor_parser"
[ 64.509416] audit: type=1400 audit(1611077488.080:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd" pid=396 comm="apparmor_parser"
[ 64.509420] audit: type=1400 audit(1611077488.080:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd//qemu_bridge_helper" pid=396 comm="apparmor_parser"
[ 64.513887] audit: type=1400 audit(1611077488.084:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="virt-aa-helper" pid=394 comm="apparmor_parser"
[ 64.546238] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input3
[ 64.562445] ACPI: Power Button [PWRB]
[ 64.562527] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
[ 64.562583] ACPI: Power Button [PWRF]
[ 66.160945] hid: raw HID events driver (C) Jiri Kosina
[ 66.170758] usbcore: registered new interface driver usbhid
[ 66.170760] usbhid: USB HID core driver
[ 66.173459] iTCO_vendor_support: vendor-support=0
[ 66.215646] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 66.215729] sd 1:0:0:0: Attached scsi generic sg1 type 0
[ 66.217338] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[ 66.217380] iTCO_wdt: Found a Panther Point TCO device (Version=2, TCOBASE=0x0460)
[ 66.217573] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[ 66.297832] input: PC Speaker as /devices/platform/pcspkr/input/input5
[ 66.298691] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 66.298941] cfg80211: Loaded X.509 cert 'benh@debian.org: 577e021cb980e0e820821ba7b54b4961b8b4fadf'
[ 66.299175] cfg80211: Loaded X.509 cert 'romain.perier@gmail.com: 3abbc6ec146e09d1b6016ab9d6cf71dd233f0328'
[ 66.299409] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 66.299712] platform regulatory.0: firmware: failed to load regulatory.db (-2)
[ 66.299714] firmware_class: See https://wiki.debian.org/Firmware for information about missing firmware
[ 66.299715] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 66.299717] cfg80211: failed to load regulatory.db
[ 66.502418] Adding 3905532k swap on /dev/sda1. Priority:-2 extents:1 across:3905532k SSFS
[ 66.518415] usb 2-1.4: reset high-speed USB device number 3 using ehci-pci
[ 66.536427] RAPL PMU: API unit is 2^-32 Joules, 2 fixed counters, 163840 ms ovfl timer
[ 66.536430] RAPL PMU: hw unit of domain pp0-core 2^-16 Joules
[ 66.536431] RAPL PMU: hw unit of domain package 2^-16 Joules
[ 66.540846] cryptd: max_cpu_qlen set to 1000
[ 66.555617] AVX version of gcm_enc/dec engaged.
[ 66.555619] AES CTR mode by8 optimization enabled
[ 66.629415] mt7601u 2-1.4:1.0: ASIC revision: 76010001 MAC revision: 76010500
[ 66.632349] mt7601u 2-1.4:1.0: firmware: direct-loading firmware mt7601u.bin
[ 66.632356] mt7601u 2-1.4:1.0: Firmware Version: 0.1.00 Build: 7640 Build time: 201302052146____
[ 66.641770] xen:xen_evtchn: Event-channel device installed
[ 66.660459] xen_acpi_processor: Uploading Xen processor PM info
[ 67.020911] mt7601u 2-1.4:1.0: EEPROM ver:0d fae:00
[ 67.248239] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
[ 67.248971] usbcore: registered new interface driver mt7601u
[ 68.457867] input: USB Multimedia Keyboard as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:099A:610C.0001/input/input6
[ 68.519002] hid-generic 0003:099A:610C.0001: input,hidraw0: USB HID v1.00 Keyboard [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input0
[ 68.519547] input: USB Multimedia Keyboard Consumer Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input7
[ 68.559004] intel_rapl_common: Found RAPL domain package
[ 68.559010] intel_rapl_common: Found RAPL domain core
[ 68.569162] mt7601u 2-1.4:1.0 wlx20e0160064bd: renamed from wlan0
[ 68.578532] input: USB Multimedia Keyboard System Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input8
[ 68.578655] hid-generic 0003:099A:610C.0002: input,hidraw1: USB HID v1.00 Device [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input1
[-- Attachment #3: IMG_20210119_154753.jpg --]
[-- Type: image/jpeg, Size: 6829755 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
[not found] ` <CANyqHYcifnCgd5C5vbYoi4CTtoMX5+jzGqHfs6JZ+e=d2Y_dmg@mail.gmail.com>
@ 2021-01-20 8:50 ` Jan Beulich
2021-01-20 15:13 ` Jürgen Groß
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-20 8:50 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel, Juergen Gross, Boris Ostrovsky
On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> I do not have serial output on this setup, so I recorded a video with
> boot_delay=50 in order to be able to get all the kernel messages:
> https://youtu.be/y95h6vqoF7Y
This doesn't show any badness afaics.
> This is running 4.14 from debian bullseye (testing).
>
> I'm also attaching the dmesg output when booting xen 4.8 with the same
> kernel version and same parameters.
>
> I visually compared all the messages, and the only thing I noticed was that
> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> with "clocksource=xen" and the problem is happening with that also.
There's some confusion here I suppose: The clock source you talk
about is the kernel's, not Xen's. I didn't think this would
change for the same kernel version with different Xen underneath,
but the Linux maintainers of the Xen code there may know better.
Cc-ing them.
> The "start" of the problem is that when the kernel gets to the "Freeing
> unused kernel image (initmem) memory: 2380K" it hangs and stays there for a
> while. After a few minutes it shows that a process (swapper) is blocked for
> sometime (image attached)
Now that's pretty unusual - the call trace seen in the screen
shot you had attached indicates the kernel didn't even make it
past its own initialization just yet. Just to have explored that
possibility - could you enable Xen's NMI watchdog (simply
"watchdog" on the Xen command line)? Among the boot messages
there ought to be one indicating whether it actually works on
your system. Without a serial console you wouldn't see anything
if it triggers, but the system would then never make it to the
kernel side issue.
As far as making sure we at least see all kernel messages -
are you having "ignore_loglevel" in place? I don't think I've
been able to spot the kernel command line anywhere in the video.
I'm afraid there's no real way around seeing the full Xen
messages, i.e. including possible ones while Dom0 already boots
(and allowing some debug keys to be issued, as the rcu_barrier
on the stack may suggest there's an issue with one of the
secondary CPUs). You could try whether "vag=keep" on the Xen
command line allows you to see more, but this option may have
quite severe an effect on the timing of Dom0's booting, which
may make an already bad situation worse.
Alternatively the kernel may need instrumenting to figure what
exactly it is that prevent forward progress.
There's one other wild guess you may want to try: "cpuidle=no"
on the Xen command line.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 8:50 ` Jan Beulich
@ 2021-01-20 15:13 ` Jürgen Groß
2021-01-20 20:13 ` Claudemir Todo Bom
` (2 more replies)
0 siblings, 3 replies; 26+ messages in thread
From: Jürgen Groß @ 2021-01-20 15:13 UTC (permalink / raw)
To: Jan Beulich, Claudemir Todo Bom; +Cc: xen-devel, Boris Ostrovsky
[-- Attachment #1.1.1: Type: text/plain, Size: 2983 bytes --]
On 20.01.21 09:50, Jan Beulich wrote:
> On 19.01.2021 20:36, Claudemir Todo Bom wrote:
>> I do not have serial output on this setup, so I recorded a video with
>> boot_delay=50 in order to be able to get all the kernel messages:
>> https://youtu.be/y95h6vqoF7Y
>
> This doesn't show any badness afaics.
>
>> This is running 4.14 from debian bullseye (testing).
>>
>> I'm also attaching the dmesg output when booting xen 4.8 with the same
>> kernel version and same parameters.
>>
>> I visually compared all the messages, and the only thing I noticed was that
>> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
>> with "clocksource=xen" and the problem is happening with that also.
>
> There's some confusion here I suppose: The clock source you talk
> about is the kernel's, not Xen's. I didn't think this would
> change for the same kernel version with different Xen underneath,
> but the Linux maintainers of the Xen code there may know better.
> Cc-ing them.
This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
TSC stability.
>
>> The "start" of the problem is that when the kernel gets to the "Freeing
>> unused kernel image (initmem) memory: 2380K" it hangs and stays there for a
>> while. After a few minutes it shows that a process (swapper) is blocked for
>> sometime (image attached)
>
> Now that's pretty unusual - the call trace seen in the screen
> shot you had attached indicates the kernel didn't even make it
> past its own initialization just yet. Just to have explored that
> possibility - could you enable Xen's NMI watchdog (simply
> "watchdog" on the Xen command line)? Among the boot messages
> there ought to be one indicating whether it actually works on
> your system. Without a serial console you wouldn't see anything
> if it triggers, but the system would then never make it to the
> kernel side issue.
>
> As far as making sure we at least see all kernel messages -
> are you having "ignore_loglevel" in place? I don't think I've
> been able to spot the kernel command line anywhere in the video.
>
> I'm afraid there's no real way around seeing the full Xen
> messages, i.e. including possible ones while Dom0 already boots
> (and allowing some debug keys to be issued, as the rcu_barrier
> on the stack may suggest there's an issue with one of the
> secondary CPUs). You could try whether "vag=keep" on the Xen
> command line allows you to see more, but this option may have
> quite severe an effect on the timing of Dom0's booting, which
> may make an already bad situation worse.
>
> Alternatively the kernel may need instrumenting to figure what
> exactly it is that prevent forward progress.
>
> There's one other wild guess you may want to try: "cpuidle=no"
> on the Xen command line.
Other wild guesses are:
- add "sched=credit" to the Xen command line
or
- add "xen.fifo_events=0" to the dom0 command line
Juergen
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 15:13 ` Jürgen Groß
@ 2021-01-20 20:13 ` Claudemir Todo Bom
2021-01-21 7:59 ` Jan Beulich
2021-01-22 12:55 ` Claudemir Todo Bom
2021-01-22 23:36 ` Claudemir Todo Bom
2 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-20 20:13 UTC (permalink / raw)
To: Jürgen Groß; +Cc: Jan Beulich, xen-devel, Boris Ostrovsky
Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>
> On 20.01.21 09:50, Jan Beulich wrote:
> > On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> >> I do not have serial output on this setup, so I recorded a video with
> >> boot_delay=50 in order to be able to get all the kernel messages:
> >> https://youtu.be/y95h6vqoF7Y
> >
> > This doesn't show any badness afaics.
> >
> >> This is running 4.14 from debian bullseye (testing).
> >>
> >> I'm also attaching the dmesg output when booting xen 4.8 with the same
> >> kernel version and same parameters.
> >>
> >> I visually compared all the messages, and the only thing I noticed was that
> >> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> >> with "clocksource=xen" and the problem is happening with that also.
> >
> > There's some confusion here I suppose: The clock source you talk
> > about is the kernel's, not Xen's. I didn't think this would
> > change for the same kernel version with different Xen underneath,
> > but the Linux maintainers of the Xen code there may know better.
> > Cc-ing them.
>
> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
> TSC stability.
Will ignore this for now, I suppose it is not the cause of the problem.
> >> The "start" of the problem is that when the kernel gets to the "Freeing
> >> unused kernel image (initmem) memory: 2380K" it hangs and stays there for a
> >> while. After a few minutes it shows that a process (swapper) is blocked for
> >> sometime (image attached)
> >
> > Now that's pretty unusual - the call trace seen in the screen
> > shot you had attached indicates the kernel didn't even make it
> > past its own initialization just yet. Just to have explored that
> > possibility - could you enable Xen's NMI watchdog (simply
> > "watchdog" on the Xen command line)? Among the boot messages
> > there ought to be one indicating whether it actually works on
> > your system. Without a serial console you wouldn't see anything
> > if it triggers, but the system would then never make it to the
> > kernel side issue.
"watchdog" parameter changed nothing.
> > As far as making sure we at least see all kernel messages -
> > are you having "ignore_loglevel" in place? I don't think I've
> > been able to spot the kernel command line anywhere in the video.
I was using loglevel=7, since it is the maximum level according to
documentation, should be the same, but tested with "ignore_loglevel"
and it looks pretty similar.
> > I'm afraid there's no real way around seeing the full Xen
> > messages, i.e. including possible ones while Dom0 already boots
> > (and allowing some debug keys to be issued, as the rcu_barrier
> > on the stack may suggest there's an issue with one of the
> > secondary CPUs). You could try whether "vag=keep" on the Xen
> > command line allows you to see more, but this option may have
> > quite severe an effect on the timing of Dom0's booting, which
> > may make an already bad situation worse.
already used "vga=keep", no new information. Will try to enable a
serial output in order to debug more. Is there any parameters I could
give to Xen in order to it write more information on serial line while
the dom0 is booting on the screen?
> > Alternatively the kernel may need instrumenting to figure what
> > exactly it is that prevent forward progress.
> >
> > There's one other wild guess you may want to try: "cpuidle=no"
> > on the Xen command line.
> Other wild guesses are:
>
> - add "sched=credit" to the Xen command line
>
> or
>
> - add "xen.fifo_events=0" to the dom0 command line
all 3 suggestions changed nothing.
I noticed that Debian have a lot of distribution managed patches, so I
think that if I want to find exactly where after 4.8.5 the problem
started I will need to build Xen from sources ignoring debian helpers.
Best regards,
Claudemir
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 20:13 ` Claudemir Todo Bom
@ 2021-01-21 7:59 ` Jan Beulich
0 siblings, 0 replies; 26+ messages in thread
From: Jan Beulich @ 2021-01-21 7:59 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel, Boris Ostrovsky, Jürgen Groß
On 20.01.2021 21:13, Claudemir Todo Bom wrote:
> Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>> On 20.01.21 09:50, Jan Beulich wrote:
>>> I'm afraid there's no real way around seeing the full Xen
>>> messages, i.e. including possible ones while Dom0 already boots
>>> (and allowing some debug keys to be issued, as the rcu_barrier
>>> on the stack may suggest there's an issue with one of the
>>> secondary CPUs). You could try whether "vag=keep" on the Xen
>>> command line allows you to see more, but this option may have
>>> quite severe an effect on the timing of Dom0's booting, which
>>> may make an already bad situation worse.
>
> already used "vga=keep", no new information. Will try to enable a
> serial output in order to debug more. Is there any parameters I could
> give to Xen in order to it write more information on serial line while
> the dom0 is booting on the screen?
You'll presumably want "console=" and "com<N>="; the exact values
to use depend on your system, so I will refer you to the command
line doc[1].
Jan
[1] https://xenbits.xen.org/docs/unstable/misc/xen-command-line.html
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 15:13 ` Jürgen Groß
2021-01-20 20:13 ` Claudemir Todo Bom
@ 2021-01-22 12:55 ` Claudemir Todo Bom
2021-01-22 23:36 ` Claudemir Todo Bom
2 siblings, 0 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-22 12:55 UTC (permalink / raw)
To: Jürgen Groß; +Cc: Jan Beulich, xen-devel, Boris Ostrovsky
[-- Attachment #1: Type: text/plain, Size: 1786 bytes --]
Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>
> On 20.01.21 09:50, Jan Beulich wrote:
> > On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> >> I visually compared all the messages, and the only thing I noticed was that
> >> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> >> with "clocksource=xen" and the problem is happening with that also.
> >
> > There's some confusion here I suppose: The clock source you talk
> > about is the kernel's, not Xen's. I didn't think this would
> > change for the same kernel version with different Xen underneath,
> > but the Linux maintainers of the Xen code there may know better.
> > Cc-ing them.
>
> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
> TSC stability.
Based on this observation I've installed the cpuid utility on the
system and obtained the output of it on all scenarios: raw kernel, xen
4.8.5 and xen 4.14.0.
I used "dom0_max_vcpus=1 dom0_vpus_pin smt=false" on both xen command
lines since this is the only way I can get to a command prompt with
xen 4.14.
the outputs of the cpuid command are attached.
I've compared with diff -u (files also attached):
* the differences of both xen with the raw kernel output
* the differences between both xen
It is clear that xen 4.14 is changing a lot how the dom0 sees the cpu,
disabling a lot of features present both on raw kernel and 4.8
outputs. I don't know if this alone can indicate where the problem is
being triggered.
Next I will try to build xen from source with a "binary tree" approach
between 4.8 and 4.9 commits, but as I will use development source, I
think that is very probable I get with a lot of other problems.
Best regards,
Claudemir
[-- Attachment #2: cpuid-xen-4.8.txt --]
[-- Type: text/plain, Size: 25023 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 0
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #3: cpuid-xen-4.14.txt --]
[-- Type: text/plain, Size: 25742 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = false
PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = false
MONITOR/MWAIT = false
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x0 (0)
largest monitor-line size (bytes) = 0x0 (0)
enum of Monitor-MWAIT exts supported = false
supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x0 (0)
hardware coordination feedback = false
ACNT2 available = false
performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
anythread deprecation = false
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
hypervisor_id = "XenVMMXenVMM"
hypervisor version (0x40000001/eax):
version = 4.14
hypervisor features (0x40000002):
number of hypercall-transfer pages = 0x1 (1)
MSR base address = 0x40000000
MMU_PT_UPDATE_PRESERVE_AD supported = true
hypervisor time features (0x40000003/00):
vtsc = false
host tsc is safe = false
boot cpu has RDTSCP = true
tsc mode = 0x0 (0)
tsc frequency (kHz) = 0
incarnation = 0x0 (0)
hypervisor time scale & offset (0x40000003/01):
vtsc offset = 0x0 (0)
vtsc mul_frac = 0x0 (0)
vtsc shift = 0x0 (0)
hypervisor time physical cpu frequency (0x40000003/02):
cpu frequency (kHZ) = 2494348
HVM-specific parameters (0x40000004):
virtualized APIC registers = false
virtualized x2APIC accesses = false
IOMMU mappings for other domain memory = false
vcpu id is valid = false
domain id is valid = false
vcpu id = 0x0 (0)
domain id = 0x0 (0)
PV-specific parameters (0x40000005):
maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 1/4
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #4: cpuid-diff-xen-4.8-4.14.diff --]
[-- Type: text/x-patch, Size: 12765 bytes --]
--- cpuid-xen-4.8.txt 2021-01-22 09:32:38.279999364 -0300
+++ cpuid-xen-4.14.txt 2021-01-22 09:24:58.776001456 -0300
@@ -18,9 +18,9 @@
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
+ VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
- PSE: page size extensions = true
+ PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
@@ -28,15 +28,15 @@
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
+ MTRR: memory type range registers = false
+ PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
- PSE-36: page size extension = true
+ PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
- DS: debug store = true
+ DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
@@ -44,41 +44,41 @@
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
- TM: therm. monitor = true
+ TM: therm. monitor = false
IA64 = false
- PBE: pending break event = true
+ PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
+ DTES64: 64-bit debug store = false
+ MONITOR/MWAIT = false
+ CPL-qualified debug store = false
+ VMX: virtual machine extensions = false
+ SMX: safer mode extensions = false
+ Enhanced Intel SpeedStep Technology = false
+ TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
+ xTPR disable = false
+ PDCM: perfmon and debug = false
+ PCID: process context identifiers = false
+ DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
- time stamp counter deadline = true
+ time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
- hypervisor guest status = false
+ hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
@@ -155,25 +155,25 @@
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
+ smallest monitor-line size (bytes) = 0x0 (0)
+ largest monitor-line size (bytes) = 0x0 (0)
+ enum of Monitor-MWAIT exts supported = false
+ supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
+ number of C1 sub C-states using MWAIT = 0x0 (0)
+ number of C2 sub C-states using MWAIT = 0x0 (0)
+ number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
- digital thermometer = true
+ digital thermometer = false
Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
+ ARAT always running APIC timer = false
+ PLN power limit notification = false
+ ECMD extended clock modulation duty = false
+ PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
@@ -188,10 +188,10 @@
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
+ digital thermometer thresholds = 0x0 (0)
+ hardware coordination feedback = false
ACNT2 available = false
- performance-energy bias capability = true
+ performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
@@ -205,7 +205,7 @@
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
+ SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
@@ -279,12 +279,12 @@
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
+ PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
+ version ID = 0x0 (0)
+ number of counters per logical processor = 0x0 (0)
+ bit width of counter = 0x0 (0)
+ length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
@@ -324,21 +324,9 @@
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
+ number of fixed counters = 0x0 (0)
+ bit width of fixed counters = 0x0 (0)
anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 0
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
@@ -377,10 +365,40 @@
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
+ hypervisor_id = "XenVMMXenVMM"
+ hypervisor version (0x40000001/eax):
+ version = 4.14
+ hypervisor features (0x40000002):
+ number of hypercall-transfer pages = 0x1 (1)
+ MSR base address = 0x40000000
+ MMU_PT_UPDATE_PRESERVE_AD supported = true
+ hypervisor time features (0x40000003/00):
+ vtsc = false
+ host tsc is safe = false
+ boot cpu has RDTSCP = true
+ tsc mode = 0x0 (0)
+ tsc frequency (kHz) = 0
+ incarnation = 0x0 (0)
+ hypervisor time scale & offset (0x40000003/01):
+ vtsc offset = 0x0 (0)
+ vtsc mul_frac = 0x0 (0)
+ vtsc shift = 0x0 (0)
+ hypervisor time physical cpu frequency (0x40000003/02):
+ cpu frequency (kHZ) = 2494348
+ HVM-specific parameters (0x40000004):
+ virtualized APIC registers = false
+ virtualized x2APIC accesses = false
+ IOMMU mappings for other domain memory = false
+ vcpu id is valid = false
+ domain id is valid = false
+ vcpu id = 0x0 (0)
+ domain id = 0x0 (0)
+ PV-specific parameters (0x40000005):
+ maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
- 1-GB large page support = true
+ 1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
@@ -476,9 +494,9 @@
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
+ (multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
+ (multi-processing method) = Intel leaf 1/4
+ (APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #5: cpuid-diff-rawkernel-xen-4.8.diff --]
[-- Type: text/x-patch, Size: 587059 bytes --]
--- cpuid-rawkernel.txt 2021-01-22 09:22:28.718600017 -0300
+++ cpuid-xen-4.8.txt 2021-01-22 09:32:38.279999364 -0300
@@ -482,11135 +482,3 @@
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 1:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x2 (2)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 2
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 2:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x4 (4)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 4
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 3:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x6 (6)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 6
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 4:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x8 (8)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 8
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 5:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xa (10)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 10
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 6:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x10 (16)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 16
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 7:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x12 (18)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 18
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 8:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x14 (20)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 20
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 9:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x16 (22)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 22
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 10:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x18 (24)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 24
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 11:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1a (26)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 26
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 12:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1 (1)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 1
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 13:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x3 (3)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 3
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 14:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x5 (5)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 5
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 15:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x7 (7)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 7
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 16:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x9 (9)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 9
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 17:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xb (11)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 11
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 18:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x11 (17)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 17
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 19:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x13 (19)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 19
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 20:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x15 (21)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 21
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 21:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x17 (23)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 23
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 22:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x19 (25)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 25
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 23:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1b (27)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 27
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #6: cpuid-rawkernel.txt --]
[-- Type: text/plain, Size: 600614 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 0
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 1:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x2 (2)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 2
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 2:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x4 (4)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 4
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 3:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x6 (6)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 6
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 4:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x8 (8)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 8
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 5:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0xa (10)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 10
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 6:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x10 (16)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 16
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 7:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x12 (18)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 18
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 8:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x14 (20)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 20
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 9:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x16 (22)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 22
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 10:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x18 (24)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 24
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 11:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1a (26)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 26
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 12:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1 (1)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 1
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 13:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x3 (3)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 3
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 14:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x5 (5)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 5
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 15:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x7 (7)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 7
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 16:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x9 (9)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 9
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 17:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0xb (11)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 11
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 18:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x11 (17)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 17
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 19:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x13 (19)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 19
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 20:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x15 (21)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 21
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 21:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x17 (23)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 23
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 22:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x19 (25)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 25
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 23:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1b (27)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 27
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #7: cpuid-diff-rawkernel-xen-4.14.diff --]
[-- Type: text/x-patch, Size: 599494 bytes --]
--- cpuid-rawkernel.txt 2021-01-22 09:22:28.718600017 -0300
+++ cpuid-xen-4.14.txt 2021-01-22 09:24:58.776001456 -0300
@@ -18,9 +18,9 @@
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
+ VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
- PSE: page size extensions = true
+ PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
@@ -28,15 +28,15 @@
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
+ MTRR: memory type range registers = false
+ PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
- PSE-36: page size extension = true
+ PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
- DS: debug store = true
+ DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
@@ -44,41 +44,41 @@
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
- TM: therm. monitor = true
+ TM: therm. monitor = false
IA64 = false
- PBE: pending break event = true
+ PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
+ DTES64: 64-bit debug store = false
+ MONITOR/MWAIT = false
+ CPL-qualified debug store = false
+ VMX: virtual machine extensions = false
+ SMX: safer mode extensions = false
+ Enhanced Intel SpeedStep Technology = false
+ TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
+ xTPR disable = false
+ PDCM: perfmon and debug = false
+ PCID: process context identifiers = false
+ DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
- time stamp counter deadline = true
+ time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
- hypervisor guest status = false
+ hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
@@ -155,25 +155,25 @@
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
+ smallest monitor-line size (bytes) = 0x0 (0)
+ largest monitor-line size (bytes) = 0x0 (0)
+ enum of Monitor-MWAIT exts supported = false
+ supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
+ number of C1 sub C-states using MWAIT = 0x0 (0)
+ number of C2 sub C-states using MWAIT = 0x0 (0)
+ number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
- digital thermometer = true
+ digital thermometer = false
Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
+ ARAT always running APIC timer = false
+ PLN power limit notification = false
+ ECMD extended clock modulation duty = false
+ PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
@@ -188,10 +188,10 @@
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
+ digital thermometer thresholds = 0x0 (0)
+ hardware coordination feedback = false
ACNT2 available = false
- performance-energy bias capability = true
+ performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
@@ -205,7 +205,7 @@
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
+ SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
@@ -279,12 +279,12 @@
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
+ PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
+ version ID = 0x0 (0)
+ number of counters per logical processor = 0x0 (0)
+ bit width of counter = 0x0 (0)
+ length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
@@ -324,21 +324,9 @@
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
+ number of fixed counters = 0x0 (0)
+ bit width of fixed counters = 0x0 (0)
anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 0
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
@@ -377,10 +365,40 @@
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
+ hypervisor_id = "XenVMMXenVMM"
+ hypervisor version (0x40000001/eax):
+ version = 4.14
+ hypervisor features (0x40000002):
+ number of hypercall-transfer pages = 0x1 (1)
+ MSR base address = 0x40000000
+ MMU_PT_UPDATE_PRESERVE_AD supported = true
+ hypervisor time features (0x40000003/00):
+ vtsc = false
+ host tsc is safe = false
+ boot cpu has RDTSCP = true
+ tsc mode = 0x0 (0)
+ tsc frequency (kHz) = 0
+ incarnation = 0x0 (0)
+ hypervisor time scale & offset (0x40000003/01):
+ vtsc offset = 0x0 (0)
+ vtsc mul_frac = 0x0 (0)
+ vtsc shift = 0x0 (0)
+ hypervisor time physical cpu frequency (0x40000003/02):
+ cpu frequency (kHZ) = 2494348
+ HVM-specific parameters (0x40000004):
+ virtualized APIC registers = false
+ virtualized x2APIC accesses = false
+ IOMMU mappings for other domain memory = false
+ vcpu id is valid = false
+ domain id is valid = false
+ vcpu id = 0x0 (0)
+ domain id = 0x0 (0)
+ PV-specific parameters (0x40000005):
+ maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
- 1-GB large page support = true
+ 1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
@@ -476,11141 +494,9 @@
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
+ (multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
+ (multi-processing method) = Intel leaf 1/4
+ (APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 1:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x2 (2)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 2
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 2:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x4 (4)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 4
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 3:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x6 (6)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 6
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 4:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x8 (8)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 8
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 5:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xa (10)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 10
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 6:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x10 (16)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 16
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 7:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x12 (18)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 18
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 8:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x14 (20)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 20
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 9:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x16 (22)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 22
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 10:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x18 (24)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 24
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 11:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1a (26)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 26
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 12:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1 (1)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 1
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 13:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x3 (3)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 3
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 14:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x5 (5)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 5
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 15:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x7 (7)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 7
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 16:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x9 (9)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 9
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 17:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xb (11)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 11
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 18:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x11 (17)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 17
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 19:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x13 (19)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 19
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 20:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x15 (21)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 21
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 21:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x17 (23)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 23
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 22:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x19 (25)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 25
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 23:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1b (27)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 27
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 15:13 ` Jürgen Groß
2021-01-20 20:13 ` Claudemir Todo Bom
2021-01-22 12:55 ` Claudemir Todo Bom
@ 2021-01-22 23:36 ` Claudemir Todo Bom
2021-01-25 9:38 ` Jan Beulich
2 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-22 23:36 UTC (permalink / raw)
To: Jürgen Groß; +Cc: Jan Beulich, xen-devel, Boris Ostrovsky
Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>
> On 20.01.21 09:50, Jan Beulich wrote:
> > On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> >> I do not have serial output on this setup, so I recorded a video with
> >> boot_delay=50 in order to be able to get all the kernel messages:
> >> https://youtu.be/y95h6vqoF7Y
> >
> > This doesn't show any badness afaics.
> >
> >> This is running 4.14 from debian bullseye (testing).
> >>
> >> I'm also attaching the dmesg output when booting xen 4.8 with the same
> >> kernel version and same parameters.
> >>
> >> I visually compared all the messages, and the only thing I noticed was that
> >> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> >> with "clocksource=xen" and the problem is happening with that also.
> >
> > There's some confusion here I suppose: The clock source you talk
> > about is the kernel's, not Xen's. I didn't think this would
> > change for the same kernel version with different Xen underneath,
> > but the Linux maintainers of the Xen code there may know better.
> > Cc-ing them.
>
> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
> TSC stability.
>
Looks like the CPUID changes I observed and wrote on the other
messages are another
problem I may end up with. I narrowed down the cause of the problem on
booting of dom0 with more than 1 core on the following commit:
https://github.com/xen-project/xen/commit/63e1d01b8fd948b3e0fa3beea494e407668aa43b
Code built from this commit doesn't boot, built from the parent of it, boots.
Now, there is something I can do on the command line to make it boots?
Or its needed to fix on the code?
Best regards,
Claudemir
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-22 23:36 ` Claudemir Todo Bom
@ 2021-01-25 9:38 ` Jan Beulich
2021-01-25 19:37 ` Claudemir Todo Bom
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-25 9:38 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel, Boris Ostrovsky, Jürgen Groß
On 23.01.2021 00:36, Claudemir Todo Bom wrote:
> Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>>
>> On 20.01.21 09:50, Jan Beulich wrote:
>>> On 19.01.2021 20:36, Claudemir Todo Bom wrote:
>>>> I do not have serial output on this setup, so I recorded a video with
>>>> boot_delay=50 in order to be able to get all the kernel messages:
>>>> https://youtu.be/y95h6vqoF7Y
>>>
>>> This doesn't show any badness afaics.
>>>
>>>> This is running 4.14 from debian bullseye (testing).
>>>>
>>>> I'm also attaching the dmesg output when booting xen 4.8 with the same
>>>> kernel version and same parameters.
>>>>
>>>> I visually compared all the messages, and the only thing I noticed was that
>>>> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
>>>> with "clocksource=xen" and the problem is happening with that also.
>>>
>>> There's some confusion here I suppose: The clock source you talk
>>> about is the kernel's, not Xen's. I didn't think this would
>>> change for the same kernel version with different Xen underneath,
>>> but the Linux maintainers of the Xen code there may know better.
>>> Cc-ing them.
>>
>> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
>> TSC stability.
>>
>
> Looks like the CPUID changes I observed and wrote on the other
> messages are another
> problem I may end up with. I narrowed down the cause of the problem on
> booting of dom0 with more than 1 core on the following commit:
>
> https://github.com/xen-project/xen/commit/63e1d01b8fd948b3e0fa3beea494e407668aa43b
>
> Code built from this commit doesn't boot, built from the parent of it, boots.
Odd.
> Now, there is something I can do on the command line to make it boots?
> Or its needed to fix on the code?
That's too early to ask. We first need to understand what's going
on. There are two things I'd like you to try: One is to use
"clocksource=tsc" on the Xen (not the kernel) command line, and
the other (without that option) is to try the debugging patch
below. Of course that patch is only going to be useful when you
can somehow record Xen's log messages up to the point where the
system hangs. (Both ideally on as new a Xen as you can arrange
for.)
Jan
--- unstable.orig/xen/arch/x86/time.c
+++ unstable/xen/arch/x86/time.c
@@ -1799,9 +1799,11 @@ static void time_calibration(void *unuse
cpumask_copy(&r.cpu_calibration_map, &cpu_online_map);
/* @wait=1 because we must wait for all cpus before freeing @r. */
+printk("TSC: %ps\n", time_calibration_rendezvous_fn);//temp
on_selected_cpus(&r.cpu_calibration_map,
time_calibration_rendezvous_fn,
&r, 1);
+printk("TSC: end rendezvous\n");//temp
}
static struct cpu_time_stamp ap_bringup_ref;
@@ -2043,6 +2045,7 @@ static int __init verify_tsc_reliability
* While with constant-rate TSCs the scale factor can be shared, when TSCs
* are not marked as 'reliable', re-sync during rendezvous.
*/
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
!boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
@@ -2056,6 +2059,7 @@ int __init init_xen_time(void)
{
tsc_check_writability();
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
/* NB. get_wallclock_time() can take over one second to execute. */
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-25 9:38 ` Jan Beulich
@ 2021-01-25 19:37 ` Claudemir Todo Bom
2021-01-26 11:48 ` Jan Beulich
0 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-25 19:37 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel, Boris Ostrovsky, Jürgen Groß
[-- Attachment #1: Type: text/plain, Size: 4784 bytes --]
Em seg., 25 de jan. de 2021 às 06:38, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 23.01.2021 00:36, Claudemir Todo Bom wrote:
> > Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
> >>
> >> On 20.01.21 09:50, Jan Beulich wrote:
> >>> On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> >>>> I do not have serial output on this setup, so I recorded a video with
> >>>> boot_delay=50 in order to be able to get all the kernel messages:
> >>>> https://youtu.be/y95h6vqoF7Y
> >>>
> >>> This doesn't show any badness afaics.
> >>>
> >>>> This is running 4.14 from debian bullseye (testing).
> >>>>
> >>>> I'm also attaching the dmesg output when booting xen 4.8 with the same
> >>>> kernel version and same parameters.
> >>>>
> >>>> I visually compared all the messages, and the only thing I noticed was that
> >>>> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> >>>> with "clocksource=xen" and the problem is happening with that also.
> >>>
> >>> There's some confusion here I suppose: The clock source you talk
> >>> about is the kernel's, not Xen's. I didn't think this would
> >>> change for the same kernel version with different Xen underneath,
> >>> but the Linux maintainers of the Xen code there may know better.
> >>> Cc-ing them.
> >>
> >> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
> >> TSC stability.
> >>
> >
> > Looks like the CPUID changes I observed and wrote on the other
> > messages are another
> > problem I may end up with. I narrowed down the cause of the problem on
> > booting of dom0 with more than 1 core on the following commit:
> >
> > https://github.com/xen-project/xen/commit/63e1d01b8fd948b3e0fa3beea494e407668aa43b
> >
> > Code built from this commit doesn't boot, built from the parent of it, boots.
>
> Odd.
>
> > Now, there is something I can do on the command line to make it boots?
> > Or its needed to fix on the code?
>
> That's too early to ask. We first need to understand what's going
> on. There are two things I'd like you to try: One is to use
> "clocksource=tsc" on the Xen (not the kernel) command line, and
> the other (without that option) is to try the debugging patch
> below. Of course that patch is only going to be useful when you
> can somehow record Xen's log messages up to the point where the
> system hangs. (Both ideally on as new a Xen as you can arrange
> for.)
>
> Jan
>
> --- unstable.orig/xen/arch/x86/time.c
> +++ unstable/xen/arch/x86/time.c
> @@ -1799,9 +1799,11 @@ static void time_calibration(void *unuse
> cpumask_copy(&r.cpu_calibration_map, &cpu_online_map);
>
> /* @wait=1 because we must wait for all cpus before freeing @r. */
> +printk("TSC: %ps\n", time_calibration_rendezvous_fn);//temp
> on_selected_cpus(&r.cpu_calibration_map,
> time_calibration_rendezvous_fn,
> &r, 1);
> +printk("TSC: end rendezvous\n");//temp
> }
>
> static struct cpu_time_stamp ap_bringup_ref;
> @@ -2043,6 +2045,7 @@ static int __init verify_tsc_reliability
> * While with constant-rate TSCs the scale factor can be shared, when TSCs
> * are not marked as 'reliable', re-sync during rendezvous.
> */
> +printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
> if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
> !boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
> time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
> @@ -2056,6 +2059,7 @@ int __init init_xen_time(void)
> {
> tsc_check_writability();
>
> +printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
> open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
>
> /* NB. get_wallclock_time() can take over one second to execute. */
>
I've managed to get the debug messages on the screen using
vga=text-80x50,keep and disabling all messages from the kernel. Two
images are attached with the output running the debug patch.
About the version I've used to test: since the 4.14 shows that other
bug with the detection of cpu features I mentioned on the other
subthread, I chose to work on 4.11 that doesn't shows that behaviour.
Calling with clocksource on the xen command line changed nothing.
I don't know if this part of code is intended to execute a lot of
times, but when starting with dom0_max_vcpus=1, the system boots up
and keeps showing the messages.
I've checked the reversion of the code on the commit #63e1d01 and the
system boots up. I've not checked with any virtual machine yet.
Best regards,
Claudemir
[-- Attachment #2: IMG_20210125_161303.jpg --]
[-- Type: image/jpeg, Size: 5135186 bytes --]
[-- Attachment #3: IMG_20210125_162313.jpg --]
[-- Type: image/jpeg, Size: 5424131 bytes --]
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-25 19:37 ` Claudemir Todo Bom
@ 2021-01-26 11:48 ` Jan Beulich
2021-01-27 12:25 ` Claudemir Todo Bom
[not found] ` <CANyqHYeDR_NUKzPtbfLiUzxAUzerKepbU4B-_6=U-7Y6uy8gpQ@mail.gmail.com>
0 siblings, 2 replies; 26+ messages in thread
From: Jan Beulich @ 2021-01-26 11:48 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel, Boris Ostrovsky, Jürgen Groß
On 25.01.2021 20:37, Claudemir Todo Bom wrote:
> I've managed to get the debug messages on the screen using
> vga=text-80x50,keep and disabling all messages from the kernel. Two
> images are attached with the output running the debug patch.
And the 1st of them (161303) was taken at the time of the hang of
the kernel (or entire system), not any earlier? I ask because one
part of the reason for the patch was to understand whether the
rendezvousing itself would fail in some way (like one of the CPUs
not calling in).
Were new log messages (from the debugging patch) still issued at
this point, showing Xen itself was still alive?
The 2nd of the pictures (162313) at least clarifies that indeed
the commit in question had a functional effect on this system,
because of
(XEN) TSC warp detected, disabling TSC_RELIABLE
I still can't figure though why the change in rendezvous handling
(from "std" to "tsc") would have broken your system.
> About the version I've used to test: since the 4.14 shows that other
> bug with the detection of cpu features I mentioned on the other
> subthread, I chose to work on 4.11 that doesn't shows that behaviour.
>
> Calling with clocksource on the xen command line changed nothing.
Oh, right, because the specific feature that causes the change
of rendezvous functions for you also is a prereq for that mode
of operation.
> I don't know if this part of code is intended to execute a lot of
> times, but when starting with dom0_max_vcpus=1, the system boots up
> and keeps showing the messages.
When there's just one CPU, there's no CPU to rendezvous with.
Iirc you did say that you observe the hang even with as little
as 2 CPUs? The problem the above quoted message is supposed to
address is normally coming into play only on multi-socket
systems. Yet from your initial report I deduce this is a
single socket system. So in the end I suppose there are two
problems - one is the hang, and the other is that your system
gets diagnosed as having an unreliable TSC (at least I didn't
think Xeon E5 v2 should have a problem there).
I will want to extend the debugging patch, but I'd like to
have clarification on some of the points above first.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-26 11:48 ` Jan Beulich
@ 2021-01-27 12:25 ` Claudemir Todo Bom
[not found] ` <CANyqHYeDR_NUKzPtbfLiUzxAUzerKepbU4B-_6=U-7Y6uy8gpQ@mail.gmail.com>
1 sibling, 0 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-27 12:25 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel, Boris Ostrovsky, Jürgen Groß
Em ter., 26 de jan. de 2021 às 08:48, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 25.01.2021 20:37, Claudemir Todo Bom wrote:
> > I've managed to get the debug messages on the screen using
> > vga=text-80x50,keep and disabling all messages from the kernel. Two
> > images are attached with the output running the debug patch.
>
> And the 1st of them (161303) was taken at the time of the hang of
> the kernel (or entire system), not any earlier? I ask because one
> part of the reason for the patch was to understand whether the
> rendezvousing itself would fail in some way (like one of the CPUs
> not calling in).
I could not tell if it already hung when I took the picture, but I can
tell the messages keep appearing after the hang. I tested this
enabling log messages... the screen became a mess, but I can assure
that the rendezvous function is being run and completed multiple times
after the "freeing memory" message that freezes the kernel.
> Were new log messages (from the debugging patch) still issued at
> this point, showing Xen itself was still alive?
>
> The 2nd of the pictures (162313) at least clarifies that indeed
> the commit in question had a functional effect on this system,
> because of
>
> (XEN) TSC warp detected, disabling TSC_RELIABLE
>
> I still can't figure though why the change in rendezvous handling
> (from "std" to "tsc") would have broken your system.
>
> > About the version I've used to test: since the 4.14 shows that other
> > bug with the detection of cpu features I mentioned on the other
> > subthread, I chose to work on 4.11 that doesn't shows that behaviour.
> >
> > Calling with clocksource on the xen command line changed nothing.
>
> Oh, right, because the specific feature that causes the change
> of rendezvous functions for you also is a prereq for that mode
> of operation.
Oh, this should be why reverting the code on 4.14 didn't work...
probably messed up with features introduced after 4.11.
> > I don't know if this part of code is intended to execute a lot of
> > times, but when starting with dom0_max_vcpus=1, the system boots up
> > and keeps showing the messages.
>
> When there's just one CPU, there's no CPU to rendezvous with.
>
> Iirc you did say that you observe the hang even with as little
> as 2 CPUs? The problem the above quoted message is supposed to
> address is normally coming into play only on multi-socket
> systems. Yet from your initial report I deduce this is a
> single socket system. So in the end I suppose there are two
> problems - one is the hang, and the other is that your system
> gets diagnosed as having an unreliable TSC (at least I didn't
> think Xeon E5 v2 should have a problem there).
It is a single socket, I was talking about virtual cpus for domain 0.
After the last tests I tried to boot it with maxcpus=1 parameter on
the xen command line. This changed the rendezvous code to std and the
system worked on all versions up to 4.14.
Is there any performance issue on using this parameter and this "std"
rendezvous code?
> I will want to extend the debugging patch, but I'd like to
> have clarification on some of the points above first.
If this information is good for more tests, please send the patch and
I will test it!
Best regards,
Claudemir
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
[not found] ` <CANyqHYeDR_NUKzPtbfLiUzxAUzerKepbU4B-_6=U-7Y6uy8gpQ@mail.gmail.com>
@ 2021-01-28 9:47 ` Jan Beulich
2021-01-28 9:49 ` Jan Beulich
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-28 9:47 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 26.01.2021 14:03, Claudemir Todo Bom wrote:
> If this information is good for more tests, please send the patch and
> I will test it!
Here you go. For simplifying analysis it may be helpful if you
could limit the number of CPUs in use, e.g. by "maxcpus=4" or
at least "smt=0". Provided the problem still reproduces with
such options, of course.
Jan
--- unstable.orig/xen/arch/x86/time.c
+++ unstable/xen/arch/x86/time.c
@@ -1574,6 +1574,12 @@ static void local_time_calibration(void)
* TSC Reliability check
*/
+static struct {//temp
+ unsigned cpu;
+ signed iter;
+ cycles_t prev, now;
+} check_log[NR_CPUS + 4];
+static unsigned check_idx;//temp
/*
* The Linux original version of this function is
* Copyright (c) 2006, Red Hat, Inc., Ingo Molnar
@@ -1582,6 +1588,7 @@ static void check_tsc_warp(unsigned long
{
static DEFINE_SPINLOCK(sync_lock);
static cycles_t last_tsc;
+unsigned idx, cpu = smp_processor_id();//temp
cycles_t start, now, prev, end;
int i;
@@ -1592,6 +1599,15 @@ static void check_tsc_warp(unsigned long
end = start + tsc_khz * 20ULL;
now = start;
+{//temp
+ spin_lock(&sync_lock);
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = -1;
+ check_log[idx].now = now;
+ spin_unlock(&sync_lock);
+}
+
for ( i = 0; ; i++ )
{
/*
@@ -1626,7 +1642,14 @@ static void check_tsc_warp(unsigned long
{
spin_lock(&sync_lock);
if ( *max_warp < prev - now )
+{//temp
*max_warp = prev - now;
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = i;
+ check_log[idx].prev = prev;
+ check_log[idx].now = now;
+}
spin_unlock(&sync_lock);
}
}
@@ -1663,6 +1686,12 @@ static void tsc_check_reliability(void)
cpu_relax();
spin_unlock(&lock);
+{//temp
+ unsigned i;
+ printk("CHK[%2u] %lx\n", cpu, tsc_max_warp);//temp
+ for(i = 0; i < ARRAY_SIZE(check_log) && check_log[i].now; ++i)
+ printk("chk[%4u] CPU%-2u %016lx %016lx #%d\n", i, check_log[i].cpu, check_log[i].prev, check_log[i].now, check_log[i].iter);
+}
}
/*
@@ -1677,6 +1706,7 @@ struct calibration_rendezvous {
u64 master_tsc_stamp;
};
+static bool rdzv_log;//temp
static void
time_calibration_rendezvous_tail(const struct calibration_rendezvous *r)
{
@@ -1686,6 +1716,7 @@ time_calibration_rendezvous_tail(const s
c->local_stime = get_s_time_fixed(c->local_tsc);
c->master_stime = r->master_stime;
+if(rdzv_log) printk("RDZV[%2u] t=%016lx(%016lx) s=%012lx(%012lx)\n", smp_processor_id(), c->local_tsc, r->master_tsc_stamp, c->local_stime, r->master_stime);//temp
raise_softirq(TIME_CALIBRATE_SOFTIRQ);
}
@@ -1699,6 +1730,7 @@ static void time_calibration_tsc_rendezv
struct calibration_rendezvous *r = _r;
unsigned int total_cpus = cpumask_weight(&r->cpu_calibration_map);
+if(rdzv_log) printk("RDZV[%2u] t=%016lx\n", smp_processor_id(), rdtsc_ordered());//temp
/* Loop to get rid of cache effects on TSC skew. */
for ( i = 4; i >= 0; i-- )
{
@@ -1788,6 +1820,12 @@ static void time_calibration(void *unuse
struct calibration_rendezvous r = {
.semaphore = ATOMIC_INIT(0)
};
+static unsigned long cnt, thr;//temp
+if(system_state > SYS_STATE_smp_boot && ++cnt > thr) {//temp
+ thr |= cnt;
+ printk("TSC: %ps\n", time_calibration_rendezvous_fn);
+ rdzv_log = true;
+}
if ( clocksource_is_tsc() )
{
@@ -1802,6 +1840,10 @@ static void time_calibration(void *unuse
on_selected_cpus(&r.cpu_calibration_map,
time_calibration_rendezvous_fn,
&r, 1);
+if(rdzv_log || system_state <= SYS_STATE_smp_boot) {//temp
+ rdzv_log = false;
+ printk("TSC: end rendezvous\n");
+}
}
static struct cpu_time_stamp ap_bringup_ref;
@@ -1898,6 +1940,7 @@ void init_percpu_time(void)
}
t->stamp.local_tsc = tsc;
t->stamp.local_stime = now;
+printk("INIT[%2u] t=%016lx s=%012lx m=%012lx\n", smp_processor_id(), tsc, now, t->stamp.master_stime);//temp
}
/*
@@ -2043,6 +2086,7 @@ static int __init verify_tsc_reliability
* While with constant-rate TSCs the scale factor can be shared, when TSCs
* are not marked as 'reliable', re-sync during rendezvous.
*/
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
!boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
@@ -2056,6 +2100,7 @@ int __init init_xen_time(void)
{
tsc_check_writability();
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
/* NB. get_wallclock_time() can take over one second to execute. */
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-28 9:47 ` Jan Beulich
@ 2021-01-28 9:49 ` Jan Beulich
2021-01-28 13:08 ` Claudemir Todo Bom
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-28 9:49 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 28.01.2021 10:47, Jan Beulich wrote:
> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
>> If this information is good for more tests, please send the patch and
>> I will test it!
>
> Here you go. For simplifying analysis it may be helpful if you
> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
> at least "smt=0". Provided the problem still reproduces with
> such options, of course.
Speaking of command line options - it doesn't look like you have
told us what else you have on the Xen command line, and without
a serial log this isn't visible (e.g. in your video).
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-28 9:49 ` Jan Beulich
@ 2021-01-28 13:08 ` Claudemir Todo Bom
2021-01-29 14:21 ` Jan Beulich
2021-01-29 16:24 ` Jan Beulich
0 siblings, 2 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-28 13:08 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel
[-- Attachment #1: Type: text/plain, Size: 1538 bytes --]
Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 28.01.2021 10:47, Jan Beulich wrote:
> > On 26.01.2021 14:03, Claudemir Todo Bom wrote:
> >> If this information is good for more tests, please send the patch and
> >> I will test it!
> >
> > Here you go. For simplifying analysis it may be helpful if you
> > could limit the number of CPUs in use, e.g. by "maxcpus=4" or
> > at least "smt=0". Provided the problem still reproduces with
> > such options, of course.
>
> Speaking of command line options - it doesn't look like you have
> told us what else you have on the Xen command line, and without
> a serial log this isn't visible (e.g. in your video).
All tests are done with xen command line:
dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
smt=false vga=text-80x50,keep
and kernel command line:
loglevel=0 earlyprintk=xen nomodeset
this way I can get all xen messages on console.
Attached are the frames I captured from a video, I manually selected
them starting from the first readable frame.
As a sidenote, I managed to get the system working with the parameter
"tsc=unstable", performance looks satisfactory but I do not know what
problems I may end with this parameter.
About the CPU: it is an E5-2696v2... it was bought used and is
probably recycled from an OEM server, since this CPU model doesn't
appear on the official Intel website, it looks similar to E5-2697v2,
but is 2.5Ghz instead of 2.7Ghz.
Best regards,
Claudemir
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^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-28 13:08 ` Claudemir Todo Bom
@ 2021-01-29 14:21 ` Jan Beulich
2021-01-29 15:07 ` Claudemir Todo Bom
2021-01-29 16:24 ` Jan Beulich
1 sibling, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-29 14:21 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 28.01.2021 14:08, Claudemir Todo Bom wrote:
> Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
>>
>> On 28.01.2021 10:47, Jan Beulich wrote:
>>> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
>>>> If this information is good for more tests, please send the patch and
>>>> I will test it!
>>>
>>> Here you go. For simplifying analysis it may be helpful if you
>>> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
>>> at least "smt=0". Provided the problem still reproduces with
>>> such options, of course.
>>
>> Speaking of command line options - it doesn't look like you have
>> told us what else you have on the Xen command line, and without
>> a serial log this isn't visible (e.g. in your video).
>
> All tests are done with xen command line:
>
> dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
> smt=false vga=text-80x50,keep
>
> and kernel command line:
>
> loglevel=0 earlyprintk=xen nomodeset
>
> this way I can get all xen messages on console.
>
> Attached are the frames I captured from a video, I manually selected
> them starting from the first readable frame.
Okay, so we seem to be hitting two previously noticed issues, neither
of which so far was necessary to address directly (because there was
always something else to be tweaked such that the problems went away).
For one, the boot CPU has a TSC value that lags by more than a
second compared to all secondary CPUs. The way
time_calibration_tsc_rendezvous() works, together with the way we
calculate system time from the TSC (get_s_time_fixed() - this is
where the known issue here is: the function breaks when trying to
scale a negative delta, hence the absurdly high s= values in the
screenshots you've provided), allows for small negative deltas
between CPUs, but expects to bring all CPUs' TSCs forward (i.e. over
the 1s interval between rendezvous' the lagging CPUs are assumed to
have made enough progress to be ahead of the more towards the future
timestamps on the previous run). Secondary lagging behind the boot
CPU more than this could also be dealt with, but on your system the
situation is the other way around.
Btw - what kind of BIOS do you have on this system? This way of the
TSCs being set is pretty odd, and must be - unless you run other
pre-boot software or an unusual boot loader - caused by the BIOS.
And then this points out (again, afaic at least) that the way we
kickstart the rendezvous handling is likely inappropriate.
Especially when TSCs are skewed like they are here, it is unhelpful
to launch Dom0 before having brought the TSC in sync. (Related to
this, I also don't think we should arm the respective timer before
AP bringup was done, or else we risk the first rendezvous instance
to not hit all CPUs.)
I'll work on addressing both, hoping that in particular for the
first one you'll be ready to help with testing (through perhaps
multiple iterations).
> As a sidenote, I managed to get the system working with the parameter
> "tsc=unstable", performance looks satisfactory but I do not know what
> problems I may end with this parameter.
I _think_ you'd be running into trouble if you removed dom0_vcpus_pin
(which imo really no-one should use without reporting a bug, despite
all the hits to the contrary that one gets when searching the web),
and if you ran any guests (PV at least) without pinning their vCPU-s
to pCPU-s.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-29 14:21 ` Jan Beulich
@ 2021-01-29 15:07 ` Claudemir Todo Bom
0 siblings, 0 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-29 15:07 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel
Em sex., 29 de jan. de 2021 às 11:21, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 28.01.2021 14:08, Claudemir Todo Bom wrote:
> > Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
> >>
> >> On 28.01.2021 10:47, Jan Beulich wrote:
> >>> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
> >>>> If this information is good for more tests, please send the patch and
> >>>> I will test it!
> >>>
> >>> Here you go. For simplifying analysis it may be helpful if you
> >>> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
> >>> at least "smt=0". Provided the problem still reproduces with
> >>> such options, of course.
> >>
> >> Speaking of command line options - it doesn't look like you have
> >> told us what else you have on the Xen command line, and without
> >> a serial log this isn't visible (e.g. in your video).
> >
> > All tests are done with xen command line:
> >
> > dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
> > smt=false vga=text-80x50,keep
> >
> > and kernel command line:
> >
> > loglevel=0 earlyprintk=xen nomodeset
> >
> > this way I can get all xen messages on console.
> >
> > Attached are the frames I captured from a video, I manually selected
> > them starting from the first readable frame.
>
> Okay, so we seem to be hitting two previously noticed issues, neither
> of which so far was necessary to address directly (because there was
> always something else to be tweaked such that the problems went away).
>
> For one, the boot CPU has a TSC value that lags by more than a
> second compared to all secondary CPUs. The way
> time_calibration_tsc_rendezvous() works, together with the way we
> calculate system time from the TSC (get_s_time_fixed() - this is
> where the known issue here is: the function breaks when trying to
> scale a negative delta, hence the absurdly high s= values in the
> screenshots you've provided), allows for small negative deltas
> between CPUs, but expects to bring all CPUs' TSCs forward (i.e. over
> the 1s interval between rendezvous' the lagging CPUs are assumed to
> have made enough progress to be ahead of the more towards the future
> timestamps on the previous run). Secondary lagging behind the boot
> CPU more than this could also be dealt with, but on your system the
> situation is the other way around.
>
> Btw - what kind of BIOS do you have on this system? This way of the
> TSCs being set is pretty odd, and must be - unless you run other
> pre-boot software or an unusual boot loader - caused by the BIOS.
It is a generic mainboard acquired from china... it is very lame! I
was already thinking the big issue is the BIOS. Unfortunately I don't
know how to upgrade it.
> And then this points out (again, afaic at least) that the way we
> kickstart the rendezvous handling is likely inappropriate.
> Especially when TSCs are skewed like they are here, it is unhelpful
> to launch Dom0 before having brought the TSC in sync. (Related to
> this, I also don't think we should arm the respective timer before
> AP bringup was done, or else we risk the first rendezvous instance
> to not hit all CPUs.)
>
> I'll work on addressing both, hoping that in particular for the
> first one you'll be ready to help with testing (through perhaps
> multiple iterations).
I can help you a little more until end of next week. After that I will
move the host to another address and I will not have a quick "hands
on" access to it.
> > As a sidenote, I managed to get the system working with the parameter
> > "tsc=unstable", performance looks satisfactory but I do not know what
> > problems I may end with this parameter.
>
> I _think_ you'd be running into trouble if you removed dom0_vcpus_pin
> (which imo really no-one should use without reporting a bug, despite
> all the hits to the contrary that one gets when searching the web),
> and if you ran any guests (PV at least) without pinning their vCPU-s
> to pCPU-s.
just tested it without the cpu pin, it worked.
I stress-tested both dom0 and a pv guest with the "yes method"
described here:
https://linuxconfig.org/how-to-stress-test-your-cpu-on-linux.
Best regards,
Claudemir
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-28 13:08 ` Claudemir Todo Bom
2021-01-29 14:21 ` Jan Beulich
@ 2021-01-29 16:24 ` Jan Beulich
2021-01-29 19:31 ` Claudemir Todo Bom
1 sibling, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-01-29 16:24 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 28.01.2021 14:08, Claudemir Todo Bom wrote:
> Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
>>
>> On 28.01.2021 10:47, Jan Beulich wrote:
>>> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
>>>> If this information is good for more tests, please send the patch and
>>>> I will test it!
>>>
>>> Here you go. For simplifying analysis it may be helpful if you
>>> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
>>> at least "smt=0". Provided the problem still reproduces with
>>> such options, of course.
>>
>> Speaking of command line options - it doesn't look like you have
>> told us what else you have on the Xen command line, and without
>> a serial log this isn't visible (e.g. in your video).
>
> All tests are done with xen command line:
>
> dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
> smt=false vga=text-80x50,keep
>
> and kernel command line:
>
> loglevel=0 earlyprintk=xen nomodeset
>
> this way I can get all xen messages on console.
>
> Attached are the frames I captured from a video, I manually selected
> them starting from the first readable frame.
I've just sent a pair of patches, with you Cc-ed on the 2nd one.
Please give that one a try, with or without the updated debugging
patch below. In case of problems I'd of course want to see the
output from the debugging patch as well. I think it's up to you
whether you also use the first patch from that series - afaict it
shouldn't directly affect your case, but I may be wrong.
Thanks, Jan
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1558,6 +1558,12 @@ static void local_time_calibration(void)
* TSC Reliability check
*/
+static struct {//temp
+ unsigned cpu;
+ signed iter;
+ cycles_t prev, now;
+} check_log[NR_CPUS + 4];
+static unsigned check_idx;//temp
/*
* The Linux original version of this function is
* Copyright (c) 2006, Red Hat, Inc., Ingo Molnar
@@ -1566,6 +1572,7 @@ static void check_tsc_warp(unsigned long
{
static DEFINE_SPINLOCK(sync_lock);
static cycles_t last_tsc;
+unsigned idx, cpu = smp_processor_id();//temp
cycles_t start, now, prev, end;
int i;
@@ -1576,6 +1583,15 @@ static void check_tsc_warp(unsigned long
end = start + tsc_khz * 20ULL;
now = start;
+{//temp
+ spin_lock(&sync_lock);
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = -1;
+ check_log[idx].now = now;
+ spin_unlock(&sync_lock);
+}
+
for ( i = 0; ; i++ )
{
/*
@@ -1610,7 +1626,14 @@ static void check_tsc_warp(unsigned long
{
spin_lock(&sync_lock);
if ( *max_warp < prev - now )
+{//temp
*max_warp = prev - now;
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = i;
+ check_log[idx].prev = prev;
+ check_log[idx].now = now;
+}
spin_unlock(&sync_lock);
}
}
@@ -1647,6 +1670,12 @@ static void tsc_check_reliability(void)
cpu_relax();
spin_unlock(&lock);
+{//temp
+ unsigned i;
+ printk("CHK[%2u] %lx\n", cpu, tsc_max_warp);//temp
+ for(i = 0; i < ARRAY_SIZE(check_log) && check_log[i].now; ++i)
+ printk("chk[%4u] CPU%-2u %016lx %016lx #%d\n", i, check_log[i].cpu, check_log[i].prev, check_log[i].now, check_log[i].iter);
+}
}
/*
@@ -1661,6 +1690,7 @@ struct calibration_rendezvous {
uint64_t master_tsc_stamp, max_tsc_stamp;
};
+static bool rdzv_log;//temp
static void
time_calibration_rendezvous_tail(const struct calibration_rendezvous *r)
{
@@ -1670,6 +1700,7 @@ time_calibration_rendezvous_tail(const s
c->local_stime = get_s_time_fixed(c->local_tsc);
c->master_stime = r->master_stime;
+if(rdzv_log) printk("RDZV[%2u] t=%016lx(%016lx) s=%012lx(%012lx)\n", smp_processor_id(), c->local_tsc, r->master_tsc_stamp, c->local_stime, r->master_stime);//temp
raise_softirq(TIME_CALIBRATE_SOFTIRQ);
}
@@ -1682,7 +1713,9 @@ static void time_calibration_tsc_rendezv
int i;
struct calibration_rendezvous *r = _r;
unsigned int total_cpus = cpumask_weight(&r->cpu_calibration_map);
+uint64_t adj = 0;//temp
+if(rdzv_log) printk("RDZV[%2u] t=%016lx\n", smp_processor_id(), rdtsc_ordered());//temp
/* Loop to get rid of cache effects on TSC skew. */
for ( i = 4; i >= 0; i-- )
{
@@ -1706,6 +1739,7 @@ static void time_calibration_tsc_rendezv
*/
uint64_t delta = r->max_tsc_stamp - r->master_tsc_stamp;
+adj = delta;//temp
r->master_stime += scale_delta(delta,
&this_cpu(cpu_time).tsc_scale);
r->master_tsc_stamp = r->max_tsc_stamp;
@@ -1747,6 +1781,13 @@ static void time_calibration_tsc_rendezv
}
time_calibration_rendezvous_tail(r);
+if(adj) {//temp
+ static unsigned long cnt, thr;
+ if(++cnt > thr) {
+ thr |= cnt;
+ printk("TSC adjusted by %lx\n", adj);
+ }
+}
}
/* Ordinary rendezvous function which does not modify TSC values. */
@@ -1798,6 +1839,12 @@ static void time_calibration(void *unuse
struct calibration_rendezvous r = {
.semaphore = ATOMIC_INIT(0)
};
+static unsigned long cnt, thr;//temp
+if(system_state > SYS_STATE_smp_boot && ++cnt > thr) {//temp
+ thr |= cnt;
+ printk("TSC: %ps\n", time_calibration_rendezvous_fn);
+ rdzv_log = true;
+}
if ( clocksource_is_tsc() )
{
@@ -1812,6 +1859,10 @@ static void time_calibration(void *unuse
on_selected_cpus(&r.cpu_calibration_map,
time_calibration_rendezvous_fn,
&r, 1);
+if(rdzv_log || system_state <= SYS_STATE_smp_boot) {//temp
+ rdzv_log = false;
+ printk("TSC: end rendezvous\n");
+}
}
static struct cpu_time_stamp ap_bringup_ref;
@@ -1908,6 +1959,7 @@ void init_percpu_time(void)
}
t->stamp.local_tsc = tsc;
t->stamp.local_stime = now;
+printk("INIT[%2u] t=%016lx s=%012lx m=%012lx\n", smp_processor_id(), tsc, now, t->stamp.master_stime);//temp
}
/*
@@ -2050,6 +2102,7 @@ static int __init verify_tsc_reliability
* While with constant-rate TSCs the scale factor can be shared, when TSCs
* are not marked as 'reliable', re-sync during rendezvous.
*/
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
!boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
@@ -2065,6 +2118,7 @@ int __init init_xen_time(void)
{
tsc_check_writability();
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
/* NB. get_wallclock_time() can take over one second to execute. */
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-29 16:24 ` Jan Beulich
@ 2021-01-29 19:31 ` Claudemir Todo Bom
2021-02-01 7:51 ` Jan Beulich
2021-02-01 12:47 ` Jan Beulich
0 siblings, 2 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-29 19:31 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel
[-- Attachment #1: Type: text/plain, Size: 2975 bytes --]
Em sex., 29 de jan. de 2021 às 13:24, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 28.01.2021 14:08, Claudemir Todo Bom wrote:
> > Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
> >>
> >> On 28.01.2021 10:47, Jan Beulich wrote:
> >>> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
> >>>> If this information is good for more tests, please send the patch and
> >>>> I will test it!
> >>>
> >>> Here you go. For simplifying analysis it may be helpful if you
> >>> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
> >>> at least "smt=0". Provided the problem still reproduces with
> >>> such options, of course.
> >>
> >> Speaking of command line options - it doesn't look like you have
> >> told us what else you have on the Xen command line, and without
> >> a serial log this isn't visible (e.g. in your video).
> >
> > All tests are done with xen command line:
> >
> > dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
> > smt=false vga=text-80x50,keep
> >
> > and kernel command line:
> >
> > loglevel=0 earlyprintk=xen nomodeset
> >
> > this way I can get all xen messages on console.
> >
> > Attached are the frames I captured from a video, I manually selected
> > them starting from the first readable frame.
>
> I've just sent a pair of patches, with you Cc-ed on the 2nd one.
> Please give that one a try, with or without the updated debugging
> patch below. In case of problems I'd of course want to see the
> output from the debugging patch as well. I think it's up to you
> whether you also use the first patch from that series - afaict it
> shouldn't directly affect your case, but I may be wrong.
I've applied both patches, system didn't booted, used following parameters:
xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
kernel: loglevel=3
The screen cleared right after the initial xen messages and frozen
there for a few minutes until I restarted the system.
I've added "vga=text-80x25,keep" to the xen command line and
"nomodeset" to the kernel command line, hoping to get some more info
and surprisingly this was sufficient to make system boot!
System prompt took a lot to appear, the kernel driver for the usb
keyboard loaded after 3 minutes and the driver for the usb wifi dongle
I am using loaded about five minutes after kernel boot, and I had to
issue "ifup -a" to get an ip address from the dhcp server, and it took
almost one minute to get it!
Also, the system became very sensible for the keyboard, a lot of
double-typing happening with it, console beeps keeps sounding longer
also.
Then with the debug patch, since it booted I was able to get the "xl
dmesg" output with all the debug messages, it is attached. I'm also
attaching the dmesg output also, but I do not know if it is useful in
any form. Kernel started to boot at stamp ~20 of the xen hypervisor.
Hope all of this helps!
[-- Attachment #2: xen-dmesg.txt --]
[-- Type: text/plain, Size: 45053 bytes --]
(XEN) parameter "placeholder" unknown!
(XEN) [ 0.000000] Xen version 4.11.4 (Debian 4.11.4+57-g41a822c392-2) (pkg-xen-devel@lists.alioth.debian.org) (gcc (Debian 8.3.0-6) 8.3.0) debug=n Fri Jan 29 14:15:17 -03 2021
(XEN) [ 0.000000] Bootloader: GRUB 2.04-12
(XEN) [ 0.000000] Command line: placeholder dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true vga=text-80x25,keep console_timestamps=boot
(XEN) [ 0.000000] Xen image load base address: 0xba200000
(XEN) [ 0.000000] Video information:
(XEN) [ 0.000000] VGA is text mode 80x25, font 8x16
(XEN) [ 0.000000] VBE/DDC methods: none; EDID transfer time: 0 seconds
(XEN) [ 0.000000] EDID info not retrieved because no DDC retrieval method detected
(XEN) [ 0.000000] Disc information:
(XEN) [ 0.000000] Found 1 MBR signatures
(XEN) [ 0.000000] Found 2 EDD information structures
(XEN) [ 0.000000] Xen-e820 RAM map:
(XEN) [ 0.000000] 0000000000000000 - 000000000009e800 (usable)
(XEN) [ 0.000000] 000000000009e800 - 00000000000a0000 (reserved)
(XEN) [ 0.000000] 00000000000e0000 - 0000000000100000 (reserved)
(XEN) [ 0.000000] 0000000000100000 - 00000000ba952000 (usable)
(XEN) [ 0.000000] 00000000ba952000 - 00000000ba98b000 (reserved)
(XEN) [ 0.000000] 00000000ba98b000 - 00000000babc3000 (usable)
(XEN) [ 0.000000] 00000000babc3000 - 00000000bb1c0000 (ACPI NVS)
(XEN) [ 0.000000] 00000000bb1c0000 - 00000000bb843000 (reserved)
(XEN) [ 0.000000] 00000000bb843000 - 00000000bb844000 (usable)
(XEN) [ 0.000000] 00000000bb844000 - 00000000bb8ca000 (ACPI NVS)
(XEN) [ 0.000000] 00000000bb8ca000 - 00000000bbd0f000 (usable)
(XEN) [ 0.000000] 00000000bbd0f000 - 00000000bbff4000 (reserved)
(XEN) [ 0.000000] 00000000bbff4000 - 00000000bc000000 (usable)
(XEN) [ 0.000000] 00000000d0000000 - 00000000e0000000 (reserved)
(XEN) [ 0.000000] 00000000fed1c000 - 00000000fed20000 (reserved)
(XEN) [ 0.000000] 00000000ff000000 - 0000000100000000 (reserved)
(XEN) [ 0.000000] 0000000100000000 - 0000000440000000 (usable)
(XEN) [ 0.000000] ACPI: RSDP 000F04A0, 0024 (r2 ALASKA)
(XEN) [ 0.000000] ACPI: XSDT BB0DD070, 005C (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: FACP BB0E5728, 010C (r5 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: DSDT BB0DD160, 85C7 (r2 ALASKA A M I 20 INTL 20051117)
(XEN) [ 0.000000] ACPI: FACS BB1B7F80, 0040
(XEN) [ 0.000000] ACPI: APIC BB0E5838, 01A8 (r3 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: FPDT BB0E59E0, 0044 (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: MCFG BB0E5A28, 003C (r1 ALASKA OEMMCFG. 1072009 MSFT 97)
(XEN) [ 0.000000] ACPI: HPET BB0E5A68, 0038 (r1 ALASKA A M I 1072009 AMI. 5)
(XEN) [ 0.000000] ACPI: SSDT BB0E5AA0, CD380 (r2 INTEL CpuPm 4000 INTL 20051117)
(XEN) [ 0.000000] ACPI: DMAR BB1B2E20, 00EC (r1 A M I OEMDMAR 1 INTL 1)
(XEN) [ 0.000000] System RAM: 16303MB (16694760kB)
(XEN) [ 0.000000] Domain heap initialised
(XEN) [ 0.000000] ACPI: 32/64X FACS address mismatch in FADT - bb1b7f80/0000000000000000, using 32
(XEN) [ 0.000000] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
(XEN) [ 0.000000] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
(XEN) [ 0.000000] Enabling APIC mode: Phys. Using 2 I/O APICs
(XEN) [ 0.000000] Switched to APIC driver x2apic_cluster
(XEN) [ 0.000000] xstate: size: 0x340 and states: 0x7
(XEN) [ 0.000000] Speculative mitigation facilities:
(XEN) [ 0.000000] Hardware features:
(XEN) [ 0.000000] Compiled-in support: INDIRECT_THUNK SHADOW_PAGING
(XEN) [ 0.000000] Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: No, Other:
(XEN) [ 0.000000] L1TF: believed vulnerable, maxphysaddr L1D 46, CPUID 46, Safe address 300000000000
(XEN) [ 0.000000] Support for VMs: PV: RSB EAGER_FPU, HVM: RSB EAGER_FPU
(XEN) [ 0.000000] XPTI (64-bit PV only): Dom0 enabled, DomU enabled
(XEN) [ 0.000000] PV L1TF shadowing: Dom0 disabled, DomU enabled
(XEN) [ 0.000000] Using scheduler: SMP Credit Scheduler (credit)
(XEN) [ 0.000000] Platform timer is 14.318MHz HPET
(XEN) [ 0.460437] Detected 2494.346 MHz processor.
(XEN) [ 0.464468] Initing memory sharing.
(XEN) [ 0.467279] Intel VT-d iommu 0 supported page sizes: 4kB, 2MB, 1GB.
(XEN) [ 0.468679] Intel VT-d Snoop Control enabled.
(XEN) [ 0.470072] Intel VT-d Dom0 DMA Passthrough not enabled.
(XEN) [ 0.471461] Intel VT-d Queued Invalidation enabled.
(XEN) [ 0.472848] Intel VT-d Interrupt Remapping enabled.
(XEN) [ 0.474237] Intel VT-d Posted Interrupt not enabled.
(XEN) [ 0.475745] Intel VT-d Shared EPT tables enabled.
(XEN) [ 0.488349] I/O virtualisation enabled
(XEN) [ 0.489753] - Dom0 mode: Relaxed
(XEN) [ 0.491253] Interrupt remapping enabled
(XEN) [ 0.492657] Enabled directed EOI with ioapic_ack_old on!
(XEN) [ 0.494993] ENABLING IO-APIC IRQs
(XEN) [ 0.496375] -> Using old ACK method
(XEN) [ 0.699046] TSC: c=1 r=1
(XEN) [ 1.275072] INIT[ 0] t=00000032c82a01ac s=00004c0006e9 m=00004c000886
(XEN) [ 1.276594] Allocated console ring of 64 KiB.
(XEN) [ 1.277994] VMX: Supported advanced features:
(XEN) [ 1.279383] - APIC MMIO access virtualisation
(XEN) [ 1.280771] - APIC TPR shadow
(XEN) [ 1.282151] - Extended Page Tables (EPT)
(XEN) [ 1.283539] - Virtual-Processor Identifiers (VPID)
(XEN) [ 1.284927] - Virtual NMI
(XEN) [ 1.286303] - MSR direct-access bitmap
(XEN) [ 1.287690] - Unrestricted Guest
(XEN) [ 1.289073] - APIC Register Virtualization
(XEN) [ 1.290459] - Virtual Interrupt Delivery
(XEN) [ 1.291959] - Posted Interrupt Processing
(XEN) [ 1.293352] HVM: ASIDs enabled.
(XEN) [ 1.294737] VMX: Disabling executable EPT superpages due to CVE-2018-12207
(XEN) [ 1.297506] HVM: VMX enabled
(XEN) [ 1.298886] HVM: Hardware Assisted Paging (HAP) detected
(XEN) [ 1.300273] HVM: HAP page sizes: 4kB, 2MB, 1GB
(XEN) [ 1.301803] INIT[ 1] t=00000033963e53c9 s=00004d97e715 m=00004d97e955
(XEN) [ 1.303397] INIT[ 2] t=00000033967af744 s=00004db036ca m=00004db038d9
(XEN) [ 1.304956] INIT[ 3] t=0000003396b65834 s=00004dc8050e m=00004dc8070b
(XEN) [ 1.306506] INIT[ 4] t=0000003396f14d08 s=00004ddfa7bb m=00004ddfa9dd
(XEN) [ 1.308178] INIT[ 5] t=000000339730fb9c s=00004df92f96 m=00004df931c1
(XEN) [ 1.309730] INIT[ 6] t=00000033976bfe40 s=00004e10d7de m=00004e10da08
(XEN) [ 1.311295] INIT[ 7] t=0000003397a79af4 s=00004e28bdd0 m=00004e28c03c
(XEN) [ 1.312866] INIT[ 8] t=0000003397e35a79 s=00004e40b222 m=00004e40b45b
(XEN) [ 1.314436] INIT[ 9] t=00000033981f2211 s=00004e58a94e m=00004e58abbf
(XEN) [ 1.316008] INIT[10] t=00000033985af070 s=00004e70a383 m=00004e70a5de
(XEN) [ 1.317584] INIT[11] t=000000339896f4a8 s=00004e88b335 m=00004e88b58b
(XEN) [ 1.319160] INIT[12] t=0000003398d2e37c s=00004ea0ba23 m=00004ea0bc7c
(XEN) [ 1.320736] INIT[13] t=00000033990ee854 s=00004eb8ca0c m=00004eb8cc6f
(XEN) [ 1.322317] INIT[14] t=00000033994b0f4b s=00004ed0e79f m=00004ed0ea05
(XEN) [ 1.323977] INIT[15] t=00000033998a498b s=00004eea40c7 m=00004eea4342
(XEN) [ 1.325553] INIT[16] t=0000003399c63617 s=00004f0246e5 m=00004f024962
(XEN) [ 1.327127] INIT[17] t=000000339a023027 s=00004f1a524e m=00004f1a54f7
(XEN) [ 1.328698] INIT[18] t=000000339a3df050 s=00004f3246cf m=00004f32495b
(XEN) [ 1.330270] INIT[19] t=000000339a79c9cc s=00004f4a4511 m=00004f4a47d8
(XEN) [ 1.331845] INIT[20] t=000000339ab5b11f s=00004f624916 m=00004f624bc9
(XEN) [ 1.333420] INIT[21] t=000000339af1b363 s=00004f7a57ee m=00004f7a5aa4
(XEN) [ 1.334994] INIT[22] t=000000339b2d8ee4 s=00004f925720 m=00004f9259f2
(XEN) [ 1.336574] INIT[23] t=000000339b69bb6c s=00004faa76ea m=00004faa79b7
(XEN) [ 1.337993] Brought up 24 CPUs
(XEN) [ 1.394884] CHK[ 0] ca1aeea9
(XEN) [ 1.396261] chk[ 0] CPU0 0000000000000000 00000032d6ffcd9c #-1
(XEN) [ 1.397657] chk[ 1] CPU1 0000000000000000 00000033a11abde5 #-1
(XEN) [ 1.399055] chk[ 2] CPU11 0000000000000000 00000033a11abe92 #-1
(XEN) [ 1.400446] chk[ 3] CPU8 0000000000000000 00000033a11abec7 #-1
(XEN) [ 1.401845] chk[ 4] CPU9 0000000000000000 00000033a11abed3 #-1
(XEN) [ 1.403242] chk[ 5] CPU4 0000000000000000 00000033a11abee1 #-1
(XEN) [ 1.404641] chk[ 6] CPU5 0000000000000000 00000033a11abeed #-1
(XEN) [ 1.406142] chk[ 7] CPU12 0000000000000000 00000033a11abfd0 #-1
(XEN) [ 1.407540] chk[ 8] CPU7 0000000000000000 00000033a11abfe0 #-1
(XEN) [ 1.408937] chk[ 9] CPU6 0000000000000000 00000033a11abfe8 #-1
(XEN) [ 1.410337] chk[ 10] CPU15 0000000000000000 00000033a11abea6 #-1
(XEN) [ 1.411737] chk[ 11] CPU20 0000000000000000 00000033a11ac00b #-1
(XEN) [ 1.413133] chk[ 12] CPU10 0000000000000000 00000033a11abe9a #-1
(XEN) [ 1.414525] chk[ 13] CPU22 0000000000000000 00000033a11abeb4 #-1
(XEN) [ 1.415923] chk[ 14] CPU23 0000000000000000 00000033a11abeac #-1
(XEN) [ 1.417319] chk[ 15] CPU13 0000000000000000 00000033a11abfc8 #-1
(XEN) [ 1.418715] chk[ 16] CPU14 0000000000000000 00000033a11abe9a #-1
(XEN) [ 1.420114] chk[ 17] CPU18 0000000000000000 00000033a11ac144 #-1
(XEN) [ 1.421628] chk[ 18] CPU2 0000000000000000 00000033a11abecc #-1
(XEN) [ 1.423026] chk[ 19] CPU3 0000000000000000 00000033a11abec0 #-1
(XEN) [ 1.424425] chk[ 20] CPU19 0000000000000000 00000033a11ac14c #-1
(XEN) [ 1.425822] chk[ 21] CPU16 0000000000000000 00000033a11ac16f #-1
(XEN) [ 1.427219] chk[ 22] CPU17 0000000000000000 00000033a11ac163 #-1
(XEN) [ 1.428613] chk[ 23] CPU21 0000000000000000 00000033a11ac003 #-1
(XEN) [ 1.430010] chk[ 24] CPU0 00000033a11af051 00000032d7001158 #1
(XEN) [ 1.431403] chk[ 25] CPU0 00000033a11b654b 00000032d70078ac #2
(XEN) [ 1.432802] chk[ 26] CPU0 00000033a11bc677 00000032d700d938 #3
(XEN) [ 1.434199] chk[ 27] CPU0 00000033a11c2763 00000032d7013a00 #4
(XEN) [ 1.435595] chk[ 28] CPU0 00000033a11db4bb 00000032d702c730 #8
(XEN) [ 1.437110] chk[ 29] CPU0 00000033a11ed703 00000032d703e910 #11
(XEN) [ 1.438507] chk[ 30] CPU0 00000033a41424bd 00000032d9f93628 #1998
(XEN) [ 1.439908] chk[ 31] CPU0 00000033a4146739 00000032d9f97890 #1999
(XEN) [ 1.441307] TSC warp detected, disabling TSC_RELIABLE
(XEN) [ 1.442695] TSC: c=1 r=0
(XEN) [ 2.803501] TSC adjusted by ca1afd83
(XEN) [ 2.804886] TSC: end rendezvous
(XEN) [ 2.806270] mtrr: your CPUs had inconsistent fixed MTRR settings
(XEN) [ 2.807692] Dom0 has maximum 816 PIRQs
(XEN) [ 3.517504] Xen kernel: 64-bit, lsb, compat32
(XEN) [ 3.518894] Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x2c2c000
(XEN) [ 3.522084] PHYSICAL MEMORY ARRANGEMENT:
(XEN) [ 3.523470] Dom0 alloc.: 0000000428000000->000000042c000000 (237067 pages to be allocated)
(XEN) [ 3.526244] Init. ramdisk: 000000043de0b000->000000043ffff664
(XEN) [ 3.527638] VIRTUAL MEMORY ARRANGEMENT:
(XEN) [ 3.529019] Loaded kernel: ffffffff81000000->ffffffff82c2c000
(XEN) [ 3.530418] Init. ramdisk: 0000000000000000->0000000000000000
(XEN) [ 3.531814] Phys-Mach map: 0000008000000000->0000008000200000
(XEN) [ 3.533328] Start info: ffffffff82c2c000->ffffffff82c2c4b8
(XEN) [ 3.534723] Xenstore ring: 0000000000000000->0000000000000000
(XEN) [ 3.536118] Console ring: 0000000000000000->0000000000000000
(XEN) [ 3.537516] Page tables: ffffffff82c2d000->ffffffff82c48000
(XEN) [ 3.538912] Boot stack: ffffffff82c48000->ffffffff82c49000
(XEN) [ 3.540307] TOTAL: ffffffff80000000->ffffffff83000000
(XEN) [ 3.541706] ENTRY ADDRESS: ffffffff8282a160
(XEN) [ 3.543910] Dom0 has maximum 4 VCPUs
(XEN) [ 3.877522] TSC adjusted by 7cc
(XEN) [ 3.878904] TSC: end rendezvous
(XEN) [ 4.281401] Initial low memory virq threshold set at 0x4000 pages.
(XEN) [ 4.282802] Scrubbing Free RAM on 1 nodes using 12 CPUs
(XEN) [ 4.365826] .........TSC: end rendezvous
(XEN) [ 5.009066] ...done.
(XEN) [ 5.113023] Std. Loglevel: Errors and warnings
(XEN) [ 5.114410] Guest Loglevel: Nothing (Rate-limited: Errors and warnings)
(XEN) [ 5.115811] Xen is keeping VGA console.
(XEN) [ 5.136858] *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen)
(XEN) [ 5.139785] Freed 476kB init memory
(XEN) [ 5.933093] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 5.934487] RDZV[ 0] t=000000357ce69d0d
(XEN) [ 4.576490] RDZV[ 1] t=000000357ce6a225
(XEN) [ 4.577959] RDZV[ 2] t=000000357ce7b201
(XEN) [ 4.579344] RDZV[ 3] t=000000357ce7b225
(XEN) [ 4.580730] RDZV[ 4] t=000000357ce7ba5c
(XEN) [ 4.582114] RDZV[ 5] t=000000357ce7b8b4
(XEN) [ 4.583503] RDZV[ 7] t=000000357ce7c57d
(XEN) [ 4.584891] RDZV[ 6] t=000000357ce7c56d
(XEN) [ 4.586282] RDZV[ 8] t=000000357ce7d2a8
(XEN) [ 4.587670] RDZV[ 9] t=000000357ce7d2f8
(XEN) [ 4.589062] RDZV[10] t=000000357ce7de71
(XEN) [ 4.590451] RDZV[11] t=000000357ce7de51
(XEN) [ 4.591838] RDZV[13] t=000000357ce7e7e9
(XEN) [ 4.593304] RDZV[12] t=000000357ce7e7d9
(XEN) [ 4.594695] RDZV[15] t=000000357ce7f24d
(XEN) [ 4.596084] RDZV[14] t=000000357ce7f23d
(XEN) [ 4.597470] RDZV[17] t=000000357ce7f9be
(XEN) [ 4.598856] RDZV[16] t=000000357ce7f9be
(XEN) [ 4.600243] RDZV[18] t=000000357ce8031e
(XEN) [ 4.601631] RDZV[19] t=000000357ce8031a
(XEN) [ 4.603017] RDZV[21] t=000000357ce80c9e
(XEN) [ 4.604399] RDZV[20] t=000000357ce80cae
(XEN) [ 4.605786] RDZV[22] t=000000357ce81736
(XEN) [ 4.607164] RDZV[23] t=000000357ce8174a
(XEN) [ 5.967933] RDZV[ 0] t=0000003581df9112(0000003581df82f2) s=000163b7655c(000112b1dd79)
(XEN) [ 4.611408] RDZV[ 1] t=0000003581df952e(0000003581df82f2) s=000112b0eab2(000112b1dd79)
(XEN) [ 4.614181] RDZV[15] t=0000003581df94fa(0000003581df82f2) s=000112b0eaea(000112b1dd79)
(XEN) [ 4.616959] RDZV[14] t=0000003581df94e6(0000003581df82f2) s=000112b0eae7(000112b1dd79)
(XEN) [ 4.619735] RDZV[21] t=0000003581df94ea(0000003581df82f2) s=000112b0eaaf(000112b1dd79)
(XEN) [ 4.622504] RDZV[ 7] t=0000003581df92fe(0000003581df82f2) s=000112b0e9d2(000112b1dd79)
(XEN) [ 4.625377] RDZV[ 6] t=0000003581df949a(0000003581df82f2) s=000112b0eaa4(000112b1dd79)
(XEN) [ 4.628154] RDZV[ 3] t=0000003581df959a(0000003581df82f2) s=000112b0eb35(000112b1dd79)
(XEN) [ 4.630924] RDZV[23] t=0000003581df9586(0000003581df82f2) s=000112b0ead6(000112b1dd79)
(XEN) [ 4.633693] RDZV[19] t=0000003581df9542(0000003581df82f2) s=000112b0ead3(000112b1dd79)
(XEN) [ 4.636460] RDZV[18] t=0000003581df9552(0000003581df82f2) s=000112b0eb14(000112b1dd79)
(XEN) [ 4.639238] RDZV[11] t=0000003581df954e(0000003581df82f2) s=000112b0eb1b(000112b1dd79)
(XEN) [ 4.642117] RDZV[10] t=0000003581df954a(0000003581df82f2) s=000112b0eb05(000112b1dd79)
(XEN) [ 4.644895] RDZV[13] t=0000003581df9426(0000003581df82f2) s=000112b0ea92(000112b1dd79)
(XEN) [ 4.647670] RDZV[12] t=0000003581df90c2(0000003581df82f2) s=000112b0e92c(000112b1dd79)
(XEN) [ 4.650443] RDZV[ 8] t=0000003581df9546(0000003581df82f2) s=000112b0eafd(000112b1dd79)
(XEN) [ 4.653219] RDZV[ 9] t=0000003581df955e(0000003581df82f2) s=000112b0eae1(000112b1dd79)
(XEN) [ 4.655997] RDZV[16] t=0000003581df9502(0000003581df82f2) s=000112b0eaea(000112b1dd79)
(XEN) [ 4.658872] RDZV[17] t=0000003581df94f2(0000003581df82f2) s=000112b0eac1(000112b1dd79)
(XEN) [ 4.661646] RDZV[20] t=0000003581df94ea(0000003581df82f2) s=000112b0eaab(000112b1dd79)
(XEN) [ 4.664410] RDZV[ 4] t=0000003581df957e(0000003581df82f2) s=000112b0eb06(000112b1dd79)
(XEN) [ 4.667188] RDZV[ 2] t=0000003581df959a(0000003581df82f2) s=000112b0eb1a(000112b1dd79)
(XEN) [ 4.669959] RDZV[22] t=0000003581df958a(0000003581df82f2) s=000112b0ead4(000112b1dd79)
(XEN) [ 4.672729] RDZV[ 5] t=0000003581df956a(0000003581df82f2) s=000112b0eb0a(000112b1dd79)
(XEN) [ 6.034998] TSC adjusted by 3d9
(XEN) [ 6.036379] TSC: end rendezvous
(XEN) [ 7.037767] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 7.039162] RDZV[ 0] t=0000003621235626
(XEN) [ 5.681168] RDZV[ 1] t=00000036212355a6
(XEN) [ 5.682555] RDZV[ 2] t=00000036212472e9
(XEN) [ 5.683941] RDZV[ 3] t=0000003621247305
(XEN) [ 5.685330] RDZV[ 5] t=000000362124787d
(XEN) [ 5.686716] RDZV[ 4] t=0000003621247889
(XEN) [ 5.688105] RDZV[ 7] t=0000003621248126
(XEN) [ 5.689489] RDZV[ 6] t=00000036212482ae
(XEN) [ 5.690874] RDZV[ 8] t=00000036212490c9
(XEN) [ 5.692264] RDZV[ 9] t=00000036212490cd
(XEN) [ 5.693655] RDZV[11] t=0000003621249c95
(XEN) [ 5.695043] RDZV[10] t=0000003621249c95
(XEN) [ 5.696429] RDZV[13] t=000000362124a4ad
(XEN) [ 5.697817] RDZV[12] t=000000362124a159
(XEN) [ 5.699206] RDZV[14] t=000000362124afbd
(XEN) [ 5.700594] RDZV[15] t=000000362124afc1
(XEN) [ 5.701982] RDZV[17] t=000000362124b787
(XEN) [ 5.703368] RDZV[16] t=000000362124b797
(XEN) [ 5.704751] RDZV[18] t=000000362124c219
(XEN) [ 5.706136] RDZV[19] t=000000362124c209
(XEN) [ 5.707523] RDZV[20] t=000000362124c9f5
(XEN) [ 5.708910] RDZV[21] t=000000362124c9f1
(XEN) [ 5.710298] RDZV[23] t=000000362124d618
(XEN) [ 5.711679] RDZV[22] t=000000362124d62c
(XEN) [ 5.713069] RDZV[ 5] t=0000003626163091(0000003626161f55) s=0001548679db(00015487bd84)
(XEN) [ 5.715850] RDZV[ 9] t=00000036261630e5(0000003626161f55) s=0001548679d9(00015487bd84)
(XEN) [ 5.718621] RDZV[ 8] t=00000036261630b9(0000003626161f55) s=0001548679ed(00015487bd84)
(XEN) [ 5.721395] RDZV[12] t=00000036261630f9(0000003626161f55) s=000154867a05(00015487bd84)
(XEN) [ 5.724173] RDZV[13] t=00000036261630f5(0000003626161f55) s=000154867a0d(00015487bd84)
(XEN) [ 5.726950] RDZV[ 4] t=0000003626163071(0000003626161f55) s=0001548679c2(00015487bd84)
(XEN) [ 5.729728] RDZV[20] t=0000003626163181(0000003626161f55) s=000154867a10(00015487bd84)
(XEN) [ 5.732496] RDZV[11] t=0000003626163155(0000003626161f55) s=000154867a46(00015487bd84)
(XEN) [ 5.735271] RDZV[ 7] t=0000003626162fb9(0000003626161f55) s=000154867945(00015487bd84)
(XEN) [ 5.738048] RDZV[ 6] t=00000036261631b5(0000003626161f55) s=000154867a3e(00015487bd84)
(XEN) [ 5.740825] RDZV[21] t=0000003626163185(0000003626161f55) s=000154867a15(00015487bd84)
(XEN) [ 5.743595] RDZV[14] t=0000003626163129(0000003626161f55) s=000154867a2a(00015487bd84)
(XEN) [ 5.746369] RDZV[15] t=0000003626163119(0000003626161f55) s=000154867a1f(00015487bd84)
(XEN) [ 5.749143] RDZV[23] t=0000003626163135(0000003626161f55) s=0001548679de(00015487bd84)
(XEN) [ 5.751914] RDZV[10] t=0000003626163151(0000003626161f55) s=000154867a30(00015487bd84)
(XEN) [ 5.754691] RDZV[16] t=00000036261630fd(0000003626161f55) s=000154867a10(00015487bd84)
(XEN) [ 5.757467] RDZV[17] t=0000003626163105(0000003626161f55) s=0001548679f1(00015487bd84)
(XEN) [ 5.760237] RDZV[18] t=000000362616310d(0000003626161f55) s=000154867a20(00015487bd84)
(XEN) [ 5.763005] RDZV[19] t=0000003626163091(0000003626161f55) s=0001548679b4(00015487bd84)
(XEN) [ 5.765779] RDZV[ 2] t=000000362616311d(0000003626161f55) s=000154867a10(00015487bd84)
(XEN) [ 5.768553] RDZV[22] t=0000003626162e75(0000003626161f55) s=0001548678c0(00015487bd84)
(XEN) [ 5.771324] RDZV[ 3] t=00000036261630d5(0000003626161f55) s=000154867a0e(00015487bd84)
(XEN) [ 5.774094] RDZV[ 1] t=0000003626163079(0000003626161f55) s=000154867992(00015487bd84)
(XEN) [ 7.136241] RDZV[ 0] t=000000362616300d(0000003626161f55) s=0001a58cf5b6(00015487bd84)
(XEN) [ 7.139010] TSC: end rendezvous
(XEN) [ 9.140447] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 9.141843] RDZV[ 0] t=0000003759c0d1c4
(XEN) [ 7.783850] RDZV[ 3] t=0000003759c0d012
(XEN) [ 7.785230] RDZV[ 2] t=0000003759c0d35a
(XEN) [ 7.786615] RDZV[ 1] t=0000003759c0e630
(XEN) [ 7.788003] RDZV[ 5] t=0000003759c1b797
(XEN) [ 7.789390] RDZV[ 4] t=0000003759c1b777
(XEN) [ 7.790777] RDZV[ 7] t=0000003759c1c21f
(XEN) [ 7.792164] RDZV[ 6] t=0000003759c1c1e7
(XEN) [ 7.793553] RDZV[ 9] t=0000003759c1cf0f
(XEN) [ 7.794941] RDZV[ 8] t=0000003759c1cf0f
(XEN) [ 7.796328] RDZV[11] t=0000003759c1d806
(XEN) [ 7.797715] RDZV[10] t=0000003759c1d7f6
(XEN) [ 7.799102] RDZV[13] t=0000003759c26e78
(XEN) [ 7.800484] RDZV[12] t=0000003759c26c30
(XEN) [ 7.801875] RDZV[14] t=0000003759c278f1
(XEN) [ 7.803263] RDZV[15] t=0000003759c278ed
(XEN) [ 7.804651] RDZV[17] t=0000003759c27ef1
(XEN) [ 7.806036] RDZV[16] t=0000003759c280ad
(XEN) [ 7.807425] RDZV[19] t=0000003759c28a3f
(XEN) [ 7.808810] RDZV[18] t=0000003759c289db
(XEN) [ 7.810195] RDZV[20] t=0000003759c2962c
(XEN) [ 7.811578] RDZV[21] t=0000003759c29628
(XEN) [ 7.812966] RDZV[23] t=0000003759c2a148
(XEN) [ 7.814345] RDZV[22] t=0000003759c2a158
(XEN) [ 7.815732] RDZV[ 1] t=000000375eb30734(000000375eb2f718) s=0001d1da921c(0001d1dc7870)
(XEN) [ 9.177882] RDZV[ 0] t=000000375eb30668(000000375eb2f718) s=000222e10e1a(0001d1dc7870)
(XEN) [ 7.821275] RDZV[16] t=000000375eb307bc(000000375eb2f718) s=0001d1da929b(0001d1dc7870)
(XEN) [ 7.824052] RDZV[17] t=000000375eb307d0(000000375eb2f718) s=0001d1da9282(0001d1dc7870)
(XEN) [ 7.826825] RDZV[ 4] t=000000375eb30720(000000375eb2f718) s=0001d1da9248(0001d1dc7870)
(XEN) [ 7.829596] RDZV[15] t=000000375eb3064c(000000375eb2f718) s=0001d1da920c(0001d1dc7870)
(XEN) [ 7.832372] RDZV[14] t=000000375eb30650(000000375eb2f718) s=0001d1da9212(0001d1dc7870)
(XEN) [ 7.835150] RDZV[20] t=000000375eb307d4(000000375eb2f718) s=0001d1da9271(0001d1dc7870)
(XEN) [ 7.837924] RDZV[10] t=000000375eb307e0(000000375eb2f718) s=0001d1da92a8(0001d1dc7870)
(XEN) [ 7.840700] RDZV[11] t=000000375eb307e0(000000375eb2f718) s=0001d1da92bd(0001d1dc7870)
(XEN) [ 7.843468] RDZV[ 5] t=000000375eb30760(000000375eb2f718) s=0001d1da926d(0001d1dc7870)
(XEN) [ 7.846244] RDZV[ 6] t=000000375eb3073c(000000375eb2f718) s=0001d1da924d(0001d1dc7870)
(XEN) [ 7.849022] RDZV[ 7] t=000000375eb306d0(000000375eb2f718) s=0001d1da91f5(0001d1dc7870)
(XEN) [ 7.851798] RDZV[ 9] t=000000375eb307f0(000000375eb2f718) s=0001d1da9283(0001d1dc7870)
(XEN) [ 7.854576] RDZV[ 8] t=000000375eb30804(000000375eb2f718) s=0001d1da92b1(0001d1dc7870)
(XEN) [ 7.857348] RDZV[ 3] t=000000375eb307dc(000000375eb2f718) s=0001d1da92b6(0001d1dc7870)
(XEN) [ 7.860122] RDZV[18] t=000000375eb30714(000000375eb2f718) s=0001d1da9262(0001d1dc7870)
(XEN) [ 7.862895] RDZV[19] t=000000375eb30714(000000375eb2f718) s=0001d1da9228(0001d1dc7870)
(XEN) [ 7.865670] RDZV[12] t=000000375eb307d8(000000375eb2f718) s=0001d1da929e(0001d1dc7870)
(XEN) [ 7.868444] RDZV[13] t=000000375eb30688(000000375eb2f718) s=0001d1da9220(0001d1dc7870)
(XEN) [ 7.871214] RDZV[22] t=000000375eb306f4(000000375eb2f718) s=0001d1da9200(0001d1dc7870)
(XEN) [ 7.873988] RDZV[21] t=000000375eb30808(000000375eb2f718) s=0001d1da9289(0001d1dc7870)
(XEN) [ 7.876761] RDZV[23] t=000000375eb30708(000000375eb2f718) s=0001d1da920b(0001d1dc7870)
(XEN) [ 7.879534] RDZV[ 2] t=000000375eb30694(000000375eb2f718) s=0001d1da9218(0001d1dc7870)
(XEN) [ 9.241686] TSC: end rendezvous
(XEN) [ 10.243119] TSC adjusted by 290
(XEN) [ 13.244616] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 13.246011] RDZV[ 0] t=00000039bbf057cc
(XEN) [ 11.888018] RDZV[ 2] t=00000039bbf05558
(XEN) [ 11.889403] RDZV[ 3] t=00000039bbf05a7c
(XEN) [ 11.890786] RDZV[ 1] t=00000039bbf05fc8
(XEN) [ 11.892172] RDZV[ 4] t=00000039bbf15f21
(XEN) [ 11.893558] RDZV[ 5] t=00000039bbf15e81
(XEN) [ 11.894950] RDZV[ 7] t=00000039bbf1679a
(XEN) [ 11.896335] RDZV[ 6] t=00000039bbf1678a
(XEN) [ 11.897727] RDZV[ 9] t=00000039bbf17615
(XEN) [ 11.899118] RDZV[ 8] t=00000039bbf17611
(XEN) [ 11.900507] RDZV[11] t=00000039bbf17ebd
(XEN) [ 11.901899] RDZV[10] t=00000039bbf17ec5
(XEN) [ 11.903290] RDZV[13] t=00000039bbf189bd
(XEN) [ 11.904673] RDZV[12] t=00000039bbf18b7d
(XEN) [ 11.906060] RDZV[15] t=00000039bbf19414
(XEN) [ 11.907447] RDZV[14] t=00000039bbf19410
(XEN) [ 11.908837] RDZV[17] t=00000039bbf19f8c
(XEN) [ 11.910223] RDZV[16] t=00000039bbf19f9c
(XEN) [ 11.911609] RDZV[18] t=00000039bbf1a711
(XEN) [ 11.912997] RDZV[19] t=00000039bbf1a6f9
(XEN) [ 11.914384] RDZV[21] t=00000039bbf1afb5
(XEN) [ 11.915769] RDZV[20] t=00000039bbf1aef5
(XEN) [ 11.917157] RDZV[22] t=00000039bbf1ba35
(XEN) [ 11.918539] RDZV[23] t=00000039bbf1bb01
(XEN) [ 11.919927] RDZV[ 1] t=00000039c0e3906e(00000039c0e381ca) s=0002c67b9dad(0002c67ed56c)
(XEN) [ 13.282079] RDZV[ 0] t=00000039c0e39076(00000039c0e381ca) s=0003178219ff(0002c67ed56c)
(XEN) [ 11.925472] RDZV[ 5] t=00000039c0e390ea(00000039c0e381ca) s=0002c67b9e1d(0002c67ed56c)
(XEN) [ 11.928247] RDZV[17] t=00000039c0e390ce(00000039c0e381ca) s=0002c67b9dfb(0002c67ed56c)
(XEN) [ 11.931017] RDZV[16] t=00000039c0e3908a(00000039c0e381ca) s=0002c67b9e00(0002c67ed56c)
(XEN) [ 11.933784] RDZV[ 8] t=00000039c0e39066(00000039c0e381ca) s=0002c67b9deb(0002c67ed56c)
(XEN) [ 11.936563] RDZV[ 9] t=00000039c0e39116(00000039c0e381ca) s=0002c67b9e0c(0002c67ed56c)
(XEN) [ 11.939338] RDZV[ 7] t=00000039c0e3901a(00000039c0e381ca) s=0002c67b9d8b(0002c67ed56c)
(XEN) [ 11.942114] RDZV[ 6] t=00000039c0e39062(00000039c0e381ca) s=0002c67b9dd5(0002c67ed56c)
(XEN) [ 11.944892] RDZV[18] t=00000039c0e38e56(00000039c0e381ca) s=0002c67b9d29(0002c67ed56c)
(XEN) [ 11.947659] RDZV[19] t=00000039c0e39072(00000039c0e381ca) s=0002c67b9dc7(0002c67ed56c)
(XEN) [ 11.950435] RDZV[13] t=00000039c0e3902a(00000039c0e381ca) s=0002c67b9dda(0002c67ed56c)
(XEN) [ 11.953211] RDZV[12] t=00000039c0e38ff2(00000039c0e381ca) s=0002c67b9dbc(0002c67ed56c)
(XEN) [ 11.955985] RDZV[23] t=00000039c0e390d6(00000039c0e381ca) s=0002c67b9dd6(0002c67ed56c)
(XEN) [ 11.958759] RDZV[22] t=00000039c0e38f52(00000039c0e381ca) s=0002c67b9d38(0002c67ed56c)
(XEN) [ 11.961524] RDZV[14] t=00000039c0e38fee(00000039c0e381ca) s=0002c67b9dca(0002c67ed56c)
(XEN) [ 11.964300] RDZV[15] t=00000039c0e39002(00000039c0e381ca) s=0002c67b9dce(0002c67ed56c)
(XEN) [ 11.967075] RDZV[10] t=00000039c0e39056(00000039c0e381ca) s=0002c67b9de9(0002c67ed56c)
(XEN) [ 11.969850] RDZV[11] t=00000039c0e39076(00000039c0e381ca) s=0002c67b9e0b(0002c67ed56c)
(XEN) [ 11.972627] RDZV[21] t=00000039c0e38fe2(00000039c0e381ca) s=0002c67b9d8b(0002c67ed56c)
(XEN) [ 11.975398] RDZV[20] t=00000039c0e38fe2(00000039c0e381ca) s=0002c67b9d88(0002c67ed56c)
(XEN) [ 11.978167] RDZV[ 2] t=00000039c0e3901e(00000039c0e381ca) s=0002c67b9dc8(0002c67ed56c)
(XEN) [ 11.980941] RDZV[ 4] t=00000039c0e390e6(00000039c0e381ca) s=0002c67b9e10(0002c67ed56c)
(XEN) [ 11.983719] RDZV[ 3] t=00000039c0e3903a(00000039c0e381ca) s=0002c67b9def(0002c67ed56c)
(XEN) [ 13.345869] TSC: end rendezvous
(XEN) [ 18.347495] TSC adjusted by 216
(XEN) [ 21.348998] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 21.350406] RDZV[ 0] t=0000003e70db4888
(XEN) [ 19.992414] RDZV[ 1] t=0000003e70db52b8
(XEN) [ 19.993801] RDZV[ 3] t=0000003e70dc6d3c
(XEN) [ 19.995183] RDZV[ 2] t=0000003e70dc6da4
(XEN) [ 19.996572] RDZV[ 4] t=0000003e70dc7063
(XEN) [ 19.997959] RDZV[ 5] t=0000003e70dc7047
(XEN) [ 19.999345] RDZV[ 7] t=0000003e70dc799f
(XEN) [ 20.000727] RDZV[ 6] t=0000003e70dc798f
(XEN) [ 20.002115] RDZV[ 8] t=0000003e70dc86fb
(XEN) [ 20.003504] RDZV[ 9] t=0000003e70dc86ff
(XEN) [ 20.004890] RDZV[10] t=0000003e70dc90f8
(XEN) [ 20.006280] RDZV[11] t=0000003e70dc9110
(XEN) [ 20.007668] RDZV[12] t=0000003e70dc9a66
(XEN) [ 20.009057] RDZV[13] t=0000003e70dc9a5a
(XEN) [ 20.010445] RDZV[14] t=0000003e70dca4fd
(XEN) [ 20.011835] RDZV[15] t=0000003e70dca4e1
(XEN) [ 20.013223] RDZV[16] t=0000003e70dcacab
(XEN) [ 20.014603] RDZV[17] t=0000003e70dcacab
(XEN) [ 20.015986] RDZV[18] t=0000003e70dcb813
(XEN) [ 20.017374] RDZV[19] t=0000003e70dcb777
(XEN) [ 20.018762] RDZV[20] t=0000003e70dcc0e3
(XEN) [ 20.020144] RDZV[21] t=0000003e70dcc0e3
(XEN) [ 20.021531] RDZV[23] t=0000003e70dccc89
(XEN) [ 20.022915] RDZV[22] t=0000003e70dccc8d
(XEN) [ 20.024305] RDZV[ 6] t=0000003e75cdd5e7(0000003e75cdc7cb) s=0004a98a98ea(0004a99069dd)
(XEN) [ 20.027078] RDZV[ 7] t=0000003e75cdd5e7(0000003e75cdc7cb) s=0004a98a98bc(0004a99069dd)
(XEN) [ 21.389228] RDZV[ 0] t=0000003e75cdd737(0000003e75cdc7cb) s=0004fa911593(0004a99069dd)
(XEN) [ 20.032625] RDZV[17] t=0000003e75cdd7f3(0000003e75cdc7cb) s=0004a98a99b6(0004a99069dd)
(XEN) [ 20.035399] RDZV[12] t=0000003e75cdd827(0000003e75cdc7cb) s=0004a98a99e5(0004a99069dd)
(XEN) [ 20.038175] RDZV[13] t=0000003e75cdd82b(0000003e75cdc7cb) s=0004a98a99ef(0004a99069dd)
(XEN) [ 20.040953] RDZV[ 1] t=0000003e75cdd7b7(0000003e75cdc7cb) s=0004a98a9978(0004a99069dd)
(XEN) [ 20.043721] RDZV[10] t=0000003e75cdd82b(0000003e75cdc7cb) s=0004a98a99ec(0004a99069dd)
(XEN) [ 20.046496] RDZV[11] t=0000003e75cdd7a7(0000003e75cdc7cb) s=0004a98a99cb(0004a99069dd)
(XEN) [ 20.049275] RDZV[ 4] t=0000003e75cdd757(0000003e75cdc7cb) s=0004a98a9983(0004a99069dd)
(XEN) [ 20.052051] RDZV[23] t=0000003e75cdd823(0000003e75cdc7cb) s=0004a98a99a2(0004a99069dd)
(XEN) [ 20.054822] RDZV[21] t=0000003e75cdd6e7(0000003e75cdc7cb) s=0004a98a9939(0004a99069dd)
(XEN) [ 20.057589] RDZV[20] t=0000003e75cdd6e7(0000003e75cdc7cb) s=0004a98a9936(0004a99069dd)
(XEN) [ 20.060356] RDZV[22] t=0000003e75cdd80f(0000003e75cdc7cb) s=0004a98a9997(0004a99069dd)
(XEN) [ 20.063133] RDZV[19] t=0000003e75cdd803(0000003e75cdc7cb) s=0004a98a99ae(0004a99069dd)
(XEN) [ 20.065904] RDZV[18] t=0000003e75cdd81b(0000003e75cdc7cb) s=0004a98a99f2(0004a99069dd)
(XEN) [ 20.068677] RDZV[16] t=0000003e75cdd603(0000003e75cdc7cb) s=0004a98a990f(0004a99069dd)
(XEN) [ 20.071449] RDZV[15] t=0000003e75cdd863(0000003e75cdc7cb) s=0004a98a9a09(0004a99069dd)
(XEN) [ 20.074221] RDZV[14] t=0000003e75cdd84f(0000003e75cdc7cb) s=0004a98a9a04(0004a99069dd)
(XEN) [ 20.076995] RDZV[ 5] t=0000003e75cdd64b(0000003e75cdc7cb) s=0004a98a9922(0004a99069dd)
(XEN) [ 20.079772] RDZV[ 8] t=0000003e75cdd7fb(0000003e75cdc7cb) s=0004a98a99d4(0004a99069dd)
(XEN) [ 20.082545] RDZV[ 9] t=0000003e75cdd7fb(0000003e75cdc7cb) s=0004a98a99ad(0004a99069dd)
(XEN) [ 20.085320] RDZV[ 3] t=0000003e75cdd81f(0000003e75cdc7cb) s=0004a98a99f6(0004a99069dd)
(XEN) [ 20.088087] RDZV[ 2] t=0000003e75cdd81f(0000003e75cdc7cb) s=0004a98a99dc(0004a99069dd)
(XEN) [ 21.450239] TSC: end rendezvous
(XEN) [ 34.452273] TSC adjusted by 14a
(XEN) [ 37.453806] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 37.455218] RDZV[ 0] t=00000047cb3bbdb1
(XEN) [ 36.097225] RDZV[ 1] t=00000047cb3bc761
(XEN) [ 36.098613] RDZV[ 2] t=00000047cb3cdcff
(XEN) [ 36.099998] RDZV[ 3] t=00000047cb3cdcf7
(XEN) [ 36.101386] RDZV[ 5] t=00000047cb3ce1c1
(XEN) [ 36.102775] RDZV[ 4] t=00000047cb3ce1b1
(XEN) [ 36.104165] RDZV[ 7] t=00000047cb3ceb78
(XEN) [ 36.105552] RDZV[ 6] t=00000047cb3ceb64
(XEN) [ 36.106941] RDZV[ 8] t=00000047cb3cf92b
(XEN) [ 36.108325] RDZV[ 9] t=00000047cb3cf8f3
(XEN) [ 36.109717] RDZV[11] t=00000047cb3d0243
(XEN) [ 36.111104] RDZV[10] t=00000047cb3d0223
(XEN) [ 36.112495] RDZV[13] t=00000047cb3d0df6
(XEN) [ 36.113884] RDZV[12] t=00000047cb3d0df6
(XEN) [ 36.115274] RDZV[15] t=00000047cb3d187d
(XEN) [ 36.116661] RDZV[14] t=00000047cb3d1881
(XEN) [ 36.118051] RDZV[17] t=00000047cb3d2059
(XEN) [ 36.119437] RDZV[16] t=00000047cb3d2085
(XEN) [ 36.120824] RDZV[19] t=00000047cb3d297a
(XEN) [ 36.122204] RDZV[18] t=00000047cb3d2a0a
(XEN) [ 36.123592] RDZV[21] t=00000047cb3d3363
(XEN) [ 36.124976] RDZV[20] t=00000047cb3d3357
(XEN) [ 36.126361] RDZV[23] t=00000047cb3d3f14
(XEN) [ 36.127748] RDZV[22] t=00000047cb3d3f08
(XEN) [ 36.129136] RDZV[ 1] t=00000047d02f0300(00000047d02ef54c) s=00086976d33e(000869838e67)
(XEN) [ 37.491286] RDZV[ 0] t=00000047d02f0278(00000047d02ef54c) s=0008ba7d4f57(000869838e67)
(XEN) [ 36.134683] RDZV[18] t=00000047d02f03b4(00000047d02ef54c) s=00086976d3da(000869838e67)
(XEN) [ 36.137450] RDZV[19] t=00000047d02f0364(00000047d02ef54c) s=00086976d37d(000869838e67)
(XEN) [ 36.140224] RDZV[10] t=00000047d02f020c(00000047d02ef54c) s=00086976d322(000869838e67)
(XEN) [ 36.143002] RDZV[11] t=00000047d02f0224(00000047d02ef54c) s=00086976d340(000869838e67)
(XEN) [ 36.145777] RDZV[ 8] t=00000047d02f02a8(00000047d02ef54c) s=00086976d35d(000869838e67)
(XEN) [ 36.148553] RDZV[ 9] t=00000047d02f0248(00000047d02ef54c) s=00086976d310(000869838e67)
(XEN) [ 36.151320] RDZV[14] t=00000047d02f0218(00000047d02ef54c) s=00086976d332(000869838e67)
(XEN) [ 36.154096] RDZV[15] t=00000047d02f02a4(00000047d02ef54c) s=00086976d366(000869838e67)
(XEN) [ 36.156870] RDZV[16] t=00000047d02f02ec(00000047d02ef54c) s=00086976d37b(000869838e67)
(XEN) [ 36.159643] RDZV[17] t=00000047d02f02e8(00000047d02ef54c) s=00086976d359(000869838e67)
(XEN) [ 36.162418] RDZV[23] t=00000047d02f037c(00000047d02ef54c) s=00086976d370(000869838e67)
(XEN) [ 36.165184] RDZV[ 5] t=00000047d02f02dc(00000047d02ef54c) s=00086976d36d(000869838e67)
(XEN) [ 36.167959] RDZV[13] t=00000047d02f027c(00000047d02ef54c) s=00086976d353(000869838e67)
(XEN) [ 36.170735] RDZV[12] t=00000047d02f0280(00000047d02ef54c) s=00086976d34b(000869838e67)
(XEN) [ 36.173510] RDZV[ 4] t=00000047d02f0310(00000047d02ef54c) s=00086976d376(000869838e67)
(XEN) [ 36.176285] RDZV[ 7] t=00000047d02f0364(00000047d02ef54c) s=00086976d365(000869838e67)
(XEN) [ 36.179058] RDZV[ 6] t=00000047d02f0368(00000047d02ef54c) s=00086976d394(000869838e67)
(XEN) [ 36.181837] RDZV[ 2] t=00000047d02f02e8(00000047d02ef54c) s=00086976d36f(000869838e67)
(XEN) [ 36.184611] RDZV[ 3] t=00000047d02f02e8(00000047d02ef54c) s=00086976d389(000869838e67)
(XEN) [ 36.187381] RDZV[20] t=00000047d02f02d8(00000047d02ef54c) s=00086976d340(000869838e67)
(XEN) [ 36.190151] RDZV[22] t=00000047d02f0328(00000047d02ef54c) s=00086976d348(000869838e67)
(XEN) [ 36.192919] RDZV[21] t=00000047d02f0234(00000047d02ef54c) s=00086976d301(000869838e67)
(XEN) [ 37.555066] TSC: end rendezvous
(XEN) [ 66.558005] TSC adjusted by 1eb
(XEN) [ 69.559522] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 69.560932] RDZV[ 0] t=0000005a7089b562
(XEN) [ 68.202938] RDZV[ 1] t=0000005a7089bf12
(XEN) [ 68.204326] RDZV[ 2] t=0000005a708ad38f
(XEN) [ 68.205712] RDZV[ 3] t=0000005a708ad38f
(XEN) [ 68.207095] RDZV[ 5] t=0000005a708ad61d
(XEN) [ 68.208480] RDZV[ 4] t=0000005a708ad619
(XEN) [ 68.209871] RDZV[ 7] t=0000005a708adfd4
(XEN) [ 68.211259] RDZV[ 6] t=0000005a708ae818
(XEN) [ 68.212647] RDZV[ 8] t=0000005a708aed9d
(XEN) [ 68.214034] RDZV[ 9] t=0000005a708aeda1
(XEN) [ 68.215425] RDZV[11] t=0000005a708af872
(XEN) [ 68.216813] RDZV[10] t=0000005a708af9d2
(XEN) [ 68.218201] RDZV[13] t=0000005a708b02f3
(XEN) [ 68.219590] RDZV[12] t=0000005a708b02ef
(XEN) [ 68.220977] RDZV[14] t=0000005a708b0bb0
(XEN) [ 68.222359] RDZV[15] t=0000005a708b0cd8
(XEN) [ 68.223749] RDZV[16] t=0000005a708b1493
(XEN) [ 68.225135] RDZV[17] t=0000005a708b149f
(XEN) [ 68.226524] RDZV[18] t=0000005a708b1eba
(XEN) [ 68.227907] RDZV[19] t=0000005a708b1eba
(XEN) [ 68.229294] RDZV[20] t=0000005a708b2731
(XEN) [ 68.230680] RDZV[21] t=0000005a708b2775
(XEN) [ 68.232066] RDZV[22] t=0000005a708b32d9
(XEN) [ 68.233448] RDZV[23] t=0000005a708b32bd
(XEN) [ 69.594216] RDZV[ 0] t=0000005a757c7651(0000005a757c68d9) s=001034236b61(000fe3389ad9)
(XEN) [ 68.237606] RDZV[ 1] t=0000005a757c7865(0000005a757c68d9) s=000fe31cefe8(000fe3389ad9)
(XEN) [ 68.240381] RDZV[ 5] t=0000005a757c77bd(0000005a757c68d9) s=000fe31cefe4(000fe3389ad9)
(XEN) [ 68.243156] RDZV[11] t=0000005a757c7945(0000005a757c68d9) s=000fe31cf09c(000fe3389ad9)
(XEN) [ 68.245934] RDZV[10] t=0000005a757c7945(0000005a757c68d9) s=000fe31cf085(000fe3389ad9)
(XEN) [ 68.248708] RDZV[ 4] t=0000005a757c77a9(0000005a757c68d9) s=000fe31cefcb(000fe3389ad9)
(XEN) [ 68.251480] RDZV[ 3] t=0000005a757c7aa1(0000005a757c68d9) s=000fe31cf122(000fe3389ad9)
(XEN) [ 68.254254] RDZV[ 9] t=0000005a757c7839(0000005a757c68d9) s=000fe31ceff0(000fe3389ad9)
(XEN) [ 68.257049] RDZV[ 8] t=0000005a757c787d(0000005a757c68d9) s=000fe31cf030(000fe3389ad9)
(XEN) [ 68.259826] RDZV[13] t=0000005a757c772d(0000005a757c68d9) s=000fe31cefb4(000fe3389ad9)
(XEN) [ 68.262605] RDZV[ 6] t=0000005a757c75cd(0000005a757c68d9) s=000fe31cef0b(000fe3389ad9)
(XEN) [ 68.265374] RDZV[ 7] t=0000005a757c773d(0000005a757c68d9) s=000fe31cef6d(000fe3389ad9)
(XEN) [ 68.268152] RDZV[16] t=0000005a757c7719(0000005a757c68d9) s=000fe31cefa9(000fe3389ad9)
(XEN) [ 68.270929] RDZV[17] t=0000005a757c7719(0000005a757c68d9) s=000fe31cef87(000fe3389ad9)
(XEN) [ 68.273703] RDZV[23] t=0000005a757c7759(0000005a757c68d9) s=000fe31cef7b(000fe3389ad9)
(XEN) [ 68.276477] RDZV[12] t=0000005a757c772d(0000005a757c68d9) s=000fe31cefa9(000fe3389ad9)
(XEN) [ 68.279245] RDZV[ 2] t=0000005a757c7a49(0000005a757c68d9) s=000fe31cf0e1(000fe3389ad9)
(XEN) [ 68.282022] RDZV[21] t=0000005a757c7839(0000005a757c68d9) s=000fe31cefe9(000fe3389ad9)
(XEN) [ 68.284794] RDZV[22] t=0000005a757c7769(0000005a757c68d9) s=000fe31cef7c(000fe3389ad9)
(XEN) [ 68.287567] RDZV[15] t=0000005a757c7785(0000005a757c68d9) s=000fe31cefdc(000fe3389ad9)
(XEN) [ 68.290343] RDZV[14] t=0000005a757c7745(0000005a757c68d9) s=000fe31cefc4(000fe3389ad9)
(XEN) [ 68.293112] RDZV[20] t=0000005a757c7839(0000005a757c68d9) s=000fe31cefe7(000fe3389ad9)
(XEN) [ 68.295885] RDZV[19] t=0000005a757c77cd(0000005a757c68d9) s=000fe31cefbf(000fe3389ad9)
(XEN) [ 68.298656] RDZV[18] t=0000005a757c77b9(0000005a757c68d9) s=000fe31ceff3(000fe3389ad9)
(XEN) [ 69.660811] TSC: end rendezvous
(XEN) [ 130.666150] TSC adjusted by 27b
(XEN) [ 133.667664] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 133.669076] RDZV[ 0] t=0000007fabca922e
(XEN) [ 132.311080] RDZV[ 1] t=0000007fabca9dce
(XEN) [ 132.312470] RDZV[ 3] t=0000007fabcba087
(XEN) [ 132.313855] RDZV[ 2] t=0000007fabcba083
(XEN) [ 132.315241] RDZV[ 4] t=0000007fabcba475
(XEN) [ 132.316628] RDZV[ 5] t=0000007fabcba479
(XEN) [ 132.318018] RDZV[ 7] t=0000007fabcbace8
(XEN) [ 132.319401] RDZV[ 6] t=0000007fabcbacf8
(XEN) [ 132.320786] RDZV[ 8] t=0000007fabcbbb83
(XEN) [ 132.322177] RDZV[ 9] t=0000007fabcbbc77
(XEN) [ 132.323565] RDZV[11] t=0000007fabcbc6d7
(XEN) [ 132.324951] RDZV[10] t=0000007fabcbc6cf
(XEN) [ 132.326337] RDZV[13] t=0000007fabcbd0da
(XEN) [ 132.327726] RDZV[12] t=0000007fabcbd0da
(XEN) [ 132.329116] RDZV[15] t=0000007fabcbdb02
(XEN) [ 132.330503] RDZV[14] t=0000007fabcbdaee
(XEN) [ 132.331891] RDZV[16] t=0000007fabcbdee3
(XEN) [ 132.333276] RDZV[17] t=0000007fabcbdf2b
(XEN) [ 132.334659] RDZV[19] t=0000007fabcbed70
(XEN) [ 132.336046] RDZV[18] t=0000007fabcbed60
(XEN) [ 132.337435] RDZV[20] t=0000007fabcbf68b
(XEN) [ 132.338821] RDZV[21] t=0000007fabcbf67f
(XEN) [ 132.340206] RDZV[22] t=0000007fabcbfa0e
(XEN) [ 132.341593] RDZV[23] t=0000007fabcbfa0e
(XEN) [ 132.342985] RDZV[ 1] t=0000007fb0bd8a58(0000007fb0bd7a0c) s=001ed041a8ba(001ed08665f3)
(XEN) [ 133.705135] RDZV[ 0] t=0000007fb0bd8a50(0000007fb0bd7a0c) s=001f21482507(001ed08665f3)
(XEN) [ 132.348522] RDZV[ 5] t=0000007fb0bd8a58(0000007fb0bd7a0c) s=001ed041a8fd(001ed08665f3)
(XEN) [ 132.351297] RDZV[16] t=0000007fb0bd8a70(0000007fb0bd7a0c) s=001ed041a909(001ed08665f3)
(XEN) [ 132.354075] RDZV[23] t=0000007fb0bd8ae4(0000007fb0bd7a0c) s=001ed041a8f8(001ed08665f3)
(XEN) [ 132.356847] RDZV[ 4] t=0000007fb0bd8a74(0000007fb0bd7a0c) s=001ed041a8f2(001ed08665f3)
(XEN) [ 132.359622] RDZV[ 2] t=0000007fb0bd8900(0000007fb0bd7a0c) s=001ed041a86a(001ed08665f3)
(XEN) [ 132.362388] RDZV[14] t=0000007fb0bd8ae0(0000007fb0bd7a0c) s=001ed041a942(001ed08665f3)
(XEN) [ 132.365161] RDZV[15] t=0000007fb0bd8ae0(0000007fb0bd7a0c) s=001ed041a93f(001ed08665f3)
(XEN) [ 132.367935] RDZV[11] t=0000007fb0bd8b40(0000007fb0bd7a0c) s=001ed041a972(001ed08665f3)
(XEN) [ 132.370712] RDZV[10] t=0000007fb0bd8b40(0000007fb0bd7a0c) s=001ed041a95d(001ed08665f3)
(XEN) [ 132.373492] RDZV[12] t=0000007fb0bd8a7c(0000007fb0bd7a0c) s=001ed041a906(001ed08665f3)
(XEN) [ 132.376268] RDZV[13] t=0000007fb0bd8a6c(0000007fb0bd7a0c) s=001ed041a90a(001ed08665f3)
(XEN) [ 132.379044] RDZV[ 9] t=0000007fb0bd8afc(0000007fb0bd7a0c) s=001ed041a915(001ed08665f3)
(XEN) [ 132.381819] RDZV[ 8] t=0000007fb0bd8b0c(0000007fb0bd7a0c) s=001ed041a943(001ed08665f3)
(XEN) [ 132.384599] RDZV[17] t=0000007fb0bd8a60(0000007fb0bd7a0c) s=001ed041a8e4(001ed08665f3)
(XEN) [ 132.387373] RDZV[22] t=0000007fb0bd8ac4(0000007fb0bd7a0c) s=001ed041a8e1(001ed08665f3)
(XEN) [ 132.390144] RDZV[19] t=0000007fb0bd8ad8(0000007fb0bd7a0c) s=001ed041a8ff(001ed08665f3)
(XEN) [ 132.392913] RDZV[ 6] t=0000007fb0bd8b08(0000007fb0bd7a0c) s=001ed041a92e(001ed08665f3)
(XEN) [ 132.395692] RDZV[ 7] t=0000007fb0bd8a08(0000007fb0bd7a0c) s=001ed041a89a(001ed08665f3)
(XEN) [ 132.398469] RDZV[18] t=0000007fb0bd8aa4(0000007fb0bd7a0c) s=001ed041a92b(001ed08665f3)
(XEN) [ 132.401241] RDZV[21] t=0000007fb0bd8c00(0000007fb0bd7a0c) s=001ed041a97c(001ed08665f3)
(XEN) [ 132.404013] RDZV[20] t=0000007fb0bd8894(0000007fb0bd7a0c) s=001ed041a81b(001ed08665f3)
(XEN) [ 132.406777] RDZV[ 3] t=0000007fb0bd88fc(0000007fb0bd7a0c) s=001ed041a884(001ed08665f3)
(XEN) [ 133.768930] TSC: end rendezvous
(XEN) [ 258.777776] TSC adjusted by 38f
(XEN) [ 261.779280] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 261.780671] RDZV[ 0] t=000000ca12bbaaa7
(XEN) [ 260.422678] RDZV[ 1] t=000000ca12bbb133
(XEN) [ 260.424067] RDZV[ 2] t=000000ca12bbb24d
(XEN) [ 260.425454] RDZV[ 3] t=000000ca12bbb251
(XEN) [ 260.426841] RDZV[ 5] t=000000ca12bc6ecf
(XEN) [ 260.428226] RDZV[ 4] t=000000ca12bc6ee3
(XEN) [ 260.429615] RDZV[ 6] t=000000ca12bcaff0
(XEN) [ 260.431003] RDZV[ 7] t=000000ca12bcae94
(XEN) [ 260.432389] RDZV[ 8] t=000000ca12bcbd56
(XEN) [ 260.433776] RDZV[ 9] t=000000ca12bcbc9e
(XEN) [ 260.435167] RDZV[11] t=000000ca12bcc687
(XEN) [ 260.436555] RDZV[10] t=000000ca12bcc56b
(XEN) [ 260.437948] RDZV[12] t=000000ca12bcd028
(XEN) [ 260.439337] RDZV[13] t=000000ca12bcd02c
(XEN) [ 260.440728] RDZV[15] t=000000ca12bcdd57
(XEN) [ 260.442114] RDZV[14] t=000000ca12bcdd67
(XEN) [ 260.443502] RDZV[17] t=000000ca12bce464
(XEN) [ 260.444889] RDZV[16] t=000000ca12bce48c
(XEN) [ 260.446272] RDZV[19] t=000000ca12bceede
(XEN) [ 260.447658] RDZV[18] t=000000ca12bcee86
(XEN) [ 260.449046] RDZV[21] t=000000ca12bcf75e
(XEN) [ 260.450432] RDZV[20] t=000000ca12bcf74e
(XEN) [ 260.451819] RDZV[22] t=000000ca12bd0302
(XEN) [ 260.453203] RDZV[23] t=000000ca12bd02de
(XEN) [ 260.454593] RDZV[ 1] t=000000ca17af13a8(000000ca17af0410) s=003ca44da60c(003ca4d957fd)
(XEN) [ 260.457367] RDZV[ 9] t=000000ca17af131c(000000ca17af0410) s=003ca44da5f1(003ca4d957fd)
(XEN) [ 260.460140] RDZV[ 8] t=000000ca17af1330(000000ca17af0410) s=003ca44da621(003ca4d957fd)
(XEN) [ 260.462913] RDZV[22] t=000000ca17af1350(000000ca17af0410) s=003ca44da5eb(003ca4d957fd)
(XEN) [ 260.465686] RDZV[16] t=000000ca17af1398(000000ca17af0410) s=003ca44da650(003ca4d957fd)
(XEN) [ 260.468457] RDZV[17] t=000000ca17af13d0(000000ca17af0410) s=003ca44da643(003ca4d957fd)
(XEN) [ 260.471234] RDZV[10] t=000000ca17af1348(000000ca17af0410) s=003ca44da62f(003ca4d957fd)
(XEN) [ 260.474007] RDZV[11] t=000000ca17af1340(000000ca17af0410) s=003ca44da640(003ca4d957fd)
(XEN) [ 260.476779] RDZV[ 5] t=000000ca17af13f8(000000ca17af0410) s=003ca44da673(003ca4d957fd)
(XEN) [ 260.479558] RDZV[19] t=000000ca17af1310(000000ca17af0410) s=003ca44da5e3(003ca4d957fd)
(XEN) [ 260.482333] RDZV[18] t=000000ca17af1300(000000ca17af0410) s=003ca44da61a(003ca4d957fd)
(XEN) [ 260.485107] RDZV[ 2] t=000000ca17af13dc(000000ca17af0410) s=003ca44da65c(003ca4d957fd)
(XEN) [ 260.487882] RDZV[ 6] t=000000ca17af12d0(000000ca17af0410) s=003ca44da5eb(003ca4d957fd)
(XEN) [ 260.490655] RDZV[ 7] t=000000ca17af12e8(000000ca17af0410) s=003ca44da5c1(003ca4d957fd)
(XEN) [ 260.493432] RDZV[ 4] t=000000ca17af13f4(000000ca17af0410) s=003ca44da65c(003ca4d957fd)
(XEN) [ 260.496209] RDZV[21] t=000000ca17af13e4(000000ca17af0410) s=003ca44da640(003ca4d957fd)
(XEN) [ 261.858361] RDZV[ 0] t=000000ca17af12b8(000000ca17af0410) s=003cf55421fb(003ca4d957fd)
(XEN) [ 260.501754] RDZV[13] t=000000ca17af1420(000000ca17af0410) s=003ca44da68a(003ca4d957fd)
(XEN) [ 260.504526] RDZV[12] t=000000ca17af13e0(000000ca17af0410) s=003ca44da65f(003ca4d957fd)
(XEN) [ 260.507302] RDZV[14] t=000000ca17af1374(000000ca17af0410) s=003ca44da64d(003ca4d957fd)
(XEN) [ 260.510080] RDZV[15] t=000000ca17af1360(000000ca17af0410) s=003ca44da63d(003ca4d957fd)
(XEN) [ 260.512858] RDZV[20] t=000000ca17af13f4(000000ca17af0410) s=003ca44da63f(003ca4d957fd)
(XEN) [ 260.515629] RDZV[ 3] t=000000ca17af1250(000000ca17af0410) s=003ca44da5d7(003ca4d957fd)
(XEN) [ 260.518395] RDZV[23] t=000000ca17af1350(000000ca17af0410) s=003ca44da5f9(003ca4d957fd)
(XEN) [ 261.880549] TSC: end rendezvous
[-- Attachment #3: kernel-dmesg.txt --]
[-- Type: text/plain, Size: 68368 bytes --]
[ 0.000000] Linux version 5.10.0-1-amd64 (debian-kernel@lists.debian.org) (gcc-10 (Debian 10.2.1-3) 10.2.1 20201224, GNU ld (GNU Binutils for Debian) 2.35.1) #1 SMP Debian 5.10.4-1 (2020-12-31)
[ 0.000000] Command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro earlyprintk=xen loglevel=0 nomodeset
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256
[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[ 0.000000] Released 0 page(s)
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable
[ 0.000000] Xen: [mem 0x000000000009e800-0x00000000000fffff] reserved
[ 0.000000] Xen: [mem 0x0000000000100000-0x0000000080061fff] usable
[ 0.000000] Xen: [mem 0x00000000ba952000-0x00000000ba98afff] reserved
[ 0.000000] Xen: [mem 0x00000000babc3000-0x00000000bb1bffff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bb1c0000-0x00000000bb842fff] reserved
[ 0.000000] Xen: [mem 0x00000000bb844000-0x00000000bb8c9fff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bbd0f000-0x00000000bbff3fff] reserved
[ 0.000000] Xen: [mem 0x00000000d0000000-0x00000000dfffffff] reserved
[ 0.000000] Xen: [mem 0x00000000fbffc000-0x00000000fbffcfff] reserved
[ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec01fff] reserved
[ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000feefffff] reserved
[ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] SMBIOS 2.7 present.
[ 0.000000] DMI: To be filled by O.E.M. To be filled by O.E.M./Intel X79, BIOS 4.6.5 07/17/2019
[ 0.000000] Hypervisor detected: Xen PV
[ 0.046591] tsc: Fast TSC calibration using PIT
[ 0.046593] tsc: Detected 2494.334 MHz processor
[ 0.046594] tsc: Detected 2494.346 MHz TSC
[ 0.052182] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.052185] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.052191] last_pfn = 0x80062 max_arch_pfn = 0x400000000
[ 0.052192] Disabled
[ 0.052193] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[ 0.052198] x86/PAT: Configuration [0-7]: WB WT UC- UC WC WP UC UC
[ 0.066973] Kernel/User page tables isolation: disabled on XEN PV.
[ 0.679417] RAMDISK: [mem 0x04000000-0x061f4fff]
[ 0.679431] ACPI: Early table checksum verification disabled
[ 0.685594] ACPI: RSDP 0x00000000000F04A0 000024 (v02 ALASKA)
[ 0.685604] ACPI: XSDT 0x00000000BB0DD070 00005C (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.685631] ACPI: FACP 0x00000000BB0E5728 00010C (v05 ALASKA A M I 01072009 AMI 00010013)
[ 0.685696] ACPI: DSDT 0x00000000BB0DD160 0085C7 (v02 ALASKA A M I 00000020 INTL 20051117)
[ 0.685710] ACPI: FACS 0x00000000BB1B7F80 000040
[ 0.685725] ACPI: APIC 0x00000000BB0E5838 0001A8 (v03 ALASKA A M I 01072009 AMI 00010013)
[ 0.685739] ACPI: FPDT 0x00000000BB0E59E0 000044 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.685754] ACPI: MCFG 0x00000000BB0E5A28 00003C (v01 ALASKA OEMMCFG. 01072009 MSFT 00000097)
[ 0.685768] ACPI: HPET 0x00000000BB0E5A68 000038 (v01 ALASKA A M I 01072009 AMI. 00000005)
[ 0.685783] ACPI: SSDT 0x00000000BB0E5AA0 0CD380 (v02 INTEL CpuPm 00004000 INTL 20051117)
[ 0.685798] ACPI: RMAD 0x00000000BB1B2E20 0000EC (v01 A M I OEMDMAR 00000001 INTL 00000001)
[ 0.685836] ACPI: Local APIC address 0xfee00000
[ 0.685838] Setting APIC routing to Xen PV.
[ 0.685871] NUMA turned off
[ 0.685872] Faking a node at [mem 0x0000000000000000-0x0000000080061fff]
[ 0.685885] NODE_DATA(0) allocated [mem 0x3fbf7000-0x3fc20fff]
[ 0.699053] Zone ranges:
[ 0.699054] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.699056] DMA32 [mem 0x0000000001000000-0x0000000080061fff]
[ 0.699057] Normal empty
[ 0.699059] Device empty
[ 0.699060] Movable zone start for each node
[ 0.699063] Early memory node ranges
[ 0.699064] node 0: [mem 0x0000000000001000-0x000000000009dfff]
[ 0.699065] node 0: [mem 0x0000000000100000-0x0000000080061fff]
[ 0.699391] Zeroed struct page in unavailable ranges: 32769 pages
[ 0.699393] Initmem setup node 0 [mem 0x0000000000001000-0x0000000080061fff]
[ 0.699394] On node 0 totalpages: 524287
[ 0.699396] DMA zone: 64 pages used for memmap
[ 0.699396] DMA zone: 21 pages reserved
[ 0.699398] DMA zone: 3997 pages, LIFO batch:0
[ 0.699448] DMA32 zone: 8130 pages used for memmap
[ 0.699449] DMA32 zone: 520290 pages, LIFO batch:63
[ 0.700176] p2m virtual area at (____ptrval____), size is 40000000
[ 1.031136] Remapped 98 page(s)
[ 1.033212] ACPI: PM-Timer IO Port: 0x408
[ 1.033219] ACPI: Local APIC address 0xfee00000
[ 1.033292] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[ 1.033293] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
[ 1.033295] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
[ 1.033297] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
[ 1.033298] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
[ 1.033299] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
[ 1.033301] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
[ 1.033303] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
[ 1.033304] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
[ 1.033305] ACPI: LAPIC_NMI (acpi_id[0x12] high edge lint[0x1])
[ 1.033307] ACPI: LAPIC_NMI (acpi_id[0x14] high edge lint[0x1])
[ 1.033308] ACPI: LAPIC_NMI (acpi_id[0x16] high edge lint[0x1])
[ 1.033310] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[ 1.033311] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
[ 1.033313] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
[ 1.033314] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
[ 1.033315] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
[ 1.033317] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
[ 1.033318] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
[ 1.033320] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
[ 1.033321] ACPI: LAPIC_NMI (acpi_id[0x11] high edge lint[0x1])
[ 1.033323] ACPI: LAPIC_NMI (acpi_id[0x13] high edge lint[0x1])
[ 1.033324] ACPI: LAPIC_NMI (acpi_id[0x15] high edge lint[0x1])
[ 1.033325] ACPI: LAPIC_NMI (acpi_id[0x17] high edge lint[0x1])
[ 1.033354] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
[ 1.033366] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
[ 1.033384] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 1.033387] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 1.033396] ACPI: IRQ0 used by override.
[ 1.033398] ACPI: IRQ9 used by override.
[ 1.033414] Using ACPI (MADT) for SMP configuration information
[ 1.033419] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 1.033427] smpboot: Allowing 24 CPUs, 0 hotplug CPUs
[ 1.033447] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 1.033449] PM: hibernation: Registered nosave memory: [mem 0x0009e000-0x0009efff]
[ 1.033450] PM: hibernation: Registered nosave memory: [mem 0x0009f000-0x000fffff]
[ 1.033452] [mem 0x80062000-0xba951fff] available for PCI devices
[ 1.033455] Booting paravirtualized kernel on Xen
[ 1.033456] Xen version: 4.11.4 (preserve-AD)
[ 1.033459] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
[ 1.037908] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:24 nr_cpu_ids:24 nr_node_ids:1
[ 1.038720] percpu: Embedded 54 pages/cpu s183960 r8192 d29032 u262144
[ 1.038727] pcpu-alloc: s183960 r8192 d29032 u262144 alloc=1*2097152
[ 1.038729] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 12 13 14 15
[ 1.038739] pcpu-alloc: [0] 16 17 18 19 20 21 22 23
[ 1.038808] xen: PV spinlocks enabled
[ 1.038813] PV qspinlock hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 1.038817] Built 1 zonelists, mobility grouping on. Total pages: 516072
[ 1.038818] Policy zone: DMA32
[ 1.038820] Kernel command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro earlyprintk=xen loglevel=0 nomodeset
[ 1.038884] You have booted with nomodeset. This means your GPU drivers are DISABLED
[ 1.038885] Any video related functionality will be severely degraded, and you may not even be able to suspend the system properly
[ 1.038885] Unless you actually understand what nomodeset does, you should reboot without enabling it
[ 1.039049] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 1.039131] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 1.039637] mem auto-init: stack:off, heap alloc:on, heap free:off
[ 1.084148] software IO TLB: mapped [mem 0x0000000038c00000-0x000000003cc00000] (64MB)
[ 1.104139] Memory: 197808K/2097148K available (12295K kernel code, 2540K rwdata, 4060K rodata, 2380K init, 1692K bss, 1229692K reserved, 0K cma-reserved)
[ 1.104148] random: get_random_u64 called from __kmem_cache_create+0x2e/0x550 with crng_init=0
[ 1.104451] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 1.105397] ftrace: allocating 35988 entries in 141 pages
[ 1.119008] ftrace: allocated 141 pages with 4 groups
[ 1.119422] rcu: Hierarchical RCU implementation.
[ 1.119424] rcu: RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=4.
[ 1.119425] Rude variant of Tasks RCU enabled.
[ 1.119425] Tracing variant of Tasks RCU enabled.
[ 1.119426] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 1.119427] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 1.130515] Using NULL legacy PIC
[ 1.130517] NR_IRQS: 524544, nr_irqs: 864, preallocated irqs: 0
[ 1.130581] xen:events: Using FIFO-based ABI
[ 1.130614] xen: --> pirq=1 -> irq=1 (gsi=1)
[ 1.130629] xen: --> pirq=2 -> irq=2 (gsi=2)
[ 1.130643] xen: --> pirq=3 -> irq=3 (gsi=3)
[ 1.130657] xen: --> pirq=4 -> irq=4 (gsi=4)
[ 1.130671] xen: --> pirq=5 -> irq=5 (gsi=5)
[ 1.130685] xen: --> pirq=6 -> irq=6 (gsi=6)
[ 1.130699] xen: --> pirq=7 -> irq=7 (gsi=7)
[ 1.130712] xen: --> pirq=8 -> irq=8 (gsi=8)
[ 1.130727] xen: --> pirq=9 -> irq=9 (gsi=9)
[ 1.130741] xen: --> pirq=10 -> irq=10 (gsi=10)
[ 1.130756] xen: --> pirq=11 -> irq=11 (gsi=11)
[ 1.130770] xen: --> pirq=12 -> irq=12 (gsi=12)
[ 1.130785] xen: --> pirq=13 -> irq=13 (gsi=13)
[ 1.130799] xen: --> pirq=14 -> irq=14 (gsi=14)
[ 1.130813] xen: --> pirq=15 -> irq=15 (gsi=15)
[ 1.130860] random: crng done (trusting CPU's manufacturer)
[ 1.135707] Console: colour VGA+ 80x25
[ 1.135719] printk: console [tty0] enabled
[ 1.135730] printk: console [hvc0] enabled
[ 1.135758] ACPI: Core revision 20200925
[ 1.209211] clocksource: xen: mask: 0xffffffffffffffff max_cycles: 0x1cd42e4dffb, max_idle_ns: 881590591483 ns
[ 1.209223] Xen: using vcpuop timer interface
[ 1.209228] installing Xen timer for CPU 0
[ 1.209268] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23f45cd4443, max_idle_ns: 440795305613 ns
[ 1.209272] Calibrating delay loop (skipped), value calculated using timer frequency.. 4988.69 BogoMIPS (lpj=9977384)
[ 1.209275] pid_max: default: 32768 minimum: 301
[ 1.209369] LSM: Security Framework initializing
[ 1.209396] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 1.209491] AppArmor: AppArmor initialized
[ 1.209496] TOMOYO Linux initialized
[ 1.209543] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.209549] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.211703] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8
[ 1.211705] Last level dTLB entries: 4KB 512, 2MB 0, 4MB 0, 1GB 4
[ 1.211708] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[ 1.211710] Spectre V2 : Mitigation: Full generic retpoline
[ 1.211711] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[ 1.211712] Speculative Store Bypass: Vulnerable
[ 1.211714] MDS: Vulnerable: Clear CPU buffers attempted, no microcode
[ 1.211851] Freeing SMP alternatives memory: 32K
[ 1.217398] cpu 0 spinlock event irq 49
[ 1.217405] VPMU disabled by hypervisor.
[ 1.217801] Performance Events: unsupported p6 CPU model 62 no PMU driver, software events only.
[ 1.217906] rcu: Hierarchical SRCU implementation.
[ 1.218383] NMI watchdog: Perf NMI watchdog permanently disabled
[ 1.218536] smp: Bringing up secondary CPUs ...
[ 1.218807] installing Xen timer for CPU 1
[ 1.225270] cpu 1 spinlock event irq 59
[ 1.321282] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.
[ 1.321628] installing Xen timer for CPU 2
[ 1.321970] cpu 2 spinlock event irq 65
[ 1.321970] installing Xen timer for CPU 3
[ 1.321970] cpu 3 spinlock event irq 71
[ 1.342236] smp: Brought up 1 node, 4 CPUs
[ 1.342237] smpboot: Max logical packages: 6
[ 1.342908] node 0 deferred pages initialised in 0ms
[ 1.342943] devtmpfs: initialized
[ 1.342943] x86/mm: Memory block size: 128MB
[ 1.342943] PM: Registering ACPI NVS region [mem 0xbabc3000-0xbb1bffff] (6279168 bytes)
[ 1.342943] PM: Registering ACPI NVS region [mem 0xbb844000-0xbb8c9fff] (548864 bytes)
[ 1.345311] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 1.345311] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[ 1.345352] pinctrl core: initialized pinctrl subsystem
[ 1.345618] NET: Registered protocol family 16
[ 1.345618] xen:grant_table: Grant tables using version 1 layout
[ 1.345618] Grant table initialized
[ 1.345618] audit: initializing netlink subsys (disabled)
[ 1.345846] audit: type=2000 audit(1611943002.795:1): state=initialized audit_enabled=0 res=1
[ 1.345846] thermal_sys: Registered thermal governor 'fair_share'
[ 1.345846] thermal_sys: Registered thermal governor 'bang_bang'
[ 1.345846] thermal_sys: Registered thermal governor 'step_wise'
[ 1.345846] thermal_sys: Registered thermal governor 'user_space'
[ 1.345846] ACPI: bus type PCI registered
[ 1.345846] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 1.345846] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xd0000000-0xdfffffff] (base 0xd0000000)
[ 1.345846] PCI: MMCONFIG at [mem 0xd0000000-0xdfffffff] reserved in E820
[ 2.528114] PCI: Using configuration type 1 for base access
[ 3.853270] clocksource: timekeeping watchdog on CPU2: Marking clocksource 'tsc-early' as unstable because the skew is too large:
[ 3.853270] clocksource: 'xen' wd_now: 2209b97b3 wd_last: 1ce4abf7b mask: ffffffffffffffff
[ 3.853270] clocksource: 'tsc-early' cs_now: 37689a0068 cs_last: 368c11307d mask: ffffffffffffffff
[ 3.853270] tsc: Marking TSC unstable due to clocksource watchdog
[ 5.298275] ACPI: Added _OSI(Module Device)
[ 5.298275] ACPI: Added _OSI(Processor Device)
[ 5.298275] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 5.298275] ACPI: Added _OSI(Processor Aggregator Device)
[ 5.298275] ACPI: Added _OSI(Linux-Dell-Video)
[ 5.298275] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[ 5.298275] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[ 6.477270] ACPI: 2 ACPI AML tables successfully acquired and loaded
[ 6.477270] xen: registering gsi 9 triggering 0 polarity 0
[ 6.477270] ACPI: Interpreter enabled
[ 6.477270] ACPI: (supports S0 S5)
[ 6.477270] ACPI: Using IOAPIC for interrupt routing
[ 6.477270] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 6.477270] ACPI: Enabled 6 GPEs in block 00 to 3F
[ 6.477270] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
[ 6.477270] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 6.477270] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug PME AER LTR]
[ 6.477270] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PCIeCapability]
[ 6.477270] PCI host bridge to bus 0000:00
[ 6.477270] pci_bus 0000:00: root bus resource [io 0x0000-0x03af window]
[ 6.477270] pci_bus 0000:00: root bus resource [io 0x03e0-0x0cf7 window]
[ 6.477270] pci_bus 0000:00: root bus resource [io 0x03b0-0x03df window]
[ 6.477270] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 6.477270] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 6.477270] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 6.477270] pci_bus 0000:00: root bus resource [mem 0xcc000000-0xffffffff window]
[ 6.477270] pci_bus 0000:00: root bus resource [mem 0x440000000-0x3fffffffffff window]
[ 6.477270] pci_bus 0000:00: root bus resource [bus 00-fe]
[ 6.477270] pci 0000:00:00.0: [8086:0e00] type 00 class 0x060000
[ 6.477270] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:01.0: [8086:0e02] type 01 class 0x060400
[ 6.477270] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:01.1: [8086:0e03] type 01 class 0x060400
[ 6.477270] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:02.0: [8086:0e04] type 01 class 0x060400
[ 6.477270] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:02.1: [8086:0e05] type 01 class 0x060400
[ 6.477270] pci 0000:00:02.1: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:02.2: [8086:0e06] type 01 class 0x060400
[ 6.477270] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:02.3: [8086:0e07] type 01 class 0x060400
[ 6.477270] pci 0000:00:02.3: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:03.0: [8086:0e08] type 01 class 0x060400
[ 6.477270] pci 0000:00:03.0: enabling Extended Tags
[ 6.477270] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:03.1: [8086:0e09] type 01 class 0x060400
[ 6.477270] pci 0000:00:03.1: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:03.2: [8086:0e0a] type 01 class 0x060400
[ 6.477270] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:03.3: [8086:0e0b] type 01 class 0x060400
[ 6.477270] pci 0000:00:03.3: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:05.0: [8086:0e28] type 00 class 0x088000
[ 6.477270] pci 0000:00:05.2: [8086:0e2a] type 00 class 0x088000
[ 6.477270] pci 0000:00:05.4: [8086:0e2c] type 00 class 0x080020
[ 6.477270] pci 0000:00:05.4: reg 0x10: [mem 0xfb304000-0xfb304fff]
[ 6.477270] pci 0000:00:06.0: [8086:0e10] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.1: [8086:0e11] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.2: [8086:0e12] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.3: [8086:0e13] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.4: [8086:0e14] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.5: [8086:0e15] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.6: [8086:0e16] type 00 class 0x088000
[ 6.477270] pci 0000:00:06.7: [8086:0e17] type 00 class 0x088000
[ 6.477270] pci 0000:00:07.0: [8086:0e18] type 00 class 0x088000
[ 6.477270] pci 0000:00:07.1: [8086:0e19] type 00 class 0x088000
[ 6.477270] pci 0000:00:07.2: [8086:0e1a] type 00 class 0x088000
[ 6.477270] pci 0000:00:07.3: [8086:0e1b] type 00 class 0x088000
[ 6.477270] pci 0000:00:07.4: [8086:0e1c] type 00 class 0x088000
[ 6.477270] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
[ 6.477270] pci 0000:00:1a.0: reg 0x10: [mem 0xfb302000-0xfb3023ff]
[ 6.477270] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
[ 6.477270] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:1c.0: Enabling MPC IRBNCE
[ 6.477270] pci 0000:00:1c.0: Intel PCH root port ACS workaround enabled
[ 6.477270] pci 0000:00:1c.1: [8086:1e12] type 01 class 0x060400
[ 6.477270] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:1c.1: Enabling MPC IRBNCE
[ 6.477270] pci 0000:00:1c.1: Intel PCH root port ACS workaround enabled
[ 6.477270] pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400
[ 6.477270] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:1c.4: Enabling MPC IRBNCE
[ 6.477270] pci 0000:00:1c.4: Intel PCH root port ACS workaround enabled
[ 6.477270] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
[ 6.477270] pci 0000:00:1d.0: reg 0x10: [mem 0xfb301000-0xfb3013ff]
[ 6.477270] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 6.477270] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
[ 6.477270] pci 0000:00:1f.0: [8086:1e48] type 00 class 0x060100
[ 6.477270] pci 0000:00:1f.2: [8086:1e02] type 00 class 0x010601
[ 6.477270] pci 0000:00:1f.2: reg 0x10: [io 0xf070-0xf077]
[ 6.477270] pci 0000:00:1f.2: reg 0x14: [io 0xf060-0xf063]
[ 6.477270] pci 0000:00:1f.2: reg 0x18: [io 0xf050-0xf057]
[ 6.477270] pci 0000:00:1f.2: reg 0x1c: [io 0xf040-0xf043]
[ 6.477270] pci 0000:00:1f.2: reg 0x20: [io 0xf020-0xf03f]
[ 6.477270] pci 0000:00:1f.2: reg 0x24: [mem 0xfb300000-0xfb3007ff]
[ 6.477270] pci 0000:00:1f.2: PME# supported from D3hot
[ 6.477270] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
[ 6.477270] pci 0000:00:1f.3: reg 0x10: [mem 0x3ffffff00000-0x3ffffff000ff 64bit]
[ 6.477270] pci 0000:00:1f.3: reg 0x20: [io 0xf000-0xf01f]
[ 6.477270] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 6.477270] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 6.477270] pci 0000:03:00.0: [10de:01d3] type 00 class 0x030000
[ 6.477270] pci 0000:03:00.0: reg 0x10: [mem 0xfa000000-0xfaffffff]
[ 6.477270] pci 0000:03:00.0: reg 0x14: [mem 0xe0000000-0xefffffff 64bit pref]
[ 6.477270] pci 0000:03:00.0: reg 0x1c: [mem 0xf9000000-0xf9ffffff 64bit]
[ 6.477270] pci 0000:03:00.0: reg 0x30: [mem 0xfb000000-0xfb01ffff pref]
[ 6.477270] pci 0000:03:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
[ 6.477270] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 6.477270] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 6.477270] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 6.477270] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 6.477270] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 6.477270] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 6.477270] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 6.477270] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 6.477270] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 6.477270] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 6.477270] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 6.477270] pci 0000:0c:00.0: [1106:3483] type 00 class 0x0c0330
[ 6.477270] pci 0000:0c:00.0: reg 0x10: [mem 0xfb200000-0xfb200fff 64bit]
[ 6.477270] pci 0000:0c:00.0: PME# supported from D0 D3cold
[ 6.477270] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 6.477270] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 6.477270] pci 0000:0d:00.0: [10ec:8168] type 00 class 0x020000
[ 6.477270] pci 0000:0d:00.0: reg 0x10: [io 0xe000-0xe0ff]
[ 6.477270] pci 0000:0d:00.0: reg 0x18: [mem 0xfb104000-0xfb104fff 64bit]
[ 6.477270] pci 0000:0d:00.0: reg 0x20: [mem 0xfb100000-0xfb103fff 64bit]
[ 6.477270] pci 0000:0d:00.0: supports D1 D2
[ 6.477270] pci 0000:0d:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 6.477270] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 6.477270] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 6.477270] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 6.477270] pci_bus 0000:0e: extended config space not accessible
[ 6.477270] pci 0000:00:1e.0: PCI bridge to [bus 0e] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [io 0x0000-0x03af window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [io 0x03e0-0x0cf7 window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [io 0x03b0-0x03df window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000dffff window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [mem 0xcc000000-0xffffffff window] (subtractive decode)
[ 6.477270] pci 0000:00:1e.0: bridge window [mem 0x440000000-0x3fffffffffff window] (subtractive decode)
[ 6.477270] xen: registering gsi 13 triggering 1 polarity 0
[ 6.477270] ACPI: PCI Root Bridge [UNC0] (domain 0000 [bus ff])
[ 6.477270] acpi PNP0A03:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 6.477270] acpi PNP0A03:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR]
[ 6.477270] PCI host bridge to bus 0000:ff
[ 6.477270] pci_bus 0000:ff: root bus resource [bus ff]
[ 6.477270] pci 0000:ff:08.0: [8086:0e80] type 00 class 0x088000
[ 6.477270] pci 0000:ff:08.2: [8086:0e32] type 00 class 0x110100
[ 6.477270] pci 0000:ff:08.3: [8086:0e83] type 00 class 0x088000
[ 6.477270] pci 0000:ff:08.4: [8086:0e84] type 00 class 0x088000
[ 6.477270] pci 0000:ff:08.5: [8086:0e85] type 00 class 0x088000
[ 6.477270] pci 0000:ff:08.6: [8086:0e86] type 00 class 0x088000
[ 6.477270] pci 0000:ff:08.7: [8086:0e87] type 00 class 0x088000
[ 6.477270] pci 0000:ff:09.0: [8086:0e90] type 00 class 0x088000
[ 6.477270] pci 0000:ff:09.2: [8086:0e33] type 00 class 0x110100
[ 6.477270] pci 0000:ff:09.3: [8086:0e93] type 00 class 0x088000
[ 6.477270] pci 0000:ff:09.4: [8086:0e94] type 00 class 0x088000
[ 6.477270] pci 0000:ff:09.5: [8086:0e95] type 00 class 0x088000
[ 6.477270] pci 0000:ff:09.6: [8086:0e96] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0a.0: [8086:0ec0] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0a.1: [8086:0ec1] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0a.2: [8086:0ec2] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0a.3: [8086:0ec3] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0b.0: [8086:0e1e] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0b.3: [8086:0e1f] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.0: [8086:0ee0] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.1: [8086:0ee2] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.2: [8086:0ee4] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.3: [8086:0ee6] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.4: [8086:0ee8] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0c.5: [8086:0eea] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.0: [8086:0ee1] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.1: [8086:0ee3] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.2: [8086:0ee5] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.3: [8086:0ee7] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.4: [8086:0ee9] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0d.5: [8086:0eeb] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0e.0: [8086:0ea0] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0e.1: [8086:0e30] type 00 class 0x110100
[ 6.477270] pci 0000:ff:0f.0: [8086:0ea8] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0f.1: [8086:0e71] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0f.2: [8086:0eaa] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0f.3: [8086:0eab] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0f.4: [8086:0eac] type 00 class 0x088000
[ 6.477270] pci 0000:ff:0f.5: [8086:0ead] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.0: [8086:0eb0] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.1: [8086:0eb1] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.2: [8086:0eb2] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.3: [8086:0eb3] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.4: [8086:0eb4] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.5: [8086:0eb5] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.6: [8086:0eb6] type 00 class 0x088000
[ 6.477270] pci 0000:ff:10.7: [8086:0eb7] type 00 class 0x088000
[ 6.477270] pci 0000:ff:13.0: [8086:0e1d] type 00 class 0x088000
[ 6.477270] pci 0000:ff:13.1: [8086:0e34] type 00 class 0x110100
[ 6.477270] pci 0000:ff:13.4: [8086:0e81] type 00 class 0x088000
[ 6.477270] pci 0000:ff:13.5: [8086:0e36] type 00 class 0x110100
[ 6.477270] pci 0000:ff:16.0: [8086:0ec8] type 00 class 0x088000
[ 6.477270] pci 0000:ff:16.1: [8086:0ec9] type 00 class 0x088000
[ 6.477270] pci 0000:ff:16.2: [8086:0eca] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1c.0: [8086:0e60] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1c.1: [8086:0e38] type 00 class 0x110100
[ 6.477270] pci 0000:ff:1d.0: [8086:0e68] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1d.1: [8086:0e79] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1d.2: [8086:0e6a] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1d.3: [8086:0e6b] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1d.4: [8086:0e6c] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1d.5: [8086:0e6d] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.0: [8086:0ef0] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.1: [8086:0ef1] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.2: [8086:0ef2] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.3: [8086:0ef3] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.4: [8086:0ef4] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.5: [8086:0ef5] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.6: [8086:0ef6] type 00 class 0x088000
[ 6.477270] pci 0000:ff:1e.7: [8086:0ef7] type 00 class 0x088000
[ 6.477270] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[ 6.477270] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[ 6.477270] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 6.477270] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 *4 5 6 10 11 12 14 15)
[ 6.477270] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 6.477270] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 6.477270] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 6.477270] ACPI: PCI Interrupt Link [LNKH] (IRQs *3 4 5 6 7 10 11 12 14 15)
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 4/0x1 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 5/0x3 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 6/0x5 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 7/0x7 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 8/0x8 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 9/0x9 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 10/0xa ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 11/0xb ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 12/0x10 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 13/0x11 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 14/0x12 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 15/0x13 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 16/0x14 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 17/0x15 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 18/0x16 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 19/0x17 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 20/0x18 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 21/0x19 ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 22/0x1a ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.477270] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 23/0x1b ignored.
[ 6.477270] ACPI: Unable to map lapic to logical cpu number
[ 6.873274] xen:balloon: Initialising balloon driver
[ 6.873274] iommu: Default domain type: Translated
[ 6.873313] pci 0000:03:00.0: vgaarb: setting as boot VGA device
[ 6.873313] pci 0000:03:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[ 6.873313] pci 0000:03:00.0: vgaarb: bridge control possible
[ 6.873313] vgaarb: loaded
[ 6.873313] EDAC MC: Ver: 3.0.0
[ 6.878205] NetLabel: Initializing
[ 6.878205] NetLabel: domain hash size = 128
[ 6.878205] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO
[ 6.878205] NetLabel: unlabeled traffic allowed by default
[ 6.878205] PCI: Using ACPI for IRQ routing
[ 6.905293] PCI: pci_cache_line_size set to 64 bytes
[ 6.905293] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 6.905293] e820: reserve RAM buffer [mem 0x80062000-0x83ffffff]
[ 7.377274] clocksource: Switched to clocksource xen
[ 8.237323] VFS: Disk quotas dquot_6.6.0
[ 8.237323] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 8.237323] hugetlbfs: disabling because there are no supported hugepage sizes
[ 8.237323] AppArmor: AppArmor Filesystem Enabled
[ 8.237323] pnp: PnP ACPI init
[ 8.237323] system 00:00: [mem 0xfc000000-0xfcffffff] has been reserved
[ 8.237323] system 00:00: [mem 0xfd000000-0xfdffffff] has been reserved
[ 8.237323] system 00:00: [mem 0xfe000000-0xfeafffff] has been reserved
[ 8.237323] system 00:00: [mem 0xfeb00000-0xfebfffff] has been reserved
[ 8.237323] system 00:00: [mem 0xfed00400-0xfed3ffff] could not be reserved
[ 8.237323] system 00:00: [mem 0xfed45000-0xfedfffff] has been reserved
[ 8.237323] system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved
[ 8.237323] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 8.237323] system 00:01: [mem 0xfbffc000-0xfbffdfff] could not be reserved
[ 8.237323] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 8.237323] system 00:02: [io 0x0a00-0x0a1f] has been reserved
[ 8.237323] system 00:02: [io 0x0a20-0x0a2f] has been reserved
[ 8.237323] system 00:02: [io 0x0a30-0x0a3f] has been reserved
[ 8.237323] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 8.237323] xen: registering gsi 1 triggering 1 polarity 0
[ 8.237323] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
[ 8.237323] xen: registering gsi 12 triggering 1 polarity 0
[ 8.237323] pnp 00:04: Plug and Play ACPI device, IDs PNP0f03 PNP0f13 (active)
[ 8.237323] xen: registering gsi 8 triggering 1 polarity 0
[ 8.237323] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 8.237323] system 00:06: [io 0x04d0-0x04d1] has been reserved
[ 8.237323] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 8.237323] system 00:07: [io 0x0400-0x0453] has been reserved
[ 8.237323] system 00:07: [io 0x0458-0x047f] has been reserved
[ 8.237323] system 00:07: [io 0x1180-0x119f] has been reserved
[ 8.237323] system 00:07: [io 0x0500-0x057f] has been reserved
[ 8.237323] system 00:07: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 8.237323] system 00:07: [mem 0xfec00000-0xfecfffff] could not be reserved
[ 8.237323] system 00:07: [mem 0xff000000-0xffffffff] has been reserved
[ 8.237323] system 00:07: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 8.237323] system 00:08: [io 0x0454-0x0457] has been reserved
[ 8.237323] system 00:08: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 8.237323] pnp: PnP ACPI: found 9 devices
[ 8.245304] PM-Timer failed consistency check (0xffffff) - aborting.
[ 8.245304] NET: Registered protocol family 2
[ 8.245304] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[ 8.245304] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 8.245304] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 8.245304] TCP: Hash tables configured (established 16384 bind 16384)
[ 8.245304] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 8.245304] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 8.245304] NET: Registered protocol family 1
[ 8.245304] NET: Registered protocol family 44
[ 8.245304] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 8.245304] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 8.245304] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 8.245304] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 8.245304] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 8.245304] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 8.245304] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 8.245304] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 8.245304] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 8.245304] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 8.245304] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 8.245304] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 8.245304] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 8.245304] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 8.245304] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 8.245304] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 8.245304] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 8.245304] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 8.245304] pci 0000:00:1e.0: PCI bridge to [bus 0e]
[ 8.245304] pci_bus 0000:00: resource 4 [io 0x0000-0x03af window]
[ 8.245304] pci_bus 0000:00: resource 5 [io 0x03e0-0x0cf7 window]
[ 8.245304] pci_bus 0000:00: resource 6 [io 0x03b0-0x03df window]
[ 8.245304] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 8.245304] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 8.245304] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 8.245304] pci_bus 0000:00: resource 10 [mem 0xcc000000-0xffffffff window]
[ 8.245304] pci_bus 0000:00: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 8.245304] pci_bus 0000:03: resource 1 [mem 0xf9000000-0xfb0fffff]
[ 8.245304] pci_bus 0000:03: resource 2 [mem 0xe0000000-0xefffffff 64bit pref]
[ 8.245304] pci_bus 0000:0c: resource 1 [mem 0xfb200000-0xfb2fffff]
[ 8.245304] pci_bus 0000:0d: resource 0 [io 0xe000-0xefff]
[ 8.245304] pci_bus 0000:0d: resource 1 [mem 0xfb100000-0xfb1fffff]
[ 8.245304] pci_bus 0000:0e: resource 4 [io 0x0000-0x03af window]
[ 8.245304] pci_bus 0000:0e: resource 5 [io 0x03e0-0x0cf7 window]
[ 8.245304] pci_bus 0000:0e: resource 6 [io 0x03b0-0x03df window]
[ 8.245304] pci_bus 0000:0e: resource 7 [io 0x0d00-0xffff window]
[ 8.245304] pci_bus 0000:0e: resource 8 [mem 0x000a0000-0x000bffff window]
[ 8.245304] pci_bus 0000:0e: resource 9 [mem 0x000c0000-0x000dffff window]
[ 8.245304] pci_bus 0000:0e: resource 10 [mem 0xcc000000-0xffffffff window]
[ 8.245304] pci_bus 0000:0e: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 8.245304] pci 0000:00:05.0: disabled boot interrupts on device [8086:0e28]
[ 8.245304] xen: registering gsi 16 triggering 0 polarity 1
[ 8.245304] xen: --> pirq=16 -> irq=16 (gsi=16)
[ 8.245304] xen: registering gsi 23 triggering 0 polarity 1
[ 8.245304] xen: --> pirq=23 -> irq=23 (gsi=23)
[ 8.245304] pci 0000:03:00.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[ 8.245304] xen: registering gsi 16 triggering 0 polarity 1
[ 8.245304] Already setup the GSI :16
[ 8.245304] xen: registering gsi 17 triggering 0 polarity 1
[ 8.245304] xen: --> pirq=17 -> irq=17 (gsi=17)
[ 8.245304] PCI: CLS 64 bytes, default 64
[ 8.245304] Trying to unpack rootfs image as initramfs...
[ 12.257295] Freeing initrd memory: 34772K
[ 12.397037] Initialise system trusted keyrings
[ 12.397037] Key type blacklist registered
[ 12.397291] workingset: timestamp_bits=36 max_order=18 bucket_order=0
[ 12.397291] zbud: loaded
[ 12.398970] integrity: Platform Keyring initialized
[ 12.398970] Key type asymmetric registered
[ 12.398970] Asymmetric key parser 'x509' registered
[ 12.398970] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 12.399150] io scheduler mq-deadline registered
[ 12.399186] xen: registering gsi 26 triggering 0 polarity 1
[ 12.399186] xen: --> pirq=26 -> irq=26 (gsi=26)
[ 12.399186] xen: registering gsi 26 triggering 0 polarity 1
[ 12.399186] Already setup the GSI :26
[ 12.399186] xen: registering gsi 32 triggering 0 polarity 1
[ 12.399186] xen: --> pirq=32 -> irq=32 (gsi=32)
[ 12.399186] xen: registering gsi 32 triggering 0 polarity 1
[ 12.399186] Already setup the GSI :32
[ 12.401286] xen: registering gsi 32 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :32
[ 12.401286] xen: registering gsi 32 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :32
[ 12.401286] xen: registering gsi 40 triggering 0 polarity 1
[ 12.401286] xen: --> pirq=40 -> irq=40 (gsi=40)
[ 12.401286] xen: registering gsi 40 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :40
[ 12.401286] xen: registering gsi 40 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :40
[ 12.401286] xen: registering gsi 40 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :40
[ 12.401286] xen: registering gsi 17 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :17
[ 12.401286] xen: registering gsi 17 triggering 0 polarity 1
[ 12.401286] Already setup the GSI :17
[ 12.403186] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 12.403186] intel_idle: MWAIT substates: 0x1120
[ 12.405621] Monitor-Mwait will be used to enter C-1 state
[ 12.405641] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 12.405641] intel_idle: v0.5.1 model 0x3E
[ 12.405641] intel_idle: intel_idle yielding to none
[ 12.405813] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 12.405935] ACPI: \_SB_.SCK0.C002: Found 1 idle states
[ 12.405935] ACPI: \_SB_.SCK0.C004: Found 1 idle states
[ 12.405935] ACPI: \_SB_.SCK0.C006: Found 1 idle states
[ 12.407425] xen_mcelog: /dev/mcelog registered by Xen
[ 12.408080] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 12.408870] hpet_acpi_add: no address or irqs in _CRS
[ 12.408893] Linux agpgart interface v0.103
[ 12.408989] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
[ 12.408990] AMD-Vi: AMD IOMMUv2 functionality not available on this system
[ 12.409390] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
[ 12.410022] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 12.410028] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 12.410254] mousedev: PS/2 mouse device common for all mice
[ 12.410337] rtc_cmos 00:05: RTC can wake from S4
[ 12.410717] rtc_cmos 00:05: registered as rtc0
[ 12.410794] rtc_cmos 00:05: setting system clock to 2021-01-29T17:56:52 UTC (1611943012)
[ 12.410816] rtc_cmos 00:05: alarms up to one month, y3k, 114 bytes nvram
[ 12.410824] intel_pstate: CPU model not supported
[ 12.410947] ledtrig-cpu: registered to indicate activity on CPUs
[ 12.411696] NET: Registered protocol family 10
[ 12.431563] Segment Routing with IPv6
[ 12.431563] mip6: Mobile IPv6
[ 12.431563] NET: Registered protocol family 17
[ 12.432415] mpls_gso: MPLS GSO support
[ 12.432536] IPI shorthand broadcast: enabled
[ 12.432536] sched_clock: Marking stable (12354092564, 78444069)->(12687811846, -255275213)
[ 12.432928] registered taskstats version 1
[ 12.432928] Loading compiled-in X.509 certificates
[ 13.786527] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1'
[ 13.786527] Loaded X.509 cert 'Debian Secure Boot Signer 2020: 00b55eb3b9'
[ 13.786527] zswap: loaded using pool lzo/zbud
[ 13.792860] Key type ._fscrypt registered
[ 13.792860] Key type .fscrypt registered
[ 13.792868] Key type fscrypt-provisioning registered
[ 13.792883] AppArmor: AppArmor sha1 policy hashing enabled
[ 13.795488] Freeing unused kernel image (initmem) memory: 2380K
[ 16.493336] Write protecting the kernel read-only data: 18432k
[ 16.507036] Freeing unused kernel image (text/rodata gap) memory: 2040K
[ 16.507412] Freeing unused kernel image (rodata/data gap) memory: 36K
[ 18.281320] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[ 18.282999] Run /init as init process
[ 18.283002] with arguments:
[ 18.283003] /init
[ 18.283003] placeholder
[ 18.283004] with environment:
[ 18.283005] HOME=/
[ 18.283006] TERM=linux
[ 21.195344] SCSI subsystem initialized
[ 21.315310] xen: registering gsi 18 triggering 0 polarity 1
[ 21.315310] xen: --> pirq=18 -> irq=18 (gsi=18)
[ 21.315310] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[ 21.315310] ACPI: bus type USB registered
[ 21.315310] usbcore: registered new interface driver usbfs
[ 21.315310] usbcore: registered new interface driver hub
[ 21.316043] i2c i2c-0: 4/4 memory slots populated (from DMI)
[ 21.316043] usbcore: registered new device driver usb
[ 22.086097] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 22.181280] libata version 3.00 loaded.
[ 22.416732] ehci-pci: EHCI PCI platform driver
[ 22.416868] xen: registering gsi 16 triggering 0 polarity 1
[ 22.416874] Already setup the GSI :16
[ 22.416990] ehci-pci 0000:00:1a.0: EHCI Host Controller
[ 22.416999] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
[ 22.417033] ehci-pci 0000:00:1a.0: debug port 2
[ 22.421006] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
[ 22.421064] ehci-pci 0000:00:1a.0: irq 16, io mem 0xfb302000
[ 22.456762] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[ 22.456916] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 22.456919] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 22.456921] usb usb1: Product: EHCI Host Controller
[ 22.456922] usb usb1: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 22.456924] usb usb1: SerialNumber: 0000:00:1a.0
[ 22.487110] hub 1-0:1.0: USB hub found
[ 22.487136] hub 1-0:1.0: 2 ports detected
[ 22.487525] xen: registering gsi 23 triggering 0 polarity 1
[ 22.487530] Already setup the GSI :23
[ 22.487608] ehci-pci 0000:00:1d.0: EHCI Host Controller
[ 22.487616] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
[ 22.487656] ehci-pci 0000:00:1d.0: debug port 2
[ 22.491597] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
[ 22.491653] ehci-pci 0000:00:1d.0: irq 23, io mem 0xfb301000
[ 22.513689] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 22.513858] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 22.513861] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 22.513862] usb usb2: Product: EHCI Host Controller
[ 22.513864] usb usb2: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 22.513866] usb usb2: SerialNumber: 0000:00:1d.0
[ 22.537207] hub 2-0:1.0: USB hub found
[ 22.537230] hub 2-0:1.0: 2 ports detected
[ 22.814953] ahci 0000:00:1f.2: version 3.0
[ 22.815007] xen: registering gsi 19 triggering 0 polarity 1
[ 22.815007] xen: --> pirq=19 -> irq=19 (gsi=19)
[ 22.815007] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
[ 22.815007] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst
[ 22.824871] usb 1-1: new high-speed USB device number 2 using ehci-pci
[ 22.885295] usb 2-1: new high-speed USB device number 2 using ehci-pci
[ 22.977615] usb 1-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 22.977618] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 22.977919] hub 1-1:1.0: USB hub found
[ 22.977991] hub 1-1:1.0: 6 ports detected
[ 23.021300] xen: registering gsi 16 triggering 0 polarity 1
[ 23.033303] Already setup the GSI :16
[ 23.041614] usb 2-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 23.041617] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 23.041918] hub 2-1:1.0: USB hub found
[ 23.041990] hub 2-1:1.0: 8 ports detected
[ 23.265296] usb 1-1.2: new low-speed USB device number 3 using ehci-pci
[ 23.336655] usb 2-1.4: new high-speed USB device number 3 using ehci-pci
[ 23.349748] scsi host0: ahci
[ 23.350103] scsi host1: ahci
[ 23.350396] scsi host2: ahci
[ 23.350706] scsi host3: ahci
[ 23.351013] scsi host4: ahci
[ 23.351307] scsi host5: ahci
[ 23.351307] ata1: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300100 irq 89
[ 23.351307] ata2: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300180 irq 89
[ 23.351307] ata3: DUMMY
[ 23.351307] ata4: DUMMY
[ 23.351307] ata5: DUMMY
[ 23.351307] ata6: DUMMY
[ 23.379592] usb 1-1.2: New USB device found, idVendor=099a, idProduct=610c, bcdDevice= 0.01
[ 23.379595] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 23.379597] usb 1-1.2: Product: USB Multimedia Keyboard
[ 23.379598] usb 1-1.2: Manufacturer:
[ 23.452466] usb 2-1.4: New USB device found, idVendor=148f, idProduct=7601, bcdDevice= 0.00
[ 23.452469] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 23.452471] usb 2-1.4: Product: 802.11 n WLAN
[ 23.452473] usb 2-1.4: Manufacturer: MediaTek
[ 23.452475] usb 2-1.4: SerialNumber: 1.0
[ 24.725275] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 24.725275] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 24.727270] ata1.00: ATA-11: KINGSTON SUV400S37120G, 0C3FD6SD, max UDMA/133
[ 24.727270] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 24.727720] ata1.00: configured for UDMA/133
[ 24.727720] scsi 0:0:0:0: Direct-Access ATA KINGSTON SUV400S D6SD PQ: 0 ANSI: 5
[ 24.747393] ata2.00: ATA-8: KINGSTON SV300S37A120G, 525ABBF0, max UDMA/133
[ 24.747393] ata2.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 24.757282] hid: raw HID events driver (C) Jiri Kosina
[ 24.763317] ata2.00: configured for UDMA/133
[ 24.763317] scsi 1:0:0:0: Direct-Access ATA KINGSTON SV300S3 BBF0 PQ: 0 ANSI: 5
[ 24.927751] xen: registering gsi 17 triggering 0 polarity 1
[ 24.927756] Already setup the GSI :17
[ 24.947759] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 24.947768] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 3
[ 24.947893] xhci_hcd 0000:0c:00.0: hcc params 0x002841eb hci version 0x100 quirks 0x0000000000000890
[ 24.948260] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 24.948263] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 24.948265] usb usb3: Product: xHCI Host Controller
[ 24.948267] usb usb3: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 24.948269] usb usb3: SerialNumber: 0000:0c:00.0
[ 24.948441] hub 3-0:1.0: USB hub found
[ 24.948465] hub 3-0:1.0: 1 port detected
[ 24.948713] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 24.948719] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 4
[ 24.948723] xhci_hcd 0000:0c:00.0: Host supports USB 3.0 SuperSpeed
[ 24.948910] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
[ 24.948912] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 24.948914] usb usb4: Product: xHCI Host Controller
[ 24.948915] usb usb4: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 24.948917] usb usb4: SerialNumber: 0000:0c:00.0
[ 24.949094] hub 4-0:1.0: USB hub found
[ 24.949120] hub 4-0:1.0: 4 ports detected
[ 25.065278] libphy: r8169: probed
[ 25.113280] r8169 0000:0d:00.0 eth0: RTL8168h/8111h, 00:e0:4c:0a:52:97, XID 541, IRQ 90
[ 25.113280] r8169 0000:0d:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
[ 25.170025] usbcore: registered new interface driver usbhid
[ 25.170027] usbhid: USB HID core driver
[ 25.309303] usb 3-1: new high-speed USB device number 2 using xhci_hcd
[ 25.458727] usb 3-1: New USB device found, idVendor=2109, idProduct=3431, bcdDevice= 4.20
[ 25.458730] usb 3-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[ 25.458732] usb 3-1: Product: USB2.0 Hub
[ 25.459730] hub 3-1:1.0: USB hub found
[ 25.460053] hub 3-1:1.0: 4 ports detected
[ 25.466414] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 25.466417] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 25.466426] sd 1:0:0:0: [sdb] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 25.466446] sd 0:0:0:0: [sda] Write Protect is off
[ 25.466448] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 25.466457] sd 1:0:0:0: [sdb] Write Protect is off
[ 25.466457] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 25.466499] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 25.466508] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 25.659008] r8169 0000:0d:00.0 enp13s0: renamed from eth0
[ 26.040096] input: USB Multimedia Keyboard as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:099A:610C.0001/input/input3
[ 27.388934] hid-generic 0003:099A:610C.0001: input,hidraw0: USB HID v1.00 Keyboard [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input0
[ 27.388942] input: USB Multimedia Keyboard Consumer Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input4
[ 28.801323] input: USB Multimedia Keyboard System Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input5
[ 28.805004] hid-generic 0003:099A:610C.0002: input,hidraw1: USB HID v1.00 Device [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input1
[ 28.808846] sda: sda1 sda2
[ 28.809287] sd 0:0:0:0: [sda] Attached SCSI disk
[ 28.812010] sd 1:0:0:0: [sdb] Attached SCSI disk
[ 28.875553] device-mapper: uevent: version 1.0.3
[ 28.875612] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[ 45.150923] PM: Image not found (code -22)
[ 49.297286] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 50.597293] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist.
[ 50.695182] systemd[1]: Inserted module 'autofs4'
[ 50.739926] systemd[1]: systemd 247.2-5 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
[ 50.739926] systemd[1]: Detected architecture x86-64.
[ 50.743491] systemd[1]: Set hostname to <debian>.
[ 51.984512] systemd-sysv-generator[223]: SysV service '/etc/init.d/xen' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 52.017700] systemd-sysv-generator[223]: SysV service '/etc/init.d/exim4' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 52.017818] systemd-sysv-generator[223]: SysV service '/etc/init.d/xencommons' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 52.020451] systemd-sysv-generator[223]: SysV service '/etc/init.d/isc-dhcp-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 53.351017] systemd[1]: /lib/systemd/system/virtlogd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-sock → /run/libvirt/virtlogd-sock; please update the unit file accordingly.
[ 53.360023] systemd[1]: /lib/systemd/system/virtlogd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-admin-sock → /run/libvirt/virtlogd-admin-sock; please update the unit file accordingly.
[ 53.360552] systemd[1]: /lib/systemd/system/virtlockd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-sock → /run/libvirt/virtlockd-sock; please update the unit file accordingly.
[ 53.361494] systemd[1]: /lib/systemd/system/virtlockd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-admin-sock → /run/libvirt/virtlockd-admin-sock; please update the unit file accordingly.
[ 53.413285] systemd[1]: Queued start job for default target Graphical Interface.
[ 53.415095] systemd[1]: Created slice Virtual Machine and Container Slice.
[ 53.415095] systemd[1]: Created slice system-getty.slice.
[ 53.417278] systemd[1]: Created slice system-modprobe.slice.
[ 53.417278] systemd[1]: Created slice system-serial\x2dgetty.slice.
[ 53.417278] systemd[1]: Created slice User and Session Slice.
[ 53.417278] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[ 53.421277] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[ 53.421277] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
[ 53.421277] systemd[1]: Reached target Local Encrypted Volumes.
[ 53.421277] systemd[1]: Reached target Paths.
[ 53.421277] systemd[1]: Reached target Remote File Systems.
[ 53.421277] systemd[1]: Reached target Slices.
[ 53.421277] systemd[1]: Reached target Libvirt guests shutdown.
[ 53.421277] systemd[1]: Listening on Device-mapper event daemon FIFOs.
[ 53.425293] systemd[1]: Listening on LVM2 poll daemon socket.
[ 53.427435] systemd[1]: Listening on Syslog Socket.
[ 53.427435] systemd[1]: Listening on fsck to fsckd communication Socket.
[ 53.427435] systemd[1]: Listening on initctl Compatibility Named Pipe.
[ 53.429293] systemd[1]: Listening on Journal Audit Socket.
[ 53.429293] systemd[1]: Listening on Journal Socket (/dev/log).
[ 53.429293] systemd[1]: Listening on Journal Socket.
[ 53.429293] systemd[1]: Listening on udev Control Socket.
[ 53.429293] systemd[1]: Listening on udev Kernel Socket.
[ 53.433293] systemd[1]: Condition check resulted in Huge Pages File System being skipped.
[ 53.433293] systemd[1]: Mounting POSIX Message Queue File System...
[ 53.439673] systemd[1]: Mounting Kernel Debug File System...
[ 53.441281] systemd[1]: Mounting Kernel Trace File System...
[ 53.441281] systemd[1]: Finished Availability of block devices.
[ 53.447674] systemd[1]: Starting Set the console keyboard layout...
[ 53.450742] systemd[1]: Starting Create list of static device nodes for the current kernel...
[ 53.454177] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[ 53.721279] systemd[1]: Starting Load Kernel Module configfs...
[ 54.705280] systemd[1]: Starting Load Kernel Module drm...
[ 54.709283] systemd[1]: Starting Load Kernel Module fuse...
[ 54.712447] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
[ 54.712447] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[ 55.025282] systemd[1]: Starting Journal Service...
[ 55.029282] systemd[1]: Starting Load Kernel Modules...
[ 55.033280] systemd[1]: Starting Remount Root and Kernel File Systems...
[ 55.034453] systemd[1]: Starting Coldplug All udev Devices...
[ 55.041283] systemd[1]: Mounted POSIX Message Queue File System.
[ 55.041283] systemd[1]: Mounted Kernel Debug File System.
[ 55.041283] systemd[1]: Mounted Kernel Trace File System.
[ 55.045281] systemd[1]: Finished Set the console keyboard layout.
[ 55.046410] fuse: init (API version 7.32)
[ 55.046757] systemd[1]: Finished Create list of static device nodes for the current kernel.
[ 55.048441] systemd[1]: modprobe@configfs.service: Succeeded.
[ 55.049283] systemd[1]: Finished Load Kernel Module configfs.
[ 55.050573] systemd[1]: modprobe@drm.service: Succeeded.
[ 55.052000] systemd[1]: Finished Load Kernel Module drm.
[ 55.053285] systemd[1]: modprobe@fuse.service: Succeeded.
[ 55.054089] systemd[1]: Finished Load Kernel Module fuse.
[ 55.333275] systemd[1]: Mounting FUSE Control File System...
[ 55.384799] xen:xen_evtchn: Event-channel device installed
[ 56.387417] systemd[1]: Mounting Kernel Configuration File System...
[ 56.391509] systemd[1]: Started Journal Service.
[ 56.396033] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[ 56.445432] xen_pciback: backend is vpci
[ 59.081658] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input6
[ 60.221691] audit: type=1400 audit(1611943060.224:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="lsb_release" pid=287 comm="apparmor_parser"
[ 60.221691] audit: type=1400 audit(1611943060.224:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd" pid=284 comm="apparmor_parser"
[ 60.221691] audit: type=1400 audit(1611943060.224:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd//qemu_bridge_helper" pid=284 comm="apparmor_parser"
[ 60.225283] audit: type=1400 audit(1611943060.224:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=286 comm="apparmor_parser"
[ 60.226444] audit: type=1400 audit(1611943060.224:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=286 comm="apparmor_parser"
[ 60.226444] audit: type=1400 audit(1611943060.224:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=286 comm="apparmor_parser"
[ 60.226553] audit: type=1400 audit(1611943060.224:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe" pid=285 comm="apparmor_parser"
[ 60.226553] audit: type=1400 audit(1611943060.224:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe//kmod" pid=285 comm="apparmor_parser"
[ 60.245793] audit: type=1400 audit(1611943060.224:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="virt-aa-helper" pid=290 comm="apparmor_parser"
[ 62.860844] ACPI: Power Button [PWRB]
[ 62.860973] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input7
[ 62.861053] ACPI: Power Button [PWRF]
[ 245.485707] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 245.486137] sd 1:0:0:0: Attached scsi generic sg1 type 0
[ 248.087446] iTCO_vendor_support: vendor-support=0
[ 248.088911] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 248.089188] cfg80211: Loaded X.509 cert 'benh@debian.org: 577e021cb980e0e820821ba7b54b4961b8b4fadf'
[ 248.089502] cfg80211: Loaded X.509 cert 'romain.perier@gmail.com: 3abbc6ec146e09d1b6016ab9d6cf71dd233f0328'
[ 248.089744] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 248.090004] platform regulatory.0: firmware: failed to load regulatory.db (-2)
[ 248.090005] firmware_class: See https://wiki.debian.org/Firmware for information about missing firmware
[ 248.090006] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 248.090009] cfg80211: failed to load regulatory.db
[ 253.471126] input: PC Speaker as /devices/platform/pcspkr/input/input8
[ 253.472753] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[ 253.472800] iTCO_wdt: Found a Panther Point TCO device (Version=2, TCOBASE=0x0460)
[ 253.472989] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[ 256.188761] usb 2-1.4: reset high-speed USB device number 3 using ehci-pci
[ 256.296374] mt7601u 2-1.4:1.0: ASIC revision: 76010001 MAC revision: 76010500
[ 256.298232] mt7601u 2-1.4:1.0: firmware: direct-loading firmware mt7601u.bin
[ 256.298238] mt7601u 2-1.4:1.0: Firmware Version: 0.1.00 Build: 7640 Build time: 201302052146____
[ 256.688353] mt7601u 2-1.4:1.0: EEPROM ver:0d fae:00
[ 261.672127] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
[ 261.672636] usbcore: registered new interface driver mt7601u
[ 290.244106] mt7601u 2-1.4:1.0 wlx20e0160064bd: renamed from wlan0
[ 309.141449] cryptd: max_cpu_qlen set to 1000
[ 309.261291] AVX version of gcm_enc/dec engaged.
[ 309.261291] AES CTR mode by8 optimization enabled
[ 393.890966] wlx20e0160064bd: authenticate with 68:ff:7b:47:86:17
[ 395.610464] wlx20e0160064bd: send auth to 68:ff:7b:47:86:17 (try 1/3)
[ 395.612993] wlx20e0160064bd: authenticated
[ 395.619365] wlx20e0160064bd: associate with 68:ff:7b:47:86:17 (try 1/3)
[ 395.623241] wlx20e0160064bd: RX AssocResp from 68:ff:7b:47:86:17 (capab=0x431 status=0 aid=2)
[ 396.966666] wlx20e0160064bd: associated
[ 397.682487] IPv6: ADDRCONF(NETDEV_CHANGE): wlx20e0160064bd: link becomes ready
[ 409.968202] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 410.004061] br-lan: port 1(enp13s0) entered blocking state
[ 410.004061] br-lan: port 1(enp13s0) entered disabled state
[ 410.004139] device enp13s0 entered promiscuous mode
[ 410.009939] r8169 0000:0d:00.0: firmware: direct-loading firmware rtl_nic/rtl8168h-2.fw
[ 410.568740] Generic FE-GE Realtek PHY r8169-d00:00: attached PHY driver [Generic FE-GE Realtek PHY] (mii_bus:phy_addr=r8169-d00:00, irq=IGNORE)
[ 413.465484] r8169 0000:0d:00.0 enp13s0: Link is Down
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-29 19:31 ` Claudemir Todo Bom
@ 2021-02-01 7:51 ` Jan Beulich
2021-02-01 12:47 ` Jan Beulich
1 sibling, 0 replies; 26+ messages in thread
From: Jan Beulich @ 2021-02-01 7:51 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 29.01.2021 20:31, Claudemir Todo Bom wrote:
> Em sex., 29 de jan. de 2021 às 13:24, Jan Beulich <jbeulich@suse.com> escreveu:
>>
>> On 28.01.2021 14:08, Claudemir Todo Bom wrote:
>>> Em qui., 28 de jan. de 2021 às 06:49, Jan Beulich <jbeulich@suse.com> escreveu:
>>>>
>>>> On 28.01.2021 10:47, Jan Beulich wrote:
>>>>> On 26.01.2021 14:03, Claudemir Todo Bom wrote:
>>>>>> If this information is good for more tests, please send the patch and
>>>>>> I will test it!
>>>>>
>>>>> Here you go. For simplifying analysis it may be helpful if you
>>>>> could limit the number of CPUs in use, e.g. by "maxcpus=4" or
>>>>> at least "smt=0". Provided the problem still reproduces with
>>>>> such options, of course.
>>>>
>>>> Speaking of command line options - it doesn't look like you have
>>>> told us what else you have on the Xen command line, and without
>>>> a serial log this isn't visible (e.g. in your video).
>>>
>>> All tests are done with xen command line:
>>>
>>> dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true
>>> smt=false vga=text-80x50,keep
>>>
>>> and kernel command line:
>>>
>>> loglevel=0 earlyprintk=xen nomodeset
>>>
>>> this way I can get all xen messages on console.
>>>
>>> Attached are the frames I captured from a video, I manually selected
>>> them starting from the first readable frame.
>>
>> I've just sent a pair of patches, with you Cc-ed on the 2nd one.
>> Please give that one a try, with or without the updated debugging
>> patch below. In case of problems I'd of course want to see the
>> output from the debugging patch as well. I think it's up to you
>> whether you also use the first patch from that series - afaict it
>> shouldn't directly affect your case, but I may be wrong.
>
> I've applied both patches, system didn't booted, used following parameters:
>
> xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
> kernel: loglevel=3
>
> The screen cleared right after the initial xen messages and frozen
> there for a few minutes until I restarted the system.
>
> I've added "vga=text-80x25,keep" to the xen command line and
> "nomodeset" to the kernel command line, hoping to get some more info
> and surprisingly this was sufficient to make system boot!
Odd, but as per my reply to the patch submission itself a
few minutes ago, over the weekend I realized a flaw. I do
think this explains the anomalies seen from the log between
CPU0 and and all other CPUs; the problem merely isn't as
severe anymore as it was before as it seems. I also did
realize I ought to be able to mimic your system's behavior;
if so I ought to be able to send out an updated series that
actually had some testing for the specific case. Later
today, hopefully.
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-29 19:31 ` Claudemir Todo Bom
2021-02-01 7:51 ` Jan Beulich
@ 2021-02-01 12:47 ` Jan Beulich
2021-02-01 14:46 ` Claudemir Todo Bom
1 sibling, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-02-01 12:47 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 29.01.2021 20:31, Claudemir Todo Bom wrote:
> I've applied both patches, system didn't booted, used following parameters:
>
> xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
> kernel: loglevel=3
>
> The screen cleared right after the initial xen messages and frozen
> there for a few minutes until I restarted the system.
>
> I've added "vga=text-80x25,keep" to the xen command line and
> "nomodeset" to the kernel command line, hoping to get some more info
> and surprisingly this was sufficient to make system boot!
>
> System prompt took a lot to appear, the kernel driver for the usb
> keyboard loaded after 3 minutes and the driver for the usb wifi dongle
> I am using loaded about five minutes after kernel boot, and I had to
> issue "ifup -a" to get an ip address from the dhcp server, and it took
> almost one minute to get it!
I was able to repro this behavior, by deliberately screwing up
CPU0's TSC early during boot. This of course did make it a lot
easier to find and fix the problem. I've Cc-ed you on the full
3-patch series that I've sent a minute ago, because while you
may continue to opt for ignoring the first patch, you'll now
need the latter two. And as before, the updated debugging patch
below.
Jan
--- a/xen/arch/x86/time.c
+++ b/xen/arch/x86/time.c
@@ -1558,6 +1558,12 @@ static void local_time_calibration(void)
* TSC Reliability check
*/
+static struct {//temp
+ unsigned cpu;
+ signed iter;
+ cycles_t prev, now;
+} check_log[NR_CPUS + 4];
+static unsigned check_idx;//temp
/*
* The Linux original version of this function is
* Copyright (c) 2006, Red Hat, Inc., Ingo Molnar
@@ -1566,6 +1572,7 @@ static void check_tsc_warp(unsigned long
{
static DEFINE_SPINLOCK(sync_lock);
static cycles_t last_tsc;
+unsigned idx, cpu = smp_processor_id();//temp
cycles_t start, now, prev, end;
int i;
@@ -1576,6 +1583,15 @@ static void check_tsc_warp(unsigned long
end = start + tsc_khz * 20ULL;
now = start;
+{//temp
+ spin_lock(&sync_lock);
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = -1;
+ check_log[idx].now = now;
+ spin_unlock(&sync_lock);
+}
+
for ( i = 0; ; i++ )
{
/*
@@ -1610,7 +1626,14 @@ static void check_tsc_warp(unsigned long
{
spin_lock(&sync_lock);
if ( *max_warp < prev - now )
+{//temp
*max_warp = prev - now;
+ idx = check_idx++;
+ check_log[idx].cpu = cpu;
+ check_log[idx].iter = i;
+ check_log[idx].prev = prev;
+ check_log[idx].now = now;
+}
spin_unlock(&sync_lock);
}
}
@@ -1647,6 +1670,12 @@ static void tsc_check_reliability(void)
cpu_relax();
spin_unlock(&lock);
+{//temp
+ unsigned i;
+ printk("CHK[%2u] %lx\n", cpu, tsc_max_warp);//temp
+ for(i = 0; i < ARRAY_SIZE(check_log) && check_log[i].now; ++i)
+ printk("chk[%4u] CPU%-2u %016lx %016lx #%d\n", i, check_log[i].cpu, check_log[i].prev, check_log[i].now, check_log[i].iter);
+}
}
/*
@@ -1661,6 +1690,7 @@ struct calibration_rendezvous {
uint64_t master_tsc_stamp, max_tsc_stamp;
};
+static bool rdzv_log;//temp
static void
time_calibration_rendezvous_tail(const struct calibration_rendezvous *r,
uint64_t old_tsc, uint64_t new_tsc)
@@ -1671,6 +1701,7 @@ time_calibration_rendezvous_tail(const s
c->local_stime = get_s_time_fixed(old_tsc ?: new_tsc);
c->master_stime = r->master_stime;
+if(rdzv_log) printk("RDZV[%2u] t=%016lx(%016lx) s=%012lx(%012lx)\n", smp_processor_id(), c->local_tsc, r->master_tsc_stamp, c->local_stime, r->master_stime);//temp
raise_softirq(TIME_CALIBRATE_SOFTIRQ);
}
@@ -1684,7 +1715,9 @@ static void time_calibration_tsc_rendezv
struct calibration_rendezvous *r = _r;
unsigned int total_cpus = cpumask_weight(&r->cpu_calibration_map);
uint64_t tsc = 0;
+uint64_t adj = 0;//temp
+if(rdzv_log) printk("RDZV[%2u] t=%016lx\n", smp_processor_id(), rdtsc_ordered());//temp
/* Loop to get rid of cache effects on TSC skew. */
for ( i = 4; i >= 0; i-- )
{
@@ -1701,6 +1734,7 @@ static void time_calibration_tsc_rendezv
* Use the largest value observed anywhere on the first
* iteration.
*/
+adj = r->max_tsc_stamp - r->master_tsc_stamp,//temp
r->master_tsc_stamp = r->max_tsc_stamp;
else if ( i == 0 )
r->master_stime = read_platform_stime(NULL);
@@ -1743,6 +1777,13 @@ static void time_calibration_tsc_rendezv
}
time_calibration_rendezvous_tail(r, tsc, r->master_tsc_stamp);
+if(adj) {//temp
+ static unsigned long cnt, thr;
+ if(++cnt > thr) {
+ thr |= cnt;
+ printk("TSC adjusted by %lx\n", adj);
+ }
+}
}
/* Ordinary rendezvous function which does not modify TSC values. */
@@ -1794,6 +1835,12 @@ static void time_calibration(void *unuse
struct calibration_rendezvous r = {
.semaphore = ATOMIC_INIT(0)
};
+static unsigned long cnt, thr;//temp
+if(++cnt > thr) {//temp
+ thr |= cnt;
+ printk("TSC: %ps\n", time_calibration_rendezvous_fn);
+ rdzv_log = true;
+}
if ( clocksource_is_tsc() )
{
@@ -1808,6 +1855,10 @@ static void time_calibration(void *unuse
on_selected_cpus(&r.cpu_calibration_map,
time_calibration_rendezvous_fn,
&r, 1);
+if(rdzv_log) {//temp
+ rdzv_log = false;
+ printk("TSC: end rendezvous\n");
+}
}
static struct cpu_time_stamp ap_bringup_ref;
@@ -1904,6 +1955,7 @@ void init_percpu_time(void)
}
t->stamp.local_tsc = tsc;
t->stamp.local_stime = now;
+printk("INIT[%2u] t=%016lx s=%012lx m=%012lx\n", smp_processor_id(), tsc, now, t->stamp.master_stime);//temp
}
/*
@@ -2046,6 +2098,7 @@ static int __init verify_tsc_reliability
* While with constant-rate TSCs the scale factor can be shared, when TSCs
* are not marked as 'reliable', re-sync during rendezvous.
*/
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
!boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
@@ -2061,6 +2114,7 @@ int __init init_xen_time(void)
{
tsc_check_writability();
+printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
/* NB. get_wallclock_time() can take over one second to execute. */
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-02-01 12:47 ` Jan Beulich
@ 2021-02-01 14:46 ` Claudemir Todo Bom
2021-02-01 15:09 ` Jan Beulich
0 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-02-01 14:46 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel
[-- Attachment #1: Type: text/plain, Size: 8203 bytes --]
Tested first without the debug patch and with following parameters:
xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
kernel: loglevel=3
same behaviour as before... black screen right after the xen messages.
adding earlyprintk=xen to the kernel command line is sufficient to
make it boot, I can imagine this can be happening because Xen is not
releasing console to the kernel at that moment.
The system worked well (with earlyprintk=xen), tested with the "yes
stress test" mentioned before on a guest and on dom0.
Then, I installed the debug patch and booted it again, it also needed
the earlyprintk=xen parameter on the kernel command line. I've also
added console_timestamps=boot to the xen command line in order to get
the time of the messages.
I'm attaching the outputs of "xl dmesg" and "dmesg" on this message.
Think it is almost done! WIll wait for the next round of tests!
Thank you very much!
Em seg., 1 de fev. de 2021 às 09:47, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 29.01.2021 20:31, Claudemir Todo Bom wrote:
> > I've applied both patches, system didn't booted, used following parameters:
> >
> > xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
> > kernel: loglevel=3
> >
> > The screen cleared right after the initial xen messages and frozen
> > there for a few minutes until I restarted the system.
> >
> > I've added "vga=text-80x25,keep" to the xen command line and
> > "nomodeset" to the kernel command line, hoping to get some more info
> > and surprisingly this was sufficient to make system boot!
> >
> > System prompt took a lot to appear, the kernel driver for the usb
> > keyboard loaded after 3 minutes and the driver for the usb wifi dongle
> > I am using loaded about five minutes after kernel boot, and I had to
> > issue "ifup -a" to get an ip address from the dhcp server, and it took
> > almost one minute to get it!
>
> I was able to repro this behavior, by deliberately screwing up
> CPU0's TSC early during boot. This of course did make it a lot
> easier to find and fix the problem. I've Cc-ed you on the full
> 3-patch series that I've sent a minute ago, because while you
> may continue to opt for ignoring the first patch, you'll now
> need the latter two. And as before, the updated debugging patch
> below.
>
> Jan
>
> --- a/xen/arch/x86/time.c
> +++ b/xen/arch/x86/time.c
> @@ -1558,6 +1558,12 @@ static void local_time_calibration(void)
> * TSC Reliability check
> */
>
> +static struct {//temp
> + unsigned cpu;
> + signed iter;
> + cycles_t prev, now;
> +} check_log[NR_CPUS + 4];
> +static unsigned check_idx;//temp
> /*
> * The Linux original version of this function is
> * Copyright (c) 2006, Red Hat, Inc., Ingo Molnar
> @@ -1566,6 +1572,7 @@ static void check_tsc_warp(unsigned long
> {
> static DEFINE_SPINLOCK(sync_lock);
> static cycles_t last_tsc;
> +unsigned idx, cpu = smp_processor_id();//temp
>
> cycles_t start, now, prev, end;
> int i;
> @@ -1576,6 +1583,15 @@ static void check_tsc_warp(unsigned long
> end = start + tsc_khz * 20ULL;
> now = start;
>
> +{//temp
> + spin_lock(&sync_lock);
> + idx = check_idx++;
> + check_log[idx].cpu = cpu;
> + check_log[idx].iter = -1;
> + check_log[idx].now = now;
> + spin_unlock(&sync_lock);
> +}
> +
> for ( i = 0; ; i++ )
> {
> /*
> @@ -1610,7 +1626,14 @@ static void check_tsc_warp(unsigned long
> {
> spin_lock(&sync_lock);
> if ( *max_warp < prev - now )
> +{//temp
> *max_warp = prev - now;
> + idx = check_idx++;
> + check_log[idx].cpu = cpu;
> + check_log[idx].iter = i;
> + check_log[idx].prev = prev;
> + check_log[idx].now = now;
> +}
> spin_unlock(&sync_lock);
> }
> }
> @@ -1647,6 +1670,12 @@ static void tsc_check_reliability(void)
> cpu_relax();
>
> spin_unlock(&lock);
> +{//temp
> + unsigned i;
> + printk("CHK[%2u] %lx\n", cpu, tsc_max_warp);//temp
> + for(i = 0; i < ARRAY_SIZE(check_log) && check_log[i].now; ++i)
> + printk("chk[%4u] CPU%-2u %016lx %016lx #%d\n", i, check_log[i].cpu, check_log[i].prev, check_log[i].now, check_log[i].iter);
> +}
> }
>
> /*
> @@ -1661,6 +1690,7 @@ struct calibration_rendezvous {
> uint64_t master_tsc_stamp, max_tsc_stamp;
> };
>
> +static bool rdzv_log;//temp
> static void
> time_calibration_rendezvous_tail(const struct calibration_rendezvous *r,
> uint64_t old_tsc, uint64_t new_tsc)
> @@ -1671,6 +1701,7 @@ time_calibration_rendezvous_tail(const s
> c->local_stime = get_s_time_fixed(old_tsc ?: new_tsc);
> c->master_stime = r->master_stime;
>
> +if(rdzv_log) printk("RDZV[%2u] t=%016lx(%016lx) s=%012lx(%012lx)\n", smp_processor_id(), c->local_tsc, r->master_tsc_stamp, c->local_stime, r->master_stime);//temp
> raise_softirq(TIME_CALIBRATE_SOFTIRQ);
> }
>
> @@ -1684,7 +1715,9 @@ static void time_calibration_tsc_rendezv
> struct calibration_rendezvous *r = _r;
> unsigned int total_cpus = cpumask_weight(&r->cpu_calibration_map);
> uint64_t tsc = 0;
> +uint64_t adj = 0;//temp
>
> +if(rdzv_log) printk("RDZV[%2u] t=%016lx\n", smp_processor_id(), rdtsc_ordered());//temp
> /* Loop to get rid of cache effects on TSC skew. */
> for ( i = 4; i >= 0; i-- )
> {
> @@ -1701,6 +1734,7 @@ static void time_calibration_tsc_rendezv
> * Use the largest value observed anywhere on the first
> * iteration.
> */
> +adj = r->max_tsc_stamp - r->master_tsc_stamp,//temp
> r->master_tsc_stamp = r->max_tsc_stamp;
> else if ( i == 0 )
> r->master_stime = read_platform_stime(NULL);
> @@ -1743,6 +1777,13 @@ static void time_calibration_tsc_rendezv
> }
>
> time_calibration_rendezvous_tail(r, tsc, r->master_tsc_stamp);
> +if(adj) {//temp
> + static unsigned long cnt, thr;
> + if(++cnt > thr) {
> + thr |= cnt;
> + printk("TSC adjusted by %lx\n", adj);
> + }
> +}
> }
>
> /* Ordinary rendezvous function which does not modify TSC values. */
> @@ -1794,6 +1835,12 @@ static void time_calibration(void *unuse
> struct calibration_rendezvous r = {
> .semaphore = ATOMIC_INIT(0)
> };
> +static unsigned long cnt, thr;//temp
> +if(++cnt > thr) {//temp
> + thr |= cnt;
> + printk("TSC: %ps\n", time_calibration_rendezvous_fn);
> + rdzv_log = true;
> +}
>
> if ( clocksource_is_tsc() )
> {
> @@ -1808,6 +1855,10 @@ static void time_calibration(void *unuse
> on_selected_cpus(&r.cpu_calibration_map,
> time_calibration_rendezvous_fn,
> &r, 1);
> +if(rdzv_log) {//temp
> + rdzv_log = false;
> + printk("TSC: end rendezvous\n");
> +}
> }
>
> static struct cpu_time_stamp ap_bringup_ref;
> @@ -1904,6 +1955,7 @@ void init_percpu_time(void)
> }
> t->stamp.local_tsc = tsc;
> t->stamp.local_stime = now;
> +printk("INIT[%2u] t=%016lx s=%012lx m=%012lx\n", smp_processor_id(), tsc, now, t->stamp.master_stime);//temp
> }
>
> /*
> @@ -2046,6 +2098,7 @@ static int __init verify_tsc_reliability
> * While with constant-rate TSCs the scale factor can be shared, when TSCs
> * are not marked as 'reliable', re-sync during rendezvous.
> */
> +printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
> if ( boot_cpu_has(X86_FEATURE_CONSTANT_TSC) &&
> !boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
> time_calibration_rendezvous_fn = time_calibration_tsc_rendezvous;
> @@ -2061,6 +2114,7 @@ int __init init_xen_time(void)
> {
> tsc_check_writability();
>
> +printk("TSC: c=%d r=%d\n", !!boot_cpu_has(X86_FEATURE_CONSTANT_TSC), !!boot_cpu_has(X86_FEATURE_TSC_RELIABLE));//temp
> open_softirq(TIME_CALIBRATE_SOFTIRQ, local_time_calibration);
>
> /* NB. get_wallclock_time() can take over one second to execute. */
[-- Attachment #2: xen-dmesg.txt --]
[-- Type: text/plain, Size: 37509 bytes --]
(XEN) parameter "placeholder" unknown!
(XEN) [ 0.000000] Xen version 4.11.4 (Debian 4.11.4+57-g41a822c392-2) (pkg-xen-devel@lists.alioth.debian.org) (gcc (Debian 8.3.0-6) 8.3.0) debug=n Mon Feb 1 11:31:44 -03 2021
(XEN) [ 0.000000] Bootloader: GRUB 2.04-12
(XEN) [ 0.000000] Command line: placeholder dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true console_timestamps=boot
(XEN) [ 0.000000] Xen image load base address: 0xba200000
(XEN) [ 0.000000] Video information:
(XEN) [ 0.000000] VGA is text mode 80x25, font 8x16
(XEN) [ 0.000000] VBE/DDC methods: none; EDID transfer time: 0 seconds
(XEN) [ 0.000000] EDID info not retrieved because no DDC retrieval method detected
(XEN) [ 0.000000] Disc information:
(XEN) [ 0.000000] Found 1 MBR signatures
(XEN) [ 0.000000] Found 2 EDD information structures
(XEN) [ 0.000000] Xen-e820 RAM map:
(XEN) [ 0.000000] 0000000000000000 - 000000000009e800 (usable)
(XEN) [ 0.000000] 000000000009e800 - 00000000000a0000 (reserved)
(XEN) [ 0.000000] 00000000000e0000 - 0000000000100000 (reserved)
(XEN) [ 0.000000] 0000000000100000 - 00000000ba952000 (usable)
(XEN) [ 0.000000] 00000000ba952000 - 00000000ba98b000 (reserved)
(XEN) [ 0.000000] 00000000ba98b000 - 00000000babc3000 (usable)
(XEN) [ 0.000000] 00000000babc3000 - 00000000bb1c0000 (ACPI NVS)
(XEN) [ 0.000000] 00000000bb1c0000 - 00000000bb843000 (reserved)
(XEN) [ 0.000000] 00000000bb843000 - 00000000bb844000 (usable)
(XEN) [ 0.000000] 00000000bb844000 - 00000000bb8ca000 (ACPI NVS)
(XEN) [ 0.000000] 00000000bb8ca000 - 00000000bbd0f000 (usable)
(XEN) [ 0.000000] 00000000bbd0f000 - 00000000bbff4000 (reserved)
(XEN) [ 0.000000] 00000000bbff4000 - 00000000bc000000 (usable)
(XEN) [ 0.000000] 00000000d0000000 - 00000000e0000000 (reserved)
(XEN) [ 0.000000] 00000000fed1c000 - 00000000fed20000 (reserved)
(XEN) [ 0.000000] 00000000ff000000 - 0000000100000000 (reserved)
(XEN) [ 0.000000] 0000000100000000 - 0000000440000000 (usable)
(XEN) [ 0.000000] ACPI: RSDP 000F04A0, 0024 (r2 ALASKA)
(XEN) [ 0.000000] ACPI: XSDT BB0DD070, 005C (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: FACP BB0E5728, 010C (r5 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: DSDT BB0DD160, 85C7 (r2 ALASKA A M I 20 INTL 20051117)
(XEN) [ 0.000000] ACPI: FACS BB1B7F80, 0040
(XEN) [ 0.000000] ACPI: APIC BB0E5838, 01A8 (r3 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: FPDT BB0E59E0, 0044 (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) [ 0.000000] ACPI: MCFG BB0E5A28, 003C (r1 ALASKA OEMMCFG. 1072009 MSFT 97)
(XEN) [ 0.000000] ACPI: HPET BB0E5A68, 0038 (r1 ALASKA A M I 1072009 AMI. 5)
(XEN) [ 0.000000] ACPI: SSDT BB0E5AA0, CD380 (r2 INTEL CpuPm 4000 INTL 20051117)
(XEN) [ 0.000000] ACPI: DMAR BB1B2E20, 00EC (r1 A M I OEMDMAR 1 INTL 1)
(XEN) [ 0.000000] System RAM: 16303MB (16694760kB)
(XEN) [ 0.000000] Domain heap initialised
(XEN) [ 0.000000] ACPI: 32/64X FACS address mismatch in FADT - bb1b7f80/0000000000000000, using 32
(XEN) [ 0.000000] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
(XEN) [ 0.000000] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
(XEN) [ 0.000000] Enabling APIC mode: Phys. Using 2 I/O APICs
(XEN) [ 0.000000] Switched to APIC driver x2apic_cluster
(XEN) [ 0.000000] xstate: size: 0x340 and states: 0x7
(XEN) [ 0.000000] Speculative mitigation facilities:
(XEN) [ 0.000000] Hardware features:
(XEN) [ 0.000000] Compiled-in support: INDIRECT_THUNK SHADOW_PAGING
(XEN) [ 0.000000] Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: No, Other:
(XEN) [ 0.000000] L1TF: believed vulnerable, maxphysaddr L1D 46, CPUID 46, Safe address 300000000000
(XEN) [ 0.000000] Support for VMs: PV: RSB EAGER_FPU, HVM: RSB EAGER_FPU
(XEN) [ 0.000000] XPTI (64-bit PV only): Dom0 enabled, DomU enabled
(XEN) [ 0.000000] PV L1TF shadowing: Dom0 disabled, DomU enabled
(XEN) [ 0.000000] Using scheduler: SMP Credit Scheduler (credit)
(XEN) [ 0.000000] Platform timer is 14.318MHz HPET
(XEN) [ 0.458887] Detected 2494.338 MHz processor.
(XEN) [ 0.462916] Initing memory sharing.
(XEN) [ 0.465729] Intel VT-d iommu 0 supported page sizes: 4kB, 2MB, 1GB.
(XEN) [ 0.467130] Intel VT-d Snoop Control enabled.
(XEN) [ 0.468525] Intel VT-d Dom0 DMA Passthrough not enabled.
(XEN) [ 0.469919] Intel VT-d Queued Invalidation enabled.
(XEN) [ 0.471313] Intel VT-d Interrupt Remapping enabled.
(XEN) [ 0.472702] Intel VT-d Posted Interrupt not enabled.
(XEN) [ 0.474212] Intel VT-d Shared EPT tables enabled.
(XEN) [ 0.486844] I/O virtualisation enabled
(XEN) [ 0.488249] - Dom0 mode: Relaxed
(XEN) [ 0.489635] Interrupt remapping enabled
(XEN) [ 0.491158] Enabled directed EOI with ioapic_ack_old on!
(XEN) [ 0.493494] ENABLING IO-APIC IRQs
(XEN) [ 0.494879] -> Using old ACK method
(XEN) [ 0.697382] TSC: c=1 r=1
(XEN) [ 1.483974] INIT[ 0] t=000000193a6297b9 s=000058739cf4 m=000058739e8f
(XEN) [ 1.485375] Allocated console ring of 64 KiB.
(XEN) [ 1.486777] VMX: Supported advanced features:
(XEN) [ 1.488165] - APIC MMIO access virtualisation
(XEN) [ 1.489556] - APIC TPR shadow
(XEN) [ 1.490940] - Extended Page Tables (EPT)
(XEN) [ 1.492327] - Virtual-Processor Identifiers (VPID)
(XEN) [ 1.493721] - Virtual NMI
(XEN) [ 1.495106] - MSR direct-access bitmap
(XEN) [ 1.496493] - Unrestricted Guest
(XEN) [ 1.497880] - APIC Register Virtualization
(XEN) [ 1.499380] - Virtual Interrupt Delivery
(XEN) [ 1.500768] - Posted Interrupt Processing
(XEN) [ 1.502162] HVM: ASIDs enabled.
(XEN) [ 1.503544] VMX: Disabling executable EPT superpages due to CVE-2018-12207
(XEN) [ 1.506320] HVM: VMX enabled
(XEN) [ 1.507701] HVM: Hardware Assisted Paging (HAP) detected
(XEN) [ 1.509097] HVM: HAP page sizes: 4kB, 2MB, 1GB
(XEN) [ 1.510631] INIT[ 1] t=0000001a0862c447 s=00005a0a5c72 m=00005a0a5e2f
(XEN) [ 1.512231] INIT[ 2] t=0000001a089f9dff s=00005a22c184 m=00005a22c340
(XEN) [ 1.513789] INIT[ 3] t=0000001a08daf7fb s=00005a3a8d31 m=00005a3a8eb8
(XEN) [ 1.515453] INIT[ 4] t=0000001a091a41ee s=00005a53ec94 m=00005a53ee3b
(XEN) [ 1.517009] INIT[ 5] t=0000001a09558cfe s=00005a6bb1f1 m=00005a6bb3b3
(XEN) [ 1.518561] INIT[ 6] t=0000001a09908c97 s=00005a83591b m=00005a835ae2
(XEN) [ 1.520127] INIT[ 7] t=0000001a09cc36cf s=00005a9b4495 m=00005a9b4646
(XEN) [ 1.521701] INIT[ 8] t=0000001a0a08129e s=00005ab34432 m=00005ab345d9
(XEN) [ 1.523278] INIT[ 9] t=0000001a0a441f82 s=00005acb5724 m=00005acb58cc
(XEN) [ 1.524854] INIT[10] t=0000001a0a800d9a s=00005ae35e1e m=00005ae35fbe
(XEN) [ 1.526428] INIT[11] t=0000001a0abbff76 s=00005afb6638 m=00005afb680c
(XEN) [ 1.527997] INIT[12] t=0000001a0af7b25a s=00005b135527 m=00005b1356fc
(XEN) [ 1.529579] INIT[13] t=0000001a0b33f53a s=00005b2b7df2 m=00005b2b7fc2
(XEN) [ 1.531252] INIT[14] t=0000001a0b7397c5 s=00005b4500e2 m=00005b4502bc
(XEN) [ 1.532822] INIT[15] t=0000001a0baf5c8d s=00005b5cf721 m=00005b5cf90a
(XEN) [ 1.534389] INIT[16] t=0000001a0beafc9e s=00005b74ded8 m=00005b74e09b
(XEN) [ 1.535963] INIT[17] t=0000001a0c26e966 s=00005b8ce4f9 m=00005b8ce6bb
(XEN) [ 1.537531] INIT[18] t=0000001a0c628d6e s=00005ba4ce2a m=00005ba4cff0
(XEN) [ 1.539105] INIT[19] t=0000001a0c9e7f5e s=00005bbcd64e m=00005bbcd83f
(XEN) [ 1.540676] INIT[20] t=0000001a0cda417d s=00005bd4cb67 m=00005bd4cd75
(XEN) [ 1.542248] INIT[21] t=0000001a0d1624f9 s=00005becce3a m=00005becd009
(XEN) [ 1.543824] INIT[22] t=0000001a0d521878 s=00005c04d708 m=00005c04d8e4
(XEN) [ 1.545417] INIT[23] t=0000001a0d8ebc60 s=00005c1d2684 m=00005c1d2867
(XEN) [ 1.546839] Brought up 24 CPUs
(XEN) [ 1.601922] CHK[ 0] ca09997e
(XEN) [ 1.603304] chk[ 0] CPU0 0000000000000000 0000001948f1cba5 #-1
(XEN) [ 1.604703] chk[ 1] CPU1 0000000000000000 0000001a12fb67bb #-1
(XEN) [ 1.606105] chk[ 2] CPU7 0000000000000000 0000001a12fb6861 #-1
(XEN) [ 1.607504] chk[ 3] CPU6 0000000000000000 0000001a12fb686d #-1
(XEN) [ 1.608902] chk[ 4] CPU18 0000000000000000 0000001a12fb68d6 #-1
(XEN) [ 1.610302] chk[ 5] CPU16 0000000000000000 0000001a12fb68d5 #-1
(XEN) [ 1.611810] chk[ 6] CPU19 0000000000000000 0000001a12fb68ce #-1
(XEN) [ 1.613206] chk[ 7] CPU8 0000000000000000 0000001a12fb688b #-1
(XEN) [ 1.614607] chk[ 8] CPU15 0000000000000000 0000001a12fb69ab #-1
(XEN) [ 1.616009] chk[ 9] CPU9 0000000000000000 0000001a12fb6897 #-1
(XEN) [ 1.617409] chk[ 10] CPU21 0000000000000000 0000001a12fb68b4 #-1
(XEN) [ 1.618810] chk[ 11] CPU14 0000000000000000 0000001a12fb69a3 #-1
(XEN) [ 1.620210] chk[ 12] CPU20 0000000000000000 0000001a12fb68bc #-1
(XEN) [ 1.621614] chk[ 13] CPU17 0000000000000000 0000001a12fb68c9 #-1
(XEN) [ 1.623015] chk[ 14] CPU13 0000000000000000 0000001a12fb68bf #-1
(XEN) [ 1.624416] chk[ 15] CPU3 0000000000000000 0000001a12fb6a43 #-1
(XEN) [ 1.625815] chk[ 16] CPU2 0000000000000000 0000001a12fb6a4f #-1
(XEN) [ 1.627328] chk[ 17] CPU12 0000000000000000 0000001a12fb68cb #-1
(XEN) [ 1.628726] chk[ 18] CPU11 0000000000000000 0000001a12fb69d7 #-1
(XEN) [ 1.630130] chk[ 19] CPU4 0000000000000000 0000001a12fb6a68 #-1
(XEN) [ 1.631535] chk[ 20] CPU5 0000000000000000 0000001a12fb6a5c #-1
(XEN) [ 1.632935] chk[ 21] CPU22 0000000000000000 0000001a12fb69bc #-1
(XEN) [ 1.634336] chk[ 22] CPU23 0000000000000000 0000001a12fb69b0 #-1
(XEN) [ 1.635737] chk[ 23] CPU10 0000000000000000 0000001a12fb69cb #-1
(XEN) [ 1.637140] chk[ 24] CPU0 0000001a12fbd163 0000001948f238d5 #1
(XEN) [ 1.638537] chk[ 25] CPU0 0000001a12fd02c7 0000001948f36a15 #4
(XEN) [ 1.639937] chk[ 26] CPU0 0000001a12fd67f7 0000001948f3cef5 #5
(XEN) [ 1.641335] chk[ 27] CPU0 0000001a12fe3217 0000001948f498bd #7
(XEN) [ 1.642734] chk[ 28] CPU0 0000001a13053f8f 0000001948fba625 #25
(XEN) [ 1.644249] chk[ 29] CPU0 0000001a131d71ff 000000194913d881 #87
(XEN) [ 1.645649] TSC warp detected, disabling TSC_RELIABLE
(XEN) [ 1.647047] TSC: c=1 r=0
(XEN) [ 1.648432] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 1.649828] RDZV[ 0] t=00000019530b1f29
(XEN) [ 1.651216] RDZV[ 1] t=0000001a1d14c273
(XEN) [ 1.652606] RDZV[ 2] t=0000001a1d15dc69
(XEN) [ 1.653993] RDZV[ 3] t=0000001a1d15dc6d
(XEN) [ 1.655381] RDZV[ 5] t=0000001a1d15e612
(XEN) [ 1.656765] RDZV[ 4] t=0000001a1d15e60a
(XEN) [ 1.658158] RDZV[ 7] t=0000001a1d15ef8f
(XEN) [ 1.659629] RDZV[ 6] t=0000001a1d15ef87
(XEN) [ 1.661022] RDZV[ 8] t=0000001a1d15fcb9
(XEN) [ 1.662409] RDZV[ 9] t=0000001a1d15fcbd
(XEN) [ 1.663800] RDZV[11] t=0000001a1d1609cb
(XEN) [ 1.665191] RDZV[10] t=0000001a1d1609d3
(XEN) [ 1.666584] RDZV[12] t=0000001a1d16127c
(XEN) [ 1.667971] RDZV[13] t=0000001a1d161274
(XEN) [ 1.669362] RDZV[15] t=0000001a1d161ceb
(XEN) [ 1.670745] RDZV[14] t=0000001a1d161cf3
(XEN) [ 1.672135] RDZV[17] t=0000001a1d162483
(XEN) [ 1.673524] RDZV[16] t=0000001a1d16247b
(XEN) [ 1.674914] RDZV[18] t=0000001a1d162eca
(XEN) [ 1.676384] RDZV[19] t=0000001a1d162ed6
(XEN) [ 1.677772] RDZV[21] t=0000001a1d1637cb
(XEN) [ 1.679159] RDZV[20] t=0000001a1d1637c3
(XEN) [ 1.680548] RDZV[22] t=0000001a1d164171
(XEN) [ 1.681935] RDZV[23] t=0000001a1d164179
(XEN) [ 1.683325] RDZV[20] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556aa7(00006455af56)
(XEN) [ 1.686095] RDZV[ 4] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a2d(00006455af56)
(XEN) [ 1.688874] RDZV[18] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a5a(00006455af56)
(XEN) [ 1.691734] RDZV[19] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a2c(00006455af56)
(XEN) [ 1.694507] RDZV[21] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556af2(00006455af56)
(XEN) [ 1.697286] RDZV[ 8] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a64(00006455af56)
(XEN) [ 1.700057] RDZV[ 9] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a3f(00006455af56)
(XEN) [ 1.702841] RDZV[12] t=0000001a220f7ce3(0000001a220f7ce3) s=0000645569f9(00006455af56)
(XEN) [ 1.705625] RDZV[13] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a09(00006455af56)
(XEN) [ 1.708515] RDZV[ 7] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a42(00006455af56)
(XEN) [ 1.711292] RDZV[ 6] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a5b(00006455af56)
(XEN) [ 1.714064] RDZV[14] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a38(00006455af56)
(XEN) [ 1.716842] RDZV[15] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a3c(00006455af56)
(XEN) [ 1.719625] RDZV[ 3] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a6d(00006455af56)
(XEN) [ 1.722400] RDZV[23] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a08(00006455af56)
(XEN) [ 1.725285] RDZV[16] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a4f(00006455af56)
(XEN) [ 1.728056] RDZV[ 1] t=0000001a220f7ce3(0000001a220f7ce3) s=0000645569f6(00006455af56)
(XEN) [ 1.730839] RDZV[10] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a56(00006455af56)
(XEN) [ 1.733615] RDZV[11] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a21(00006455af56)
(XEN) [ 1.736397] RDZV[17] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a2d(00006455af56)
(XEN) [ 1.739284] RDZV[22] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a2f(00006455af56)
(XEN) [ 3.100981] RDZV[ 0] t=0000001a220f7ce3(0000001a220f7ce3) s=00006455687d(00006455af56)
(XEN) [ 1.744831] RDZV[ 2] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a21(00006455af56)
(XEN) [ 1.747607] RDZV[ 5] t=0000001a220f7ce3(0000001a220f7ce3) s=000064556a1d(00006455af56)
(XEN) [ 3.109313] TSC adjusted by ca09a102
(XEN) [ 3.110699] TSC: end rendezvous
(XEN) [ 3.112087] mtrr: your CPUs had inconsistent fixed MTRR settings
(XEN) [ 3.113511] Dom0 has maximum 816 PIRQs
(XEN) [ 2.464395] Xen kernel: 64-bit, lsb, compat32
(XEN) [ 2.465786] Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x2c2c000
(XEN) [ 2.468975] PHYSICAL MEMORY ARRANGEMENT:
(XEN) [ 2.470362] Dom0 alloc.: 0000000428000000->000000042c000000 (237067 pages to be allocated)
(XEN) [ 2.473145] Init. ramdisk: 000000043de0b000->000000043ffff664
(XEN) [ 2.474546] VIRTUAL MEMORY ARRANGEMENT:
(XEN) [ 2.476051] Loaded kernel: ffffffff81000000->ffffffff82c2c000
(XEN) [ 2.477450] Init. ramdisk: 0000000000000000->0000000000000000
(XEN) [ 2.478849] Phys-Mach map: 0000008000000000->0000008000200000
(XEN) [ 2.480248] Start info: ffffffff82c2c000->ffffffff82c2c4b8
(XEN) [ 2.481645] Xenstore ring: 0000000000000000->0000000000000000
(XEN) [ 2.483040] Console ring: 0000000000000000->0000000000000000
(XEN) [ 2.484438] Page tables: ffffffff82c2d000->ffffffff82c48000
(XEN) [ 2.485837] Boot stack: ffffffff82c48000->ffffffff82c49000
(XEN) [ 2.487238] TOTAL: ffffffff80000000->ffffffff83000000
(XEN) [ 2.488637] ENTRY ADDRESS: ffffffff8282a160
(XEN) [ 2.490854] Dom0 has maximum 4 VCPUs
(XEN) [ 2.820823] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 2.822222] RDZV[ 0] t=0000001acb62c27f
(XEN) [ 2.823611] RDZV[ 1] t=0000001acb62c3ab
(XEN) [ 2.824997] RDZV[ 2] t=0000001acb63e38d
(XEN) [ 2.826384] RDZV[ 3] t=0000001acb63e3f9
(XEN) [ 2.827855] RDZV[ 5] t=0000001acb63ed55
(XEN) [ 2.829241] RDZV[ 4] t=0000001acb63e8f1
(XEN) [ 2.830633] RDZV[ 7] t=0000001acb63f5b1
(XEN) [ 2.832023] RDZV[ 6] t=0000001acb63f5a1
(XEN) [ 2.833414] RDZV[ 9] t=0000001acb63fffd
(XEN) [ 2.834803] RDZV[ 8] t=0000001acb63fffd
(XEN) [ 2.836197] RDZV[11] t=0000001acb640fb5
(XEN) [ 2.837588] RDZV[10] t=0000001acb640f85
(XEN) [ 2.838974] RDZV[13] t=0000001acb64179d
(XEN) [ 2.840363] RDZV[12] t=0000001acb641971
(XEN) [ 2.841756] RDZV[15] t=0000001acb64233c
(XEN) [ 2.843146] RDZV[14] t=0000001acb6421c4
(XEN) [ 2.844620] RDZV[17] t=0000001acb642b0e
(XEN) [ 2.846007] RDZV[16] t=0000001acb642b22
(XEN) [ 2.847396] RDZV[18] t=0000001acb643526
(XEN) [ 2.848785] RDZV[19] t=0000001acb643522
(XEN) [ 2.850176] RDZV[20] t=0000001acb643edd
(XEN) [ 2.851562] RDZV[21] t=0000001acb643ecd
(XEN) [ 2.852949] RDZV[22] t=0000001acb6447b9
(XEN) [ 2.854334] RDZV[23] t=0000001acb6447d5
(XEN) [ 2.855722] RDZV[ 0] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c787(0000aa3765a9)
(XEN) [ 2.858502] RDZV[23] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c985(0000aa3765a9)
(XEN) [ 2.861364] RDZV[22] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c99e(0000aa3765a9)
(XEN) [ 2.864140] RDZV[ 8] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c8f9(0000aa3765a9)
(XEN) [ 2.866921] RDZV[ 9] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c8d4(0000aa3765a9)
(XEN) [ 2.869698] RDZV[20] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca36(0000aa3765a9)
(XEN) [ 2.872472] RDZV[21] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca84(0000aa3765a9)
(XEN) [ 2.875248] RDZV[14] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36cb85(0000aa3765a9)
(XEN) [ 2.878135] RDZV[15] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36cc1a(0000aa3765a9)
(XEN) [ 2.880915] RDZV[17] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36cc84(0000aa3765a9)
(XEN) [ 2.883686] RDZV[16] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ccb1(0000aa3765a9)
(XEN) [ 2.886464] RDZV[ 7] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca4e(0000aa3765a9)
(XEN) [ 2.889246] RDZV[ 6] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca6a(0000aa3765a9)
(XEN) [ 2.892135] RDZV[12] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca43(0000aa3765a9)
(XEN) [ 2.894915] RDZV[13] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c990(0000aa3765a9)
(XEN) [ 2.897690] RDZV[ 2] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c9f3(0000aa3765a9)
(XEN) [ 2.900467] RDZV[ 1] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c95a(0000aa3765a9)
(XEN) [ 2.903250] RDZV[10] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c9ed(0000aa3765a9)
(XEN) [ 2.906031] RDZV[11] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c9c5(0000aa3765a9)
(XEN) [ 2.908926] RDZV[18] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca36(0000aa3765a9)
(XEN) [ 2.911699] RDZV[ 3] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca71(0000aa3765a9)
(XEN) [ 2.914478] RDZV[ 5] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca1f(0000aa3765a9)
(XEN) [ 2.917256] RDZV[19] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36ca0d(0000aa3765a9)
(XEN) [ 2.920033] RDZV[ 4] t=0000001ad05daa86(0000001ad05daa86) s=0000aa36c86d(0000aa3765a9)
(XEN) [ 2.922810] TSC adjusted by 857
(XEN) [ 2.924304] TSC: end rendezvous
(XEN) [ 3.325505] Initial low memory virq threshold set at 0x4000 pages.
(XEN) [ 3.326910] Scrubbing Free RAM on 1 nodes using 12 CPUs
(XEN) [ 3.410122] ............done.
(XEN) [ 4.156432] Std. Loglevel: Errors and warnings
(XEN) [ 4.157921] Guest Loglevel: Nothing (Rate-limited: Errors and warnings)
(XEN) [ 4.159324] Xen is relinquishing VGA console.
(XEN) [ 4.161170] *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen)
(XEN) [ 4.161333] Freed 476kB init memory
(XEN) [ 4.976218] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 4.976222] RDZV[ 0] t=0000001c0ba16049
(XEN) [ 4.976225] RDZV[ 1] t=0000001c0ba165b9
(XEN) [ 4.976253] RDZV[ 3] t=0000001c0ba26df7
(XEN) [ 4.976255] RDZV[ 2] t=0000001c0ba26de7
(XEN) [ 4.976258] RDZV[ 4] t=0000001c0ba2767c
(XEN) [ 4.976260] RDZV[ 5] t=0000001c0ba2768c
(XEN) [ 4.976263] RDZV[ 7] t=0000001c0ba27f92
(XEN) [ 4.976266] RDZV[ 6] t=0000001c0ba27fd6
(XEN) [ 4.976269] RDZV[ 8] t=0000001c0ba28e27
(XEN) [ 4.976271] RDZV[ 9] t=0000001c0ba28e17
(XEN) [ 4.976274] RDZV[10] t=0000001c0ba299c2
(XEN) [ 4.976277] RDZV[11] t=0000001c0ba299be
(XEN) [ 4.976279] RDZV[13] t=0000001c0ba2a37a
(XEN) [ 4.976282] RDZV[12] t=0000001c0ba2a28e
(XEN) [ 4.976285] RDZV[15] t=0000001c0ba2acff
(XEN) [ 4.976288] RDZV[14] t=0000001c0ba2acff
(XEN) [ 4.976292] RDZV[17] t=0000001c0ba2b568
(XEN) [ 4.976294] RDZV[16] t=0000001c0ba2b578
(XEN) [ 4.976295] RDZV[19] t=0000001c0ba2be8d
(XEN) [ 4.976297] RDZV[18] t=0000001c0ba2bea5
(XEN) [ 4.976301] RDZV[20] t=0000001c0ba2c806
(XEN) [ 4.976303] RDZV[21] t=0000001c0ba2c7d2
(XEN) [ 4.976306] RDZV[22] t=0000001c0ba2d23a
(XEN) [ 4.976308] RDZV[23] t=0000001c0ba2d23a
(XEN) [ 4.976312] RDZV[ 0] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c713e(0001289da3cb)
(XEN) [ 4.976315] RDZV[ 1] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7477(0001289da3cb)
(XEN) [ 4.976318] RDZV[ 2] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c753e(0001289da3cb)
(XEN) [ 4.976320] RDZV[ 8] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c75fb(0001289da3cb)
(XEN) [ 4.976322] RDZV[ 9] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c75da(0001289da3cb)
(XEN) [ 4.976325] RDZV[21] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c759f(0001289da3cb)
(XEN) [ 4.976328] RDZV[18] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c750e(0001289da3cb)
(XEN) [ 4.976330] RDZV[19] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c74cd(0001289da3cb)
(XEN) [ 4.976332] RDZV[ 3] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c75ca(0001289da3cb)
(XEN) [ 4.976335] RDZV[23] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c748d(0001289da3cb)
(XEN) [ 4.976338] RDZV[ 6] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c768c(0001289da3cb)
(XEN) [ 4.976340] RDZV[ 7] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c764a(0001289da3cb)
(XEN) [ 4.976344] RDZV[17] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7ce3(0001289da3cb)
(XEN) [ 4.976346] RDZV[16] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7d18(0001289da3cb)
(XEN) [ 4.976347] RDZV[ 4] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7336(0001289da3cb)
(XEN) [ 4.976350] RDZV[20] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7561(0001289da3cb)
(XEN) [ 4.976353] RDZV[15] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c773a(0001289da3cb)
(XEN) [ 4.976355] RDZV[14] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c769e(0001289da3cb)
(XEN) [ 4.976357] RDZV[13] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c7477(0001289da3cb)
(XEN) [ 4.976360] RDZV[12] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c74d3(0001289da3cb)
(XEN) [ 4.976361] RDZV[22] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c74a9(0001289da3cb)
(XEN) [ 4.976364] RDZV[ 5] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c74ed(0001289da3cb)
(XEN) [ 4.976367] RDZV[10] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c789f(0001289da3cb)
(XEN) [ 4.976369] RDZV[11] t=0000001c0ba4b4b2(0000001c0ba4b4b2) s=0001289c787b(0001289da3cb)
(XEN) [ 4.976369] TSC adjusted by 6bd
(XEN) [ 4.976370] TSC: end rendezvous
(XEN) [ 8.976532] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 8.976556] RDZV[ 0] t=0000001e5e607d8f
(XEN) [ 8.976559] RDZV[ 1] t=0000001e5e607fdf
(XEN) [ 8.976578] RDZV[ 2] t=0000001e5e6139be
(XEN) [ 8.976581] RDZV[ 3] t=0000001e5e6139a6
(XEN) [ 8.976584] RDZV[ 4] t=0000001e5e613d43
(XEN) [ 8.976587] RDZV[ 5] t=0000001e5e613d37
(XEN) [ 8.976590] RDZV[ 6] t=0000001e5e61481f
(XEN) [ 8.976592] RDZV[ 7] t=0000001e5e61481f
(XEN) [ 8.976595] RDZV[ 8] t=0000001e5e615370
(XEN) [ 8.976598] RDZV[ 9] t=0000001e5e615370
(XEN) [ 8.976602] RDZV[10] t=0000001e5e616220
(XEN) [ 8.976604] RDZV[11] t=0000001e5e616244
(XEN) [ 8.976606] RDZV[13] t=0000001e5e61f6d8
(XEN) [ 8.976609] RDZV[12] t=0000001e5e61f520
(XEN) [ 8.976612] RDZV[14] t=0000001e5e620205
(XEN) [ 8.976615] RDZV[15] t=0000001e5e620225
(XEN) [ 8.976619] RDZV[16] t=0000001e5e620bd4
(XEN) [ 8.976622] RDZV[17] t=0000001e5e620bd4
(XEN) [ 8.976623] RDZV[18] t=0000001e5e621414
(XEN) [ 8.976625] RDZV[19] t=0000001e5e621414
(XEN) [ 8.976628] RDZV[20] t=0000001e5e622016
(XEN) [ 8.976630] RDZV[21] t=0000001e5e622002
(XEN) [ 8.976633] RDZV[22] t=0000001e5e622861
(XEN) [ 8.976636] RDZV[23] t=0000001e5e6227d5
(XEN) [ 8.976640] RDZV[ 0] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9971(0002170eef7b)
(XEN) [ 8.976644] RDZV[ 6] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca05e(0002170eef7b)
(XEN) [ 8.976646] RDZV[ 7] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca025(0002170eef7b)
(XEN) [ 8.976648] RDZV[ 1] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9e24(0002170eef7b)
(XEN) [ 8.976651] RDZV[14] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca24a(0002170eef7b)
(XEN) [ 8.976654] RDZV[15] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca308(0002170eef7b)
(XEN) [ 8.976658] RDZV[17] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca6a8(0002170eef7b)
(XEN) [ 8.976658] RDZV[18] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9ecd(0002170eef7b)
(XEN) [ 8.976661] RDZV[19] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9e94(0002170eef7b)
(XEN) [ 8.976663] RDZV[22] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9deb(0002170eef7b)
(XEN) [ 8.976668] RDZV[16] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca6ec(0002170eef7b)
(XEN) [ 8.976668] RDZV[ 9] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9f16(0002170eef7b)
(XEN) [ 8.976671] RDZV[ 8] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9f40(0002170eef7b)
(XEN) [ 8.976673] RDZV[23] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9d9d(0002170eef7b)
(XEN) [ 8.976675] RDZV[13] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9e38(0002170eef7b)
(XEN) [ 8.976678] RDZV[12] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9dd4(0002170eef7b)
(XEN) [ 8.976680] RDZV[ 4] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca022(0002170eef7b)
(XEN) [ 8.976684] RDZV[10] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca1df(0002170eef7b)
(XEN) [ 8.976686] RDZV[11] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca1a6(0002170eef7b)
(XEN) [ 8.976688] RDZV[ 5] t=0000001e5e63966d(0000001e5e63966d) s=0002170ca1d6(0002170eef7b)
(XEN) [ 8.976691] RDZV[ 3] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9f2c(0002170eef7b)
(XEN) [ 8.976692] RDZV[ 2] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9e93(0002170eef7b)
(XEN) [ 8.976695] RDZV[21] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9eb8(0002170eef7b)
(XEN) [ 8.976697] RDZV[20] t=0000001e5e63966d(0000001e5e63966d) s=0002170c9e70(0002170eef7b)
(XEN) [ 8.976697] TSC adjusted by 5a6
(XEN) [ 8.976698] TSC: end rendezvous
(XEN) [ 16.977079] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 16.977103] RDZV[ 0] t=0000002303d9bb6a
(XEN) [ 16.977107] RDZV[ 1] t=0000002303da5df4
(XEN) [ 16.977129] RDZV[ 3] t=0000002303db2496
(XEN) [ 16.977131] RDZV[ 2] t=0000002303db24aa
(XEN) [ 16.977136] RDZV[ 4] t=0000002303db26a6
(XEN) [ 16.977138] RDZV[ 5] t=0000002303db26ba
(XEN) [ 16.977140] RDZV[ 7] t=0000002303db3131
(XEN) [ 16.977142] RDZV[ 6] t=0000002303db311d
(XEN) [ 16.977149] RDZV[ 8] t=0000002303db4014
(XEN) [ 16.977151] RDZV[ 9] t=0000002303db4028
(XEN) [ 16.977151] RDZV[11] t=0000002303db4a7c
(XEN) [ 16.977153] RDZV[10] t=0000002303db4aa4
(XEN) [ 16.977156] RDZV[13] t=0000002303db5453
(XEN) [ 16.977158] RDZV[12] t=0000002303db5453
(XEN) [ 16.977164] RDZV[15] t=0000002303db5d8f
(XEN) [ 16.977166] RDZV[14] t=0000002303db5e4b
(XEN) [ 16.977171] RDZV[16] t=0000002303db65a4
(XEN) [ 16.977174] RDZV[17] t=0000002303db65c4
(XEN) [ 16.977172] RDZV[19] t=0000002303db6f73
(XEN) [ 16.977174] RDZV[18] t=0000002303db6f7f
(XEN) [ 16.977177] RDZV[21] t=0000002303db79c9
(XEN) [ 16.977180] RDZV[20] t=0000002303db79d1
(XEN) [ 16.977182] RDZV[23] t=0000002303db835d
(XEN) [ 16.977184] RDZV[22] t=0000002303db8391
(XEN) [ 16.977189] RDZV[ 1] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4cb7(0003f3f0be57)
(XEN) [ 16.977192] RDZV[20] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4eb8(0003f3f0be57)
(XEN) [ 16.977194] RDZV[22] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4db7(0003f3f0be57)
(XEN) [ 16.977197] RDZV[ 3] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4e5d(0003f3f0be57)
(XEN) [ 16.977200] RDZV[11] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb506a(0003f3f0be57)
(XEN) [ 16.977203] RDZV[10] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb50b4(0003f3f0be57)
(XEN) [ 16.977208] RDZV[ 8] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5f01(0003f3f0be57)
(XEN) [ 16.977211] RDZV[ 9] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5eaf(0003f3f0be57)
(XEN) [ 16.977209] RDZV[19] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4f09(0003f3f0be57)
(XEN) [ 16.977212] RDZV[18] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4f69(0003f3f0be57)
(XEN) [ 16.977214] RDZV[12] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4dd2(0003f3f0be57)
(XEN) [ 16.977217] RDZV[13] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4e22(0003f3f0be57)
(XEN) [ 16.977217] RDZV[ 0] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4381(0003f3f0be57)
(XEN) [ 16.977227] RDZV[17] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb6033(0003f3f0be57)
(XEN) [ 16.977229] RDZV[16] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5fee(0003f3f0be57)
(XEN) [ 16.977227] RDZV[ 6] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5082(0003f3f0be57)
(XEN) [ 16.977229] RDZV[ 7] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5063(0003f3f0be57)
(XEN) [ 16.977231] RDZV[23] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4ce0(0003f3f0be57)
(XEN) [ 16.977233] RDZV[21] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4df8(0003f3f0be57)
(XEN) [ 16.977239] RDZV[15] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb58b4(0003f3f0be57)
(XEN) [ 16.977241] RDZV[14] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb581a(0003f3f0be57)
(XEN) [ 16.977240] RDZV[ 2] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb4dc7(0003f3f0be57)
(XEN) [ 16.977244] RDZV[ 4] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb5447(0003f3f0be57)
(XEN) [ 16.977246] RDZV[ 5] t=0000002303dd6eff(0000002303dd6eff) s=0003f3eb54f8(0003f3f0be57)
(XEN) [ 16.977244] TSC adjusted by 513
(XEN) [ 16.977246] TSC: end rendezvous
(XEN) [ 32.978179] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 32.978203] RDZV[ 0] t=0000002c4ecd4749
(XEN) [ 32.978209] RDZV[ 1] t=0000002c4ecdec2a
(XEN) [ 32.978232] RDZV[ 3] t=0000002c4eceaf8e
(XEN) [ 32.978234] RDZV[ 2] t=0000002c4eceaf8a
(XEN) [ 32.978239] RDZV[ 4] t=0000002c4eceb200
(XEN) [ 32.978241] RDZV[ 5] t=0000002c4eceb1f0
(XEN) [ 32.978245] RDZV[ 7] t=0000002c4ecebc78
(XEN) [ 32.978247] RDZV[ 6] t=0000002c4ecebb74
(XEN) [ 32.978252] RDZV[ 9] t=0000002c4ecec95a
(XEN) [ 32.978254] RDZV[ 8] t=0000002c4ecec94a
(XEN) [ 32.978254] RDZV[11] t=0000002c4eced4fa
(XEN) [ 32.978256] RDZV[10] t=0000002c4eced56e
(XEN) [ 32.978258] RDZV[12] t=0000002c4ecedd35
(XEN) [ 32.978260] RDZV[13] t=0000002c4ecede59
(XEN) [ 32.978267] RDZV[14] t=0000002c4ecee7b5
(XEN) [ 32.978270] RDZV[15] t=0000002c4ecee92d
(XEN) [ 32.978274] RDZV[17] t=0000002c4ecef08f
(XEN) [ 32.978276] RDZV[16] t=0000002c4ecef08b
(XEN) [ 32.978275] RDZV[19] t=0000002c4ecef8fd
(XEN) [ 32.978278] RDZV[18] t=0000002c4ecefa21
(XEN) [ 32.978281] RDZV[20] t=0000002c4ecf0492
(XEN) [ 32.978283] RDZV[21] t=0000002c4ecf0332
(XEN) [ 32.978286] RDZV[22] t=0000002c4ecf0ed9
(XEN) [ 32.978288] RDZV[23] t=0000002c4ecf0edd
(XEN) [ 32.978291] RDZV[ 1] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8bb51(0007adb76209)
(XEN) [ 32.978295] RDZV[ 2] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c14c(0007adb76209)
(XEN) [ 32.978297] RDZV[ 3] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c233(0007adb76209)
(XEN) [ 32.978303] RDZV[ 8] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8d135(0007adb76209)
(XEN) [ 32.978305] RDZV[ 9] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8d0d1(0007adb76209)
(XEN) [ 32.978304] RDZV[19] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c409(0007adb76209)
(XEN) [ 32.978306] RDZV[13] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8bdc3(0007adb76209)
(XEN) [ 32.978308] RDZV[12] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8be1d(0007adb76209)
(XEN) [ 32.978314] RDZV[14] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8cc39(0007adb76209)
(XEN) [ 32.978317] RDZV[15] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8cda7(0007adb76209)
(XEN) [ 32.978317] RDZV[23] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c4e3(0007adb76209)
(XEN) [ 32.978319] RDZV[21] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c392(0007adb76209)
(XEN) [ 32.978323] RDZV[ 4] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c71c(0007adb76209)
(XEN) [ 32.978325] RDZV[22] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c50e(0007adb76209)
(XEN) [ 32.978321] RDZV[ 0] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8aa24(0007adb76209)
(XEN) [ 32.978333] RDZV[17] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8d415(0007adb76209)
(XEN) [ 32.978336] RDZV[16] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8d49a(0007adb76209)
(XEN) [ 32.978336] RDZV[ 7] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c9ce(0007adb76209)
(XEN) [ 32.978338] RDZV[ 6] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c964(0007adb76209)
(XEN) [ 32.978339] RDZV[20] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c54c(0007adb76209)
(XEN) [ 32.978342] RDZV[18] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c5fb(0007adb76209)
(XEN) [ 32.978344] RDZV[10] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c3a2(0007adb76209)
(XEN) [ 32.978346] RDZV[11] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c27e(0007adb76209)
(XEN) [ 32.978350] RDZV[ 5] t=0000002c4ed0f82f(0000002c4ed0f82f) s=0007ada8c7d5(0007adb76209)
(XEN) [ 32.978344] TSC adjusted by 5d1
(XEN) [ 32.978345] TSC: end rendezvous
(XEN) [ 64.980354] TSC: time.c#time_calibration_tsc_rendezvous
(XEN) [ 64.980358] RDZV[ 0] t=0000003ee4b3bd48
(XEN) [ 64.980369] RDZV[ 1] t=0000003ee4b3c3a4
(XEN) [ 64.980385] RDZV[ 3] t=0000003ee4b3c569
(XEN) [ 64.980386] RDZV[ 2] t=0000003ee4b3c565
(XEN) [ 64.980404] RDZV[ 5] t=0000003ee4b4b959
(XEN) [ 64.980406] RDZV[ 4] t=0000003ee4b4b965
(XEN) [ 64.980409] RDZV[ 6] t=0000003ee4b4c2b0
(XEN) [ 64.980412] RDZV[ 7] t=0000003ee4b4c2a0
(XEN) [ 64.980415] RDZV[ 8] t=0000003ee4b4d08f
(XEN) [ 64.980418] RDZV[ 9] t=0000003ee4b4d0a3
(XEN) [ 64.980418] RDZV[10] t=0000003ee4b4da06
(XEN) [ 64.980421] RDZV[11] t=0000003ee4b4da42
(XEN) [ 64.980419] RDZV[13] t=0000003ee4b4e602
(XEN) [ 64.980421] RDZV[12] t=0000003ee4b4e652
(XEN) [ 64.980428] RDZV[15] t=0000003ee4b4f070
(XEN) [ 64.980429] RDZV[14] t=0000003ee4b4f074
(XEN) [ 64.980436] RDZV[16] t=0000003ee4b4f97b
(XEN) [ 64.980438] RDZV[17] t=0000003ee4b4f977
(XEN) [ 64.980439] RDZV[18] t=0000003ee4b50186
(XEN) [ 64.980441] RDZV[19] t=0000003ee4b50192
(XEN) [ 64.980442] RDZV[20] t=0000003ee4b50aac
(XEN) [ 64.980444] RDZV[21] t=0000003ee4b50aa0
(XEN) [ 64.980448] RDZV[22] t=0000003ee4b515f0
(XEN) [ 64.980451] RDZV[23] t=0000003ee4b515cc
(XEN) [ 64.980441] RDZV[ 0] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122caac(000f21457c08)
(XEN) [ 64.980466] RDZV[ 3] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21232119(000f21457c08)
(XEN) [ 64.980460] RDZV[20] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122fee0(000f21457c08)
(XEN) [ 64.980463] RDZV[22] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21230370(000f21457c08)
(XEN) [ 64.980467] RDZV[19] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21230841(000f21457c08)
(XEN) [ 64.980469] RDZV[18] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f212307f9(000f21457c08)
(XEN) [ 64.980469] RDZV[21] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122fdcc(000f21457c08)
(XEN) [ 64.980473] RDZV[23] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21230681(000f21457c08)
(XEN) [ 64.980480] RDZV[ 5] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2123145a(000f21457c08)
(XEN) [ 64.980482] RDZV[ 4] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2123149f(000f21457c08)
(XEN) [ 64.980482] RDZV[10] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21230a6d(000f21457c08)
(XEN) [ 64.980485] RDZV[11] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21230be3(000f21457c08)
(XEN) [ 64.980484] RDZV[14] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f212300f7(000f21457c08)
(XEN) [ 64.980488] RDZV[15] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2123073a(000f21457c08)
(XEN) [ 64.980494] RDZV[ 6] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2123112f(000f21457c08)
(XEN) [ 64.980496] RDZV[ 7] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f212312ff(000f21457c08)
(XEN) [ 64.980499] RDZV[ 8] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21231515(000f21457c08)
(XEN) [ 64.980502] RDZV[ 9] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21231773(000f21457c08)
(XEN) [ 64.980496] RDZV[12] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122f7cd(000f21457c08)
(XEN) [ 64.980499] RDZV[13] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122f970(000f21457c08)
(XEN) [ 64.980508] RDZV[17] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21231126(000f21457c08)
(XEN) [ 64.980510] RDZV[16] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21231142(000f21457c08)
(XEN) [ 64.980503] RDZV[ 1] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f2122edc3(000f21457c08)
(XEN) [ 64.980518] RDZV[ 2] t=0000003ee4b6ce3e(0000003ee4b6ce3e) s=000f21231ec8(000f21457c08)
(XEN) [ 64.980498] TSC adjusted by 14e
(XEN) [ 64.980499] TSC: end rendezvous
[-- Attachment #3: kernel-dmesg.txt --]
[-- Type: text/plain, Size: 70204 bytes --]
[ 0.000000] Linux version 5.10.0-1-amd64 (debian-kernel@lists.debian.org) (gcc-10 (Debian 10.2.1-3) 10.2.1 20201224, GNU ld (GNU Binutils for Debian) 2.35.1) #1 SMP Debian 5.10.4-1 (2020-12-31)
[ 0.000000] Command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro loglevel=3 earlyprintk=xen
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256
[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[ 0.000000] Released 0 page(s)
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable
[ 0.000000] Xen: [mem 0x000000000009e800-0x00000000000fffff] reserved
[ 0.000000] Xen: [mem 0x0000000000100000-0x0000000080061fff] usable
[ 0.000000] Xen: [mem 0x00000000ba952000-0x00000000ba98afff] reserved
[ 0.000000] Xen: [mem 0x00000000babc3000-0x00000000bb1bffff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bb1c0000-0x00000000bb842fff] reserved
[ 0.000000] Xen: [mem 0x00000000bb844000-0x00000000bb8c9fff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bbd0f000-0x00000000bbff3fff] reserved
[ 0.000000] Xen: [mem 0x00000000d0000000-0x00000000dfffffff] reserved
[ 0.000000] Xen: [mem 0x00000000fbffc000-0x00000000fbffcfff] reserved
[ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec01fff] reserved
[ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000feefffff] reserved
[ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] SMBIOS 2.7 present.
[ 0.000000] DMI: To be filled by O.E.M. To be filled by O.E.M./Intel X79, BIOS 4.6.5 07/17/2019
[ 0.000000] Hypervisor detected: Xen PV
[ 0.046807] tsc: Fast TSC calibration using PIT
[ 0.046809] tsc: Detected 2494.406 MHz processor
[ 0.046810] tsc: Detected 2494.338 MHz TSC
[ 0.052257] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.052260] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.052266] last_pfn = 0x80062 max_arch_pfn = 0x400000000
[ 0.052267] Disabled
[ 0.052268] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[ 0.052274] x86/PAT: Configuration [0-7]: WB WT UC- UC WC WP UC UC
[ 0.067087] Kernel/User page tables isolation: disabled on XEN PV.
[ 0.679369] RAMDISK: [mem 0x04000000-0x061f4fff]
[ 0.679382] ACPI: Early table checksum verification disabled
[ 0.685536] ACPI: RSDP 0x00000000000F04A0 000024 (v02 ALASKA)
[ 0.685547] ACPI: XSDT 0x00000000BB0DD070 00005C (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.685574] ACPI: FACP 0x00000000BB0E5728 00010C (v05 ALASKA A M I 01072009 AMI 00010013)
[ 0.685640] ACPI: DSDT 0x00000000BB0DD160 0085C7 (v02 ALASKA A M I 00000020 INTL 20051117)
[ 0.685655] ACPI: FACS 0x00000000BB1B7F80 000040
[ 0.685669] ACPI: APIC 0x00000000BB0E5838 0001A8 (v03 ALASKA A M I 01072009 AMI 00010013)
[ 0.685683] ACPI: FPDT 0x00000000BB0E59E0 000044 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.685698] ACPI: MCFG 0x00000000BB0E5A28 00003C (v01 ALASKA OEMMCFG. 01072009 MSFT 00000097)
[ 0.685712] ACPI: HPET 0x00000000BB0E5A68 000038 (v01 ALASKA A M I 01072009 AMI. 00000005)
[ 0.685727] ACPI: SSDT 0x00000000BB0E5AA0 0CD380 (v02 INTEL CpuPm 00004000 INTL 20051117)
[ 0.685742] ACPI: RMAD 0x00000000BB1B2E20 0000EC (v01 A M I OEMDMAR 00000001 INTL 00000001)
[ 0.685780] ACPI: Local APIC address 0xfee00000
[ 0.685782] Setting APIC routing to Xen PV.
[ 0.685815] NUMA turned off
[ 0.685816] Faking a node at [mem 0x0000000000000000-0x0000000080061fff]
[ 0.685829] NODE_DATA(0) allocated [mem 0x3fbf7000-0x3fc20fff]
[ 0.698997] Zone ranges:
[ 0.698998] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.699000] DMA32 [mem 0x0000000001000000-0x0000000080061fff]
[ 0.699002] Normal empty
[ 0.699003] Device empty
[ 0.699004] Movable zone start for each node
[ 0.699008] Early memory node ranges
[ 0.699009] node 0: [mem 0x0000000000001000-0x000000000009dfff]
[ 0.699010] node 0: [mem 0x0000000000100000-0x0000000080061fff]
[ 0.699332] Zeroed struct page in unavailable ranges: 32769 pages
[ 0.699334] Initmem setup node 0 [mem 0x0000000000001000-0x0000000080061fff]
[ 0.699335] On node 0 totalpages: 524287
[ 0.699337] DMA zone: 64 pages used for memmap
[ 0.699337] DMA zone: 21 pages reserved
[ 0.699338] DMA zone: 3997 pages, LIFO batch:0
[ 0.699389] DMA32 zone: 8130 pages used for memmap
[ 0.699390] DMA32 zone: 520290 pages, LIFO batch:63
[ 0.700118] p2m virtual area at (____ptrval____), size is 40000000
[ 0.926549] Remapped 98 page(s)
[ 0.928639] ACPI: PM-Timer IO Port: 0x408
[ 0.928646] ACPI: Local APIC address 0xfee00000
[ 0.928718] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[ 0.928720] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
[ 0.928722] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
[ 0.928723] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
[ 0.928725] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
[ 0.928726] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
[ 0.928728] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
[ 0.928729] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
[ 0.928730] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
[ 0.928732] ACPI: LAPIC_NMI (acpi_id[0x12] high edge lint[0x1])
[ 0.928733] ACPI: LAPIC_NMI (acpi_id[0x14] high edge lint[0x1])
[ 0.928735] ACPI: LAPIC_NMI (acpi_id[0x16] high edge lint[0x1])
[ 0.928736] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[ 0.928738] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
[ 0.928739] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
[ 0.928741] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
[ 0.928742] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
[ 0.928743] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
[ 0.928745] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
[ 0.928746] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
[ 0.928747] ACPI: LAPIC_NMI (acpi_id[0x11] high edge lint[0x1])
[ 0.928749] ACPI: LAPIC_NMI (acpi_id[0x13] high edge lint[0x1])
[ 0.928750] ACPI: LAPIC_NMI (acpi_id[0x15] high edge lint[0x1])
[ 0.928752] ACPI: LAPIC_NMI (acpi_id[0x17] high edge lint[0x1])
[ 0.928780] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
[ 0.928793] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
[ 0.928811] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 0.928814] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 0.928822] ACPI: IRQ0 used by override.
[ 0.928824] ACPI: IRQ9 used by override.
[ 0.928840] Using ACPI (MADT) for SMP configuration information
[ 0.928845] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 0.928854] smpboot: Allowing 24 CPUs, 0 hotplug CPUs
[ 0.928873] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 0.928875] PM: hibernation: Registered nosave memory: [mem 0x0009e000-0x0009efff]
[ 0.928876] PM: hibernation: Registered nosave memory: [mem 0x0009f000-0x000fffff]
[ 0.928878] [mem 0x80062000-0xba951fff] available for PCI devices
[ 0.928881] Booting paravirtualized kernel on Xen
[ 0.928882] Xen version: 4.11.4 (preserve-AD)
[ 0.928885] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
[ 0.933328] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:24 nr_cpu_ids:24 nr_node_ids:1
[ 0.934282] percpu: Embedded 54 pages/cpu s183960 r8192 d29032 u262144
[ 0.934290] pcpu-alloc: s183960 r8192 d29032 u262144 alloc=1*2097152
[ 0.934292] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 12 13 14 15
[ 0.934302] pcpu-alloc: [0] 16 17 18 19 20 21 22 23
[ 0.934371] xen: PV spinlocks enabled
[ 0.934375] PV qspinlock hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 0.934380] Built 1 zonelists, mobility grouping on. Total pages: 516072
[ 0.934381] Policy zone: DMA32
[ 0.934382] Kernel command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro loglevel=3 earlyprintk=xen
[ 0.934599] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.934679] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.935187] mem auto-init: stack:off, heap alloc:on, heap free:off
[ 0.980711] software IO TLB: mapped [mem 0x0000000038c00000-0x000000003cc00000] (64MB)
[ 1.000510] Memory: 197808K/2097148K available (12295K kernel code, 2540K rwdata, 4060K rodata, 2380K init, 1692K bss, 1229692K reserved, 0K cma-reserved)
[ 1.000518] random: get_random_u64 called from __kmem_cache_create+0x2e/0x550 with crng_init=0
[ 1.000821] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 1.001758] ftrace: allocating 35988 entries in 141 pages
[ 1.015381] ftrace: allocated 141 pages with 4 groups
[ 1.015793] rcu: Hierarchical RCU implementation.
[ 1.015795] rcu: RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=4.
[ 1.015796] Rude variant of Tasks RCU enabled.
[ 1.015797] Tracing variant of Tasks RCU enabled.
[ 1.015798] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 1.015799] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 1.026755] Using NULL legacy PIC
[ 1.026757] NR_IRQS: 524544, nr_irqs: 864, preallocated irqs: 0
[ 1.026820] xen:events: Using FIFO-based ABI
[ 1.026853] xen: --> pirq=1 -> irq=1 (gsi=1)
[ 1.026868] xen: --> pirq=2 -> irq=2 (gsi=2)
[ 1.026882] xen: --> pirq=3 -> irq=3 (gsi=3)
[ 1.026896] xen: --> pirq=4 -> irq=4 (gsi=4)
[ 1.026909] xen: --> pirq=5 -> irq=5 (gsi=5)
[ 1.026923] xen: --> pirq=6 -> irq=6 (gsi=6)
[ 1.026937] xen: --> pirq=7 -> irq=7 (gsi=7)
[ 1.026950] xen: --> pirq=8 -> irq=8 (gsi=8)
[ 1.026965] xen: --> pirq=9 -> irq=9 (gsi=9)
[ 1.026979] xen: --> pirq=10 -> irq=10 (gsi=10)
[ 1.026994] xen: --> pirq=11 -> irq=11 (gsi=11)
[ 1.027008] xen: --> pirq=12 -> irq=12 (gsi=12)
[ 1.027022] xen: --> pirq=13 -> irq=13 (gsi=13)
[ 1.027036] xen: --> pirq=14 -> irq=14 (gsi=14)
[ 1.027050] xen: --> pirq=15 -> irq=15 (gsi=15)
[ 1.027096] random: crng done (trusting CPU's manufacturer)
[ 1.032061] Console: colour VGA+ 80x25
[ 1.032073] printk: console [tty0] enabled
[ 1.032084] printk: console [hvc0] enabled
[ 1.032112] ACPI: Core revision 20200925
[ 1.105241] clocksource: xen: mask: 0xffffffffffffffff max_cycles: 0x1cd42e4dffb, max_idle_ns: 881590591483 ns
[ 1.105253] Xen: using vcpuop timer interface
[ 1.105258] installing Xen timer for CPU 0
[ 1.105298] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23f454f0625, max_idle_ns: 440795228661 ns
[ 1.105301] Calibrating delay loop (skipped), value calculated using timer frequency.. 4988.67 BogoMIPS (lpj=9977352)
[ 1.105304] pid_max: default: 32768 minimum: 301
[ 1.105398] LSM: Security Framework initializing
[ 1.105425] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 1.105521] AppArmor: AppArmor initialized
[ 1.105526] TOMOYO Linux initialized
[ 1.105573] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.105578] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.106358] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8
[ 1.106359] Last level dTLB entries: 4KB 512, 2MB 0, 4MB 0, 1GB 4
[ 1.106363] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[ 1.106364] Spectre V2 : Mitigation: Full generic retpoline
[ 1.106365] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[ 1.106366] Speculative Store Bypass: Vulnerable
[ 1.106368] MDS: Vulnerable: Clear CPU buffers attempted, no microcode
[ 1.106506] Freeing SMP alternatives memory: 32K
[ 1.109431] cpu 0 spinlock event irq 49
[ 1.109439] VPMU disabled by hypervisor.
[ 1.109833] Performance Events: unsupported p6 CPU model 62 no PMU driver, software events only.
[ 1.109938] rcu: Hierarchical SRCU implementation.
[ 1.110416] NMI watchdog: Perf NMI watchdog permanently disabled
[ 1.110569] smp: Bringing up secondary CPUs ...
[ 1.110839] installing Xen timer for CPU 1
[ 1.111206] cpu 1 spinlock event irq 59
[ 1.111206] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.
[ 1.111206] installing Xen timer for CPU 2
[ 1.111206] cpu 2 spinlock event irq 65
[ 1.111206] installing Xen timer for CPU 3
[ 1.111206] cpu 3 spinlock event irq 71
[ 1.111206] smp: Brought up 1 node, 4 CPUs
[ 1.111206] smpboot: Max logical packages: 6
[ 1.114928] node 0 deferred pages initialised in 0ms
[ 1.114965] devtmpfs: initialized
[ 1.114965] x86/mm: Memory block size: 128MB
[ 1.114965] PM: Registering ACPI NVS region [mem 0xbabc3000-0xbb1bffff] (6279168 bytes)
[ 1.114965] PM: Registering ACPI NVS region [mem 0xbb844000-0xbb8c9fff] (548864 bytes)
[ 1.114965] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 1.114965] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[ 1.114965] pinctrl core: initialized pinctrl subsystem
[ 1.114965] NET: Registered protocol family 16
[ 1.114965] xen:grant_table: Grant tables using version 1 layout
[ 1.114965] Grant table initialized
[ 1.114965] audit: initializing netlink subsys (disabled)
[ 1.114965] audit: type=2000 audit(1612190532.582:1): state=initialized audit_enabled=0 res=1
[ 1.114965] thermal_sys: Registered thermal governor 'fair_share'
[ 1.114965] thermal_sys: Registered thermal governor 'bang_bang'
[ 1.114965] thermal_sys: Registered thermal governor 'step_wise'
[ 1.114965] thermal_sys: Registered thermal governor 'user_space'
[ 1.114965] ACPI: bus type PCI registered
[ 1.114965] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 1.114965] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xd0000000-0xdfffffff] (base 0xd0000000)
[ 1.114965] PCI: MMCONFIG at [mem 0xd0000000-0xdfffffff] reserved in E820
[ 1.207901] PCI: Using configuration type 1 for base access
[ 1.389470] ACPI: Added _OSI(Module Device)
[ 1.389472] ACPI: Added _OSI(Processor Device)
[ 1.389474] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 1.389475] ACPI: Added _OSI(Processor Aggregator Device)
[ 1.389477] ACPI: Added _OSI(Linux-Dell-Video)
[ 1.389478] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[ 1.389480] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[ 1.557336] ACPI: 2 ACPI AML tables successfully acquired and loaded
[ 1.571420] xen: registering gsi 9 triggering 0 polarity 0
[ 1.576799] ACPI: Interpreter enabled
[ 1.576813] ACPI: (supports S0 S5)
[ 1.576814] ACPI: Using IOAPIC for interrupt routing
[ 1.576855] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 1.577440] ACPI: Enabled 6 GPEs in block 00 to 3F
[ 1.595979] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
[ 1.595985] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 1.596208] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug PME AER LTR]
[ 1.596413] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PCIeCapability]
[ 1.596978] PCI host bridge to bus 0000:00
[ 1.596981] pci_bus 0000:00: root bus resource [io 0x0000-0x03af window]
[ 1.596982] pci_bus 0000:00: root bus resource [io 0x03e0-0x0cf7 window]
[ 1.596983] pci_bus 0000:00: root bus resource [io 0x03b0-0x03df window]
[ 1.596984] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 1.596985] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 1.596987] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 1.596988] pci_bus 0000:00: root bus resource [mem 0xcc000000-0xffffffff window]
[ 1.596989] pci_bus 0000:00: root bus resource [mem 0x440000000-0x3fffffffffff window]
[ 1.596991] pci_bus 0000:00: root bus resource [bus 00-fe]
[ 1.597047] pci 0000:00:00.0: [8086:0e00] type 00 class 0x060000
[ 1.597340] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 1.597578] pci 0000:00:01.0: [8086:0e02] type 01 class 0x060400
[ 1.597930] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 1.598217] pci 0000:00:01.1: [8086:0e03] type 01 class 0x060400
[ 1.598568] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[ 1.598868] pci 0000:00:02.0: [8086:0e04] type 01 class 0x060400
[ 1.599219] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[ 1.599490] pci 0000:00:02.1: [8086:0e05] type 01 class 0x060400
[ 1.599840] pci 0000:00:02.1: PME# supported from D0 D3hot D3cold
[ 1.600112] pci 0000:00:02.2: [8086:0e06] type 01 class 0x060400
[ 1.600462] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[ 1.600731] pci 0000:00:02.3: [8086:0e07] type 01 class 0x060400
[ 1.601081] pci 0000:00:02.3: PME# supported from D0 D3hot D3cold
[ 1.601380] pci 0000:00:03.0: [8086:0e08] type 01 class 0x060400
[ 1.601545] pci 0000:00:03.0: enabling Extended Tags
[ 1.601754] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 1.602026] pci 0000:00:03.1: [8086:0e09] type 01 class 0x060400
[ 1.602382] pci 0000:00:03.1: PME# supported from D0 D3hot D3cold
[ 1.602653] pci 0000:00:03.2: [8086:0e0a] type 01 class 0x060400
[ 1.603003] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[ 1.603275] pci 0000:00:03.3: [8086:0e0b] type 01 class 0x060400
[ 1.603625] pci 0000:00:03.3: PME# supported from D0 D3hot D3cold
[ 1.603895] pci 0000:00:05.0: [8086:0e28] type 00 class 0x088000
[ 1.604321] pci 0000:00:05.2: [8086:0e2a] type 00 class 0x088000
[ 1.604744] pci 0000:00:05.4: [8086:0e2c] type 00 class 0x080020
[ 1.604795] pci 0000:00:05.4: reg 0x10: [mem 0xfb304000-0xfb304fff]
[ 1.605266] pci 0000:00:06.0: [8086:0e10] type 00 class 0x088000
[ 1.605697] pci 0000:00:06.1: [8086:0e11] type 00 class 0x088000
[ 1.606116] pci 0000:00:06.2: [8086:0e12] type 00 class 0x088000
[ 1.606545] pci 0000:00:06.3: [8086:0e13] type 00 class 0x088000
[ 1.606964] pci 0000:00:06.4: [8086:0e14] type 00 class 0x088000
[ 1.607385] pci 0000:00:06.5: [8086:0e15] type 00 class 0x088000
[ 1.607803] pci 0000:00:06.6: [8086:0e16] type 00 class 0x088000
[ 1.608220] pci 0000:00:06.7: [8086:0e17] type 00 class 0x088000
[ 1.608645] pci 0000:00:07.0: [8086:0e18] type 00 class 0x088000
[ 1.609067] pci 0000:00:07.1: [8086:0e19] type 00 class 0x088000
[ 1.609493] pci 0000:00:07.2: [8086:0e1a] type 00 class 0x088000
[ 1.609911] pci 0000:00:07.3: [8086:0e1b] type 00 class 0x088000
[ 1.610339] pci 0000:00:07.4: [8086:0e1c] type 00 class 0x088000
[ 1.610866] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
[ 1.610924] pci 0000:00:1a.0: reg 0x10: [mem 0xfb302000-0xfb3023ff]
[ 1.611240] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 1.611451] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
[ 1.611800] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 1.611872] pci 0000:00:1c.0: Enabling MPC IRBNCE
[ 1.611879] pci 0000:00:1c.0: Intel PCH root port ACS workaround enabled
[ 1.612072] pci 0000:00:1c.1: [8086:1e12] type 01 class 0x060400
[ 1.612422] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[ 1.612491] pci 0000:00:1c.1: Enabling MPC IRBNCE
[ 1.612498] pci 0000:00:1c.1: Intel PCH root port ACS workaround enabled
[ 1.612697] pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400
[ 1.613046] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[ 1.613116] pci 0000:00:1c.4: Enabling MPC IRBNCE
[ 1.613122] pci 0000:00:1c.4: Intel PCH root port ACS workaround enabled
[ 1.613344] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
[ 1.613402] pci 0000:00:1d.0: reg 0x10: [mem 0xfb301000-0xfb3013ff]
[ 1.613718] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 1.613915] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
[ 1.614322] pci 0000:00:1f.0: [8086:1e48] type 00 class 0x060100
[ 1.614847] pci 0000:00:1f.2: [8086:1e02] type 00 class 0x010601
[ 1.614903] pci 0000:00:1f.2: reg 0x10: [io 0xf070-0xf077]
[ 1.614933] pci 0000:00:1f.2: reg 0x14: [io 0xf060-0xf063]
[ 1.614963] pci 0000:00:1f.2: reg 0x18: [io 0xf050-0xf057]
[ 1.614993] pci 0000:00:1f.2: reg 0x1c: [io 0xf040-0xf043]
[ 1.615023] pci 0000:00:1f.2: reg 0x20: [io 0xf020-0xf03f]
[ 1.615053] pci 0000:00:1f.2: reg 0x24: [mem 0xfb300000-0xfb3007ff]
[ 1.615236] pci 0000:00:1f.2: PME# supported from D3hot
[ 1.615419] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
[ 1.615490] pci 0000:00:1f.3: reg 0x10: [mem 0x3ffffff00000-0x3ffffff000ff 64bit]
[ 1.615576] pci 0000:00:1f.3: reg 0x20: [io 0xf000-0xf01f]
[ 1.615916] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 1.616084] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 1.616287] pci 0000:03:00.0: [10de:01d3] type 00 class 0x030000
[ 1.616339] pci 0000:03:00.0: reg 0x10: [mem 0xfa000000-0xfaffffff]
[ 1.616382] pci 0000:03:00.0: reg 0x14: [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.616425] pci 0000:03:00.0: reg 0x1c: [mem 0xf9000000-0xf9ffffff 64bit]
[ 1.616479] pci 0000:03:00.0: reg 0x30: [mem 0xfb000000-0xfb01ffff pref]
[ 1.616760] pci 0000:03:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
[ 1.616787] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 1.616806] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 1.616823] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.616954] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 1.617119] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 1.617279] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 1.617452] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 1.617615] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 1.617775] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 1.617937] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 1.618094] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 1.618316] pci 0000:0c:00.0: [1106:3483] type 00 class 0x0c0330
[ 1.618399] pci 0000:0c:00.0: reg 0x10: [mem 0xfb200000-0xfb200fff 64bit]
[ 1.618761] pci 0000:0c:00.0: PME# supported from D0 D3cold
[ 1.618953] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 1.618972] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 1.619181] pci 0000:0d:00.0: [10ec:8168] type 00 class 0x020000
[ 1.619247] pci 0000:0d:00.0: reg 0x10: [io 0xe000-0xe0ff]
[ 1.619337] pci 0000:0d:00.0: reg 0x18: [mem 0xfb104000-0xfb104fff 64bit]
[ 1.619392] pci 0000:0d:00.0: reg 0x20: [mem 0xfb100000-0xfb103fff 64bit]
[ 1.619722] pci 0000:0d:00.0: supports D1 D2
[ 1.619723] pci 0000:0d:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.619988] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 1.619999] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 1.620009] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 1.620094] pci_bus 0000:0e: extended config space not accessible
[ 1.620255] pci 0000:00:1e.0: PCI bridge to [bus 0e] (subtractive decode)
[ 1.620290] pci 0000:00:1e.0: bridge window [io 0x0000-0x03af window] (subtractive decode)
[ 1.620291] pci 0000:00:1e.0: bridge window [io 0x03e0-0x0cf7 window] (subtractive decode)
[ 1.620293] pci 0000:00:1e.0: bridge window [io 0x03b0-0x03df window] (subtractive decode)
[ 1.620294] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff window] (subtractive decode)
[ 1.620295] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode)
[ 1.620296] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000dffff window] (subtractive decode)
[ 1.620297] pci 0000:00:1e.0: bridge window [mem 0xcc000000-0xffffffff window] (subtractive decode)
[ 1.620299] pci 0000:00:1e.0: bridge window [mem 0x440000000-0x3fffffffffff window] (subtractive decode)
[ 1.620843] xen: registering gsi 13 triggering 1 polarity 0
[ 1.621072] ACPI: PCI Root Bridge [UNC0] (domain 0000 [bus ff])
[ 1.621076] acpi PNP0A03:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 1.621101] acpi PNP0A03:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR]
[ 1.621164] PCI host bridge to bus 0000:ff
[ 1.621166] pci_bus 0000:ff: root bus resource [bus ff]
[ 1.621224] pci 0000:ff:08.0: [8086:0e80] type 00 class 0x088000
[ 1.621479] pci 0000:ff:08.2: [8086:0e32] type 00 class 0x110100
[ 1.621738] pci 0000:ff:08.3: [8086:0e83] type 00 class 0x088000
[ 1.622081] pci 0000:ff:08.4: [8086:0e84] type 00 class 0x088000
[ 1.622440] pci 0000:ff:08.5: [8086:0e85] type 00 class 0x088000
[ 1.622778] pci 0000:ff:08.6: [8086:0e86] type 00 class 0x088000
[ 1.623116] pci 0000:ff:08.7: [8086:0e87] type 00 class 0x088000
[ 1.623447] pci 0000:ff:09.0: [8086:0e90] type 00 class 0x088000
[ 1.623697] pci 0000:ff:09.2: [8086:0e33] type 00 class 0x110100
[ 1.623954] pci 0000:ff:09.3: [8086:0e93] type 00 class 0x088000
[ 1.624292] pci 0000:ff:09.4: [8086:0e94] type 00 class 0x088000
[ 1.624637] pci 0000:ff:09.5: [8086:0e95] type 00 class 0x088000
[ 1.624973] pci 0000:ff:09.6: [8086:0e96] type 00 class 0x088000
[ 1.625297] pci 0000:ff:0a.0: [8086:0ec0] type 00 class 0x088000
[ 1.625540] pci 0000:ff:0a.1: [8086:0ec1] type 00 class 0x088000
[ 1.625777] pci 0000:ff:0a.2: [8086:0ec2] type 00 class 0x088000
[ 1.626021] pci 0000:ff:0a.3: [8086:0ec3] type 00 class 0x088000
[ 1.626282] pci 0000:ff:0b.0: [8086:0e1e] type 00 class 0x088000
[ 1.626523] pci 0000:ff:0b.3: [8086:0e1f] type 00 class 0x088000
[ 1.626771] pci 0000:ff:0c.0: [8086:0ee0] type 00 class 0x088000
[ 1.627008] pci 0000:ff:0c.1: [8086:0ee2] type 00 class 0x088000
[ 1.627242] pci 0000:ff:0c.2: [8086:0ee4] type 00 class 0x088000
[ 1.627476] pci 0000:ff:0c.3: [8086:0ee6] type 00 class 0x088000
[ 1.627712] pci 0000:ff:0c.4: [8086:0ee8] type 00 class 0x088000
[ 1.627950] pci 0000:ff:0c.5: [8086:0eea] type 00 class 0x088000
[ 1.628192] pci 0000:ff:0d.0: [8086:0ee1] type 00 class 0x088000
[ 1.628427] pci 0000:ff:0d.1: [8086:0ee3] type 00 class 0x088000
[ 1.628664] pci 0000:ff:0d.2: [8086:0ee5] type 00 class 0x088000
[ 1.628898] pci 0000:ff:0d.3: [8086:0ee7] type 00 class 0x088000
[ 1.629132] pci 0000:ff:0d.4: [8086:0ee9] type 00 class 0x088000
[ 1.629377] pci 0000:ff:0d.5: [8086:0eeb] type 00 class 0x088000
[ 1.629620] pci 0000:ff:0e.0: [8086:0ea0] type 00 class 0x088000
[ 1.629863] pci 0000:ff:0e.1: [8086:0e30] type 00 class 0x110100
[ 1.630142] pci 0000:ff:0f.0: [8086:0ea8] type 00 class 0x088000
[ 1.630486] pci 0000:ff:0f.1: [8086:0e71] type 00 class 0x088000
[ 1.630825] pci 0000:ff:0f.2: [8086:0eaa] type 00 class 0x088000
[ 1.631159] pci 0000:ff:0f.3: [8086:0eab] type 00 class 0x088000
[ 1.631491] pci 0000:ff:0f.4: [8086:0eac] type 00 class 0x088000
[ 1.631824] pci 0000:ff:0f.5: [8086:0ead] type 00 class 0x088000
[ 1.632170] pci 0000:ff:10.0: [8086:0eb0] type 00 class 0x088000
[ 1.632510] pci 0000:ff:10.1: [8086:0eb1] type 00 class 0x088000
[ 1.632844] pci 0000:ff:10.2: [8086:0eb2] type 00 class 0x088000
[ 1.633179] pci 0000:ff:10.3: [8086:0eb3] type 00 class 0x088000
[ 1.633517] pci 0000:ff:10.4: [8086:0eb4] type 00 class 0x088000
[ 1.633852] pci 0000:ff:10.5: [8086:0eb5] type 00 class 0x088000
[ 1.634190] pci 0000:ff:10.6: [8086:0eb6] type 00 class 0x088000
[ 1.634528] pci 0000:ff:10.7: [8086:0eb7] type 00 class 0x088000
[ 1.634856] pci 0000:ff:13.0: [8086:0e1d] type 00 class 0x088000
[ 1.635096] pci 0000:ff:13.1: [8086:0e34] type 00 class 0x110100
[ 1.635340] pci 0000:ff:13.4: [8086:0e81] type 00 class 0x088000
[ 1.635575] pci 0000:ff:13.5: [8086:0e36] type 00 class 0x110100
[ 1.635830] pci 0000:ff:16.0: [8086:0ec8] type 00 class 0x088000
[ 1.636065] pci 0000:ff:16.1: [8086:0ec9] type 00 class 0x088000
[ 1.636299] pci 0000:ff:16.2: [8086:0eca] type 00 class 0x088000
[ 1.636583] pci 0000:ff:1c.0: [8086:0e60] type 00 class 0x088000
[ 1.636822] pci 0000:ff:1c.1: [8086:0e38] type 00 class 0x110100
[ 1.637112] pci 0000:ff:1d.0: [8086:0e68] type 00 class 0x088000
[ 1.637452] pci 0000:ff:1d.1: [8086:0e79] type 00 class 0x088000
[ 1.637787] pci 0000:ff:1d.2: [8086:0e6a] type 00 class 0x088000
[ 1.638122] pci 0000:ff:1d.3: [8086:0e6b] type 00 class 0x088000
[ 1.638467] pci 0000:ff:1d.4: [8086:0e6c] type 00 class 0x088000
[ 1.638806] pci 0000:ff:1d.5: [8086:0e6d] type 00 class 0x088000
[ 1.639151] pci 0000:ff:1e.0: [8086:0ef0] type 00 class 0x088000
[ 1.639486] pci 0000:ff:1e.1: [8086:0ef1] type 00 class 0x088000
[ 1.639826] pci 0000:ff:1e.2: [8086:0ef2] type 00 class 0x088000
[ 1.640161] pci 0000:ff:1e.3: [8086:0ef3] type 00 class 0x088000
[ 1.640495] pci 0000:ff:1e.4: [8086:0ef4] type 00 class 0x088000
[ 1.640831] pci 0000:ff:1e.5: [8086:0ef5] type 00 class 0x088000
[ 1.641166] pci 0000:ff:1e.6: [8086:0ef6] type 00 class 0x088000
[ 1.641506] pci 0000:ff:1e.7: [8086:0ef7] type 00 class 0x088000
[ 1.641972] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[ 1.642060] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[ 1.642144] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 1.642238] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 *4 5 6 10 11 12 14 15)
[ 1.642322] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.642407] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.642491] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.642576] ACPI: PCI Interrupt Link [LNKH] (IRQs *3 4 5 6 7 10 11 12 14 15)
[ 1.645319] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 4/0x1 ignored.
[ 1.645319] ACPI: Unable to map lapic to logical cpu number
[ 1.645490] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 5/0x3 ignored.
[ 1.645491] ACPI: Unable to map lapic to logical cpu number
[ 1.645638] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 6/0x5 ignored.
[ 1.645639] ACPI: Unable to map lapic to logical cpu number
[ 1.645786] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 7/0x7 ignored.
[ 1.645787] ACPI: Unable to map lapic to logical cpu number
[ 1.645876] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 8/0x8 ignored.
[ 1.645877] ACPI: Unable to map lapic to logical cpu number
[ 1.645970] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 9/0x9 ignored.
[ 1.645971] ACPI: Unable to map lapic to logical cpu number
[ 1.646060] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 10/0xa ignored.
[ 1.646061] ACPI: Unable to map lapic to logical cpu number
[ 1.646154] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 11/0xb ignored.
[ 1.646155] ACPI: Unable to map lapic to logical cpu number
[ 1.646244] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 12/0x10 ignored.
[ 1.646245] ACPI: Unable to map lapic to logical cpu number
[ 1.646339] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 13/0x11 ignored.
[ 1.646340] ACPI: Unable to map lapic to logical cpu number
[ 1.646430] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 14/0x12 ignored.
[ 1.646430] ACPI: Unable to map lapic to logical cpu number
[ 1.646525] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 15/0x13 ignored.
[ 1.646526] ACPI: Unable to map lapic to logical cpu number
[ 1.646616] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 16/0x14 ignored.
[ 1.646617] ACPI: Unable to map lapic to logical cpu number
[ 1.646711] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 17/0x15 ignored.
[ 1.646712] ACPI: Unable to map lapic to logical cpu number
[ 1.646807] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 18/0x16 ignored.
[ 1.646808] ACPI: Unable to map lapic to logical cpu number
[ 1.646903] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 19/0x17 ignored.
[ 1.646904] ACPI: Unable to map lapic to logical cpu number
[ 1.646997] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 20/0x18 ignored.
[ 1.646998] ACPI: Unable to map lapic to logical cpu number
[ 1.647093] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 21/0x19 ignored.
[ 1.647094] ACPI: Unable to map lapic to logical cpu number
[ 1.647186] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 22/0x1a ignored.
[ 1.647187] ACPI: Unable to map lapic to logical cpu number
[ 1.647283] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 23/0x1b ignored.
[ 1.647283] ACPI: Unable to map lapic to logical cpu number
[ 1.647816] xen:balloon: Initialising balloon driver
[ 1.647816] iommu: Default domain type: Translated
[ 1.649339] pci 0000:03:00.0: vgaarb: setting as boot VGA device
[ 1.649340] pci 0000:03:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[ 1.649354] pci 0000:03:00.0: vgaarb: bridge control possible
[ 1.649355] vgaarb: loaded
[ 1.649451] EDAC MC: Ver: 3.0.0
[ 1.650417] NetLabel: Initializing
[ 1.650417] NetLabel: domain hash size = 128
[ 1.650417] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO
[ 1.650417] NetLabel: unlabeled traffic allowed by default
[ 1.650417] PCI: Using ACPI for IRQ routing
[ 1.678180] PCI: pci_cache_line_size set to 64 bytes
[ 1.679029] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 1.679032] e820: reserve RAM buffer [mem 0x80062000-0x83ffffff]
[ 1.681330] clocksource: Switched to clocksource tsc-early
[ 1.692898] VFS: Disk quotas dquot_6.6.0
[ 1.692915] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.692937] hugetlbfs: disabling because there are no supported hugepage sizes
[ 1.693029] AppArmor: AppArmor Filesystem Enabled
[ 1.693047] pnp: PnP ACPI init
[ 1.693193] system 00:00: [mem 0xfc000000-0xfcffffff] has been reserved
[ 1.693195] system 00:00: [mem 0xfd000000-0xfdffffff] has been reserved
[ 1.693196] system 00:00: [mem 0xfe000000-0xfeafffff] has been reserved
[ 1.693198] system 00:00: [mem 0xfeb00000-0xfebfffff] has been reserved
[ 1.693199] system 00:00: [mem 0xfed00400-0xfed3ffff] could not be reserved
[ 1.693201] system 00:00: [mem 0xfed45000-0xfedfffff] has been reserved
[ 1.693202] system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved
[ 1.693208] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.693357] system 00:01: [mem 0xfbffc000-0xfbffdfff] could not be reserved
[ 1.693362] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.693598] system 00:02: [io 0x0a00-0x0a1f] has been reserved
[ 1.693599] system 00:02: [io 0x0a20-0x0a2f] has been reserved
[ 1.693601] system 00:02: [io 0x0a30-0x0a3f] has been reserved
[ 1.693605] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.693634] xen: registering gsi 1 triggering 1 polarity 0
[ 1.693679] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
[ 1.693715] xen: registering gsi 12 triggering 1 polarity 0
[ 1.693756] pnp 00:04: Plug and Play ACPI device, IDs PNP0f03 PNP0f13 (active)
[ 1.693783] xen: registering gsi 8 triggering 1 polarity 0
[ 1.693820] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 1.693912] system 00:06: [io 0x04d0-0x04d1] has been reserved
[ 1.693917] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.694191] system 00:07: [io 0x0400-0x0453] has been reserved
[ 1.694192] system 00:07: [io 0x0458-0x047f] has been reserved
[ 1.694194] system 00:07: [io 0x1180-0x119f] has been reserved
[ 1.694195] system 00:07: [io 0x0500-0x057f] has been reserved
[ 1.694197] system 00:07: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 1.694199] system 00:07: [mem 0xfec00000-0xfecfffff] could not be reserved
[ 1.694201] system 00:07: [mem 0xff000000-0xffffffff] has been reserved
[ 1.694205] system 00:07: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.694319] system 00:08: [io 0x0454-0x0457] has been reserved
[ 1.694324] system 00:08: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 1.694787] pnp: PnP ACPI: found 9 devices
[ 1.714225] PM-Timer failed consistency check (0xffffff) - aborting.
[ 1.714286] NET: Registered protocol family 2
[ 1.714593] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[ 1.714613] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 1.714663] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 1.714685] TCP: Hash tables configured (established 16384 bind 16384)
[ 1.714728] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 1.714737] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 1.714905] NET: Registered protocol family 1
[ 1.714914] NET: Registered protocol family 44
[ 1.714949] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 1.714990] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 1.715028] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 1.715042] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 1.715052] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.715069] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 1.715107] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 1.715145] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 1.715182] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 1.715220] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 1.715258] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 1.715295] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 1.715334] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 1.715373] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 1.715387] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 1.715414] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 1.715420] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 1.715434] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 1.715460] pci 0000:00:1e.0: PCI bridge to [bus 0e]
[ 1.715500] pci_bus 0000:00: resource 4 [io 0x0000-0x03af window]
[ 1.715501] pci_bus 0000:00: resource 5 [io 0x03e0-0x0cf7 window]
[ 1.715502] pci_bus 0000:00: resource 6 [io 0x03b0-0x03df window]
[ 1.715503] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 1.715505] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 1.715506] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 1.715507] pci_bus 0000:00: resource 10 [mem 0xcc000000-0xffffffff window]
[ 1.715508] pci_bus 0000:00: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 1.715510] pci_bus 0000:03: resource 1 [mem 0xf9000000-0xfb0fffff]
[ 1.715511] pci_bus 0000:03: resource 2 [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.715513] pci_bus 0000:0c: resource 1 [mem 0xfb200000-0xfb2fffff]
[ 1.715514] pci_bus 0000:0d: resource 0 [io 0xe000-0xefff]
[ 1.715516] pci_bus 0000:0d: resource 1 [mem 0xfb100000-0xfb1fffff]
[ 1.715517] pci_bus 0000:0e: resource 4 [io 0x0000-0x03af window]
[ 1.715518] pci_bus 0000:0e: resource 5 [io 0x03e0-0x0cf7 window]
[ 1.715520] pci_bus 0000:0e: resource 6 [io 0x03b0-0x03df window]
[ 1.715521] pci_bus 0000:0e: resource 7 [io 0x0d00-0xffff window]
[ 1.715522] pci_bus 0000:0e: resource 8 [mem 0x000a0000-0x000bffff window]
[ 1.715523] pci_bus 0000:0e: resource 9 [mem 0x000c0000-0x000dffff window]
[ 1.715525] pci_bus 0000:0e: resource 10 [mem 0xcc000000-0xffffffff window]
[ 1.715526] pci_bus 0000:0e: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 1.715667] pci 0000:00:05.0: disabled boot interrupts on device [8086:0e28]
[ 1.715854] xen: registering gsi 16 triggering 0 polarity 1
[ 1.715882] xen: --> pirq=16 -> irq=16 (gsi=16)
[ 1.716124] xen: registering gsi 23 triggering 0 polarity 1
[ 1.716144] xen: --> pirq=23 -> irq=23 (gsi=23)
[ 1.716346] pci 0000:03:00.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[ 1.716429] xen: registering gsi 16 triggering 0 polarity 1
[ 1.716433] Already setup the GSI :16
[ 1.716479] xen: registering gsi 17 triggering 0 polarity 1
[ 1.716496] xen: --> pirq=17 -> irq=17 (gsi=17)
[ 1.716946] PCI: CLS 64 bytes, default 64
[ 1.717001] Trying to unpack rootfs image as initramfs...
[ 2.249216] Freeing initrd memory: 34772K
[ 2.249272] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x23f454f0625, max_idle_ns: 440795228661 ns
[ 2.249378] clocksource: Switched to clocksource tsc
[ 2.249848] Initialise system trusted keyrings
[ 2.249861] Key type blacklist registered
[ 2.250006] workingset: timestamp_bits=36 max_order=18 bucket_order=0
[ 2.251095] zbud: loaded
[ 2.251551] integrity: Platform Keyring initialized
[ 2.251555] Key type asymmetric registered
[ 2.251556] Asymmetric key parser 'x509' registered
[ 2.251566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 2.251721] io scheduler mq-deadline registered
[ 2.252044] xen: registering gsi 26 triggering 0 polarity 1
[ 2.252074] xen: --> pirq=26 -> irq=26 (gsi=26)
[ 2.252617] xen: registering gsi 26 triggering 0 polarity 1
[ 2.252622] Already setup the GSI :26
[ 2.253120] xen: registering gsi 32 triggering 0 polarity 1
[ 2.253138] xen: --> pirq=32 -> irq=32 (gsi=32)
[ 2.253646] xen: registering gsi 32 triggering 0 polarity 1
[ 2.253650] Already setup the GSI :32
[ 2.254145] xen: registering gsi 32 triggering 0 polarity 1
[ 2.254149] Already setup the GSI :32
[ 2.254635] xen: registering gsi 32 triggering 0 polarity 1
[ 2.254640] Already setup the GSI :32
[ 2.255134] xen: registering gsi 40 triggering 0 polarity 1
[ 2.255152] xen: --> pirq=40 -> irq=40 (gsi=40)
[ 2.255651] xen: registering gsi 40 triggering 0 polarity 1
[ 2.255656] Already setup the GSI :40
[ 2.256141] xen: registering gsi 40 triggering 0 polarity 1
[ 2.256146] Already setup the GSI :40
[ 2.256635] xen: registering gsi 40 triggering 0 polarity 1
[ 2.256640] Already setup the GSI :40
[ 2.257129] xen: registering gsi 17 triggering 0 polarity 1
[ 2.257134] Already setup the GSI :17
[ 2.257753] xen: registering gsi 17 triggering 0 polarity 1
[ 2.257757] Already setup the GSI :17
[ 2.258120] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 2.258132] intel_idle: MWAIT substates: 0x1120
[ 2.258260] Monitor-Mwait will be used to enter C-1 state
[ 2.258270] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 2.258271] intel_idle: v0.5.1 model 0x3E
[ 2.258276] intel_idle: intel_idle yielding to none
[ 2.258415] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 2.258700] ACPI: \_SB_.SCK0.C002: Found 1 idle states
[ 2.259064] ACPI: \_SB_.SCK0.C004: Found 1 idle states
[ 2.259367] ACPI: \_SB_.SCK0.C006: Found 1 idle states
[ 2.260033] xen_mcelog: /dev/mcelog registered by Xen
[ 2.260607] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 2.261340] hpet_acpi_add: no address or irqs in _CRS
[ 2.261363] Linux agpgart interface v0.103
[ 2.261461] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
[ 2.261462] AMD-Vi: AMD IOMMUv2 functionality not available on this system
[ 2.261866] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
[ 2.262495] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 2.262501] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 2.262707] mousedev: PS/2 mouse device common for all mice
[ 2.262788] rtc_cmos 00:05: RTC can wake from S4
[ 2.263155] rtc_cmos 00:05: registered as rtc0
[ 2.263231] rtc_cmos 00:05: setting system clock to 2021-02-01T14:42:12 UTC (1612190532)
[ 2.263253] rtc_cmos 00:05: alarms up to one month, y3k, 114 bytes nvram
[ 2.263261] intel_pstate: CPU model not supported
[ 2.263386] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.264139] NET: Registered protocol family 10
[ 2.284721] Segment Routing with IPv6
[ 2.284742] mip6: Mobile IPv6
[ 2.284745] NET: Registered protocol family 17
[ 2.284858] mpls_gso: MPLS GSO support
[ 2.285150] IPI shorthand broadcast: enabled
[ 2.285157] sched_clock: Marking stable (2206874906, 78236752)->(2297763652, -12651994)
[ 2.285490] registered taskstats version 1
[ 2.285493] Loading compiled-in X.509 certificates
[ 2.325233] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1'
[ 2.325253] Loaded X.509 cert 'Debian Secure Boot Signer 2020: 00b55eb3b9'
[ 2.325289] zswap: loaded using pool lzo/zbud
[ 2.325738] Key type ._fscrypt registered
[ 2.325739] Key type .fscrypt registered
[ 2.325740] Key type fscrypt-provisioning registered
[ 2.325786] AppArmor: AppArmor sha1 policy hashing enabled
[ 2.328318] Freeing unused kernel image (initmem) memory: 2380K
[ 2.357373] Write protecting the kernel read-only data: 18432k
[ 2.371440] Freeing unused kernel image (text/rodata gap) memory: 2040K
[ 2.371511] Freeing unused kernel image (rodata/data gap) memory: 36K
[ 2.822307] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[ 2.822386] Run /init as init process
[ 2.822389] with arguments:
[ 2.822390] /init
[ 2.822391] placeholder
[ 2.822391] with environment:
[ 2.822393] HOME=/
[ 2.822393] TERM=linux
[ 3.146199] xen: registering gsi 18 triggering 0 polarity 1
[ 3.146239] xen: --> pirq=18 -> irq=18 (gsi=18)
[ 3.146404] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[ 3.147113] i2c i2c-0: 4/4 memory slots populated (from DMI)
[ 3.148825] ACPI: bus type USB registered
[ 3.148861] usbcore: registered new interface driver usbfs
[ 3.148874] usbcore: registered new interface driver hub
[ 3.149461] usbcore: registered new device driver usb
[ 3.154274] SCSI subsystem initialized
[ 3.156140] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 3.158342] xen: registering gsi 16 triggering 0 polarity 1
[ 3.158348] Already setup the GSI :16
[ 3.159163] ehci-pci: EHCI PCI platform driver
[ 3.159298] xen: registering gsi 16 triggering 0 polarity 1
[ 3.159308] Already setup the GSI :16
[ 3.160334] ehci-pci 0000:00:1a.0: EHCI Host Controller
[ 3.160345] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
[ 3.160390] ehci-pci 0000:00:1a.0: debug port 2
[ 3.164368] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
[ 3.165340] ehci-pci 0000:00:1a.0: irq 16, io mem 0xfb302000
[ 3.182604] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[ 3.184260] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.184263] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.184264] usb usb1: Product: EHCI Host Controller
[ 3.184266] usb usb1: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 3.184267] usb usb1: SerialNumber: 0000:00:1a.0
[ 3.184463] hub 1-0:1.0: USB hub found
[ 3.184488] hub 1-0:1.0: 2 ports detected
[ 3.184945] xen: registering gsi 23 triggering 0 polarity 1
[ 3.184950] Already setup the GSI :23
[ 3.185076] ehci-pci 0000:00:1d.0: EHCI Host Controller
[ 3.185085] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
[ 3.185130] ehci-pci 0000:00:1d.0: debug port 2
[ 3.185284] xen: registering gsi 17 triggering 0 polarity 1
[ 3.185289] Already setup the GSI :17
[ 3.189117] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
[ 3.189177] ehci-pci 0000:00:1d.0: irq 23, io mem 0xfb301000
[ 3.189267] libata version 3.00 loaded.
[ 3.194907] libphy: r8169: probed
[ 3.195172] r8169 0000:0d:00.0 eth0: RTL8168h/8111h, 00:e0:4c:0a:52:97, XID 541, IRQ 89
[ 3.195175] r8169 0000:0d:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
[ 3.198062] ahci 0000:00:1f.2: version 3.0
[ 3.198176] xen: registering gsi 19 triggering 0 polarity 1
[ 3.198197] xen: --> pirq=19 -> irq=19 (gsi=19)
[ 3.198375] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
[ 3.198378] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst
[ 3.201345] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 3.201519] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.201522] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.201524] usb usb2: Product: EHCI Host Controller
[ 3.201526] usb usb2: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 3.201528] usb usb2: SerialNumber: 0000:00:1d.0
[ 3.201747] hub 2-0:1.0: USB hub found
[ 3.201777] hub 2-0:1.0: 2 ports detected
[ 3.202063] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 3.202072] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 3
[ 3.202636] xhci_hcd 0000:0c:00.0: hcc params 0x002841eb hci version 0x100 quirks 0x0000000000000890
[ 3.203041] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.203043] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.203045] usb usb3: Product: xHCI Host Controller
[ 3.203047] usb usb3: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 3.203049] usb usb3: SerialNumber: 0000:0c:00.0
[ 3.203227] hub 3-0:1.0: USB hub found
[ 3.203256] hub 3-0:1.0: 1 port detected
[ 3.203544] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 3.203550] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 4
[ 3.203555] xhci_hcd 0000:0c:00.0: Host supports USB 3.0 SuperSpeed
[ 3.203776] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
[ 3.203779] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.203781] usb usb4: Product: xHCI Host Controller
[ 3.203782] usb usb4: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 3.203783] usb usb4: SerialNumber: 0000:0c:00.0
[ 3.203978] hub 4-0:1.0: USB hub found
[ 3.204008] hub 4-0:1.0: 4 ports detected
[ 3.209996] scsi host0: ahci
[ 3.210379] scsi host1: ahci
[ 3.210683] scsi host2: ahci
[ 3.211191] scsi host3: ahci
[ 3.213429] scsi host4: ahci
[ 3.214474] scsi host5: ahci
[ 3.214556] ata1: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300100 irq 90
[ 3.214559] ata2: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300180 irq 90
[ 3.214561] ata3: DUMMY
[ 3.214562] ata4: DUMMY
[ 3.214563] ata5: DUMMY
[ 3.214564] ata6: DUMMY
[ 3.231993] r8169 0000:0d:00.0 enp13s0: renamed from eth0
[ 3.517376] usb 1-1: new high-speed USB device number 2 using ehci-pci
[ 3.528784] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.528809] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.529199] ata1.00: ATA-11: KINGSTON SUV400S37120G, 0C3FD6SD, max UDMA/133
[ 3.529202] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 3.530032] ata1.00: configured for UDMA/133
[ 3.530192] scsi 0:0:0:0: Direct-Access ATA KINGSTON SUV400S D6SD PQ: 0 ANSI: 5
[ 3.537373] usb 3-1: new high-speed USB device number 2 using xhci_hcd
[ 3.537386] usb 2-1: new high-speed USB device number 2 using ehci-pci
[ 3.545522] ata2.00: ATA-8: KINGSTON SV300S37A120G, 525ABBF0, max UDMA/133
[ 3.545524] ata2.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 3.566634] ata2.00: configured for UDMA/133
[ 3.566764] scsi 1:0:0:0: Direct-Access ATA KINGSTON SV300S3 BBF0 PQ: 0 ANSI: 5
[ 3.577199] sd 1:0:0:0: [sdb] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 3.577217] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 3.577220] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 3.577223] sd 1:0:0:0: [sdb] Write Protect is off
[ 3.577227] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 3.577243] sd 0:0:0:0: [sda] Write Protect is off
[ 3.577245] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.577268] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 3.577286] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 3.594805] sd 1:0:0:0: [sdb] Attached SCSI disk
[ 3.602006] sda: sda1 sda2
[ 3.602690] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.665476] device-mapper: uevent: version 1.0.3
[ 3.665601] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[ 3.673658] usb 1-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 3.673661] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.674005] hub 1-1:1.0: USB hub found
[ 3.674179] hub 1-1:1.0: 6 ports detected
[ 3.690657] usb 3-1: New USB device found, idVendor=2109, idProduct=3431, bcdDevice= 4.20
[ 3.690660] usb 3-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[ 3.690661] usb 3-1: Product: USB2.0 Hub
[ 3.691645] hub 3-1:1.0: USB hub found
[ 3.691989] hub 3-1:1.0: 4 ports detected
[ 3.693654] usb 2-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 3.693657] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.694157] hub 2-1:1.0: USB hub found
[ 3.694283] hub 2-1:1.0: 8 ports detected
[ 3.811430] PM: Image not found (code -22)
[ 3.969332] usb 1-1.2: new low-speed USB device number 3 using ehci-pci
[ 3.970134] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 3.989350] usb 2-1.4: new high-speed USB device number 3 using ehci-pci
[ 4.084193] usb 1-1.2: New USB device found, idVendor=099a, idProduct=610c, bcdDevice= 0.01
[ 4.084196] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 4.084198] usb 1-1.2: Product: USB Multimedia Keyboard
[ 4.084199] usb 1-1.2: Manufacturer:
[ 4.109504] usb 2-1.4: New USB device found, idVendor=148f, idProduct=7601, bcdDevice= 0.00
[ 4.109507] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.109508] usb 2-1.4: Product: 802.11 n WLAN
[ 4.109509] usb 2-1.4: Manufacturer: MediaTek
[ 4.109510] usb 2-1.4: SerialNumber: 1.0
[ 4.209068] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist.
[ 5.459433] systemd[1]: Inserted module 'autofs4'
[ 5.505335] systemd[1]: systemd 247.2-5 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
[ 5.505618] systemd[1]: Detected architecture x86-64.
[ 5.508215] systemd[1]: Set hostname to <debian>.
[ 5.576257] systemd-sysv-generator[223]: SysV service '/etc/init.d/xen' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 5.593520] systemd-sysv-generator[223]: SysV service '/etc/init.d/exim4' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 5.593650] systemd-sysv-generator[223]: SysV service '/etc/init.d/xencommons' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 5.596808] systemd-sysv-generator[223]: SysV service '/etc/init.d/isc-dhcp-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 5.656794] systemd[1]: /lib/systemd/system/virtlogd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-sock → /run/libvirt/virtlogd-sock; please update the unit file accordingly.
[ 5.665747] systemd[1]: /lib/systemd/system/virtlogd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-admin-sock → /run/libvirt/virtlogd-admin-sock; please update the unit file accordingly.
[ 5.666326] systemd[1]: /lib/systemd/system/virtlockd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-sock → /run/libvirt/virtlockd-sock; please update the unit file accordingly.
[ 5.667359] systemd[1]: /lib/systemd/system/virtlockd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-admin-sock → /run/libvirt/virtlockd-admin-sock; please update the unit file accordingly.
[ 5.718990] systemd[1]: Queued start job for default target Graphical Interface.
[ 5.720940] systemd[1]: Created slice Virtual Machine and Container Slice.
[ 5.722527] systemd[1]: Created slice system-getty.slice.
[ 5.723458] systemd[1]: Created slice system-modprobe.slice.
[ 5.724350] systemd[1]: Created slice system-serial\x2dgetty.slice.
[ 5.725209] systemd[1]: Created slice User and Session Slice.
[ 5.725858] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[ 5.726463] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[ 5.727229] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
[ 5.727724] systemd[1]: Reached target Local Encrypted Volumes.
[ 5.728218] systemd[1]: Reached target Paths.
[ 5.728688] systemd[1]: Reached target Remote File Systems.
[ 5.729159] systemd[1]: Reached target Slices.
[ 5.729674] systemd[1]: Reached target Libvirt guests shutdown.
[ 5.730269] systemd[1]: Listening on Device-mapper event daemon FIFOs.
[ 5.730900] systemd[1]: Listening on LVM2 poll daemon socket.
[ 5.732452] systemd[1]: Listening on Syslog Socket.
[ 5.733096] systemd[1]: Listening on fsck to fsckd communication Socket.
[ 5.733687] systemd[1]: Listening on initctl Compatibility Named Pipe.
[ 5.734528] systemd[1]: Listening on Journal Audit Socket.
[ 5.735202] systemd[1]: Listening on Journal Socket (/dev/log).
[ 5.735937] systemd[1]: Listening on Journal Socket.
[ 5.736659] systemd[1]: Listening on udev Control Socket.
[ 5.737328] systemd[1]: Listening on udev Kernel Socket.
[ 5.738131] systemd[1]: Condition check resulted in Huge Pages File System being skipped.
[ 5.740825] systemd[1]: Mounting POSIX Message Queue File System...
[ 5.744163] systemd[1]: Mounting Kernel Debug File System...
[ 5.747458] systemd[1]: Mounting Kernel Trace File System...
[ 5.748517] systemd[1]: Finished Availability of block devices.
[ 5.752551] systemd[1]: Starting Set the console keyboard layout...
[ 5.756271] systemd[1]: Starting Create list of static device nodes for the current kernel...
[ 5.759362] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[ 5.763222] systemd[1]: Starting Load Kernel Module configfs...
[ 5.766943] systemd[1]: Starting Load Kernel Module drm...
[ 5.770748] systemd[1]: Starting Load Kernel Module fuse...
[ 5.772353] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
[ 5.772490] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[ 5.778946] systemd[1]: Starting Journal Service...
[ 5.784249] systemd[1]: Starting Load Kernel Modules...
[ 5.788792] systemd[1]: Starting Remount Root and Kernel File Systems...
[ 5.793151] systemd[1]: Starting Coldplug All udev Devices...
[ 5.798696] systemd[1]: Mounted POSIX Message Queue File System.
[ 5.799378] systemd[1]: Mounted Kernel Debug File System.
[ 5.800063] systemd[1]: Mounted Kernel Trace File System.
[ 5.801139] systemd[1]: Finished Create list of static device nodes for the current kernel.
[ 5.802268] systemd[1]: modprobe@configfs.service: Succeeded.
[ 5.802702] systemd[1]: Finished Load Kernel Module configfs.
[ 5.805935] systemd[1]: Mounting Kernel Configuration File System...
[ 5.816628] systemd[1]: Mounted Kernel Configuration File System.
[ 5.851830] fuse: init (API version 7.32)
[ 5.859341] systemd[1]: modprobe@fuse.service: Succeeded.
[ 5.859948] systemd[1]: Finished Load Kernel Module fuse.
[ 5.864206] systemd[1]: Mounting FUSE Control File System...
[ 5.869345] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[ 5.872954] xen:xen_evtchn: Event-channel device installed
[ 5.877858] systemd[1]: Finished Remount Root and Kernel File Systems.
[ 5.879579] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
[ 5.879671] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
[ 5.882999] systemd[1]: Starting Load/Save Random Seed...
[ 5.891772] systemd[1]: Starting Create System Users...
[ 5.894002] systemd[1]: Finished Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling.
[ 5.895491] systemd[1]: modprobe@drm.service: Succeeded.
[ 5.896190] systemd[1]: Finished Load Kernel Module drm.
[ 5.906180] systemd[1]: Mounted FUSE Control File System.
[ 5.917344] xen_pciback: backend is vpci
[ 5.941496] systemd[1]: Finished Create System Users.
[ 5.944934] systemd[1]: Starting Create Static Device Nodes in /dev...
[ 5.950800] systemd[1]: Finished Load/Save Random Seed.
[ 5.951724] systemd[1]: Condition check resulted in First Boot Complete being skipped.
[ 5.984479] systemd[1]: Finished Create Static Device Nodes in /dev.
[ 5.989593] systemd[1]: Starting Rule-based Manager for Device Events and Files...
[ 6.001099] systemd[1]: Finished Set the console keyboard layout.
[ 6.002977] systemd[1]: Finished Load Kernel Modules.
[ 6.004003] systemd[1]: Reached target Local File Systems (Pre).
[ 6.004672] systemd[1]: Condition check resulted in Virtual Machine and Container Storage (Compatibility) being skipped.
[ 6.004724] systemd[1]: Reached target Local File Systems.
[ 6.005343] systemd[1]: Reached target Containers.
[ 6.008834] systemd[1]: Starting Load AppArmor profiles...
[ 6.012478] systemd[1]: Starting Set console font and keymap...
[ 6.013232] systemd[1]: Condition check resulted in Mark the need to relabel after reboot being skipped.
[ 6.013447] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped.
[ 6.013591] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped.
[ 6.018486] systemd[1]: Starting Apply Kernel Variables...
[ 6.051021] systemd[1]: Finished Apply Kernel Variables.
[ 6.058996] systemd[1]: Finished Set console font and keymap.
[ 6.066370] systemd[1]: Started Rule-based Manager for Device Events and Files.
[ 6.125440] systemd[1]: Started Journal Service.
[ 6.161795] audit: type=1400 audit(1612190536.392:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="lsb_release" pid=282 comm="apparmor_parser"
[ 6.164477] audit: type=1400 audit(1612190536.396:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=281 comm="apparmor_parser"
[ 6.164483] audit: type=1400 audit(1612190536.396:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=281 comm="apparmor_parser"
[ 6.164487] audit: type=1400 audit(1612190536.396:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=281 comm="apparmor_parser"
[ 6.164893] audit: type=1400 audit(1612190536.396:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe" pid=280 comm="apparmor_parser"
[ 6.164900] audit: type=1400 audit(1612190536.396:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe//kmod" pid=280 comm="apparmor_parser"
[ 6.168739] audit: type=1400 audit(1612190536.400:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd" pid=279 comm="apparmor_parser"
[ 6.168746] audit: type=1400 audit(1612190536.400:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd//qemu_bridge_helper" pid=279 comm="apparmor_parser"
[ 6.174628] audit: type=1400 audit(1612190536.408:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="virt-aa-helper" pid=283 comm="apparmor_parser"
[ 6.231795] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input3
[ 6.245376] ACPI: Power Button [PWRB]
[ 6.245478] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
[ 6.245562] ACPI: Power Button [PWRF]
[ 7.738212] hid: raw HID events driver (C) Jiri Kosina
[ 7.742009] iTCO_vendor_support: vendor-support=0
[ 7.746422] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[ 7.746471] iTCO_wdt: Found a Panther Point TCO device (Version=2, TCOBASE=0x0460)
[ 7.746919] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[ 7.752394] usbcore: registered new interface driver usbhid
[ 7.752396] usbhid: USB HID core driver
[ 7.771586] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 7.771665] sd 1:0:0:0: Attached scsi generic sg1 type 0
[ 7.869954] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 7.870322] cfg80211: Loaded X.509 cert 'benh@debian.org: 577e021cb980e0e820821ba7b54b4961b8b4fadf'
[ 7.870682] cfg80211: Loaded X.509 cert 'romain.perier@gmail.com: 3abbc6ec146e09d1b6016ab9d6cf71dd233f0328'
[ 7.871027] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 7.871345] platform regulatory.0: firmware: failed to load regulatory.db (-2)
[ 7.871347] firmware_class: See https://wiki.debian.org/Firmware for information about missing firmware
[ 7.871349] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 7.871352] cfg80211: failed to load regulatory.db
[ 7.927923] input: PC Speaker as /devices/platform/pcspkr/input/input5
[ 8.061333] usb 2-1.4: reset high-speed USB device number 3 using ehci-pci
[ 8.164689] cryptd: max_cpu_qlen set to 1000
[ 8.165410] Adding 3905532k swap on /dev/sda1. Priority:-2 extents:1 across:3905532k SSFS
[ 8.177540] mt7601u 2-1.4:1.0: ASIC revision: 76010001 MAC revision: 76010500
[ 8.179506] mt7601u 2-1.4:1.0: firmware: direct-loading firmware mt7601u.bin
[ 8.179515] mt7601u 2-1.4:1.0: Firmware Version: 0.1.00 Build: 7640 Build time: 201302052146____
[ 8.221034] AVX version of gcm_enc/dec engaged.
[ 8.221037] AES CTR mode by8 optimization enabled
[ 8.239217] input: USB Multimedia Keyboard as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:099A:610C.0001/input/input6
[ 8.299430] hid-generic 0003:099A:610C.0001: input,hidraw0: USB HID v1.00 Keyboard [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input0
[ 8.299826] input: USB Multimedia Keyboard Consumer Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input7
[ 8.365222] input: USB Multimedia Keyboard System Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input8
[ 8.365559] hid-generic 0003:099A:610C.0002: input,hidraw1: USB HID v1.00 Device [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input1
[ 8.583763] mt7601u 2-1.4:1.0: EEPROM ver:0d fae:00
[ 8.812171] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
[ 8.812783] usbcore: registered new interface driver mt7601u
[ 8.820438] mt7601u 2-1.4:1.0 wlx20e0160064bd: renamed from wlan0
[ 11.550930] wlx20e0160064bd: authenticate with 68:ff:7b:47:86:17
[ 11.587055] wlx20e0160064bd: send auth to 68:ff:7b:47:86:17 (try 1/3)
[ 11.589458] wlx20e0160064bd: authenticated
[ 11.593337] wlx20e0160064bd: associate with 68:ff:7b:47:86:17 (try 1/3)
[ 11.598565] wlx20e0160064bd: RX AssocResp from 68:ff:7b:47:86:17 (capab=0x431 status=0 aid=2)
[ 11.636551] wlx20e0160064bd: associated
[ 11.694192] IPv6: ADDRCONF(NETDEV_CHANGE): wlx20e0160064bd: link becomes ready
[ 14.900296] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 14.935999] br-lan: port 1(enp13s0) entered blocking state
[ 14.936002] br-lan: port 1(enp13s0) entered disabled state
[ 14.936086] device enp13s0 entered promiscuous mode
[ 14.941244] r8169 0000:0d:00.0: firmware: direct-loading firmware rtl_nic/rtl8168h-2.fw
[ 14.969349] Generic FE-GE Realtek PHY r8169-d00:00: attached PHY driver [Generic FE-GE Realtek PHY] (mii_bus:phy_addr=r8169-d00:00, irq=IGNORE)
[ 15.169472] r8169 0000:0d:00.0 enp13s0: Link is Down
[ 15.173447] br-lan: port 1(enp13s0) entered blocking state
[ 15.173451] br-lan: port 1(enp13s0) entered forwarding state
[ 15.917396] br-lan: port 1(enp13s0) entered disabled state
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-02-01 14:46 ` Claudemir Todo Bom
@ 2021-02-01 15:09 ` Jan Beulich
2021-02-01 15:26 ` Claudemir Todo Bom
0 siblings, 1 reply; 26+ messages in thread
From: Jan Beulich @ 2021-02-01 15:09 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 01.02.2021 15:46, Claudemir Todo Bom wrote:
> Tested first without the debug patch and with following parameters:
And this test was all three of the non-debugging patches?
> xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
> kernel: loglevel=3
>
> same behaviour as before... black screen right after the xen messages.
>
> adding earlyprintk=xen to the kernel command line is sufficient to
> make it boot, I can imagine this can be happening because Xen is not
> releasing console to the kernel at that moment.
If the answer to the above question is "yes", then I start
suspecting this to be a different problem. I'm not sure I
see a way to debug this without having access to any output
(i.e. neither video nor serial). Without "earlyprintk=xen"
and instead with "vga=keep watchdog" on the Xen command
line, is there anything helpful (without or if need be with
the debugging patch in place)?
> The system worked well (with earlyprintk=xen), tested with the "yes
> stress test" mentioned before on a guest and on dom0.
>
> Then, I installed the debug patch and booted it again, it also needed
> the earlyprintk=xen parameter on the kernel command line. I've also
> added console_timestamps=boot to the xen command line in order to get
> the time of the messages.
>
> I'm attaching the outputs of "xl dmesg" and "dmesg" on this message.
>
> Think it is almost done! WIll wait for the next round of tests!
As per above, not sure if there's going to be one. Thanks
for your patient testing!
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-02-01 15:09 ` Jan Beulich
@ 2021-02-01 15:26 ` Claudemir Todo Bom
2021-02-01 16:48 ` Jan Beulich
0 siblings, 1 reply; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-02-01 15:26 UTC (permalink / raw)
To: Jan Beulich; +Cc: xen-devel
[-- Attachment #1: Type: text/plain, Size: 2123 bytes --]
Em seg., 1 de fev. de 2021 às 12:09, Jan Beulich <jbeulich@suse.com> escreveu:
>
> On 01.02.2021 15:46, Claudemir Todo Bom wrote:
> > Tested first without the debug patch and with following parameters:
>
> And this test was all three of the non-debugging patches?
Yes, all three patches.
> > xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
> > kernel: loglevel=3
> >
> > same behaviour as before... black screen right after the xen messages.
> >
> > adding earlyprintk=xen to the kernel command line is sufficient to
> > make it boot, I can imagine this can be happening because Xen is not
> > releasing console to the kernel at that moment.
>
> If the answer to the above question is "yes", then I start
> suspecting this to be a different problem. I'm not sure I
> see a way to debug this without having access to any output
> (i.e. neither video nor serial). Without "earlyprintk=xen"
> and instead with "vga=keep watchdog" on the Xen command
> line, is there anything helpful (without or if need be with
> the debugging patch in place)?
with "vga=text-80x25,keep watchdog" and without the earlyprintk,
system booted. I'm attaching the "xl dmesg" and "dmesg" outputs here.
>
> > The system worked well (with earlyprintk=xen), tested with the "yes
> > stress test" mentioned before on a guest and on dom0.
> >
> > Then, I installed the debug patch and booted it again, it also needed
> > the earlyprintk=xen parameter on the kernel command line. I've also
> > added console_timestamps=boot to the xen command line in order to get
> > the time of the messages.
> >
> > I'm attaching the outputs of "xl dmesg" and "dmesg" on this message.
> >
> > Think it is almost done! WIll wait for the next round of tests!
>
> As per above, not sure if there's going to be one. Thanks
> for your patient testing!
I can live with the "earlyprintk=xen" or any other solution that makes
it boot. I'm pretty sure this problem will appear in tests of other
people with a setup that helps debug deeper.
Thank you for your work!
Best regards,
Claudemir
[-- Attachment #2: xen-dmesg.txt --]
[-- Type: text/plain, Size: 32603 bytes --]
(XEN) parameter "placeholder" unknown!
(XEN) Xen version 4.11.4 (Debian 4.11.4+57-g41a822c392-2) (pkg-xen-devel@lists.alioth.debian.org) (gcc (Debian 8.3.0-6) 8.3.0) debug=n Mon Feb 1 11:31:44 -03 2021
(XEN) Bootloader: GRUB 2.04-12
(XEN) Command line: placeholder dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true vga=text-80x25,keep watchdog
(XEN) Xen image load base address: 0xba200000
(XEN) Video information:
(XEN) VGA is text mode 80x25, font 8x16
(XEN) VBE/DDC methods: none; EDID transfer time: 0 seconds
(XEN) EDID info not retrieved because no DDC retrieval method detected
(XEN) Disc information:
(XEN) Found 1 MBR signatures
(XEN) Found 2 EDD information structures
(XEN) Xen-e820 RAM map:
(XEN) 0000000000000000 - 000000000009e800 (usable)
(XEN) 000000000009e800 - 00000000000a0000 (reserved)
(XEN) 00000000000e0000 - 0000000000100000 (reserved)
(XEN) 0000000000100000 - 00000000ba952000 (usable)
(XEN) 00000000ba952000 - 00000000ba98b000 (reserved)
(XEN) 00000000ba98b000 - 00000000babc3000 (usable)
(XEN) 00000000babc3000 - 00000000bb1c0000 (ACPI NVS)
(XEN) 00000000bb1c0000 - 00000000bb843000 (reserved)
(XEN) 00000000bb843000 - 00000000bb844000 (usable)
(XEN) 00000000bb844000 - 00000000bb8ca000 (ACPI NVS)
(XEN) 00000000bb8ca000 - 00000000bbd0f000 (usable)
(XEN) 00000000bbd0f000 - 00000000bbff4000 (reserved)
(XEN) 00000000bbff4000 - 00000000bc000000 (usable)
(XEN) 00000000d0000000 - 00000000e0000000 (reserved)
(XEN) 00000000fed1c000 - 00000000fed20000 (reserved)
(XEN) 00000000ff000000 - 0000000100000000 (reserved)
(XEN) 0000000100000000 - 0000000440000000 (usable)
(XEN) ACPI: RSDP 000F04A0, 0024 (r2 ALASKA)
(XEN) ACPI: XSDT BB0DD070, 005C (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) ACPI: FACP BB0E5728, 010C (r5 ALASKA A M I 1072009 AMI 10013)
(XEN) ACPI: DSDT BB0DD160, 85C7 (r2 ALASKA A M I 20 INTL 20051117)
(XEN) ACPI: FACS BB1B7F80, 0040
(XEN) ACPI: APIC BB0E5838, 01A8 (r3 ALASKA A M I 1072009 AMI 10013)
(XEN) ACPI: FPDT BB0E59E0, 0044 (r1 ALASKA A M I 1072009 AMI 10013)
(XEN) ACPI: MCFG BB0E5A28, 003C (r1 ALASKA OEMMCFG. 1072009 MSFT 97)
(XEN) ACPI: HPET BB0E5A68, 0038 (r1 ALASKA A M I 1072009 AMI. 5)
(XEN) ACPI: SSDT BB0E5AA0, CD380 (r2 INTEL CpuPm 4000 INTL 20051117)
(XEN) ACPI: DMAR BB1B2E20, 00EC (r1 A M I OEMDMAR 1 INTL 1)
(XEN) System RAM: 16303MB (16694760kB)
(XEN) Domain heap initialised
(XEN) ACPI: 32/64X FACS address mismatch in FADT - bb1b7f80/0000000000000000, using 32
(XEN) IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
(XEN) IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
(XEN) Enabling APIC mode: Phys. Using 2 I/O APICs
(XEN) Switched to APIC driver x2apic_cluster
(XEN) xstate: size: 0x340 and states: 0x7
(XEN) Speculative mitigation facilities:
(XEN) Hardware features:
(XEN) Compiled-in support: INDIRECT_THUNK SHADOW_PAGING
(XEN) Xen settings: BTI-Thunk RETPOLINE, SPEC_CTRL: No, Other:
(XEN) L1TF: believed vulnerable, maxphysaddr L1D 46, CPUID 46, Safe address 300000000000
(XEN) Support for VMs: PV: RSB EAGER_FPU, HVM: RSB EAGER_FPU
(XEN) XPTI (64-bit PV only): Dom0 enabled, DomU enabled
(XEN) PV L1TF shadowing: Dom0 disabled, DomU enabled
(XEN) Using scheduler: SMP Credit Scheduler (credit)
(XEN) Platform timer is 14.318MHz HPET
(XEN) Detected 2494.341 MHz processor.
(XEN) Initing memory sharing.
(XEN) Intel VT-d iommu 0 supported page sizes: 4kB, 2MB, 1GB.
(XEN) Intel VT-d Snoop Control enabled.
(XEN) Intel VT-d Dom0 DMA Passthrough not enabled.
(XEN) Intel VT-d Queued Invalidation enabled.
(XEN) Intel VT-d Interrupt Remapping enabled.
(XEN) Intel VT-d Posted Interrupt not enabled.
(XEN) Intel VT-d Shared EPT tables enabled.
(XEN) I/O virtualisation enabled
(XEN) - Dom0 mode: Relaxed
(XEN) Interrupt remapping enabled
(XEN) Enabled directed EOI with ioapic_ack_old on!
(XEN) ENABLING IO-APIC IRQs
(XEN) -> Using old ACK method
(XEN) TSC: c=1 r=1
(XEN) INIT[ 0] t=00000019edcb876b s=00002e6c00f6 m=00002e6c0291
(XEN) Allocated console ring of 64 KiB.
(XEN) VMX: Supported advanced features:
(XEN) - APIC MMIO access virtualisation
(XEN) - APIC TPR shadow
(XEN) - Extended Page Tables (EPT)
(XEN) - Virtual-Processor Identifiers (VPID)
(XEN) - Virtual NMI
(XEN) - MSR direct-access bitmap
(XEN) - Unrestricted Guest
(XEN) - APIC Register Virtualization
(XEN) - Virtual Interrupt Delivery
(XEN) - Posted Interrupt Processing
(XEN) HVM: ASIDs enabled.
(XEN) VMX: Disabling executable EPT superpages due to CVE-2018-12207
(XEN) HVM: VMX enabled
(XEN) HVM: Hardware Assisted Paging (HAP) detected
(XEN) HVM: HAP page sizes: 4kB, 2MB, 1GB
(XEN) INIT[ 1] t=0000001abbb944be s=00002fec7229 m=00002fec741f
(XEN) INIT[ 2] t=0000001abbf5e2d9 s=00003004bf8d m=00003004c173
(XEN) INIT[ 3] t=0000001abc3590e9 s=0000301e4789 m=0000301e4957
(XEN) INIT[ 4] t=0000001abc7041e4 s=00003035cefc m=00003035d0e1
(XEN) INIT[ 5] t=0000001abcab6010 s=0000304d8267 m=0000304d8457
(XEN) INIT[ 6] t=0000001abce62453 s=0000306511b8 m=000030651384
(XEN) INIT[ 7] t=0000001abd2178c3 s=0000307cdacb m=0000307cdcce
(XEN) INIT[ 8] t=0000001abd5ce797 s=00003094ae7f m=00003094b075
(XEN) INIT[ 9] t=0000001abd98ab83 s=000030aca472 m=000030aca67c
(XEN) INIT[10] t=0000001abdd44ccc s=000030c48c5a m=000030c48e54
(XEN) INIT[11] t=0000001abe106a84 s=000030dca67d m=000030dca85f
(XEN) INIT[12] t=0000001abe4c48bf s=000030f4a69a m=000030f4a8c4
(XEN) INIT[13] t=0000001abe8bd4e7 s=0000310e2181 m=0000310e22be
(XEN) INIT[14] t=0000001abec7ce2d s=000031262be3 m=000031262e0d
(XEN) INIT[15] t=0000001abf03acf9 s=0000313e2c79 m=0000313e2eb8
(XEN) INIT[16] t=0000001abf3f43aa s=000031561070 m=000031561278
(XEN) INIT[17] t=0000001abf7b0af2 s=0000316e0788 m=0000316e0997
(XEN) INIT[18] t=0000001abfb6bf27 s=00003185f6e8 m=00003185f912
(XEN) INIT[19] t=0000001abff263cb s=0000319de08b m=0000319de28d
(XEN) INIT[20] t=0000001ac02dff6e s=000031b5c603 m=000031b5c836
(XEN) INIT[21] t=0000001ac069d45a s=000031cdc2a3 m=000031cdc4c9
(XEN) INIT[22] t=0000001ac0a5a654 s=000031e5be5c m=000031e5c08b
(XEN) INIT[23] t=0000001ac0e1af64 s=000031fdcfc8 m=000031fdd221
(XEN) Brought up 24 CPUs
(XEN) Testing NMI watchdog on all CPUs: ok
(XEN) CHK[ 0] ca2eccf8
(XEN) chk[ 0] CPU0 0000000000000000 00000019ff4fab4b #-1
(XEN) chk[ 1] CPU1 0000000000000000 0000001ac97e7aba #-1
(XEN) chk[ 2] CPU12 0000000000000000 0000001ac97e7b61 #-1
(XEN) chk[ 3] CPU7 0000000000000000 0000001ac97e7c43 #-1
(XEN) chk[ 4] CPU6 0000000000000000 0000001ac97e7c2f #-1
(XEN) chk[ 5] CPU14 0000000000000000 0000001ac97e7c18 #-1
(XEN) chk[ 6] CPU18 0000000000000000 0000001ac97e7d77 #-1
(XEN) chk[ 7] CPU3 0000000000000000 0000001ac97e7c53 #-1
(XEN) chk[ 8] CPU2 0000000000000000 0000001ac97e7c5f #-1
(XEN) chk[ 9] CPU10 0000000000000000 0000001ac97e7d77 #-1
(XEN) chk[ 10] CPU9 0000000000000000 0000001ac97e7d57 #-1
(XEN) chk[ 11] CPU22 0000000000000000 0000001ac97e7dc4 #-1
(XEN) chk[ 12] CPU23 0000000000000000 0000001ac97e7db8 #-1
(XEN) chk[ 13] CPU16 0000000000000000 0000001ac97e7d2d #-1
(XEN) chk[ 14] CPU19 0000000000000000 0000001ac97e7d83 #-1
(XEN) chk[ 15] CPU11 0000000000000000 0000001ac97e7d6b #-1
(XEN) chk[ 16] CPU21 0000000000000000 0000001ac97e7c56 #-1
(XEN) chk[ 17] CPU13 0000000000000000 0000001ac97e7b55 #-1
(XEN) chk[ 18] CPU15 0000000000000000 0000001ac97e7c10 #-1
(XEN) chk[ 19] CPU8 0000000000000000 0000001ac97e7d63 #-1
(XEN) chk[ 20] CPU17 0000000000000000 0000001ac97e7d21 #-1
(XEN) chk[ 21] CPU5 0000000000000000 0000001ac97e7df0 #-1
(XEN) chk[ 22] CPU4 0000000000000000 0000001ac97e7dfc #-1
(XEN) chk[ 23] CPU20 0000000000000000 0000001ac97e7c5e #-1
(XEN) chk[ 24] CPU0 0000001ac97e902a 00000019ff4fe663 #1
(XEN) chk[ 25] CPU0 0000001ac97f2173 00000019ff5054ff #2
(XEN) chk[ 26] CPU0 0000001ac9811bcb 00000019ff524f2b #7
(XEN) chk[ 27] CPU0 0000001ac983147b 00000019ff5447d7 #12
(XEN) chk[ 28] CPU0 0000001ac98441e3 00000019ff557533 #15
(XEN) chk[ 29] CPU0 0000001ac993ec57 00000019ff651f9f #55
(XEN) chk[ 30] CPU0 0000001aca0d59ab 00000019ffde8cef #366
(XEN) chk[ 31] CPU0 0000001aca45d873 0000001a00170bb3 #510
(XEN) chk[ 32] CPU0 0000001acc77e3df 0000001a024916e7 #1934
(XEN) TSC warp detected, disabling TSC_RELIABLE
(XEN) TSC: c=1 r=0
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=0000001a0a057b57
(XEN) RDZV[ 1] t=0000001ad434529e
(XEN) RDZV[ 3] t=0000001ad43560b2
(XEN) RDZV[ 2] t=0000001ad43560aa
(XEN) RDZV[ 4] t=0000001ad435693b
(XEN) RDZV[ 5] t=0000001ad4356943
(XEN) RDZV[ 7] t=0000001ad43572fc
(XEN) RDZV[ 6] t=0000001ad4357304
(XEN) RDZV[ 9] t=0000001ad43580a6
(XEN) RDZV[ 8] t=0000001ad435809e
(XEN) RDZV[11] t=0000001ad4358cac
(XEN) RDZV[10] t=0000001ad4358cb4
(XEN) RDZV[13] t=0000001ad4359605
(XEN) RDZV[12] t=0000001ad435960d
(XEN) RDZV[14] t=0000001ad4359fff
(XEN) RDZV[15] t=0000001ad435a007
(XEN) RDZV[17] t=0000001ad435a853
(XEN) RDZV[16] t=0000001ad435a857
(XEN) RDZV[18] t=0000001ad435b1da
(XEN) RDZV[19] t=0000001ad435b1d2
(XEN) RDZV[21] t=0000001ad435bb38
(XEN) RDZV[20] t=0000001ad435bb3c
(XEN) RDZV[23] t=0000001ad435c58e
(XEN) RDZV[22] t=0000001ad435c59a
(XEN) RDZV[22] t=0000001ad929b567(0000001ad929b567) s=00003bb9db2a(00003bba20cf)
(XEN) RDZV[23] t=0000001ad929b567(0000001ad929b567) s=00003bb9db09(00003bba20cf)
(XEN) RDZV[20] t=0000001ad929b567(0000001ad929b567) s=00003bb9db06(00003bba20cf)
(XEN) RDZV[12] t=0000001ad929b567(0000001ad929b567) s=00003bb9dae8(00003bba20cf)
(XEN) RDZV[13] t=0000001ad929b567(0000001ad929b567) s=00003bb9dbc1(00003bba20cf)
(XEN) RDZV[ 8] t=0000001ad929b567(0000001ad929b567) s=00003bb9dae7(00003bba20cf)
(XEN) RDZV[ 9] t=0000001ad929b567(0000001ad929b567) s=00003bb9dafd(00003bba20cf)
(XEN) RDZV[14] t=0000001ad929b567(0000001ad929b567) s=00003bb9db06(00003bba20cf)
(XEN) RDZV[15] t=0000001ad929b567(0000001ad929b567) s=00003bb9daff(00003bba20cf)
(XEN) RDZV[ 6] t=0000001ad929b567(0000001ad929b567) s=00003bb9db21(00003bba20cf)
(XEN) RDZV[ 7] t=0000001ad929b567(0000001ad929b567) s=00003bb9db09(00003bba20cf)
(XEN) RDZV[21] t=0000001ad929b567(0000001ad929b567) s=00003bb9daf2(00003bba20cf)
(XEN) RDZV[17] t=0000001ad929b567(0000001ad929b567) s=00003bb9dbc8(00003bba20cf)
(XEN) RDZV[16] t=0000001ad929b567(0000001ad929b567) s=00003bb9dbe9(00003bba20cf)
(XEN) RDZV[ 2] t=0000001ad929b567(0000001ad929b567) s=00003bb9dacc(00003bba20cf)
(XEN) RDZV[ 1] t=0000001ad929b567(0000001ad929b567) s=00003bb9da91(00003bba20cf)
(XEN) RDZV[19] t=0000001ad929b567(0000001ad929b567) s=00003bb9db52(00003bba20cf)
(XEN) RDZV[18] t=0000001ad929b567(0000001ad929b567) s=00003bb9dafc(00003bba20cf)
(XEN) RDZV[ 3] t=0000001ad929b567(0000001ad929b567) s=00003bb9db25(00003bba20cf)
(XEN) RDZV[10] t=0000001ad929b567(0000001ad929b567) s=00003bb9dbc6(00003bba20cf)
(XEN) RDZV[11] t=0000001ad929b567(0000001ad929b567) s=00003bb9dc06(00003bba20cf)
(XEN) RDZV[ 0] t=0000001ad929b567(0000001ad929b567) s=00003bb9d95d(00003bba20cf)
(XEN) RDZV[ 4] t=0000001ad929b567(0000001ad929b567) s=00003bb9dc89(00003bba20cf)
(XEN) RDZV[ 5] t=0000001ad929b567(0000001ad929b567) s=00003bb9dc90(00003bba20cf)
(XEN) TSC adjusted by ca2ed684
(XEN) TSC: end rendezvous
(XEN) mtrr: your CPUs had inconsistent fixed MTRR settings
(XEN) Dom0 has maximum 816 PIRQs
(XEN) Xen kernel: 64-bit, lsb, compat32
(XEN) Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x2c2c000
(XEN) PHYSICAL MEMORY ARRANGEMENT:
(XEN) Dom0 alloc.: 0000000428000000->000000042c000000 (237067 pages to be allocated)
(XEN) Init. ramdisk: 000000043de0b000->000000043ffff664
(XEN) VIRTUAL MEMORY ARRANGEMENT:
(XEN) Loaded kernel: ffffffff81000000->ffffffff82c2c000
(XEN) Init. ramdisk: 0000000000000000->0000000000000000
(XEN) Phys-Mach map: 0000008000000000->0000008000200000
(XEN) Start info: ffffffff82c2c000->ffffffff82c2c4b8
(XEN) Xenstore ring: 0000000000000000->0000000000000000
(XEN) Console ring: 0000000000000000->0000000000000000
(XEN) Page tables: ffffffff82c2d000->ffffffff82c48000
(XEN) Boot stack: ffffffff82c48000->ffffffff82c49000
(XEN) TOTAL: ffffffff80000000->ffffffff83000000
(XEN) ENTRY ADDRESS: ffffffff8282a160
(XEN) Dom0 has maximum 4 VCPUs
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=0000001b7d5f40ab
(XEN) RDZV[ 1] t=0000001b7d5f4557
(XEN) RDZV[ 2] t=0000001b7d605924
(XEN) RDZV[ 3] t=0000001b7d605914
(XEN) RDZV[ 5] t=0000001b7d605f02
(XEN) RDZV[ 4] t=0000001b7d605f16
(XEN) RDZV[ 6] t=0000001b7d606a4e
(XEN) RDZV[ 7] t=0000001b7d606a4a
(XEN) RDZV[ 8] t=0000001b7d60785a
(XEN) RDZV[ 9] t=0000001b7d6077b6
(XEN) RDZV[10] t=0000001b7d6082aa
(XEN) RDZV[11] t=0000001b7d608292
(XEN) RDZV[12] t=0000001b7d608ce2
(XEN) RDZV[13] t=0000001b7d608d72
(XEN) RDZV[15] t=0000001b7d609789
(XEN) RDZV[14] t=0000001b7d60978d
(XEN) RDZV[17] t=0000001b7d609f12
(XEN) RDZV[16] t=0000001b7d609efa
(XEN) RDZV[19] t=0000001b7d60a88c
(XEN) RDZV[18] t=0000001b7d60a88c
(XEN) RDZV[21] t=0000001b7d60b12b
(XEN) RDZV[20] t=0000001b7d60b113
(XEN) RDZV[22] t=0000001b7d60baae
(XEN) RDZV[23] t=0000001b7d60baaa
(XEN) RDZV[ 0] t=0000001b82548784(0000001b82548784) s=00007f8bdd1e(00007f8c7c7b)
(XEN) RDZV[ 1] t=0000001b82548784(0000001b82548784) s=00007f8bdf11(00007f8c7c7b)
(XEN) RDZV[ 7] t=0000001b82548784(0000001b82548784) s=00007f8bdf6c(00007f8c7c7b)
(XEN) RDZV[ 6] t=0000001b82548784(0000001b82548784) s=00007f8bdf7d(00007f8c7c7b)
(XEN) RDZV[ 9] t=0000001b82548784(0000001b82548784) s=00007f8bdefc(00007f8c7c7b)
(XEN) RDZV[ 8] t=0000001b82548784(0000001b82548784) s=00007f8bdf20(00007f8c7c7b)
(XEN) RDZV[ 4] t=0000001b82548784(0000001b82548784) s=00007f8be0a5(00007f8c7c7b)
(XEN) RDZV[13] t=0000001b82548784(0000001b82548784) s=00007f8be012(00007f8c7c7b)
(XEN) RDZV[12] t=0000001b82548784(0000001b82548784) s=00007f8bdef2(00007f8c7c7b)
(XEN) RDZV[14] t=0000001b82548784(0000001b82548784) s=00007f8bdf52(00007f8c7c7b)
(XEN) RDZV[15] t=0000001b82548784(0000001b82548784) s=00007f8bdf4b(00007f8c7c7b)
(XEN) RDZV[17] t=0000001b82548784(0000001b82548784) s=00007f8be108(00007f8c7c7b)
(XEN) RDZV[16] t=0000001b82548784(0000001b82548784) s=00007f8be141(00007f8c7c7b)
(XEN) RDZV[18] t=0000001b82548784(0000001b82548784) s=00007f8bded4(00007f8c7c7b)
(XEN) RDZV[20] t=0000001b82548784(0000001b82548784) s=00007f8be028(00007f8c7c7b)
(XEN) RDZV[22] t=0000001b82548784(0000001b82548784) s=00007f8be022(00007f8c7c7b)
(XEN) RDZV[ 2] t=0000001b82548784(0000001b82548784) s=00007f8be120(00007f8c7c7b)
(XEN) RDZV[ 5] t=0000001b82548784(0000001b82548784) s=00007f8be0a2(00007f8c7c7b)
(XEN) RDZV[ 3] t=0000001b82548784(0000001b82548784) s=00007f8be17e(00007f8c7c7b)
(XEN) RDZV[10] t=0000001b82548784(0000001b82548784) s=00007f8bdfc8(00007f8c7c7b)
(XEN) RDZV[11] t=0000001b82548784(0000001b82548784) s=00007f8be007(00007f8c7c7b)
(XEN) RDZV[21] t=0000001b82548784(0000001b82548784) s=00007f8be01e(00007f8c7c7b)
(XEN) RDZV[19] t=0000001b82548784(0000001b82548784) s=00007f8bdf27(00007f8c7c7b)
(XEN) RDZV[23] t=0000001b82548784(0000001b82548784) s=00007f8be001(00007f8c7c7b)
(XEN) TSC adjusted by 679
(XEN) TSC: end rendezvous
(XEN) Initial low memory virq threshold set at 0x4000 pages.
(XEN) Scrubbing Free RAM on 1 nodes using 12 CPUs
(XEN) ............done.
(XEN) Std. Loglevel: Errors and warnings
(XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings)
(XEN) Xen is keeping VGA console.
(XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch input to Xen)
(XEN) Freed 476kB init memory
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=0000001cb8e13f4a
(XEN) RDZV[ 1] t=0000001cb8e14466
(XEN) RDZV[ 3] t=0000001cb8e25743
(XEN) RDZV[ 2] t=0000001cb8e2573f
(XEN) RDZV[ 5] t=0000001cb8e25f52
(XEN) RDZV[ 4] t=0000001cb8e25f46
(XEN) RDZV[ 6] t=0000001cb8e26953
(XEN) RDZV[ 7] t=0000001cb8e2698b
(XEN) RDZV[ 9] t=0000001cb8e277b7
(XEN) RDZV[ 8] t=0000001cb8e27803
(XEN) RDZV[11] t=0000001cb8e2829b
(XEN) RDZV[10] t=0000001cb8e2824f
(XEN) RDZV[13] t=0000001cb8e28ccc
(XEN) RDZV[12] t=0000001cb8e28ccc
(XEN) RDZV[14] t=0000001cb8e2967b
(XEN) RDZV[15] t=0000001cb8e2961b
(XEN) RDZV[17] t=0000001cb8e29e15
(XEN) RDZV[16] t=0000001cb8e29e39
(XEN) RDZV[19] t=0000001cb8e2a790
(XEN) RDZV[18] t=0000001cb8e2a79c
(XEN) RDZV[21] t=0000001cb8e2b1d4
(XEN) RDZV[20] t=0000001cb8e2b1a0
(XEN) RDZV[23] t=0000001cb8e2b984
(XEN) RDZV[22] t=0000001cb8e2b978
(XEN) RDZV[ 0] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093b03(0000fe0a79cd)
(XEN) RDZV[ 1] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093d98(0000fe0a79cd)
(XEN) RDZV[22] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093f63(0000fe0a79cd)
(XEN) RDZV[18] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093dee(0000fe0a79cd)
(XEN) RDZV[19] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093e3a(0000fe0a79cd)
(XEN) RDZV[16] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe094142(0000fe0a79cd)
(XEN) RDZV[17] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe0940ec(0000fe0a79cd)
(XEN) RDZV[ 7] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093f7d(0000fe0a79cd)
(XEN) RDZV[ 6] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093f69(0000fe0a79cd)
(XEN) RDZV[11] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093e8c(0000fe0a79cd)
(XEN) RDZV[10] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093e35(0000fe0a79cd)
(XEN) RDZV[ 3] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe094105(0000fe0a79cd)
(XEN) RDZV[21] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093efd(0000fe0a79cd)
(XEN) RDZV[14] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093ddc(0000fe0a79cd)
(XEN) RDZV[15] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093dac(0000fe0a79cd)
(XEN) RDZV[20] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093efb(0000fe0a79cd)
(XEN) RDZV[ 5] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe094157(0000fe0a79cd)
(XEN) RDZV[ 2] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe0940ab(0000fe0a79cd)
(XEN) RDZV[12] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093d75(0000fe0a79cd)
(XEN) RDZV[13] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093e8e(0000fe0a79cd)
(XEN) RDZV[23] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093f46(0000fe0a79cd)
(XEN) RDZV[ 9] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093db6(0000fe0a79cd)
(XEN) RDZV[ 8] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe093e06(0000fe0a79cd)
(XEN) RDZV[ 4] t=0000001cbdd6c389(0000001cbdd6c389) s=0000fe094163(0000fe0a79cd)
(XEN) TSC adjusted by 533
(XEN) TSC: end rendezvous
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 3] t=0000001f1637c6eb
(XEN) RDZV[ 2] t=0000001f1637c6ef
(XEN) RDZV[ 1] t=0000001f1637cd79
(XEN) RDZV[ 0] t=0000001f1637cfe9
(XEN) RDZV[ 5] t=0000001f1638d078
(XEN) RDZV[ 4] t=0000001f1638d088
(XEN) RDZV[ 7] t=0000001f1638da21
(XEN) RDZV[ 6] t=0000001f1638da49
(XEN) RDZV[ 8] t=0000001f1638e7ca
(XEN) RDZV[ 9] t=0000001f1638e7ba
(XEN) RDZV[11] t=0000001f1638f43a
(XEN) RDZV[10] t=0000001f1638f326
(XEN) RDZV[13] t=0000001f1639005f
(XEN) RDZV[12] t=0000001f1639008f
(XEN) RDZV[15] t=0000001f163908c9
(XEN) RDZV[14] t=0000001f163908cd
(XEN) RDZV[16] t=0000001f163911fe
(XEN) RDZV[17] t=0000001f163911fe
(XEN) RDZV[18] t=0000001f16391a43
(XEN) RDZV[19] t=0000001f16391b53
(XEN) RDZV[21] t=0000001f163925d2
(XEN) RDZV[20] t=0000001f1639254a
(XEN) RDZV[22] t=0000001f16392d0e
(XEN) RDZV[23] t=0000001f16392d02
(XEN) RDZV[ 0] t=0000001f1b280823(0000001f1b280823) s=0001f0b6506e(0001f0b8c7d1)
(XEN) RDZV[ 1] t=0000001f1b280823(0000001f1b280823) s=0001f0b654f6(0001f0b8c7d1)
(XEN) RDZV[ 6] t=0000001f1b280823(0000001f1b280823) s=0001f0b65806(0001f0b8c7d1)
(XEN) RDZV[ 7] t=0000001f1b280823(0000001f1b280823) s=0001f0b6580d(0001f0b8c7d1)
(XEN) RDZV[21] t=0000001f1b280823(0000001f1b280823) s=0001f0b6590f(0001f0b8c7d1)
(XEN) RDZV[ 4] t=0000001f1b280823(0000001f1b280823) s=0001f0b65bb1(0001f0b8c7d1)
(XEN) RDZV[17] t=0000001f1b280823(0000001f1b280823) s=0001f0b658fb(0001f0b8c7d1)
(XEN) RDZV[16] t=0000001f1b280823(0000001f1b280823) s=0001f0b6594a(0001f0b8c7d1)
(XEN) RDZV[ 3] t=0000001f1b280823(0000001f1b280823) s=0001f0b65a49(0001f0b8c7d1)
(XEN) RDZV[12] t=0000001f1b280823(0000001f1b280823) s=0001f0b6589e(0001f0b8c7d1)
(XEN) RDZV[13] t=0000001f1b280823(0000001f1b280823) s=0001f0b659a3(0001f0b8c7d1)
(XEN) RDZV[ 8] t=0000001f1b280823(0000001f1b280823) s=0001f0b65510(0001f0b8c7d1)
(XEN) RDZV[ 9] t=0000001f1b280823(0000001f1b280823) s=0001f0b65586(0001f0b8c7d1)
(XEN) RDZV[22] t=0000001f1b280823(0000001f1b280823) s=0001f0b6597c(0001f0b8c7d1)
(XEN) RDZV[15] t=0000001f1b280823(0000001f1b280823) s=0001f0b654fb(0001f0b8c7d1)
(XEN) RDZV[14] t=0000001f1b280823(0000001f1b280823) s=0001f0b65531(0001f0b8c7d1)
(XEN) RDZV[20] t=0000001f1b280823(0000001f1b280823) s=0001f0b658e1(0001f0b8c7d1)
(XEN) RDZV[18] t=0000001f1b280823(0000001f1b280823) s=0001f0b654e5(0001f0b8c7d1)
(XEN) RDZV[19] t=0000001f1b280823(0000001f1b280823) s=0001f0b6559c(0001f0b8c7d1)
(XEN) RDZV[11] t=0000001f1b280823(0000001f1b280823) s=0001f0b65687(0001f0b8c7d1)
(XEN) RDZV[10] t=0000001f1b280823(0000001f1b280823) s=0001f0b655cc(0001f0b8c7d1)
(XEN) RDZV[ 5] t=0000001f1b280823(0000001f1b280823) s=0001f0b65bb8(0001f0b8c7d1)
(XEN) RDZV[ 2] t=0000001f1b280823(0000001f1b280823) s=0001f0b659f0(0001f0b8c7d1)
(XEN) RDZV[23] t=0000001f1b280823(0000001f1b280823) s=0001f0b65958(0001f0b8c7d1)
(XEN) TSC adjusted by 55a
(XEN) TSC: end rendezvous
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=00000023c63fbf96
(XEN) RDZV[ 1] t=00000023c63fca92
(XEN) RDZV[ 3] t=00000023c640ede9
(XEN) RDZV[ 2] t=00000023c640edf5
(XEN) RDZV[ 4] t=00000023c640ef33
(XEN) RDZV[ 5] t=00000023c640ef3f
(XEN) RDZV[ 6] t=00000023c640fb42
(XEN) RDZV[ 7] t=00000023c640f8d6
(XEN) RDZV[ 8] t=00000023c6410951
(XEN) RDZV[ 9] t=00000023c6410951
(XEN) RDZV[10] t=00000023c6411491
(XEN) RDZV[11] t=00000023c6411341
(XEN) RDZV[13] t=00000023c6411e78
(XEN) RDZV[12] t=00000023c6411eb4
(XEN) RDZV[14] t=00000023c6412907
(XEN) RDZV[15] t=00000023c6412943
(XEN) RDZV[17] t=00000023c6412ff3
(XEN) RDZV[16] t=00000023c6412efb
(XEN) RDZV[18] t=00000023c64139c5
(XEN) RDZV[19] t=00000023c64139b5
(XEN) RDZV[21] t=00000023c6414335
(XEN) RDZV[20] t=00000023c64141fd
(XEN) RDZV[23] t=00000023c6414fe5
(XEN) RDZV[22] t=00000023c6414fd5
(XEN) RDZV[ 0] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1cffcd7(0003d1d5ee97)
(XEN) RDZV[ 1] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d004e4(0003d1d5ee97)
(XEN) RDZV[22] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00dd6(0003d1d5ee97)
(XEN) RDZV[23] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00d97(0003d1d5ee97)
(XEN) RDZV[17] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d009a6(0003d1d5ee97)
(XEN) RDZV[16] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d009c3(0003d1d5ee97)
(XEN) RDZV[10] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d0077f(0003d1d5ee97)
(XEN) RDZV[11] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00890(0003d1d5ee97)
(XEN) RDZV[ 5] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00f42(0003d1d5ee97)
(XEN) RDZV[ 8] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00510(0003d1d5ee97)
(XEN) RDZV[ 9] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d005b3(0003d1d5ee97)
(XEN) RDZV[21] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d007c9(0003d1d5ee97)
(XEN) RDZV[ 7] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00add(0003d1d5ee97)
(XEN) RDZV[ 6] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00bda(0003d1d5ee97)
(XEN) RDZV[20] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d007e8(0003d1d5ee97)
(XEN) RDZV[19] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00457(0003d1d5ee97)
(XEN) RDZV[18] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d0037f(0003d1d5ee97)
(XEN) RDZV[15] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00914(0003d1d5ee97)
(XEN) RDZV[14] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00950(0003d1d5ee97)
(XEN) RDZV[ 2] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00f58(0003d1d5ee97)
(XEN) RDZV[13] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00b1b(0003d1d5ee97)
(XEN) RDZV[12] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00a7a(0003d1d5ee97)
(XEN) RDZV[ 3] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00f8a(0003d1d5ee97)
(XEN) RDZV[ 4] t=00000023cb2f82c3(00000023cb2f82c3) s=0003d1d00f44(0003d1d5ee97)
(XEN) TSC adjusted by 249
(XEN) TSC: end rendezvous
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=0000002d1bbfbfeb
(XEN) RDZV[ 1] t=0000002d1bbfc9af
(XEN) RDZV[ 2] t=0000002d1bc0e20c
(XEN) RDZV[ 3] t=0000002d1bc0e20c
(XEN) RDZV[ 5] t=0000002d1bc0e586
(XEN) RDZV[ 4] t=0000002d1bc0e576
(XEN) RDZV[ 6] t=0000002d1bc0ef26
(XEN) RDZV[ 7] t=0000002d1bc0ef36
(XEN) RDZV[ 9] t=0000002d1bc0fd04
(XEN) RDZV[ 8] t=0000002d1bc0fd04
(XEN) RDZV[10] t=0000002d1bc1061c
(XEN) RDZV[11] t=0000002d1bc10658
(XEN) RDZV[13] t=0000002d1bc1115b
(XEN) RDZV[12] t=0000002d1bc11187
(XEN) RDZV[15] t=0000002d1bc11b80
(XEN) RDZV[14] t=0000002d1bc11b8c
(XEN) RDZV[17] t=0000002d1bc121da
(XEN) RDZV[16] t=0000002d1bc121ea
(XEN) RDZV[18] t=0000002d1bc12a88
(XEN) RDZV[19] t=0000002d1bc12a9c
(XEN) RDZV[21] t=0000002d1bc1361a
(XEN) RDZV[20] t=0000002d1bc1361e
(XEN) RDZV[22] t=0000002d1bc141dc
(XEN) RDZV[23] t=0000002d1bc141dc
(XEN) RDZV[23] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a811(00078fd82565)
(XEN) RDZV[10] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a055(00078fd82565)
(XEN) RDZV[ 6] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a48a(00078fd82565)
(XEN) RDZV[ 7] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a53b(00078fd82565)
(XEN) RDZV[20] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a3a7(00078fd82565)
(XEN) RDZV[22] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7ab37(00078fd82565)
(XEN) RDZV[18] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a098(00078fd82565)
(XEN) RDZV[19] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a11a(00078fd82565)
(XEN) RDZV[21] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a07a(00078fd82565)
(XEN) RDZV[ 1] t=0000002d20af22fa(0000002d20af22fa) s=00078fc799e8(00078fd82565)
(XEN) RDZV[11] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a449(00078fd82565)
(XEN) RDZV[ 8] t=0000002d20af22fa(0000002d20af22fa) s=00078fc79ccd(00078fd82565)
(XEN) RDZV[ 9] t=0000002d20af22fa(0000002d20af22fa) s=00078fc79fcc(00078fd82565)
(XEN) RDZV[ 5] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7ac41(00078fd82565)
(XEN) RDZV[13] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a54d(00078fd82565)
(XEN) RDZV[12] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a4fe(00078fd82565)
(XEN) RDZV[ 0] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7874e(00078fd82565)
(XEN) RDZV[ 2] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7ac3d(00078fd82565)
(XEN) RDZV[16] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a29d(00078fd82565)
(XEN) RDZV[17] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a242(00078fd82565)
(XEN) RDZV[ 3] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7abf7(00078fd82565)
(XEN) RDZV[ 4] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7abd6(00078fd82565)
(XEN) RDZV[14] t=0000002d20af22fa(0000002d20af22fa) s=00078fc7a030(00078fd82565)
(XEN) RDZV[15] t=0000002d20af22fa(0000002d20af22fa) s=00078fc79e2a(00078fd82565)
(XEN) TSC adjusted by 3ef
(XEN) TSC: end rendezvous
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=0000003fbc335573
(XEN) RDZV[ 1] t=0000003fbc3361bb
(XEN) RDZV[ 2] t=0000003fbc345c50
(XEN) RDZV[ 3] t=0000003fbc345c4c
(XEN) RDZV[ 4] t=0000003fbc34692f
(XEN) RDZV[ 5] t=0000003fbc34693f
(XEN) RDZV[ 6] t=0000003fbc347095
(XEN) RDZV[ 7] t=0000003fbc347095
(XEN) RDZV[ 9] t=0000003fbc347e95
(XEN) RDZV[ 8] t=0000003fbc347e95
(XEN) RDZV[11] t=0000003fbc348bf8
(XEN) RDZV[10] t=0000003fbc348c68
(XEN) RDZV[13] t=0000003fbc349457
(XEN) RDZV[12] t=0000003fbc349493
(XEN) RDZV[14] t=0000003fbc349f5e
(XEN) RDZV[15] t=0000003fbc349f6a
(XEN) RDZV[17] t=0000003fbc34a5e5
(XEN) RDZV[16] t=0000003fbc34a5cd
(XEN) RDZV[18] t=0000003fbc34b0a7
(XEN) RDZV[19] t=0000003fbc34b07f
(XEN) RDZV[21] t=0000003fbc34b936
(XEN) RDZV[20] t=0000003fbc34b936
(XEN) RDZV[23] t=0000003fbc34c5ae
(XEN) RDZV[22] t=0000003fbc34c5e2
(XEN) RDZV[ 0] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c39a2(000f07a29ca9)
(XEN) RDZV[15] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c2c78(000f07a29ca9)
(XEN) RDZV[14] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c2dac(000f07a29ca9)
(XEN) RDZV[16] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3783(000f07a29ca9)
(XEN) RDZV[17] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c373a(000f07a29ca9)
(XEN) RDZV[18] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3c27(000f07a29ca9)
(XEN) RDZV[ 1] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c19d7(000f07a29ca9)
(XEN) RDZV[13] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c2ce1(000f07a29ca9)
(XEN) RDZV[12] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c2cee(000f07a29ca9)
(XEN) RDZV[ 6] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c40eb(000f07a29ca9)
(XEN) RDZV[ 7] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c42ff(000f07a29ca9)
(XEN) RDZV[21] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c38ab(000f07a29ca9)
(XEN) RDZV[19] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3d03(000f07a29ca9)
(XEN) RDZV[ 8] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c28ef(000f07a29ca9)
(XEN) RDZV[ 9] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c2c4f(000f07a29ca9)
(XEN) RDZV[11] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c41cc(000f07a29ca9)
(XEN) RDZV[10] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3cf3(000f07a29ca9)
(XEN) RDZV[20] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c38ee(000f07a29ca9)
(XEN) RDZV[22] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c4141(000f07a29ca9)
(XEN) RDZV[ 3] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c374d(000f07a29ca9)
(XEN) RDZV[ 5] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c379b(000f07a29ca9)
(XEN) RDZV[23] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3ef0(000f07a29ca9)
(XEN) RDZV[ 2] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3425(000f07a29ca9)
(XEN) RDZV[ 4] t=0000003fc122d4ca(0000003fc122d4ca) s=000f077c3548(000f07a29ca9)
(XEN) TSC: end rendezvous
(XEN) TSC adjusted by 974
(XEN) TSC: time.c#time_calibration_tsc_rendezvous
(XEN) RDZV[ 0] t=00000064f28509f1
(XEN) RDZV[ 1] t=00000064f28513b1
(XEN) RDZV[ 8] t=00000064f28610fa
(XEN) RDZV[ 9] t=00000064f286159a
(XEN) RDZV[ 3] t=00000064f2862f93
(XEN) RDZV[ 2] t=00000064f2862f8b
(XEN) RDZV[ 5] t=00000064f28639a1
(XEN) RDZV[ 4] t=00000064f28638ed
(XEN) RDZV[ 6] t=00000064f2864399
(XEN) RDZV[ 7] t=00000064f2864349
(XEN) RDZV[10] t=00000064f286515f
(XEN) RDZV[11] t=00000064f286516f
(XEN) RDZV[13] t=00000064f2865992
(XEN) RDZV[12] t=00000064f2865c12
(XEN) RDZV[15] t=00000064f2866584
(XEN) RDZV[14] t=00000064f2866564
(XEN) RDZV[17] t=00000064f2866e53
(XEN) RDZV[16] t=00000064f2866e53
(XEN) RDZV[19] t=00000064f286785b
(XEN) RDZV[18] t=00000064f286786f
(XEN) RDZV[21] t=00000064f286820b
(XEN) RDZV[20] t=00000064f286820f
(XEN) RDZV[23] t=00000064f2868ad6
(XEN) RDZV[22] t=00000064f2868bb2
(XEN) RDZV[ 3] t=00000064f7744933(00000064f7744933) s=001df2a78982(001df2f7d65b)
(XEN) RDZV[18] t=00000064f7744933(00000064f7744933) s=001df2a788cf(001df2f7d65b)
(XEN) RDZV[19] t=00000064f7744933(00000064f7744933) s=001df2a789f8(001df2f7d65b)
(XEN) RDZV[16] t=00000064f7744933(00000064f7744933) s=001df2a78088(001df2f7d65b)
(XEN) RDZV[17] t=00000064f7744933(00000064f7744933) s=001df2a7832a(001df2f7d65b)
(XEN) RDZV[22] t=00000064f7744933(00000064f7744933) s=001df2a79f32(001df2f7d65b)
(XEN) RDZV[ 2] t=00000064f7744933(00000064f7744933) s=001df2a7851a(001df2f7d65b)
(XEN) RDZV[ 5] t=00000064f7744933(00000064f7744933) s=001df2a78187(001df2f7d65b)
(XEN) RDZV[ 1] t=00000064f7744933(00000064f7744933) s=001df2a7481b(001df2f7d65b)
(XEN) RDZV[23] t=00000064f7744933(00000064f7744933) s=001df2a796e9(001df2f7d65b)
(XEN) RDZV[12] t=00000064f7744933(00000064f7744933) s=001df2a777aa(001df2f7d65b)
(XEN) RDZV[13] t=00000064f7744933(00000064f7744933) s=001df2a7778f(001df2f7d65b)
(XEN) RDZV[ 0] t=00000064f7744933(00000064f7744933) s=001df2a73cfd(001df2f7d65b)
(XEN) RDZV[20] t=00000064f7744933(00000064f7744933) s=001df2a7373a(001df2f7d65b)
(XEN) RDZV[ 9] t=00000064f7744933(00000064f7744933) s=001df2a779e5(001df2f7d65b)
(XEN) RDZV[ 8] t=00000064f7744933(00000064f7744933) s=001df2a77344(001df2f7d65b)
(XEN) RDZV[11] t=00000064f7744933(00000064f7744933) s=001df2a79817(001df2f7d65b)
(XEN) RDZV[10] t=00000064f7744933(00000064f7744933) s=001df2a78e37(001df2f7d65b)
(XEN) RDZV[15] t=00000064f7744933(00000064f7744933) s=001df2a76f0c(001df2f7d65b)
(XEN) RDZV[14] t=00000064f7744933(00000064f7744933) s=001df2a76ed9(001df2f7d65b)
(XEN) RDZV[ 7] t=00000064f7744933(00000064f7744933) s=001df2a79990(001df2f7d65b)
(XEN) RDZV[ 6] t=00000064f7744933(00000064f7744933) s=001df2a79498(001df2f7d65b)
(XEN) RDZV[21] t=00000064f7744933(00000064f7744933) s=001df2a74279(001df2f7d65b)
(XEN) RDZV[ 4] t=00000064f7744933(00000064f7744933) s=001df2a77cf2(001df2f7d65b)
(XEN) TSC: end rendezvous
(XEN) TSC adjusted by 734
[-- Attachment #3: kernel-dmesg.txt --]
[-- Type: text/plain, Size: 70172 bytes --]
[ 0.000000] Linux version 5.10.0-1-amd64 (debian-kernel@lists.debian.org) (gcc-10 (Debian 10.2.1-3) 10.2.1 20201224, GNU ld (GNU Binutils for Debian) 2.35.1) #1 SMP Debian 5.10.4-1 (2020-12-31)
[ 0.000000] Command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro loglevel=3
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256
[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[ 0.000000] Released 0 page(s)
[ 0.000000] BIOS-provided physical RAM map:
[ 0.000000] Xen: [mem 0x0000000000000000-0x000000000009dfff] usable
[ 0.000000] Xen: [mem 0x000000000009e800-0x00000000000fffff] reserved
[ 0.000000] Xen: [mem 0x0000000000100000-0x0000000080061fff] usable
[ 0.000000] Xen: [mem 0x00000000ba952000-0x00000000ba98afff] reserved
[ 0.000000] Xen: [mem 0x00000000babc3000-0x00000000bb1bffff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bb1c0000-0x00000000bb842fff] reserved
[ 0.000000] Xen: [mem 0x00000000bb844000-0x00000000bb8c9fff] ACPI NVS
[ 0.000000] Xen: [mem 0x00000000bbd0f000-0x00000000bbff3fff] reserved
[ 0.000000] Xen: [mem 0x00000000d0000000-0x00000000dfffffff] reserved
[ 0.000000] Xen: [mem 0x00000000fbffc000-0x00000000fbffcfff] reserved
[ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000fec01fff] reserved
[ 0.000000] Xen: [mem 0x00000000fed1c000-0x00000000fed1ffff] reserved
[ 0.000000] Xen: [mem 0x00000000fee00000-0x00000000feefffff] reserved
[ 0.000000] Xen: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
[ 0.000000] NX (Execute Disable) protection: active
[ 0.000000] SMBIOS 2.7 present.
[ 0.000000] DMI: To be filled by O.E.M. To be filled by O.E.M./Intel X79, BIOS 4.6.5 07/17/2019
[ 0.000000] Hypervisor detected: Xen PV
[ 0.046803] tsc: Fast TSC calibration using PIT
[ 0.046805] tsc: Detected 2494.279 MHz processor
[ 0.046806] tsc: Detected 2494.340 MHz TSC
[ 0.052290] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
[ 0.052293] e820: remove [mem 0x000a0000-0x000fffff] usable
[ 0.052298] last_pfn = 0x80062 max_arch_pfn = 0x400000000
[ 0.052299] Disabled
[ 0.052300] x86/PAT: MTRRs disabled, skipping PAT initialization too.
[ 0.052306] x86/PAT: Configuration [0-7]: WB WT UC- UC WC WP UC UC
[ 0.067090] Kernel/User page tables isolation: disabled on XEN PV.
[ 0.679640] RAMDISK: [mem 0x04000000-0x061f4fff]
[ 0.679653] ACPI: Early table checksum verification disabled
[ 0.685907] ACPI: RSDP 0x00000000000F04A0 000024 (v02 ALASKA)
[ 0.685918] ACPI: XSDT 0x00000000BB0DD070 00005C (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.685945] ACPI: FACP 0x00000000BB0E5728 00010C (v05 ALASKA A M I 01072009 AMI 00010013)
[ 0.686010] ACPI: DSDT 0x00000000BB0DD160 0085C7 (v02 ALASKA A M I 00000020 INTL 20051117)
[ 0.686025] ACPI: FACS 0x00000000BB1B7F80 000040
[ 0.686039] ACPI: APIC 0x00000000BB0E5838 0001A8 (v03 ALASKA A M I 01072009 AMI 00010013)
[ 0.686053] ACPI: FPDT 0x00000000BB0E59E0 000044 (v01 ALASKA A M I 01072009 AMI 00010013)
[ 0.686068] ACPI: MCFG 0x00000000BB0E5A28 00003C (v01 ALASKA OEMMCFG. 01072009 MSFT 00000097)
[ 0.686082] ACPI: HPET 0x00000000BB0E5A68 000038 (v01 ALASKA A M I 01072009 AMI. 00000005)
[ 0.686097] ACPI: SSDT 0x00000000BB0E5AA0 0CD380 (v02 INTEL CpuPm 00004000 INTL 20051117)
[ 0.686112] ACPI: RMAD 0x00000000BB1B2E20 0000EC (v01 A M I OEMDMAR 00000001 INTL 00000001)
[ 0.686151] ACPI: Local APIC address 0xfee00000
[ 0.686152] Setting APIC routing to Xen PV.
[ 0.686185] NUMA turned off
[ 0.686187] Faking a node at [mem 0x0000000000000000-0x0000000080061fff]
[ 0.686199] NODE_DATA(0) allocated [mem 0x3fbf7000-0x3fc20fff]
[ 0.699249] Zone ranges:
[ 0.699251] DMA [mem 0x0000000000001000-0x0000000000ffffff]
[ 0.699253] DMA32 [mem 0x0000000001000000-0x0000000080061fff]
[ 0.699254] Normal empty
[ 0.699255] Device empty
[ 0.699257] Movable zone start for each node
[ 0.699260] Early memory node ranges
[ 0.699261] node 0: [mem 0x0000000000001000-0x000000000009dfff]
[ 0.699262] node 0: [mem 0x0000000000100000-0x0000000080061fff]
[ 0.699587] Zeroed struct page in unavailable ranges: 32769 pages
[ 0.699589] Initmem setup node 0 [mem 0x0000000000001000-0x0000000080061fff]
[ 0.699590] On node 0 totalpages: 524287
[ 0.699592] DMA zone: 64 pages used for memmap
[ 0.699592] DMA zone: 21 pages reserved
[ 0.699593] DMA zone: 3997 pages, LIFO batch:0
[ 0.699644] DMA32 zone: 8130 pages used for memmap
[ 0.699645] DMA32 zone: 520290 pages, LIFO batch:63
[ 0.700375] p2m virtual area at (____ptrval____), size is 40000000
[ 0.998178] Remapped 98 page(s)
[ 1.000267] ACPI: PM-Timer IO Port: 0x408
[ 1.000274] ACPI: Local APIC address 0xfee00000
[ 1.000347] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
[ 1.000349] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
[ 1.000350] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
[ 1.000352] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
[ 1.000353] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
[ 1.000354] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
[ 1.000356] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
[ 1.000357] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
[ 1.000359] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
[ 1.000360] ACPI: LAPIC_NMI (acpi_id[0x12] high edge lint[0x1])
[ 1.000362] ACPI: LAPIC_NMI (acpi_id[0x14] high edge lint[0x1])
[ 1.000363] ACPI: LAPIC_NMI (acpi_id[0x16] high edge lint[0x1])
[ 1.000365] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
[ 1.000366] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
[ 1.000367] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
[ 1.000369] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
[ 1.000370] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
[ 1.000372] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
[ 1.000373] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
[ 1.000374] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
[ 1.000376] ACPI: LAPIC_NMI (acpi_id[0x11] high edge lint[0x1])
[ 1.000377] ACPI: LAPIC_NMI (acpi_id[0x13] high edge lint[0x1])
[ 1.000379] ACPI: LAPIC_NMI (acpi_id[0x15] high edge lint[0x1])
[ 1.000380] ACPI: LAPIC_NMI (acpi_id[0x17] high edge lint[0x1])
[ 1.000409] IOAPIC[0]: apic_id 0, version 32, address 0xfec00000, GSI 0-23
[ 1.000422] IOAPIC[1]: apic_id 2, version 32, address 0xfec01000, GSI 24-47
[ 1.000440] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
[ 1.000443] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
[ 1.000452] ACPI: IRQ0 used by override.
[ 1.000453] ACPI: IRQ9 used by override.
[ 1.000469] Using ACPI (MADT) for SMP configuration information
[ 1.000475] ACPI: HPET id: 0x8086a701 base: 0xfed00000
[ 1.000483] smpboot: Allowing 24 CPUs, 0 hotplug CPUs
[ 1.000503] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff]
[ 1.000505] PM: hibernation: Registered nosave memory: [mem 0x0009e000-0x0009efff]
[ 1.000505] PM: hibernation: Registered nosave memory: [mem 0x0009f000-0x000fffff]
[ 1.000507] [mem 0x80062000-0xba951fff] available for PCI devices
[ 1.000510] Booting paravirtualized kernel on Xen
[ 1.000511] Xen version: 4.11.4 (preserve-AD)
[ 1.000515] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
[ 1.005077] setup_percpu: NR_CPUS:8192 nr_cpumask_bits:24 nr_cpu_ids:24 nr_node_ids:1
[ 1.005897] percpu: Embedded 54 pages/cpu s183960 r8192 d29032 u262144
[ 1.005904] pcpu-alloc: s183960 r8192 d29032 u262144 alloc=1*2097152
[ 1.005906] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 12 13 14 15
[ 1.005916] pcpu-alloc: [0] 16 17 18 19 20 21 22 23
[ 1.005986] xen: PV spinlocks enabled
[ 1.005991] PV qspinlock hash table entries: 256 (order: 0, 4096 bytes, linear)
[ 1.005995] Built 1 zonelists, mobility grouping on. Total pages: 516072
[ 1.005996] Policy zone: DMA32
[ 1.005998] Kernel command line: placeholder root=UUID=ffd2e44e-3eb7-4c4d-a028-dad7da03c831 ro loglevel=3
[ 1.006202] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 1.006283] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 1.006789] mem auto-init: stack:off, heap alloc:on, heap free:off
[ 1.051558] software IO TLB: mapped [mem 0x0000000038c00000-0x000000003cc00000] (64MB)
[ 1.072057] Memory: 197808K/2097148K available (12295K kernel code, 2540K rwdata, 4060K rodata, 2380K init, 1692K bss, 1229692K reserved, 0K cma-reserved)
[ 1.072065] random: get_random_u64 called from __kmem_cache_create+0x2e/0x550 with crng_init=0
[ 1.072368] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[ 1.073305] ftrace: allocating 35988 entries in 141 pages
[ 1.086924] ftrace: allocated 141 pages with 4 groups
[ 1.087335] rcu: Hierarchical RCU implementation.
[ 1.087337] rcu: RCU restricting CPUs from NR_CPUS=8192 to nr_cpu_ids=4.
[ 1.087338] Rude variant of Tasks RCU enabled.
[ 1.087339] Tracing variant of Tasks RCU enabled.
[ 1.087340] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 1.087341] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 1.098325] Using NULL legacy PIC
[ 1.098326] NR_IRQS: 524544, nr_irqs: 864, preallocated irqs: 0
[ 1.098391] xen:events: Using FIFO-based ABI
[ 1.098424] xen: --> pirq=1 -> irq=1 (gsi=1)
[ 1.098439] xen: --> pirq=2 -> irq=2 (gsi=2)
[ 1.098453] xen: --> pirq=3 -> irq=3 (gsi=3)
[ 1.098467] xen: --> pirq=4 -> irq=4 (gsi=4)
[ 1.098480] xen: --> pirq=5 -> irq=5 (gsi=5)
[ 1.098494] xen: --> pirq=6 -> irq=6 (gsi=6)
[ 1.098508] xen: --> pirq=7 -> irq=7 (gsi=7)
[ 1.098521] xen: --> pirq=8 -> irq=8 (gsi=8)
[ 1.098536] xen: --> pirq=9 -> irq=9 (gsi=9)
[ 1.098550] xen: --> pirq=10 -> irq=10 (gsi=10)
[ 1.098565] xen: --> pirq=11 -> irq=11 (gsi=11)
[ 1.098579] xen: --> pirq=12 -> irq=12 (gsi=12)
[ 1.098593] xen: --> pirq=13 -> irq=13 (gsi=13)
[ 1.098607] xen: --> pirq=14 -> irq=14 (gsi=14)
[ 1.098621] xen: --> pirq=15 -> irq=15 (gsi=15)
[ 1.098667] random: crng done (trusting CPU's manufacturer)
[ 1.103635] Console: colour VGA+ 80x25
[ 1.103647] printk: console [tty0] enabled
[ 1.103658] printk: console [hvc0] enabled
[ 1.103686] ACPI: Core revision 20200925
[ 1.176998] clocksource: xen: mask: 0xffffffffffffffff max_cycles: 0x1cd42e4dffb, max_idle_ns: 881590591483 ns
[ 1.177010] Xen: using vcpuop timer interface
[ 1.177015] installing Xen timer for CPU 0
[ 1.177055] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x23f45725f32, max_idle_ns: 440795273770 ns
[ 1.177058] Calibrating delay loop (skipped), value calculated using timer frequency.. 4988.68 BogoMIPS (lpj=9977360)
[ 1.177061] pid_max: default: 32768 minimum: 301
[ 1.177155] LSM: Security Framework initializing
[ 1.177182] Yama: disabled by default; enable with sysctl kernel.yama.*
[ 1.177277] AppArmor: AppArmor initialized
[ 1.177283] TOMOYO Linux initialized
[ 1.177330] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.177335] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes, linear)
[ 1.178102] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8
[ 1.178104] Last level dTLB entries: 4KB 512, 2MB 0, 4MB 0, 1GB 4
[ 1.178108] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization
[ 1.178109] Spectre V2 : Mitigation: Full generic retpoline
[ 1.178110] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
[ 1.178111] Speculative Store Bypass: Vulnerable
[ 1.178113] MDS: Vulnerable: Clear CPU buffers attempted, no microcode
[ 1.178253] Freeing SMP alternatives memory: 32K
[ 1.181187] cpu 0 spinlock event irq 49
[ 1.181194] VPMU disabled by hypervisor.
[ 1.181588] Performance Events: unsupported p6 CPU model 62 no PMU driver, software events only.
[ 1.181693] rcu: Hierarchical SRCU implementation.
[ 1.182169] NMI watchdog: Perf NMI watchdog permanently disabled
[ 1.182321] smp: Bringing up secondary CPUs ...
[ 1.182590] installing Xen timer for CPU 1
[ 1.182960] cpu 1 spinlock event irq 59
[ 1.182960] MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.
[ 1.182960] installing Xen timer for CPU 2
[ 1.182960] cpu 2 spinlock event irq 65
[ 1.182960] installing Xen timer for CPU 3
[ 1.182960] cpu 3 spinlock event irq 71
[ 1.182960] smp: Brought up 1 node, 4 CPUs
[ 1.182960] smpboot: Max logical packages: 6
[ 1.186776] node 0 deferred pages initialised in 0ms
[ 1.186814] devtmpfs: initialized
[ 1.186814] x86/mm: Memory block size: 128MB
[ 1.186814] PM: Registering ACPI NVS region [mem 0xbabc3000-0xbb1bffff] (6279168 bytes)
[ 1.186814] PM: Registering ACPI NVS region [mem 0xbb844000-0xbb8c9fff] (548864 bytes)
[ 1.186814] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 1.186814] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
[ 1.186814] pinctrl core: initialized pinctrl subsystem
[ 1.186814] NET: Registered protocol family 16
[ 1.186814] xen:grant_table: Grant tables using version 1 layout
[ 1.186814] Grant table initialized
[ 1.186814] audit: initializing netlink subsys (disabled)
[ 1.186814] audit: type=2000 audit(1612192794.947:1): state=initialized audit_enabled=0 res=1
[ 1.186814] thermal_sys: Registered thermal governor 'fair_share'
[ 1.186814] thermal_sys: Registered thermal governor 'bang_bang'
[ 1.186814] thermal_sys: Registered thermal governor 'step_wise'
[ 1.186814] thermal_sys: Registered thermal governor 'user_space'
[ 1.186814] ACPI: bus type PCI registered
[ 1.186814] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
[ 1.186814] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xd0000000-0xdfffffff] (base 0xd0000000)
[ 1.186814] PCI: MMCONFIG at [mem 0xd0000000-0xdfffffff] reserved in E820
[ 1.277591] PCI: Using configuration type 1 for base access
[ 1.461249] ACPI: Added _OSI(Module Device)
[ 1.461251] ACPI: Added _OSI(Processor Device)
[ 1.461252] ACPI: Added _OSI(3.0 _SCP Extensions)
[ 1.461254] ACPI: Added _OSI(Processor Aggregator Device)
[ 1.461255] ACPI: Added _OSI(Linux-Dell-Video)
[ 1.461257] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
[ 1.461259] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics)
[ 1.629408] ACPI: 2 ACPI AML tables successfully acquired and loaded
[ 1.643731] xen: registering gsi 9 triggering 0 polarity 0
[ 1.649095] ACPI: Interpreter enabled
[ 1.649108] ACPI: (supports S0 S5)
[ 1.649110] ACPI: Using IOAPIC for interrupt routing
[ 1.649149] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
[ 1.649719] ACPI: Enabled 6 GPEs in block 00 to 3F
[ 1.668271] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
[ 1.668277] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 1.668501] acpi PNP0A08:00: _OSC: platform does not support [SHPCHotplug PME AER LTR]
[ 1.668707] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PCIeCapability]
[ 1.669273] PCI host bridge to bus 0000:00
[ 1.669276] pci_bus 0000:00: root bus resource [io 0x0000-0x03af window]
[ 1.669278] pci_bus 0000:00: root bus resource [io 0x03e0-0x0cf7 window]
[ 1.669279] pci_bus 0000:00: root bus resource [io 0x03b0-0x03df window]
[ 1.669280] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
[ 1.669282] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
[ 1.669283] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
[ 1.669284] pci_bus 0000:00: root bus resource [mem 0xcc000000-0xffffffff window]
[ 1.669285] pci_bus 0000:00: root bus resource [mem 0x440000000-0x3fffffffffff window]
[ 1.669287] pci_bus 0000:00: root bus resource [bus 00-fe]
[ 1.669344] pci 0000:00:00.0: [8086:0e00] type 00 class 0x060000
[ 1.669625] pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
[ 1.669877] pci 0000:00:01.0: [8086:0e02] type 01 class 0x060400
[ 1.670228] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
[ 1.670510] pci 0000:00:01.1: [8086:0e03] type 01 class 0x060400
[ 1.670860] pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
[ 1.671159] pci 0000:00:02.0: [8086:0e04] type 01 class 0x060400
[ 1.671509] pci 0000:00:02.0: PME# supported from D0 D3hot D3cold
[ 1.671780] pci 0000:00:02.1: [8086:0e05] type 01 class 0x060400
[ 1.672130] pci 0000:00:02.1: PME# supported from D0 D3hot D3cold
[ 1.672401] pci 0000:00:02.2: [8086:0e06] type 01 class 0x060400
[ 1.672751] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold
[ 1.673021] pci 0000:00:02.3: [8086:0e07] type 01 class 0x060400
[ 1.673373] pci 0000:00:02.3: PME# supported from D0 D3hot D3cold
[ 1.673662] pci 0000:00:03.0: [8086:0e08] type 01 class 0x060400
[ 1.673833] pci 0000:00:03.0: enabling Extended Tags
[ 1.674041] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold
[ 1.674317] pci 0000:00:03.1: [8086:0e09] type 01 class 0x060400
[ 1.674666] pci 0000:00:03.1: PME# supported from D0 D3hot D3cold
[ 1.674935] pci 0000:00:03.2: [8086:0e0a] type 01 class 0x060400
[ 1.675285] pci 0000:00:03.2: PME# supported from D0 D3hot D3cold
[ 1.675553] pci 0000:00:03.3: [8086:0e0b] type 01 class 0x060400
[ 1.675903] pci 0000:00:03.3: PME# supported from D0 D3hot D3cold
[ 1.676173] pci 0000:00:05.0: [8086:0e28] type 00 class 0x088000
[ 1.676598] pci 0000:00:05.2: [8086:0e2a] type 00 class 0x088000
[ 1.677021] pci 0000:00:05.4: [8086:0e2c] type 00 class 0x080020
[ 1.677086] pci 0000:00:05.4: reg 0x10: [mem 0xfb304000-0xfb304fff]
[ 1.677562] pci 0000:00:06.0: [8086:0e10] type 00 class 0x088000
[ 1.678000] pci 0000:00:06.1: [8086:0e11] type 00 class 0x088000
[ 1.678420] pci 0000:00:06.2: [8086:0e12] type 00 class 0x088000
[ 1.678839] pci 0000:00:06.3: [8086:0e13] type 00 class 0x088000
[ 1.679256] pci 0000:00:06.4: [8086:0e14] type 00 class 0x088000
[ 1.679673] pci 0000:00:06.5: [8086:0e15] type 00 class 0x088000
[ 1.680090] pci 0000:00:06.6: [8086:0e16] type 00 class 0x088000
[ 1.680506] pci 0000:00:06.7: [8086:0e17] type 00 class 0x088000
[ 1.680923] pci 0000:00:07.0: [8086:0e18] type 00 class 0x088000
[ 1.681353] pci 0000:00:07.1: [8086:0e19] type 00 class 0x088000
[ 1.681777] pci 0000:00:07.2: [8086:0e1a] type 00 class 0x088000
[ 1.682198] pci 0000:00:07.3: [8086:0e1b] type 00 class 0x088000
[ 1.682616] pci 0000:00:07.4: [8086:0e1c] type 00 class 0x088000
[ 1.683140] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
[ 1.683198] pci 0000:00:1a.0: reg 0x10: [mem 0xfb302000-0xfb3023ff]
[ 1.683513] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
[ 1.683723] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
[ 1.684072] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
[ 1.684144] pci 0000:00:1c.0: Enabling MPC IRBNCE
[ 1.684151] pci 0000:00:1c.0: Intel PCH root port ACS workaround enabled
[ 1.684348] pci 0000:00:1c.1: [8086:1e12] type 01 class 0x060400
[ 1.684698] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold
[ 1.684767] pci 0000:00:1c.1: Enabling MPC IRBNCE
[ 1.684773] pci 0000:00:1c.1: Intel PCH root port ACS workaround enabled
[ 1.684974] pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400
[ 1.685325] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
[ 1.685395] pci 0000:00:1c.4: Enabling MPC IRBNCE
[ 1.685402] pci 0000:00:1c.4: Intel PCH root port ACS workaround enabled
[ 1.685623] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
[ 1.685681] pci 0000:00:1d.0: reg 0x10: [mem 0xfb301000-0xfb3013ff]
[ 1.686003] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
[ 1.686202] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
[ 1.686600] pci 0000:00:1f.0: [8086:1e48] type 00 class 0x060100
[ 1.687125] pci 0000:00:1f.2: [8086:1e02] type 00 class 0x010601
[ 1.687181] pci 0000:00:1f.2: reg 0x10: [io 0xf070-0xf077]
[ 1.687211] pci 0000:00:1f.2: reg 0x14: [io 0xf060-0xf063]
[ 1.687241] pci 0000:00:1f.2: reg 0x18: [io 0xf050-0xf057]
[ 1.687271] pci 0000:00:1f.2: reg 0x1c: [io 0xf040-0xf043]
[ 1.687301] pci 0000:00:1f.2: reg 0x20: [io 0xf020-0xf03f]
[ 1.687331] pci 0000:00:1f.2: reg 0x24: [mem 0xfb300000-0xfb3007ff]
[ 1.687514] pci 0000:00:1f.2: PME# supported from D3hot
[ 1.687697] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
[ 1.687768] pci 0000:00:1f.3: reg 0x10: [mem 0x3ffffff00000-0x3ffffff000ff 64bit]
[ 1.687854] pci 0000:00:1f.3: reg 0x20: [io 0xf000-0xf01f]
[ 1.688194] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 1.688356] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 1.688560] pci 0000:03:00.0: [10de:01d3] type 00 class 0x030000
[ 1.688612] pci 0000:03:00.0: reg 0x10: [mem 0xfa000000-0xfaffffff]
[ 1.688655] pci 0000:03:00.0: reg 0x14: [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.688698] pci 0000:03:00.0: reg 0x1c: [mem 0xf9000000-0xf9ffffff 64bit]
[ 1.688752] pci 0000:03:00.0: reg 0x30: [mem 0xfb000000-0xfb01ffff pref]
[ 1.689032] pci 0000:03:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'
[ 1.689057] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 1.689081] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 1.689099] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.689233] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 1.689394] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 1.689556] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 1.689723] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 1.689892] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 1.690056] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 1.690218] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 1.690377] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 1.690588] pci 0000:0c:00.0: [1106:3483] type 00 class 0x0c0330
[ 1.690670] pci 0000:0c:00.0: reg 0x10: [mem 0xfb200000-0xfb200fff 64bit]
[ 1.691033] pci 0000:0c:00.0: PME# supported from D0 D3cold
[ 1.691224] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 1.691243] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 1.691452] pci 0000:0d:00.0: [10ec:8168] type 00 class 0x020000
[ 1.691518] pci 0000:0d:00.0: reg 0x10: [io 0xe000-0xe0ff]
[ 1.691609] pci 0000:0d:00.0: reg 0x18: [mem 0xfb104000-0xfb104fff 64bit]
[ 1.691664] pci 0000:0d:00.0: reg 0x20: [mem 0xfb100000-0xfb103fff 64bit]
[ 1.691996] pci 0000:0d:00.0: supports D1 D2
[ 1.691997] pci 0000:0d:00.0: PME# supported from D0 D1 D2 D3hot D3cold
[ 1.692262] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 1.692273] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 1.692283] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 1.692369] pci_bus 0000:0e: extended config space not accessible
[ 1.692529] pci 0000:00:1e.0: PCI bridge to [bus 0e] (subtractive decode)
[ 1.692563] pci 0000:00:1e.0: bridge window [io 0x0000-0x03af window] (subtractive decode)
[ 1.692565] pci 0000:00:1e.0: bridge window [io 0x03e0-0x0cf7 window] (subtractive decode)
[ 1.692566] pci 0000:00:1e.0: bridge window [io 0x03b0-0x03df window] (subtractive decode)
[ 1.692567] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff window] (subtractive decode)
[ 1.692568] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff window] (subtractive decode)
[ 1.692569] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000dffff window] (subtractive decode)
[ 1.692571] pci 0000:00:1e.0: bridge window [mem 0xcc000000-0xffffffff window] (subtractive decode)
[ 1.692572] pci 0000:00:1e.0: bridge window [mem 0x440000000-0x3fffffffffff window] (subtractive decode)
[ 1.693122] xen: registering gsi 13 triggering 1 polarity 0
[ 1.693350] ACPI: PCI Root Bridge [UNC0] (domain 0000 [bus ff])
[ 1.693354] acpi PNP0A03:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3]
[ 1.693379] acpi PNP0A03:00: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME AER PCIeCapability LTR]
[ 1.693442] PCI host bridge to bus 0000:ff
[ 1.693444] pci_bus 0000:ff: root bus resource [bus ff]
[ 1.693503] pci 0000:ff:08.0: [8086:0e80] type 00 class 0x088000
[ 1.693757] pci 0000:ff:08.2: [8086:0e32] type 00 class 0x110100
[ 1.694024] pci 0000:ff:08.3: [8086:0e83] type 00 class 0x088000
[ 1.694363] pci 0000:ff:08.4: [8086:0e84] type 00 class 0x088000
[ 1.694709] pci 0000:ff:08.5: [8086:0e85] type 00 class 0x088000
[ 1.695045] pci 0000:ff:08.6: [8086:0e86] type 00 class 0x088000
[ 1.695383] pci 0000:ff:08.7: [8086:0e87] type 00 class 0x088000
[ 1.695712] pci 0000:ff:09.0: [8086:0e90] type 00 class 0x088000
[ 1.695960] pci 0000:ff:09.2: [8086:0e33] type 00 class 0x110100
[ 1.696216] pci 0000:ff:09.3: [8086:0e93] type 00 class 0x088000
[ 1.696553] pci 0000:ff:09.4: [8086:0e94] type 00 class 0x088000
[ 1.696898] pci 0000:ff:09.5: [8086:0e95] type 00 class 0x088000
[ 1.697239] pci 0000:ff:09.6: [8086:0e96] type 00 class 0x088000
[ 1.697563] pci 0000:ff:0a.0: [8086:0ec0] type 00 class 0x088000
[ 1.697810] pci 0000:ff:0a.1: [8086:0ec1] type 00 class 0x088000
[ 1.698047] pci 0000:ff:0a.2: [8086:0ec2] type 00 class 0x088000
[ 1.698296] pci 0000:ff:0a.3: [8086:0ec3] type 00 class 0x088000
[ 1.698547] pci 0000:ff:0b.0: [8086:0e1e] type 00 class 0x088000
[ 1.698786] pci 0000:ff:0b.3: [8086:0e1f] type 00 class 0x088000
[ 1.699033] pci 0000:ff:0c.0: [8086:0ee0] type 00 class 0x088000
[ 1.699266] pci 0000:ff:0c.1: [8086:0ee2] type 00 class 0x088000
[ 1.699503] pci 0000:ff:0c.2: [8086:0ee4] type 00 class 0x088000
[ 1.699736] pci 0000:ff:0c.3: [8086:0ee6] type 00 class 0x088000
[ 1.699969] pci 0000:ff:0c.4: [8086:0ee8] type 00 class 0x088000
[ 1.700206] pci 0000:ff:0c.5: [8086:0eea] type 00 class 0x088000
[ 1.700447] pci 0000:ff:0d.0: [8086:0ee1] type 00 class 0x088000
[ 1.700680] pci 0000:ff:0d.1: [8086:0ee3] type 00 class 0x088000
[ 1.700914] pci 0000:ff:0d.2: [8086:0ee5] type 00 class 0x088000
[ 1.701113] pci 0000:ff:0d.3: [8086:0ee7] type 00 class 0x088000
[ 1.701348] pci 0000:ff:0d.4: [8086:0ee9] type 00 class 0x088000
[ 1.701581] pci 0000:ff:0d.5: [8086:0eeb] type 00 class 0x088000
[ 1.701835] pci 0000:ff:0e.0: [8086:0ea0] type 00 class 0x088000
[ 1.702078] pci 0000:ff:0e.1: [8086:0e30] type 00 class 0x110100
[ 1.702360] pci 0000:ff:0f.0: [8086:0ea8] type 00 class 0x088000
[ 1.702694] pci 0000:ff:0f.1: [8086:0e71] type 00 class 0x088000
[ 1.703029] pci 0000:ff:0f.2: [8086:0eaa] type 00 class 0x088000
[ 1.703362] pci 0000:ff:0f.3: [8086:0eab] type 00 class 0x088000
[ 1.703695] pci 0000:ff:0f.4: [8086:0eac] type 00 class 0x088000
[ 1.704028] pci 0000:ff:0f.5: [8086:0ead] type 00 class 0x088000
[ 1.704369] pci 0000:ff:10.0: [8086:0eb0] type 00 class 0x088000
[ 1.704707] pci 0000:ff:10.1: [8086:0eb1] type 00 class 0x088000
[ 1.705043] pci 0000:ff:10.2: [8086:0eb2] type 00 class 0x088000
[ 1.705380] pci 0000:ff:10.3: [8086:0eb3] type 00 class 0x088000
[ 1.705719] pci 0000:ff:10.4: [8086:0eb4] type 00 class 0x088000
[ 1.706059] pci 0000:ff:10.5: [8086:0eb5] type 00 class 0x088000
[ 1.706393] pci 0000:ff:10.6: [8086:0eb6] type 00 class 0x088000
[ 1.706726] pci 0000:ff:10.7: [8086:0eb7] type 00 class 0x088000
[ 1.707054] pci 0000:ff:13.0: [8086:0e1d] type 00 class 0x088000
[ 1.707293] pci 0000:ff:13.1: [8086:0e34] type 00 class 0x110100
[ 1.707538] pci 0000:ff:13.4: [8086:0e81] type 00 class 0x088000
[ 1.707773] pci 0000:ff:13.5: [8086:0e36] type 00 class 0x110100
[ 1.708027] pci 0000:ff:16.0: [8086:0ec8] type 00 class 0x088000
[ 1.708261] pci 0000:ff:16.1: [8086:0ec9] type 00 class 0x088000
[ 1.708493] pci 0000:ff:16.2: [8086:0eca] type 00 class 0x088000
[ 1.708777] pci 0000:ff:1c.0: [8086:0e60] type 00 class 0x088000
[ 1.709016] pci 0000:ff:1c.1: [8086:0e38] type 00 class 0x110100
[ 1.709311] pci 0000:ff:1d.0: [8086:0e68] type 00 class 0x088000
[ 1.709646] pci 0000:ff:1d.1: [8086:0e79] type 00 class 0x088000
[ 1.709991] pci 0000:ff:1d.2: [8086:0e6a] type 00 class 0x088000
[ 1.710327] pci 0000:ff:1d.3: [8086:0e6b] type 00 class 0x088000
[ 1.710660] pci 0000:ff:1d.4: [8086:0e6c] type 00 class 0x088000
[ 1.710999] pci 0000:ff:1d.5: [8086:0e6d] type 00 class 0x088000
[ 1.711346] pci 0000:ff:1e.0: [8086:0ef0] type 00 class 0x088000
[ 1.711680] pci 0000:ff:1e.1: [8086:0ef1] type 00 class 0x088000
[ 1.712019] pci 0000:ff:1e.2: [8086:0ef2] type 00 class 0x088000
[ 1.712353] pci 0000:ff:1e.3: [8086:0ef3] type 00 class 0x088000
[ 1.712687] pci 0000:ff:1e.4: [8086:0ef4] type 00 class 0x088000
[ 1.713026] pci 0000:ff:1e.5: [8086:0ef5] type 00 class 0x088000
[ 1.713369] pci 0000:ff:1e.6: [8086:0ef6] type 00 class 0x088000
[ 1.713703] pci 0000:ff:1e.7: [8086:0ef7] type 00 class 0x088000
[ 1.714175] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 *11 12 14 15)
[ 1.714261] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *10 11 12 14 15)
[ 1.714345] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
[ 1.714428] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 *4 5 6 10 11 12 14 15)
[ 1.714511] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.714594] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.714677] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 11 12 14 15) *0, disabled.
[ 1.714760] ACPI: PCI Interrupt Link [LNKH] (IRQs *3 4 5 6 7 10 11 12 14 15)
[ 1.717118] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 4/0x1 ignored.
[ 1.717118] ACPI: Unable to map lapic to logical cpu number
[ 1.717243] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 5/0x3 ignored.
[ 1.717244] ACPI: Unable to map lapic to logical cpu number
[ 1.717392] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 6/0x5 ignored.
[ 1.717393] ACPI: Unable to map lapic to logical cpu number
[ 1.717540] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 7/0x7 ignored.
[ 1.717540] ACPI: Unable to map lapic to logical cpu number
[ 1.717630] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 8/0x8 ignored.
[ 1.717631] ACPI: Unable to map lapic to logical cpu number
[ 1.717724] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 9/0x9 ignored.
[ 1.717725] ACPI: Unable to map lapic to logical cpu number
[ 1.717815] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 10/0xa ignored.
[ 1.717816] ACPI: Unable to map lapic to logical cpu number
[ 1.717910] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 11/0xb ignored.
[ 1.717910] ACPI: Unable to map lapic to logical cpu number
[ 1.718005] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 12/0x10 ignored.
[ 1.718006] ACPI: Unable to map lapic to logical cpu number
[ 1.718100] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 13/0x11 ignored.
[ 1.718101] ACPI: Unable to map lapic to logical cpu number
[ 1.718192] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 14/0x12 ignored.
[ 1.718193] ACPI: Unable to map lapic to logical cpu number
[ 1.718288] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 15/0x13 ignored.
[ 1.718289] ACPI: Unable to map lapic to logical cpu number
[ 1.718380] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 16/0x14 ignored.
[ 1.718381] ACPI: Unable to map lapic to logical cpu number
[ 1.718475] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 17/0x15 ignored.
[ 1.718476] ACPI: Unable to map lapic to logical cpu number
[ 1.718567] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 18/0x16 ignored.
[ 1.718567] ACPI: Unable to map lapic to logical cpu number
[ 1.718662] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 19/0x17 ignored.
[ 1.718663] ACPI: Unable to map lapic to logical cpu number
[ 1.718754] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 20/0x18 ignored.
[ 1.718755] ACPI: Unable to map lapic to logical cpu number
[ 1.718850] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 21/0x19 ignored.
[ 1.718851] ACPI: Unable to map lapic to logical cpu number
[ 1.718943] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 22/0x1a ignored.
[ 1.718944] ACPI: Unable to map lapic to logical cpu number
[ 1.719057] APIC: NR_CPUS/possible_cpus limit of 4 reached. Processor 23/0x1b ignored.
[ 1.719058] ACPI: Unable to map lapic to logical cpu number
[ 1.719564] xen:balloon: Initialising balloon driver
[ 1.719564] iommu: Default domain type: Translated
[ 1.721106] pci 0000:03:00.0: vgaarb: setting as boot VGA device
[ 1.721106] pci 0000:03:00.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
[ 1.721107] pci 0000:03:00.0: vgaarb: bridge control possible
[ 1.721108] vgaarb: loaded
[ 1.721199] EDAC MC: Ver: 3.0.0
[ 1.722173] NetLabel: Initializing
[ 1.722173] NetLabel: domain hash size = 128
[ 1.722173] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO
[ 1.722173] NetLabel: unlabeled traffic allowed by default
[ 1.722173] PCI: Using ACPI for IRQ routing
[ 1.750682] PCI: pci_cache_line_size set to 64 bytes
[ 1.751527] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
[ 1.751529] e820: reserve RAM buffer [mem 0x80062000-0x83ffffff]
[ 1.753064] clocksource: Switched to clocksource tsc-early
[ 1.764675] VFS: Disk quotas dquot_6.6.0
[ 1.764692] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 1.764713] hugetlbfs: disabling because there are no supported hugepage sizes
[ 1.764806] AppArmor: AppArmor Filesystem Enabled
[ 1.764823] pnp: PnP ACPI init
[ 1.764972] system 00:00: [mem 0xfc000000-0xfcffffff] has been reserved
[ 1.764974] system 00:00: [mem 0xfd000000-0xfdffffff] has been reserved
[ 1.764975] system 00:00: [mem 0xfe000000-0xfeafffff] has been reserved
[ 1.764976] system 00:00: [mem 0xfeb00000-0xfebfffff] has been reserved
[ 1.764978] system 00:00: [mem 0xfed00400-0xfed3ffff] could not be reserved
[ 1.764979] system 00:00: [mem 0xfed45000-0xfedfffff] has been reserved
[ 1.764981] system 00:00: [mem 0xfee00000-0xfeefffff] has been reserved
[ 1.764987] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.765134] system 00:01: [mem 0xfbffc000-0xfbffdfff] could not be reserved
[ 1.765139] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.765369] system 00:02: [io 0x0a00-0x0a1f] has been reserved
[ 1.765370] system 00:02: [io 0x0a20-0x0a2f] has been reserved
[ 1.765372] system 00:02: [io 0x0a30-0x0a3f] has been reserved
[ 1.765376] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.765405] xen: registering gsi 1 triggering 1 polarity 0
[ 1.765450] pnp 00:03: Plug and Play ACPI device, IDs PNP0303 PNP030b (active)
[ 1.765487] xen: registering gsi 12 triggering 1 polarity 0
[ 1.765528] pnp 00:04: Plug and Play ACPI device, IDs PNP0f03 PNP0f13 (active)
[ 1.765556] xen: registering gsi 8 triggering 1 polarity 0
[ 1.765591] pnp 00:05: Plug and Play ACPI device, IDs PNP0b00 (active)
[ 1.765686] system 00:06: [io 0x04d0-0x04d1] has been reserved
[ 1.765691] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
[ 1.765967] system 00:07: [io 0x0400-0x0453] has been reserved
[ 1.765969] system 00:07: [io 0x0458-0x047f] has been reserved
[ 1.765970] system 00:07: [io 0x1180-0x119f] has been reserved
[ 1.765972] system 00:07: [io 0x0500-0x057f] has been reserved
[ 1.765974] system 00:07: [mem 0xfed1c000-0xfed1ffff] has been reserved
[ 1.765975] system 00:07: [mem 0xfec00000-0xfecfffff] could not be reserved
[ 1.765977] system 00:07: [mem 0xff000000-0xffffffff] has been reserved
[ 1.765981] system 00:07: Plug and Play ACPI device, IDs PNP0c01 (active)
[ 1.766096] system 00:08: [io 0x0454-0x0457] has been reserved
[ 1.766101] system 00:08: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
[ 1.766562] pnp: PnP ACPI: found 9 devices
[ 1.785356] PM-Timer failed consistency check (0xffffff) - aborting.
[ 1.785419] NET: Registered protocol family 2
[ 1.785595] tcp_listen_portaddr_hash hash table entries: 1024 (order: 2, 16384 bytes, linear)
[ 1.785614] TCP established hash table entries: 16384 (order: 5, 131072 bytes, linear)
[ 1.785663] TCP bind hash table entries: 16384 (order: 6, 262144 bytes, linear)
[ 1.785685] TCP: Hash tables configured (established 16384 bind 16384)
[ 1.785724] UDP hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 1.785734] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes, linear)
[ 1.785919] NET: Registered protocol family 1
[ 1.785924] NET: Registered protocol family 44
[ 1.785952] pci 0000:00:01.0: PCI bridge to [bus 01]
[ 1.785991] pci 0000:00:01.1: PCI bridge to [bus 02]
[ 1.786029] pci 0000:00:02.0: PCI bridge to [bus 03]
[ 1.786043] pci 0000:00:02.0: bridge window [mem 0xf9000000-0xfb0fffff]
[ 1.786053] pci 0000:00:02.0: bridge window [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.786071] pci 0000:00:02.1: PCI bridge to [bus 04]
[ 1.786108] pci 0000:00:02.2: PCI bridge to [bus 05]
[ 1.786145] pci 0000:00:02.3: PCI bridge to [bus 06]
[ 1.786183] pci 0000:00:03.0: PCI bridge to [bus 07]
[ 1.786220] pci 0000:00:03.1: PCI bridge to [bus 08]
[ 1.786257] pci 0000:00:03.2: PCI bridge to [bus 09]
[ 1.786294] pci 0000:00:03.3: PCI bridge to [bus 0a]
[ 1.786332] pci 0000:00:1c.0: PCI bridge to [bus 0b]
[ 1.786371] pci 0000:00:1c.1: PCI bridge to [bus 0c]
[ 1.786385] pci 0000:00:1c.1: bridge window [mem 0xfb200000-0xfb2fffff]
[ 1.786412] pci 0000:00:1c.4: PCI bridge to [bus 0d]
[ 1.786418] pci 0000:00:1c.4: bridge window [io 0xe000-0xefff]
[ 1.786432] pci 0000:00:1c.4: bridge window [mem 0xfb100000-0xfb1fffff]
[ 1.786458] pci 0000:00:1e.0: PCI bridge to [bus 0e]
[ 1.786497] pci_bus 0000:00: resource 4 [io 0x0000-0x03af window]
[ 1.786498] pci_bus 0000:00: resource 5 [io 0x03e0-0x0cf7 window]
[ 1.786499] pci_bus 0000:00: resource 6 [io 0x03b0-0x03df window]
[ 1.786501] pci_bus 0000:00: resource 7 [io 0x0d00-0xffff window]
[ 1.786502] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
[ 1.786503] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
[ 1.786504] pci_bus 0000:00: resource 10 [mem 0xcc000000-0xffffffff window]
[ 1.786505] pci_bus 0000:00: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 1.786507] pci_bus 0000:03: resource 1 [mem 0xf9000000-0xfb0fffff]
[ 1.786508] pci_bus 0000:03: resource 2 [mem 0xe0000000-0xefffffff 64bit pref]
[ 1.786510] pci_bus 0000:0c: resource 1 [mem 0xfb200000-0xfb2fffff]
[ 1.786511] pci_bus 0000:0d: resource 0 [io 0xe000-0xefff]
[ 1.786513] pci_bus 0000:0d: resource 1 [mem 0xfb100000-0xfb1fffff]
[ 1.786514] pci_bus 0000:0e: resource 4 [io 0x0000-0x03af window]
[ 1.786515] pci_bus 0000:0e: resource 5 [io 0x03e0-0x0cf7 window]
[ 1.786516] pci_bus 0000:0e: resource 6 [io 0x03b0-0x03df window]
[ 1.786517] pci_bus 0000:0e: resource 7 [io 0x0d00-0xffff window]
[ 1.786518] pci_bus 0000:0e: resource 8 [mem 0x000a0000-0x000bffff window]
[ 1.786519] pci_bus 0000:0e: resource 9 [mem 0x000c0000-0x000dffff window]
[ 1.786521] pci_bus 0000:0e: resource 10 [mem 0xcc000000-0xffffffff window]
[ 1.786522] pci_bus 0000:0e: resource 11 [mem 0x440000000-0x3fffffffffff window]
[ 1.786652] pci 0000:00:05.0: disabled boot interrupts on device [8086:0e28]
[ 1.786824] xen: registering gsi 16 triggering 0 polarity 1
[ 1.786848] xen: --> pirq=16 -> irq=16 (gsi=16)
[ 1.787085] xen: registering gsi 23 triggering 0 polarity 1
[ 1.787103] xen: --> pirq=23 -> irq=23 (gsi=23)
[ 1.787304] pci 0000:03:00.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
[ 1.787386] xen: registering gsi 16 triggering 0 polarity 1
[ 1.787390] Already setup the GSI :16
[ 1.787432] xen: registering gsi 17 triggering 0 polarity 1
[ 1.787448] xen: --> pirq=17 -> irq=17 (gsi=17)
[ 1.787894] PCI: CLS 64 bytes, default 64
[ 1.787945] Trying to unpack rootfs image as initramfs...
[ 2.320780] Freeing initrd memory: 34772K
[ 2.320830] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x23f45725f32, max_idle_ns: 440795273770 ns
[ 2.320914] clocksource: Switched to clocksource tsc
[ 2.321505] Initialise system trusted keyrings
[ 2.321517] Key type blacklist registered
[ 2.321665] workingset: timestamp_bits=36 max_order=18 bucket_order=0
[ 2.322761] zbud: loaded
[ 2.323218] integrity: Platform Keyring initialized
[ 2.323221] Key type asymmetric registered
[ 2.323223] Asymmetric key parser 'x509' registered
[ 2.323233] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 251)
[ 2.323389] io scheduler mq-deadline registered
[ 2.323720] xen: registering gsi 26 triggering 0 polarity 1
[ 2.323748] xen: --> pirq=26 -> irq=26 (gsi=26)
[ 2.324290] xen: registering gsi 26 triggering 0 polarity 1
[ 2.324295] Already setup the GSI :26
[ 2.324791] xen: registering gsi 32 triggering 0 polarity 1
[ 2.324809] xen: --> pirq=32 -> irq=32 (gsi=32)
[ 2.325297] xen: registering gsi 32 triggering 0 polarity 1
[ 2.325302] Already setup the GSI :32
[ 2.325789] xen: registering gsi 32 triggering 0 polarity 1
[ 2.325793] Already setup the GSI :32
[ 2.326277] xen: registering gsi 32 triggering 0 polarity 1
[ 2.326282] Already setup the GSI :32
[ 2.326766] xen: registering gsi 40 triggering 0 polarity 1
[ 2.326784] xen: --> pirq=40 -> irq=40 (gsi=40)
[ 2.327285] xen: registering gsi 40 triggering 0 polarity 1
[ 2.327289] Already setup the GSI :40
[ 2.327768] xen: registering gsi 40 triggering 0 polarity 1
[ 2.327773] Already setup the GSI :40
[ 2.328262] xen: registering gsi 40 triggering 0 polarity 1
[ 2.328267] Already setup the GSI :40
[ 2.328756] xen: registering gsi 17 triggering 0 polarity 1
[ 2.328760] Already setup the GSI :17
[ 2.329432] xen: registering gsi 17 triggering 0 polarity 1
[ 2.329437] Already setup the GSI :17
[ 2.329799] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
[ 2.329811] intel_idle: MWAIT substates: 0x1120
[ 2.329991] Monitor-Mwait will be used to enter C-1 state
[ 2.330020] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 2.330022] intel_idle: v0.5.1 model 0x3E
[ 2.330027] intel_idle: intel_idle yielding to none
[ 2.330197] ACPI: \_SB_.SCK0.C000: Found 1 idle states
[ 2.330520] ACPI: \_SB_.SCK0.C002: Found 1 idle states
[ 2.330833] ACPI: \_SB_.SCK0.C004: Found 1 idle states
[ 2.331136] ACPI: \_SB_.SCK0.C006: Found 1 idle states
[ 2.331791] xen_mcelog: /dev/mcelog registered by Xen
[ 2.332369] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 2.333094] hpet_acpi_add: no address or irqs in _CRS
[ 2.333117] Linux agpgart interface v0.103
[ 2.333215] AMD-Vi: AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
[ 2.333216] AMD-Vi: AMD IOMMUv2 functionality not available on this system
[ 2.333618] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f03:PS2M] at 0x60,0x64 irq 1,12
[ 2.334259] serio: i8042 KBD port at 0x60,0x64 irq 1
[ 2.334265] serio: i8042 AUX port at 0x60,0x64 irq 12
[ 2.334468] mousedev: PS/2 mouse device common for all mice
[ 2.334546] rtc_cmos 00:05: RTC can wake from S4
[ 2.334912] rtc_cmos 00:05: registered as rtc0
[ 2.334989] rtc_cmos 00:05: setting system clock to 2021-02-01T15:19:56 UTC (1612192796)
[ 2.335014] rtc_cmos 00:05: alarms up to one month, y3k, 114 bytes nvram
[ 2.335023] intel_pstate: CPU model not supported
[ 2.335146] ledtrig-cpu: registered to indicate activity on CPUs
[ 2.335905] NET: Registered protocol family 10
[ 2.356778] Segment Routing with IPv6
[ 2.356803] mip6: Mobile IPv6
[ 2.356806] NET: Registered protocol family 17
[ 2.356919] mpls_gso: MPLS GSO support
[ 2.357218] IPI shorthand broadcast: enabled
[ 2.357226] sched_clock: Marking stable (2278760525, 78422631)->(2371388831, -14205675)
[ 2.357516] registered taskstats version 1
[ 2.357519] Loading compiled-in X.509 certificates
[ 2.397333] Loaded X.509 cert 'Debian Secure Boot CA: 6ccece7e4c6c0d1f6149f3dd27dfcc5cbb419ea1'
[ 2.397353] Loaded X.509 cert 'Debian Secure Boot Signer 2020: 00b55eb3b9'
[ 2.397390] zswap: loaded using pool lzo/zbud
[ 2.397798] Key type ._fscrypt registered
[ 2.397799] Key type .fscrypt registered
[ 2.397800] Key type fscrypt-provisioning registered
[ 2.397846] AppArmor: AppArmor sha1 policy hashing enabled
[ 2.400414] Freeing unused kernel image (initmem) memory: 2380K
[ 2.433151] Write protecting the kernel read-only data: 18432k
[ 2.447246] Freeing unused kernel image (text/rodata gap) memory: 2040K
[ 2.447317] Freeing unused kernel image (rodata/data gap) memory: 36K
[ 2.899184] x86/mm: Checked W+X mappings: passed, no W+X pages found.
[ 2.899192] Run /init as init process
[ 2.899194] with arguments:
[ 2.899194] /init
[ 2.899195] placeholder
[ 2.899196] with environment:
[ 2.899197] HOME=/
[ 2.899198] TERM=linux
[ 3.185964] xen: registering gsi 18 triggering 0 polarity 1
[ 3.185997] xen: --> pirq=18 -> irq=18 (gsi=18)
[ 3.186159] i801_smbus 0000:00:1f.3: SMBus using PCI interrupt
[ 3.186879] i2c i2c-0: 4/4 memory slots populated (from DMI)
[ 3.222630] xen: registering gsi 16 triggering 0 polarity 1
[ 3.222636] Already setup the GSI :16
[ 3.231037] ACPI: bus type USB registered
[ 3.231060] usbcore: registered new interface driver usbfs
[ 3.231067] usbcore: registered new interface driver hub
[ 3.231175] usbcore: registered new device driver usb
[ 3.231587] SCSI subsystem initialized
[ 3.243171] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 3.244707] ehci-pci: EHCI PCI platform driver
[ 3.245048] xen: registering gsi 16 triggering 0 polarity 1
[ 3.245053] Already setup the GSI :16
[ 3.245182] ehci-pci 0000:00:1a.0: EHCI Host Controller
[ 3.245193] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
[ 3.245228] ehci-pci 0000:00:1a.0: debug port 2
[ 3.249198] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
[ 3.249493] ehci-pci 0000:00:1a.0: irq 16, io mem 0xfb302000
[ 3.255840] libata version 3.00 loaded.
[ 3.256544] libphy: r8169: probed
[ 3.256787] r8169 0000:0d:00.0 eth0: RTL8168h/8111h, 00:e0:4c:0a:52:97, XID 541, IRQ 89
[ 3.256790] r8169 0000:0d:00.0 eth0: jumbo features [frames: 9194 bytes, tx checksumming: ko]
[ 3.265121] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
[ 3.265294] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.265297] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.265299] usb usb1: Product: EHCI Host Controller
[ 3.265303] usb usb1: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 3.265311] usb usb1: SerialNumber: 0000:00:1a.0
[ 3.265527] hub 1-0:1.0: USB hub found
[ 3.266129] hub 1-0:1.0: 2 ports detected
[ 3.266564] xen: registering gsi 23 triggering 0 polarity 1
[ 3.266570] Already setup the GSI :23
[ 3.266652] ehci-pci 0000:00:1d.0: EHCI Host Controller
[ 3.266661] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
[ 3.266696] ehci-pci 0000:00:1d.0: debug port 2
[ 3.267375] xen: registering gsi 17 triggering 0 polarity 1
[ 3.267381] Already setup the GSI :17
[ 3.270651] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
[ 3.271748] ehci-pci 0000:00:1d.0: irq 23, io mem 0xfb301000
[ 3.272531] ahci 0000:00:1f.2: version 3.0
[ 3.272652] xen: registering gsi 19 triggering 0 polarity 1
[ 3.272686] xen: --> pirq=19 -> irq=19 (gsi=19)
[ 3.272897] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
[ 3.272901] ahci 0000:00:1f.2: flags: 64bit ncq sntf pm led clo pio slum part ems apst
[ 3.285129] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
[ 3.285289] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.285292] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.285294] usb usb2: Product: EHCI Host Controller
[ 3.285296] usb usb2: Manufacturer: Linux 5.10.0-1-amd64 ehci_hcd
[ 3.285297] usb usb2: SerialNumber: 0000:00:1d.0
[ 3.285512] hub 2-0:1.0: USB hub found
[ 3.285538] hub 2-0:1.0: 2 ports detected
[ 3.286219] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 3.286228] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 3
[ 3.286520] xhci_hcd 0000:0c:00.0: hcc params 0x002841eb hci version 0x100 quirks 0x0000000000000890
[ 3.287292] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
[ 3.287294] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.287296] usb usb3: Product: xHCI Host Controller
[ 3.287298] usb usb3: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 3.287300] usb usb3: SerialNumber: 0000:0c:00.0
[ 3.287695] hub 3-0:1.0: USB hub found
[ 3.287726] hub 3-0:1.0: 1 port detected
[ 3.288010] xhci_hcd 0000:0c:00.0: xHCI Host Controller
[ 3.288016] xhci_hcd 0000:0c:00.0: new USB bus registered, assigned bus number 4
[ 3.288020] xhci_hcd 0000:0c:00.0: Host supports USB 3.0 SuperSpeed
[ 3.288206] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
[ 3.288209] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
[ 3.288210] usb usb4: Product: xHCI Host Controller
[ 3.288212] usb usb4: Manufacturer: Linux 5.10.0-1-amd64 xhci-hcd
[ 3.288214] usb usb4: SerialNumber: 0000:0c:00.0
[ 3.288582] hub 4-0:1.0: USB hub found
[ 3.288615] hub 4-0:1.0: 4 ports detected
[ 3.289502] scsi host0: ahci
[ 3.289864] scsi host1: ahci
[ 3.292868] r8169 0000:0d:00.0 enp13s0: renamed from eth0
[ 3.296341] scsi host2: ahci
[ 3.297158] scsi host3: ahci
[ 3.297682] scsi host4: ahci
[ 3.298147] scsi host5: ahci
[ 3.298236] ata1: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300100 irq 90
[ 3.298239] ata2: SATA max UDMA/133 abar m2048@0xfb300000 port 0xfb300180 irq 90
[ 3.298240] ata3: DUMMY
[ 3.298241] ata4: DUMMY
[ 3.298243] ata5: DUMMY
[ 3.298244] ata6: DUMMY
[ 3.601132] usb 1-1: new high-speed USB device number 2 using ehci-pci
[ 3.612129] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
[ 3.612249] ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
[ 3.612427] ata1.00: ATA-11: KINGSTON SUV400S37120G, 0C3FD6SD, max UDMA/133
[ 3.612429] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 3.612963] ata1.00: configured for UDMA/133
[ 3.613122] scsi 0:0:0:0: Direct-Access ATA KINGSTON SUV400S D6SD PQ: 0 ANSI: 5
[ 3.621135] usb 2-1: new high-speed USB device number 2 using ehci-pci
[ 3.621139] usb 3-1: new high-speed USB device number 2 using xhci_hcd
[ 3.628856] ata2.00: ATA-8: KINGSTON SV300S37A120G, 525ABBF0, max UDMA/133
[ 3.628859] ata2.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 32), AA
[ 3.650125] ata2.00: configured for UDMA/133
[ 3.650270] scsi 1:0:0:0: Direct-Access ATA KINGSTON SV300S3 BBF0 PQ: 0 ANSI: 5
[ 3.661147] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 3.661150] sd 0:0:0:0: [sda] 4096-byte physical blocks
[ 3.661179] sd 0:0:0:0: [sda] Write Protect is off
[ 3.661182] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
[ 3.661199] sd 1:0:0:0: [sdb] 234441648 512-byte logical blocks: (120 GB/112 GiB)
[ 3.661226] sd 1:0:0:0: [sdb] Write Protect is off
[ 3.661228] sd 1:0:0:0: [sdb] Mode Sense: 00 3a 00 00
[ 3.661238] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 3.661277] sd 1:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
[ 3.695557] sda: sda1 sda2
[ 3.696149] sd 0:0:0:0: [sda] Attached SCSI disk
[ 3.698510] sd 1:0:0:0: [sdb] Attached SCSI disk
[ 3.761182] device-mapper: uevent: version 1.0.3
[ 3.761310] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com
[ 3.769430] usb 1-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 3.769433] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.769892] hub 1-1:1.0: USB hub found
[ 3.770066] hub 1-1:1.0: 6 ports detected
[ 3.770833] usb 3-1: New USB device found, idVendor=2109, idProduct=3431, bcdDevice= 4.20
[ 3.770836] usb 3-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[ 3.770838] usb 3-1: Product: USB2.0 Hub
[ 3.771997] hub 3-1:1.0: USB hub found
[ 3.772307] hub 3-1:1.0: 4 ports detected
[ 3.781438] usb 2-1: New USB device found, idVendor=8087, idProduct=0024, bcdDevice= 0.00
[ 3.781441] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
[ 3.781745] hub 2-1:1.0: USB hub found
[ 3.781832] hub 2-1:1.0: 8 ports detected
[ 3.915253] PM: Image not found (code -22)
[ 4.065104] usb 1-1.2: new low-speed USB device number 3 using ehci-pci
[ 4.073093] usb 2-1.4: new high-speed USB device number 3 using ehci-pci
[ 4.083033] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
[ 4.173983] Not activating Mandatory Access Control as /sbin/tomoyo-init does not exist.
[ 4.187304] usb 1-1.2: New USB device found, idVendor=099a, idProduct=610c, bcdDevice= 0.01
[ 4.187307] usb 1-1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 4.187309] usb 1-1.2: Product: USB Multimedia Keyboard
[ 4.187310] usb 1-1.2: Manufacturer:
[ 4.192538] usb 2-1.4: New USB device found, idVendor=148f, idProduct=7601, bcdDevice= 0.00
[ 4.192540] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.192541] usb 2-1.4: Product: 802.11 n WLAN
[ 4.192542] usb 2-1.4: Manufacturer: MediaTek
[ 4.192543] usb 2-1.4: SerialNumber: 1.0
[ 4.264431] systemd[1]: Inserted module 'autofs4'
[ 4.310242] systemd[1]: systemd 247.2-5 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
[ 4.310522] systemd[1]: Detected architecture x86-64.
[ 4.313124] systemd[1]: Set hostname to <debian>.
[ 4.387063] systemd-sysv-generator[225]: SysV service '/etc/init.d/xen' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 4.402276] systemd-sysv-generator[225]: SysV service '/etc/init.d/exim4' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 4.402403] systemd-sysv-generator[225]: SysV service '/etc/init.d/xencommons' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 4.404976] systemd-sysv-generator[225]: SysV service '/etc/init.d/isc-dhcp-server' lacks a native systemd unit file. Automatically generating a unit file for compatibility. Please update package to include a native systemd unit file, in order to make it more safe and robust.
[ 4.467049] systemd[1]: /lib/systemd/system/virtlogd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-sock → /run/libvirt/virtlogd-sock; please update the unit file accordingly.
[ 4.475984] systemd[1]: /lib/systemd/system/virtlogd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlogd-admin-sock → /run/libvirt/virtlogd-admin-sock; please update the unit file accordingly.
[ 4.476561] systemd[1]: /lib/systemd/system/virtlockd.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-sock → /run/libvirt/virtlockd-sock; please update the unit file accordingly.
[ 4.477606] systemd[1]: /lib/systemd/system/virtlockd-admin.socket:6: ListenStream= references a path below legacy directory /var/run/, updating /var/run/libvirt/virtlockd-admin-sock → /run/libvirt/virtlockd-admin-sock; please update the unit file accordingly.
[ 4.529016] systemd[1]: Queued start job for default target Graphical Interface.
[ 4.530954] systemd[1]: Created slice Virtual Machine and Container Slice.
[ 4.532543] systemd[1]: Created slice system-getty.slice.
[ 4.533497] systemd[1]: Created slice system-modprobe.slice.
[ 4.534391] systemd[1]: Created slice system-serial\x2dgetty.slice.
[ 4.535251] systemd[1]: Created slice User and Session Slice.
[ 4.535872] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[ 4.536478] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[ 4.537272] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point.
[ 4.537782] systemd[1]: Reached target Local Encrypted Volumes.
[ 4.538282] systemd[1]: Reached target Paths.
[ 4.538754] systemd[1]: Reached target Remote File Systems.
[ 4.539220] systemd[1]: Reached target Slices.
[ 4.539709] systemd[1]: Reached target Libvirt guests shutdown.
[ 4.540306] systemd[1]: Listening on Device-mapper event daemon FIFOs.
[ 4.540940] systemd[1]: Listening on LVM2 poll daemon socket.
[ 4.542503] systemd[1]: Listening on Syslog Socket.
[ 4.543147] systemd[1]: Listening on fsck to fsckd communication Socket.
[ 4.543716] systemd[1]: Listening on initctl Compatibility Named Pipe.
[ 4.544562] systemd[1]: Listening on Journal Audit Socket.
[ 4.545266] systemd[1]: Listening on Journal Socket (/dev/log).
[ 4.546000] systemd[1]: Listening on Journal Socket.
[ 4.546726] systemd[1]: Listening on udev Control Socket.
[ 4.547376] systemd[1]: Listening on udev Kernel Socket.
[ 4.548178] systemd[1]: Condition check resulted in Huge Pages File System being skipped.
[ 4.550946] systemd[1]: Mounting POSIX Message Queue File System...
[ 4.554870] systemd[1]: Mounting Kernel Debug File System...
[ 4.559269] systemd[1]: Mounting Kernel Trace File System...
[ 4.560475] systemd[1]: Finished Availability of block devices.
[ 4.564386] systemd[1]: Starting Set the console keyboard layout...
[ 4.568389] systemd[1]: Starting Create list of static device nodes for the current kernel...
[ 4.571768] systemd[1]: Starting Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling...
[ 4.575519] systemd[1]: Starting Load Kernel Module configfs...
[ 4.579312] systemd[1]: Starting Load Kernel Module drm...
[ 4.583138] systemd[1]: Starting Load Kernel Module fuse...
[ 4.584711] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
[ 4.584859] systemd[1]: Condition check resulted in File System Check on Root Device being skipped.
[ 4.591475] systemd[1]: Starting Journal Service...
[ 4.608127] systemd[1]: Starting Load Kernel Modules...
[ 4.611369] systemd[1]: Starting Remount Root and Kernel File Systems...
[ 4.616077] systemd[1]: Starting Coldplug All udev Devices...
[ 4.616331] fuse: init (API version 7.32)
[ 4.625621] systemd[1]: Mounted POSIX Message Queue File System.
[ 4.626914] systemd[1]: Mounted Kernel Debug File System.
[ 4.627686] systemd[1]: Mounted Kernel Trace File System.
[ 4.628985] systemd[1]: Finished Create list of static device nodes for the current kernel.
[ 4.630519] systemd[1]: modprobe@configfs.service: Succeeded.
[ 4.631114] systemd[1]: Finished Load Kernel Module configfs.
[ 4.632434] systemd[1]: modprobe@fuse.service: Succeeded.
[ 4.633017] systemd[1]: Finished Load Kernel Module fuse.
[ 4.637524] systemd[1]: Mounting FUSE Control File System...
[ 4.641402] systemd[1]: Mounting Kernel Configuration File System...
[ 4.643471] systemd[1]: modprobe@drm.service: Succeeded.
[ 4.644153] systemd[1]: Finished Load Kernel Module drm.
[ 4.651290] systemd[1]: Mounted FUSE Control File System.
[ 4.655065] xen:xen_evtchn: Event-channel device installed
[ 4.655621] EXT4-fs (sda2): re-mounted. Opts: errors=remount-ro
[ 4.658810] systemd[1]: Finished Remount Root and Kernel File Systems.
[ 4.660486] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
[ 4.660578] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
[ 4.664090] systemd[1]: Starting Load/Save Random Seed...
[ 4.675933] systemd[1]: Starting Create System Users...
[ 4.681305] systemd[1]: Finished Monitoring of LVM2 mirrors, snapshots etc. using dmeventd or progress polling.
[ 4.682306] systemd[1]: Mounted Kernel Configuration File System.
[ 4.704614] xen_pciback: backend is vpci
[ 4.723145] systemd[1]: Finished Load/Save Random Seed.
[ 4.724511] systemd[1]: Condition check resulted in First Boot Complete being skipped.
[ 4.727981] systemd[1]: Finished Create System Users.
[ 4.731300] systemd[1]: Starting Create Static Device Nodes in /dev...
[ 4.767047] systemd[1]: Finished Create Static Device Nodes in /dev.
[ 4.768633] systemd[1]: Finished Load Kernel Modules.
[ 4.772026] systemd[1]: Starting Apply Kernel Variables...
[ 4.777154] systemd[1]: Starting Rule-based Manager for Device Events and Files...
[ 4.820252] systemd[1]: Finished Set the console keyboard layout.
[ 4.821024] systemd[1]: Reached target Local File Systems (Pre).
[ 4.821654] systemd[1]: Condition check resulted in Virtual Machine and Container Storage (Compatibility) being skipped.
[ 4.821699] systemd[1]: Reached target Local File Systems.
[ 4.822306] systemd[1]: Reached target Containers.
[ 4.825600] systemd[1]: Starting Load AppArmor profiles...
[ 4.828601] systemd[1]: Starting Set console font and keymap...
[ 4.829306] systemd[1]: Condition check resulted in Mark the need to relabel after reboot being skipped.
[ 4.829499] systemd[1]: Condition check resulted in Store a System Token in an EFI Variable being skipped.
[ 4.829648] systemd[1]: Condition check resulted in Commit a transient machine-id on disk being skipped.
[ 4.831343] systemd[1]: Finished Apply Kernel Variables.
[ 4.928612] systemd[1]: Started Rule-based Manager for Device Events and Files.
[ 4.946298] systemd[1]: Finished Set console font and keymap.
[ 4.965869] systemd[1]: Started Journal Service.
[ 5.058420] audit: type=1400 audit(1612192799.219:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe" pid=282 comm="apparmor_parser"
[ 5.058427] audit: type=1400 audit(1612192799.219:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="nvidia_modprobe//kmod" pid=282 comm="apparmor_parser"
[ 5.058568] audit: type=1400 audit(1612192799.219:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="lsb_release" pid=284 comm="apparmor_parser"
[ 5.059173] audit: type=1400 audit(1612192799.219:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd" pid=281 comm="apparmor_parser"
[ 5.059178] audit: type=1400 audit(1612192799.219:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/libvirtd//qemu_bridge_helper" pid=281 comm="apparmor_parser"
[ 5.063356] audit: type=1400 audit(1612192799.223:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/bin/man" pid=283 comm="apparmor_parser"
[ 5.063361] audit: type=1400 audit(1612192799.223:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_filter" pid=283 comm="apparmor_parser"
[ 5.063365] audit: type=1400 audit(1612192799.223:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="man_groff" pid=283 comm="apparmor_parser"
[ 5.075832] audit: type=1400 audit(1612192799.235:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="virt-aa-helper" pid=285 comm="apparmor_parser"
[ 5.086238] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input3
[ 5.101154] ACPI: Power Button [PWRB]
[ 5.101281] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input4
[ 5.101362] ACPI: Power Button [PWRF]
[ 6.632356] hid: raw HID events driver (C) Jiri Kosina
[ 6.637863] iTCO_vendor_support: vendor-support=0
[ 6.644457] iTCO_wdt: Intel TCO WatchDog Timer Driver v1.11
[ 6.644506] iTCO_wdt: Found a Panther Point TCO device (Version=2, TCOBASE=0x0460)
[ 6.644755] iTCO_wdt: initialized. heartbeat=30 sec (nowayout=0)
[ 6.650057] usbcore: registered new interface driver usbhid
[ 6.650060] usbhid: USB HID core driver
[ 6.669050] sd 0:0:0:0: Attached scsi generic sg0 type 0
[ 6.686254] sd 1:0:0:0: Attached scsi generic sg1 type 0
[ 6.728059] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[ 6.728395] cfg80211: Loaded X.509 cert 'benh@debian.org: 577e021cb980e0e820821ba7b54b4961b8b4fadf'
[ 6.728737] cfg80211: Loaded X.509 cert 'romain.perier@gmail.com: 3abbc6ec146e09d1b6016ab9d6cf71dd233f0328'
[ 6.729232] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[ 6.730315] platform regulatory.0: firmware: failed to load regulatory.db (-2)
[ 6.730317] firmware_class: See https://wiki.debian.org/Firmware for information about missing firmware
[ 6.730320] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[ 6.730323] cfg80211: failed to load regulatory.db
[ 6.834092] input: PC Speaker as /devices/platform/pcspkr/input/input5
[ 6.959121] usb 2-1.4: reset high-speed USB device number 3 using ehci-pci
[ 7.068098] mt7601u 2-1.4:1.0: ASIC revision: 76010001 MAC revision: 76010500
[ 7.069940] mt7601u 2-1.4:1.0: firmware: direct-loading firmware mt7601u.bin
[ 7.069948] mt7601u 2-1.4:1.0: Firmware Version: 0.1.00 Build: 7640 Build time: 201302052146____
[ 7.086386] input: USB Multimedia Keyboard as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.0/0003:099A:610C.0001/input/input6
[ 7.089904] cryptd: max_cpu_qlen set to 1000
[ 7.094544] Adding 3905532k swap on /dev/sda1. Priority:-2 extents:1 across:3905532k SSFS
[ 7.148468] AVX version of gcm_enc/dec engaged.
[ 7.148470] AES CTR mode by8 optimization enabled
[ 7.149710] hid-generic 0003:099A:610C.0001: input,hidraw0: USB HID v1.00 Keyboard [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input0
[ 7.150072] input: USB Multimedia Keyboard Consumer Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input7
[ 7.213264] input: USB Multimedia Keyboard System Control as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.2/1-1.2:1.1/0003:099A:610C.0002/input/input8
[ 7.213742] hid-generic 0003:099A:610C.0002: input,hidraw1: USB HID v1.00 Device [ USB Multimedia Keyboard ] on usb-0000:00:1a.0-1.2/input1
[ 7.475713] mt7601u 2-1.4:1.0: EEPROM ver:0d fae:00
[ 7.704506] ieee80211 phy0: Selected rate control algorithm 'minstrel_ht'
[ 7.706192] usbcore: registered new interface driver mt7601u
[ 7.718325] mt7601u 2-1.4:1.0 wlx20e0160064bd: renamed from wlan0
[ 10.459142] wlx20e0160064bd: authenticate with 68:ff:7b:47:86:17
[ 10.493855] wlx20e0160064bd: send auth to 68:ff:7b:47:86:17 (try 1/3)
[ 10.497613] wlx20e0160064bd: authenticated
[ 10.501110] wlx20e0160064bd: associate with 68:ff:7b:47:86:17 (try 1/3)
[ 10.508058] wlx20e0160064bd: RX AssocResp from 68:ff:7b:47:86:17 (capab=0x431 status=0 aid=2)
[ 10.545847] wlx20e0160064bd: associated
[ 10.599233] IPv6: ADDRCONF(NETDEV_CHANGE): wlx20e0160064bd: link becomes ready
[ 14.156418] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[ 14.190609] br-lan: port 1(enp13s0) entered blocking state
[ 14.190611] br-lan: port 1(enp13s0) entered disabled state
[ 14.190697] device enp13s0 entered promiscuous mode
[ 14.195933] r8169 0000:0d:00.0: firmware: direct-loading firmware rtl_nic/rtl8168h-2.fw
[ 14.221144] Generic FE-GE Realtek PHY r8169-d00:00: attached PHY driver [Generic FE-GE Realtek PHY] (mii_bus:phy_addr=r8169-d00:00, irq=IGNORE)
[ 14.401259] r8169 0000:0d:00.0 enp13s0: Link is Down
[ 14.405272] br-lan: port 1(enp13s0) entered blocking state
[ 14.405274] br-lan: port 1(enp13s0) entered forwarding state
[ 15.189165] br-lan: port 1(enp13s0) entered disabled state
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-02-01 15:26 ` Claudemir Todo Bom
@ 2021-02-01 16:48 ` Jan Beulich
0 siblings, 0 replies; 26+ messages in thread
From: Jan Beulich @ 2021-02-01 16:48 UTC (permalink / raw)
To: Claudemir Todo Bom; +Cc: xen-devel
On 01.02.2021 16:26, Claudemir Todo Bom wrote:
> Em seg., 1 de fev. de 2021 às 12:09, Jan Beulich <jbeulich@suse.com> escreveu:
>>
>> On 01.02.2021 15:46, Claudemir Todo Bom wrote:
>>> Tested first without the debug patch and with following parameters:
>>
>> And this test was all three of the non-debugging patches?
>
> Yes, all three patches.
>
>>> xen: dom0_mem=1024M,max:2048M dom0_max_vcpus=4 dom0_vcpus_pin=true smt=true
>>> kernel: loglevel=3
>>>
>>> same behaviour as before... black screen right after the xen messages.
>>>
>>> adding earlyprintk=xen to the kernel command line is sufficient to
>>> make it boot, I can imagine this can be happening because Xen is not
>>> releasing console to the kernel at that moment.
>>
>> If the answer to the above question is "yes", then I start
>> suspecting this to be a different problem. I'm not sure I
>> see a way to debug this without having access to any output
>> (i.e. neither video nor serial). Without "earlyprintk=xen"
>> and instead with "vga=keep watchdog" on the Xen command
>> line, is there anything helpful (without or if need be with
>> the debugging patch in place)?
>
> with "vga=text-80x25,keep watchdog" and without the earlyprintk,
> system booted.
Well, you clearly don't want to keep "vga=keep". There has to
be something that's still going wrong, but this may now be a
kernel side issue. In the logs you provided I couldn't spot
anything odd, but these were from working cases after all. So
as said, for now I'm lost, and you may need to live with some
form of workaround (which you've said you're okay with).
Jan
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2021-02-01 16:48 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-01-18 20:15 Problems with APIC on versions 4.9 and later (4.8 works) Claudemir Todo Bom
2021-01-19 9:07 ` Jan Beulich
2021-01-19 19:47 ` Claudemir Todo Bom
[not found] ` <CANyqHYcifnCgd5C5vbYoi4CTtoMX5+jzGqHfs6JZ+e=d2Y_dmg@mail.gmail.com>
2021-01-20 8:50 ` Jan Beulich
2021-01-20 15:13 ` Jürgen Groß
2021-01-20 20:13 ` Claudemir Todo Bom
2021-01-21 7:59 ` Jan Beulich
2021-01-22 12:55 ` Claudemir Todo Bom
2021-01-22 23:36 ` Claudemir Todo Bom
2021-01-25 9:38 ` Jan Beulich
2021-01-25 19:37 ` Claudemir Todo Bom
2021-01-26 11:48 ` Jan Beulich
2021-01-27 12:25 ` Claudemir Todo Bom
[not found] ` <CANyqHYeDR_NUKzPtbfLiUzxAUzerKepbU4B-_6=U-7Y6uy8gpQ@mail.gmail.com>
2021-01-28 9:47 ` Jan Beulich
2021-01-28 9:49 ` Jan Beulich
2021-01-28 13:08 ` Claudemir Todo Bom
2021-01-29 14:21 ` Jan Beulich
2021-01-29 15:07 ` Claudemir Todo Bom
2021-01-29 16:24 ` Jan Beulich
2021-01-29 19:31 ` Claudemir Todo Bom
2021-02-01 7:51 ` Jan Beulich
2021-02-01 12:47 ` Jan Beulich
2021-02-01 14:46 ` Claudemir Todo Bom
2021-02-01 15:09 ` Jan Beulich
2021-02-01 15:26 ` Claudemir Todo Bom
2021-02-01 16:48 ` Jan Beulich
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