* Re: Problems with APIC on versions 4.9 and later (4.8 works)
2021-01-20 15:13 ` Jürgen Groß
2021-01-20 20:13 ` Claudemir Todo Bom
@ 2021-01-22 12:55 ` Claudemir Todo Bom
2021-01-22 23:36 ` Claudemir Todo Bom
2 siblings, 0 replies; 26+ messages in thread
From: Claudemir Todo Bom @ 2021-01-22 12:55 UTC (permalink / raw)
To: Jürgen Groß; +Cc: Jan Beulich, xen-devel, Boris Ostrovsky
[-- Attachment #1: Type: text/plain, Size: 1786 bytes --]
Em qua., 20 de jan. de 2021 às 12:13, Jürgen Groß <jgross@suse.com> escreveu:
>
> On 20.01.21 09:50, Jan Beulich wrote:
> > On 19.01.2021 20:36, Claudemir Todo Bom wrote:
> >> I visually compared all the messages, and the only thing I noticed was that
> >> 4.14 used tsc as clocksource and 4.8 used xen. I tried to boot the kernel
> >> with "clocksource=xen" and the problem is happening with that also.
> >
> > There's some confusion here I suppose: The clock source you talk
> > about is the kernel's, not Xen's. I didn't think this would
> > change for the same kernel version with different Xen underneath,
> > but the Linux maintainers of the Xen code there may know better.
> > Cc-ing them.
>
> This might depend on CPUID bits given to dom0 by Xen, e.g. regarding
> TSC stability.
Based on this observation I've installed the cpuid utility on the
system and obtained the output of it on all scenarios: raw kernel, xen
4.8.5 and xen 4.14.0.
I used "dom0_max_vcpus=1 dom0_vpus_pin smt=false" on both xen command
lines since this is the only way I can get to a command prompt with
xen 4.14.
the outputs of the cpuid command are attached.
I've compared with diff -u (files also attached):
* the differences of both xen with the raw kernel output
* the differences between both xen
It is clear that xen 4.14 is changing a lot how the dom0 sees the cpu,
disabling a lot of features present both on raw kernel and 4.8
outputs. I don't know if this alone can indicate where the problem is
being triggered.
Next I will try to build xen from source with a "binary tree" approach
between 4.8 and 4.9 commits, but as I will use development source, I
think that is very probable I get with a lot of other problems.
Best regards,
Claudemir
[-- Attachment #2: cpuid-xen-4.8.txt --]
[-- Type: text/plain, Size: 25023 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 0
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #3: cpuid-xen-4.14.txt --]
[-- Type: text/plain, Size: 25742 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = false
PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = false
IA64 = false
PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = false
MONITOR/MWAIT = false
CPL-qualified debug store = false
VMX: virtual machine extensions = false
SMX: safer mode extensions = false
Enhanced Intel SpeedStep Technology = false
TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = false
PDCM: perfmon and debug = false
PCID: process context identifiers = false
DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x0 (0)
largest monitor-line size (bytes) = 0x0 (0)
enum of Monitor-MWAIT exts supported = false
supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = false
Intel Turbo Boost Technology = false
ARAT always running APIC timer = false
PLN power limit notification = false
ECMD extended clock modulation duty = false
PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x0 (0)
hardware coordination feedback = false
ACNT2 available = false
performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
version ID = 0x0 (0)
number of counters per logical processor = 0x0 (0)
bit width of counter = 0x0 (0)
length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x0 (0)
bit width of fixed counters = 0x0 (0)
anythread deprecation = false
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
hypervisor_id = "XenVMMXenVMM"
hypervisor version (0x40000001/eax):
version = 4.14
hypervisor features (0x40000002):
number of hypercall-transfer pages = 0x1 (1)
MSR base address = 0x40000000
MMU_PT_UPDATE_PRESERVE_AD supported = true
hypervisor time features (0x40000003/00):
vtsc = false
host tsc is safe = false
boot cpu has RDTSCP = true
tsc mode = 0x0 (0)
tsc frequency (kHz) = 0
incarnation = 0x0 (0)
hypervisor time scale & offset (0x40000003/01):
vtsc offset = 0x0 (0)
vtsc mul_frac = 0x0 (0)
vtsc shift = 0x0 (0)
hypervisor time physical cpu frequency (0x40000003/02):
cpu frequency (kHZ) = 2494348
HVM-specific parameters (0x40000004):
virtualized APIC registers = false
virtualized x2APIC accesses = false
IOMMU mappings for other domain memory = false
vcpu id is valid = false
domain id is valid = false
vcpu id = 0x0 (0)
domain id = 0x0 (0)
PV-specific parameters (0x40000005):
maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 1/4
(APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #4: cpuid-diff-xen-4.8-4.14.diff --]
[-- Type: text/x-patch, Size: 12765 bytes --]
--- cpuid-xen-4.8.txt 2021-01-22 09:32:38.279999364 -0300
+++ cpuid-xen-4.14.txt 2021-01-22 09:24:58.776001456 -0300
@@ -18,9 +18,9 @@
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
+ VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
- PSE: page size extensions = true
+ PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
@@ -28,15 +28,15 @@
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
+ MTRR: memory type range registers = false
+ PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
- PSE-36: page size extension = true
+ PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
- DS: debug store = true
+ DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
@@ -44,41 +44,41 @@
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
- TM: therm. monitor = true
+ TM: therm. monitor = false
IA64 = false
- PBE: pending break event = true
+ PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
+ DTES64: 64-bit debug store = false
+ MONITOR/MWAIT = false
+ CPL-qualified debug store = false
+ VMX: virtual machine extensions = false
+ SMX: safer mode extensions = false
+ Enhanced Intel SpeedStep Technology = false
+ TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
+ xTPR disable = false
+ PDCM: perfmon and debug = false
+ PCID: process context identifiers = false
+ DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
- time stamp counter deadline = true
+ time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
- hypervisor guest status = false
+ hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
@@ -155,25 +155,25 @@
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
+ smallest monitor-line size (bytes) = 0x0 (0)
+ largest monitor-line size (bytes) = 0x0 (0)
+ enum of Monitor-MWAIT exts supported = false
+ supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
+ number of C1 sub C-states using MWAIT = 0x0 (0)
+ number of C2 sub C-states using MWAIT = 0x0 (0)
+ number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
- digital thermometer = true
+ digital thermometer = false
Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
+ ARAT always running APIC timer = false
+ PLN power limit notification = false
+ ECMD extended clock modulation duty = false
+ PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
@@ -188,10 +188,10 @@
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
+ digital thermometer thresholds = 0x0 (0)
+ hardware coordination feedback = false
ACNT2 available = false
- performance-energy bias capability = true
+ performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
@@ -205,7 +205,7 @@
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
+ SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
@@ -279,12 +279,12 @@
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
+ PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
+ version ID = 0x0 (0)
+ number of counters per logical processor = 0x0 (0)
+ bit width of counter = 0x0 (0)
+ length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
@@ -324,21 +324,9 @@
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
+ number of fixed counters = 0x0 (0)
+ bit width of fixed counters = 0x0 (0)
anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 0
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
@@ -377,10 +365,40 @@
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
+ hypervisor_id = "XenVMMXenVMM"
+ hypervisor version (0x40000001/eax):
+ version = 4.14
+ hypervisor features (0x40000002):
+ number of hypercall-transfer pages = 0x1 (1)
+ MSR base address = 0x40000000
+ MMU_PT_UPDATE_PRESERVE_AD supported = true
+ hypervisor time features (0x40000003/00):
+ vtsc = false
+ host tsc is safe = false
+ boot cpu has RDTSCP = true
+ tsc mode = 0x0 (0)
+ tsc frequency (kHz) = 0
+ incarnation = 0x0 (0)
+ hypervisor time scale & offset (0x40000003/01):
+ vtsc offset = 0x0 (0)
+ vtsc mul_frac = 0x0 (0)
+ vtsc shift = 0x0 (0)
+ hypervisor time physical cpu frequency (0x40000003/02):
+ cpu frequency (kHZ) = 2494348
+ HVM-specific parameters (0x40000004):
+ virtualized APIC registers = false
+ virtualized x2APIC accesses = false
+ IOMMU mappings for other domain memory = false
+ vcpu id is valid = false
+ domain id is valid = false
+ vcpu id = 0x0 (0)
+ domain id = 0x0 (0)
+ PV-specific parameters (0x40000005):
+ maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
- 1-GB large page support = true
+ 1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
@@ -476,9 +494,9 @@
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
+ (multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
+ (multi-processing method) = Intel leaf 1/4
+ (APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #5: cpuid-diff-rawkernel-xen-4.8.diff --]
[-- Type: text/x-patch, Size: 587059 bytes --]
--- cpuid-rawkernel.txt 2021-01-22 09:22:28.718600017 -0300
+++ cpuid-xen-4.8.txt 2021-01-22 09:32:38.279999364 -0300
@@ -482,11135 +482,3 @@
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 1:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x2 (2)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 2
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 2:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x4 (4)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 4
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 3:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x6 (6)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 6
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 4:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x8 (8)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 8
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 5:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xa (10)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 10
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 6:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x10 (16)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 16
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 7:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x12 (18)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 18
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 8:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x14 (20)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 20
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 9:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x16 (22)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 22
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 10:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x18 (24)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 24
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 11:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1a (26)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 26
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 12:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1 (1)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 1
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 13:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x3 (3)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 3
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 14:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x5 (5)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 5
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 15:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x7 (7)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 7
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 16:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x9 (9)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 9
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 17:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xb (11)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 11
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 18:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x11 (17)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 17
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 19:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x13 (19)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 19
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 20:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x15 (21)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 21
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 21:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x17 (23)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 23
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 22:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x19 (25)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 25
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 23:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1b (27)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 27
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #6: cpuid-rawkernel.txt --]
[-- Type: text/plain, Size: 600614 bytes --]
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 0
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 1:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x2 (2)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 2
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 2:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x4 (4)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 4
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 3:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x6 (6)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 6
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 4:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x8 (8)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 8
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 5:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0xa (10)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 10
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 6:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x10 (16)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 16
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 7:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x12 (18)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 18
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 8:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x14 (20)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 20
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 9:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x16 (22)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 22
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 10:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x18 (24)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 24
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 11:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1a (26)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 26
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 12:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1 (1)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 1
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 13:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x3 (3)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 3
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 14:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x5 (5)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 5
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 15:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x7 (7)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 7
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 16:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x9 (9)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 9
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 17:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0xb (11)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 11
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 18:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x11 (17)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 17
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 19:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x13 (19)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 19
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 20:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x15 (21)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 21
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 21:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x17 (23)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 23
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 22:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x19 (25)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 25
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
CPU 23:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = 0x6 (6)
model = 0xe (14)
stepping id = 0x4 (4)
extended family = 0x0 (0)
extended model = 0x3 (3)
(family synth) = 0x6 (6)
(model synth) = 0x3e (62)
(simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x1b (27)
maximum IDs for CPUs in pkg = 0x20 (32)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
VME: virtual-8086 mode enhancement = true
DE: debugging extensions = true
PSE: page size extensions = true
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
MCE: machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
MTRR: memory type range registers = true
PTE global bit = true
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
PSE-36: page size extension = true
PSN: processor serial number = false
CLFLUSH instruction = true
DS: debug store = true
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
TM: therm. monitor = true
IA64 = false
PBE: pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
DTES64: 64-bit debug store = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = true
SMX: safer mode extensions = true
Enhanced Intel SpeedStep Technology = true
TM2: thermal monitor 2 = true
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
xTPR disable = true
PDCM: perfmon and debug = true
PCID: process context identifiers = true
DCA: direct cache access = true
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
time stamp counter deadline = true
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
hypervisor guest status = false
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
0x03: data TLB: 4K pages, 4-way, 64 entries
0x76: instruction TLB: 2M/4M pages, fully, 8 entries
0xff: cache data is in CPUID leaf 4
0xb2: instruction TLB: 4K, 4-way, 64 entries
0xf0: 64 byte prefetching
0xca: L2 TLB: 4K pages, 4-way, 512 entries
processor serial number = 0003-06E4-0000-0000-0000-0000
deterministic cache parameters (4):
--- cache 0 ---
cache type = data cache (1)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 1 ---
cache type = instruction cache (2)
cache level = 0x1 (1)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x40 (64)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 64
(size synth) = 32768 (32 KB)
--- cache 2 ---
cache type = unified cache (3)
cache level = 0x2 (2)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1 (1)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x8 (8)
number of sets = 0x200 (512)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = false
complex cache indexing = false
number of sets (s) = 512
(size synth) = 262144 (256 KB)
--- cache 3 ---
cache type = unified cache (3)
cache level = 0x3 (3)
self-initializing cache level = true
fully associative cache = false
maximum IDs for CPUs sharing cache = 0x1f (31)
maximum IDs for cores in pkg = 0xf (15)
system coherency line size = 0x40 (64)
physical line partitions = 0x1 (1)
ways of associativity = 0x14 (20)
number of sets = 0x6000 (24576)
WBINVD/INVD acts on lower caches = false
inclusive to lower caches = true
complex cache indexing = true
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = true
supports intrs as break-event for MWAIT = true
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x2 (2)
number of C2 sub C-states using MWAIT = 0x1 (1)
number of C3 sub C-states using MWAIT = 0x1 (1)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
digital thermometer = true
Intel Turbo Boost Technology = false
ARAT always running APIC timer = true
PLN power limit notification = true
ECMD extended clock modulation duty = true
PTM package thermal management = true
HWP base registers = false
HWP notification = false
HWP activity window = false
HWP energy performance preference = false
HWP package level request = false
HDC base registers = false
Intel Turbo Boost Max Technology 3.0 = false
HWP capabilities = false
HWP PECI override = false
flexible HWP = false
IA32_HWP_REQUEST MSR fast access mode = false
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
digital thermometer thresholds = 0x2 (2)
hardware coordination feedback = true
ACNT2 available = false
performance-energy bias capability = true
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
size of feedback struct (4KB pages) = 0x1 (1)
index of CPU's row in feedback struct = 0x0 (0)
extended feature flags (7):
FSGSBASE instructions = true
IA32_TSC_ADJUST MSR supported = false
SGX: Software Guard Extensions supported = false
BMI1 instructions = false
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
SMEP supervisor mode exec protection = true
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
RTM: restricted transactional memory = false
RDT-CMT/PQoS cache monitoring = false
deprecated FPU CS/DS = false
MPX: intel memory protection extensions = false
RDT-CAT/PQE cache allocation = false
AVX512F: AVX-512 foundation instructions = false
AVX512DQ: double & quadword instructions = false
RDSEED instruction = false
ADX instructions = false
SMAP: supervisor mode access prevention = false
AVX512IFMA: fused multiply add = false
PCOMMIT instruction = false
CLFLUSHOPT instruction = false
CLWB instruction = false
Intel processor trace = false
AVX512PF: prefetch instructions = false
AVX512ER: exponent & reciprocal instrs = false
AVX512CD: conflict detection instrs = false
SHA instructions = false
AVX512BW: byte & word instructions = false
AVX512VL: vector length = false
PREFETCHWT1 = false
AVX512VBMI: vector byte manipulation = false
UMIP: user-mode instruction prevention = false
PKU protection keys for user-mode = false
OSPKE CR4.PKE and RDPKRU/WRPKRU = false
WAITPKG instructions = false
AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
CET_SS: CET shadow stack = false
GFNI: Galois Field New Instructions = false
VAES instructions = false
VPCLMULQDQ instruction = false
AVX512_VNNI: neural network instructions = false
AVX512_BITALG: bit count/shiffle = false
TME: Total Memory Encryption = false
AVX512: VPOPCNTDQ instruction = false
5-level paging = false
BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
RDPID: read processor D supported = false
KL: key locker = false
CLDEMOTE supports cache line demote = false
MOVDIRI instruction = false
MOVDIR64B instruction = false
ENQCMD instruction = false
SGX_LC: SGX launch config supported = false
PKS: supervisor protection keys = false
AVX512_4VNNIW: neural network instrs = false
AVX512_4FMAPS: multiply acc single prec = false
fast short REP MOV = false
UINTR: user interrupts = false
AVX512_VP2INTERSECT: intersect mask regs = false
SRBDS mitigation MSR available = false
VERW MD_CLEAR microcode support = false
SERIALIZE instruction = false
hybrid part = false
TSXLDTRK: TSX suspend load addr tracking = false
PCONFIG instruction = false
LBR: architectural last branch records = false
CET_IBT: CET indirect branch tracking = false
AMX-BF16: tile bfloat16 support = false
AVX512_FP16: fp16 support = false
AMX-TILE: tile architecture support = false
AMX-INT8: tile 8-bit integer support = false
IBRS/IBPB: indirect branch restrictions = false
STIBP: 1 thr indirect branch predictor = false
L1D_FLUSH: IA32_FLUSH_CMD MSR = false
IA32_ARCH_CAPABILITIES MSR = false
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
PLATFORM_DCA_CAP MSR bits = 1
Architecture Performance Monitoring Features (0xa):
version ID = 0x3 (3)
number of counters per logical processor = 0x4 (4)
bit width of counter = 0x30 (48)
length of EBX bit vector = 0x7 (7)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
last-level cache ref event not available = false
last-level cache miss event not avail = false
branch inst retired event not available = false
branch mispred retired event not avail = false
fixed counter 0 supported = false
fixed counter 1 supported = false
fixed counter 2 supported = false
fixed counter 3 supported = false
fixed counter 4 supported = false
fixed counter 5 supported = false
fixed counter 6 supported = false
fixed counter 7 supported = false
fixed counter 8 supported = false
fixed counter 9 supported = false
fixed counter 10 supported = false
fixed counter 11 supported = false
fixed counter 12 supported = false
fixed counter 13 supported = false
fixed counter 14 supported = false
fixed counter 15 supported = false
fixed counter 16 supported = false
fixed counter 17 supported = false
fixed counter 18 supported = false
fixed counter 19 supported = false
fixed counter 20 supported = false
fixed counter 21 supported = false
fixed counter 22 supported = false
fixed counter 23 supported = false
fixed counter 24 supported = false
fixed counter 25 supported = false
fixed counter 26 supported = false
fixed counter 27 supported = false
fixed counter 28 supported = false
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
number of fixed counters = 0x3 (3)
bit width of fixed counters = 0x30 (48)
anythread deprecation = false
x2APIC features / processor topology (0xb):
extended APIC ID = 27
--- level 0 ---
level number = 0x0 (0)
level type = thread (1)
bit width of level = 0x1 (1)
number of logical processors at level = 0x2 (2)
--- level 1 ---
level number = 0x1 (1)
level type = core (2)
bit width of level = 0x5 (5)
number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
XCR0 supported: x87 state = true
XCR0 supported: SSE state = true
XCR0 supported: AVX state = true
XCR0 supported: MPX BNDREGS = false
XCR0 supported: MPX BNDCSR = false
XCR0 supported: AVX-512 opmask = false
XCR0 supported: AVX-512 ZMM_Hi256 = false
XCR0 supported: AVX-512 Hi16_ZMM = false
IA32_XSS supported: PT state = false
XCR0 supported: PKRU state = false
XCR0 supported: CET_U state = false
XCR0 supported: CET_S state = false
IA32_XSS supported: HDC state = false
IA32_XSS supported: UINTR state = false
LBR supported = false
IA32_XSS supported: HWP state = false
XTILECFG supported = false
XTILEDATA supported = false
bytes required by fields in XCR0 = 0x00000340 (832)
bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
XSAVE features (0xd/1):
XSAVEOPT instruction = true
XSAVEC instruction = false
XGETBV instruction = false
XSAVES/XRSTORS instructions = false
XFD: extended feature disable supported = false
SAVE area size in bytes = 0x00000000 (0)
IA32_XSS lower 32 bits valid bit field mask = 0x00000000
IA32_XSS upper 32 bits valid bit field mask = 0x00000000
AVX/YMM features (0xd/2):
AVX/YMM save state byte size = 0x00000100 (256)
AVX/YMM save state byte offset = 0x00000240 (576)
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
1-GB large page support = true
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = true
LZCNT advanced bit manipulation = false
3DNow! PREFETCH/PREFETCHW instructions = false
brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L1 instruction cache information (0x80000005/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (KB) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (KB) = 0x100 (256)
L3 cache information (0x80000006/edx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = L2 off (0)
size (in 512KB units) = 0x0 (0)
RAS Capability (0x80000007/ebx):
MCA overflow recovery support = false
SUCCOR support = false
HWA: hardware assert support = false
scalable MCA support = false
Advanced Power Management Features (0x80000007/ecx):
CmpUnitPwrSampleTimeRatio = 0x0 (0)
Advanced Power Management Features (0x80000007/edx):
TS: temperature sensing diode = false
FID: frequency ID control = false
VID: voltage ID control = false
TTP: thermal trip = false
TM: thermal monitor = false
STC: software thermal control = false
100 MHz multiplier control = false
hardware P-State control = false
TscInvariant = true
CPB: core performance boost = false
read-only effective frequency interface = false
processor feedback interface = false
APM power reporting = false
connected standby = false
RAPL: running average power limit = false
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address bits = 0x2e (46)
maximum linear (virtual) address bits = 0x30 (48)
maximum guest physical address bits = 0x0 (0)
Extended Feature Extensions ID (0x80000008/ebx):
CLZERO instruction = false
instructions retired count support = false
always save/restore error pointers = false
RDPRU instruction = false
memory bandwidth enforcement = false
WBNOINVD instruction = false
IBPB: indirect branch prediction barrier = false
IBRS: indirect branch restr speculation = false
STIBP: 1 thr indirect branch predictor = false
STIBP always on preferred mode = false
ppin processor id number supported = false
SSBD: speculative store bypass disable = false
virtualized SSBD = false
SSBD fixed in hardware = false
Size Identifiers (0x80000008/ecx):
number of CPU cores = 0x1 (1)
ApicIdCoreIdSize = 0x0 (0)
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
(multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
(multi-processing method) = Intel leaf 0xb
(APIC widths synth): CORE_width=5 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
[-- Attachment #7: cpuid-diff-rawkernel-xen-4.14.diff --]
[-- Type: text/x-patch, Size: 599494 bytes --]
--- cpuid-rawkernel.txt 2021-01-22 09:22:28.718600017 -0300
+++ cpuid-xen-4.14.txt 2021-01-22 09:24:58.776001456 -0300
@@ -18,9 +18,9 @@
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
+ VME: virtual-8086 mode enhancement = false
DE: debugging extensions = true
- PSE: page size extensions = true
+ PSE: page size extensions = false
TSC: time stamp counter = true
RDMSR and WRMSR support = true
PAE: physical address extensions = true
@@ -28,15 +28,15 @@
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
+ MTRR: memory type range registers = false
+ PTE global bit = false
MCA: machine check architecture = true
CMOV: conditional move/compare instr = true
PAT: page attribute table = true
- PSE-36: page size extension = true
+ PSE-36: page size extension = false
PSN: processor serial number = false
CLFLUSH instruction = true
- DS: debug store = true
+ DS: debug store = false
ACPI: thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
@@ -44,41 +44,41 @@
SSE2 extensions = true
SS: self snoop = true
hyper-threading / multi-core supported = true
- TM: therm. monitor = true
+ TM: therm. monitor = false
IA64 = false
- PBE: pending break event = true
+ PBE: pending break event = false
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
+ DTES64: 64-bit debug store = false
+ MONITOR/MWAIT = false
+ CPL-qualified debug store = false
+ VMX: virtual machine extensions = false
+ SMX: safer mode extensions = false
+ Enhanced Intel SpeedStep Technology = false
+ TM2: thermal monitor 2 = false
SSSE3 extensions = true
context ID: adaptive or shared L1 data = false
SDBG: IA32_DEBUG_INTERFACE = false
FMA instruction = false
CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
+ xTPR disable = false
+ PDCM: perfmon and debug = false
+ PCID: process context identifiers = false
+ DCA: direct cache access = false
SSE4.1 extensions = true
SSE4.2 extensions = true
x2APIC: extended xAPIC support = true
MOVBE instruction = false
POPCNT instruction = true
- time stamp counter deadline = true
+ time stamp counter deadline = false
AES instruction = true
XSAVE/XSTOR states = true
OS-enabled XSAVE/XSTOR = true
AVX: advanced vector extensions = true
F16C half-precision convert instruction = true
RDRAND instruction = true
- hypervisor guest status = false
+ hypervisor guest status = true
cache and TLB information (2):
0x63: data TLB: 2M/4M pages, 4-way, 32 entries
data TLB: 1G pages, 4-way, 4 entries
@@ -155,25 +155,25 @@
number of sets (s) = 24576
(size synth) = 31457280 (30 MB)
MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
+ smallest monitor-line size (bytes) = 0x0 (0)
+ largest monitor-line size (bytes) = 0x0 (0)
+ enum of Monitor-MWAIT exts supported = false
+ supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
+ number of C1 sub C-states using MWAIT = 0x0 (0)
+ number of C2 sub C-states using MWAIT = 0x0 (0)
+ number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
number of C5 sub C-states using MWAIT = 0x0 (0)
number of C6 sub C-states using MWAIT = 0x0 (0)
number of C7 sub C-states using MWAIT = 0x0 (0)
Thermal and Power Management Features (6):
- digital thermometer = true
+ digital thermometer = false
Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
+ ARAT always running APIC timer = false
+ PLN power limit notification = false
+ ECMD extended clock modulation duty = false
+ PTM package thermal management = false
HWP base registers = false
HWP notification = false
HWP activity window = false
@@ -188,10 +188,10 @@
HW_FEEDBACK MSRs supported = false
ignoring idle logical processor HWP req = false
enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
+ digital thermometer thresholds = 0x0 (0)
+ hardware coordination feedback = false
ACNT2 available = false
- performance-energy bias capability = true
+ performance-energy bias capability = false
number of enh hardware feedback classes = 0x0 (0)
performance capability reporting = false
energy efficiency capability reporting = false
@@ -205,7 +205,7 @@
HLE hardware lock elision = false
AVX2: advanced vector extensions 2 = false
FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
+ SMEP supervisor mode exec protection = false
BMI2 instructions = false
enhanced REP MOVSB/STOSB = true
INVPCID instruction = false
@@ -279,12 +279,12 @@
IA32_CORE_CAPABILITIES MSR = false
SSBD: speculative store bypass disable = false
Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
+ PLATFORM_DCA_CAP MSR bits = 0
Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
+ version ID = 0x0 (0)
+ number of counters per logical processor = 0x0 (0)
+ bit width of counter = 0x0 (0)
+ length of EBX bit vector = 0x0 (0)
core cycle event not available = false
instruction retired event not available = false
reference cycles event not available = false
@@ -324,21 +324,9 @@
fixed counter 29 supported = false
fixed counter 30 supported = false
fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
+ number of fixed counters = 0x0 (0)
+ bit width of fixed counters = 0x0 (0)
anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 0
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
XSAVE features (0xd/0):
XCR0 lower 32 bits valid bit field mask = 0x00000007
XCR0 upper 32 bits valid bit field mask = 0x00000000
@@ -377,10 +365,40 @@
supported in IA32_XSS or XCR0 = XCR0 (user state)
64-byte alignment in compacted XSAVE = false
XFD faulting supported = false
+ hypervisor_id = "XenVMMXenVMM"
+ hypervisor version (0x40000001/eax):
+ version = 4.14
+ hypervisor features (0x40000002):
+ number of hypercall-transfer pages = 0x1 (1)
+ MSR base address = 0x40000000
+ MMU_PT_UPDATE_PRESERVE_AD supported = true
+ hypervisor time features (0x40000003/00):
+ vtsc = false
+ host tsc is safe = false
+ boot cpu has RDTSCP = true
+ tsc mode = 0x0 (0)
+ tsc frequency (kHz) = 0
+ incarnation = 0x0 (0)
+ hypervisor time scale & offset (0x40000003/01):
+ vtsc offset = 0x0 (0)
+ vtsc mul_frac = 0x0 (0)
+ vtsc shift = 0x0 (0)
+ hypervisor time physical cpu frequency (0x40000003/02):
+ cpu frequency (kHZ) = 2494348
+ HVM-specific parameters (0x40000004):
+ virtualized APIC registers = false
+ virtualized x2APIC accesses = false
+ IOMMU mappings for other domain memory = false
+ vcpu id is valid = false
+ domain id is valid = false
+ vcpu id = 0x0 (0)
+ domain id = 0x0 (0)
+ PV-specific parameters (0x40000005):
+ maximum machine address width = 0x24 (36)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = true
execution disable = true
- 1-GB large page support = true
+ 1-GB large page support = false
RDTSCP = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
@@ -476,11141 +494,9 @@
performance time-stamp counter size = 0x0 (0)
Feature Extended Size (0x80000008/edx):
RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
+ (multi-processing synth) = multi-core (c=16), hyper-threaded (t=2)
+ (multi-processing method) = Intel leaf 1/4
+ (APIC widths synth): CORE_width=4 SMT_width=1
(APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=0
(uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
(synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 1:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x2 (2)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 2
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 2:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x4 (4)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 4
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 3:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x6 (6)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 6
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 4:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x8 (8)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 8
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 5:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xa (10)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 10
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 6:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x10 (16)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 16
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 7:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x12 (18)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 18
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 8:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x14 (20)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 20
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 9:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x16 (22)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 22
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 10:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x18 (24)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 24
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 11:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1a (26)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 26
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=0
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 12:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1 (1)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 1
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=0 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 13:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x3 (3)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 3
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=1 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 14:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x5 (5)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 5
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=2 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 15:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x7 (7)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 7
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=3 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 16:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x9 (9)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 9
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=4 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 17:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0xb (11)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 11
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=5 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 18:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x11 (17)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 17
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=8 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 19:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x13 (19)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 19
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=9 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 20:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x15 (21)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 21
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=10 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 21:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x17 (23)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 23
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=11 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 22:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x19 (25)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 25
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=12 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
-CPU 23:
- vendor_id = "GenuineIntel"
- version information (1/eax):
- processor type = primary processor (0)
- family = 0x6 (6)
- model = 0xe (14)
- stepping id = 0x4 (4)
- extended family = 0x0 (0)
- extended model = 0x3 (3)
- (family synth) = 0x6 (6)
- (model synth) = 0x3e (62)
- (simple synth) = Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
- miscellaneous (1/ebx):
- process local APIC physical ID = 0x1b (27)
- maximum IDs for CPUs in pkg = 0x20 (32)
- CLFLUSH line size = 0x8 (8)
- brand index = 0x0 (0)
- brand id = 0x00 (0): unknown
- feature information (1/edx):
- x87 FPU on chip = true
- VME: virtual-8086 mode enhancement = true
- DE: debugging extensions = true
- PSE: page size extensions = true
- TSC: time stamp counter = true
- RDMSR and WRMSR support = true
- PAE: physical address extensions = true
- MCE: machine check exception = true
- CMPXCHG8B inst. = true
- APIC on chip = true
- SYSENTER and SYSEXIT = true
- MTRR: memory type range registers = true
- PTE global bit = true
- MCA: machine check architecture = true
- CMOV: conditional move/compare instr = true
- PAT: page attribute table = true
- PSE-36: page size extension = true
- PSN: processor serial number = false
- CLFLUSH instruction = true
- DS: debug store = true
- ACPI: thermal monitor and clock ctrl = true
- MMX Technology = true
- FXSAVE/FXRSTOR = true
- SSE extensions = true
- SSE2 extensions = true
- SS: self snoop = true
- hyper-threading / multi-core supported = true
- TM: therm. monitor = true
- IA64 = false
- PBE: pending break event = true
- feature information (1/ecx):
- PNI/SSE3: Prescott New Instructions = true
- PCLMULDQ instruction = true
- DTES64: 64-bit debug store = true
- MONITOR/MWAIT = true
- CPL-qualified debug store = true
- VMX: virtual machine extensions = true
- SMX: safer mode extensions = true
- Enhanced Intel SpeedStep Technology = true
- TM2: thermal monitor 2 = true
- SSSE3 extensions = true
- context ID: adaptive or shared L1 data = false
- SDBG: IA32_DEBUG_INTERFACE = false
- FMA instruction = false
- CMPXCHG16B instruction = true
- xTPR disable = true
- PDCM: perfmon and debug = true
- PCID: process context identifiers = true
- DCA: direct cache access = true
- SSE4.1 extensions = true
- SSE4.2 extensions = true
- x2APIC: extended xAPIC support = true
- MOVBE instruction = false
- POPCNT instruction = true
- time stamp counter deadline = true
- AES instruction = true
- XSAVE/XSTOR states = true
- OS-enabled XSAVE/XSTOR = true
- AVX: advanced vector extensions = true
- F16C half-precision convert instruction = true
- RDRAND instruction = true
- hypervisor guest status = false
- cache and TLB information (2):
- 0x63: data TLB: 2M/4M pages, 4-way, 32 entries
- data TLB: 1G pages, 4-way, 4 entries
- 0x03: data TLB: 4K pages, 4-way, 64 entries
- 0x76: instruction TLB: 2M/4M pages, fully, 8 entries
- 0xff: cache data is in CPUID leaf 4
- 0xb2: instruction TLB: 4K, 4-way, 64 entries
- 0xf0: 64 byte prefetching
- 0xca: L2 TLB: 4K pages, 4-way, 512 entries
- processor serial number = 0003-06E4-0000-0000-0000-0000
- deterministic cache parameters (4):
- --- cache 0 ---
- cache type = data cache (1)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 1 ---
- cache type = instruction cache (2)
- cache level = 0x1 (1)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x40 (64)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 64
- (size synth) = 32768 (32 KB)
- --- cache 2 ---
- cache type = unified cache (3)
- cache level = 0x2 (2)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1 (1)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x8 (8)
- number of sets = 0x200 (512)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = false
- complex cache indexing = false
- number of sets (s) = 512
- (size synth) = 262144 (256 KB)
- --- cache 3 ---
- cache type = unified cache (3)
- cache level = 0x3 (3)
- self-initializing cache level = true
- fully associative cache = false
- maximum IDs for CPUs sharing cache = 0x1f (31)
- maximum IDs for cores in pkg = 0xf (15)
- system coherency line size = 0x40 (64)
- physical line partitions = 0x1 (1)
- ways of associativity = 0x14 (20)
- number of sets = 0x6000 (24576)
- WBINVD/INVD acts on lower caches = false
- inclusive to lower caches = true
- complex cache indexing = true
- number of sets (s) = 24576
- (size synth) = 31457280 (30 MB)
- MONITOR/MWAIT (5):
- smallest monitor-line size (bytes) = 0x40 (64)
- largest monitor-line size (bytes) = 0x40 (64)
- enum of Monitor-MWAIT exts supported = true
- supports intrs as break-event for MWAIT = true
- number of C0 sub C-states using MWAIT = 0x0 (0)
- number of C1 sub C-states using MWAIT = 0x2 (2)
- number of C2 sub C-states using MWAIT = 0x1 (1)
- number of C3 sub C-states using MWAIT = 0x1 (1)
- number of C4 sub C-states using MWAIT = 0x0 (0)
- number of C5 sub C-states using MWAIT = 0x0 (0)
- number of C6 sub C-states using MWAIT = 0x0 (0)
- number of C7 sub C-states using MWAIT = 0x0 (0)
- Thermal and Power Management Features (6):
- digital thermometer = true
- Intel Turbo Boost Technology = false
- ARAT always running APIC timer = true
- PLN power limit notification = true
- ECMD extended clock modulation duty = true
- PTM package thermal management = true
- HWP base registers = false
- HWP notification = false
- HWP activity window = false
- HWP energy performance preference = false
- HWP package level request = false
- HDC base registers = false
- Intel Turbo Boost Max Technology 3.0 = false
- HWP capabilities = false
- HWP PECI override = false
- flexible HWP = false
- IA32_HWP_REQUEST MSR fast access mode = false
- HW_FEEDBACK MSRs supported = false
- ignoring idle logical processor HWP req = false
- enhanced hardware feedback interface = false
- digital thermometer thresholds = 0x2 (2)
- hardware coordination feedback = true
- ACNT2 available = false
- performance-energy bias capability = true
- number of enh hardware feedback classes = 0x0 (0)
- performance capability reporting = false
- energy efficiency capability reporting = false
- size of feedback struct (4KB pages) = 0x1 (1)
- index of CPU's row in feedback struct = 0x0 (0)
- extended feature flags (7):
- FSGSBASE instructions = true
- IA32_TSC_ADJUST MSR supported = false
- SGX: Software Guard Extensions supported = false
- BMI1 instructions = false
- HLE hardware lock elision = false
- AVX2: advanced vector extensions 2 = false
- FDP_EXCPTN_ONLY = false
- SMEP supervisor mode exec protection = true
- BMI2 instructions = false
- enhanced REP MOVSB/STOSB = true
- INVPCID instruction = false
- RTM: restricted transactional memory = false
- RDT-CMT/PQoS cache monitoring = false
- deprecated FPU CS/DS = false
- MPX: intel memory protection extensions = false
- RDT-CAT/PQE cache allocation = false
- AVX512F: AVX-512 foundation instructions = false
- AVX512DQ: double & quadword instructions = false
- RDSEED instruction = false
- ADX instructions = false
- SMAP: supervisor mode access prevention = false
- AVX512IFMA: fused multiply add = false
- PCOMMIT instruction = false
- CLFLUSHOPT instruction = false
- CLWB instruction = false
- Intel processor trace = false
- AVX512PF: prefetch instructions = false
- AVX512ER: exponent & reciprocal instrs = false
- AVX512CD: conflict detection instrs = false
- SHA instructions = false
- AVX512BW: byte & word instructions = false
- AVX512VL: vector length = false
- PREFETCHWT1 = false
- AVX512VBMI: vector byte manipulation = false
- UMIP: user-mode instruction prevention = false
- PKU protection keys for user-mode = false
- OSPKE CR4.PKE and RDPKRU/WRPKRU = false
- WAITPKG instructions = false
- AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND = false
- CET_SS: CET shadow stack = false
- GFNI: Galois Field New Instructions = false
- VAES instructions = false
- VPCLMULQDQ instruction = false
- AVX512_VNNI: neural network instructions = false
- AVX512_BITALG: bit count/shiffle = false
- TME: Total Memory Encryption = false
- AVX512: VPOPCNTDQ instruction = false
- 5-level paging = false
- BNDLDX/BNDSTX MAWAU value in 64-bit mode = 0x0 (0)
- RDPID: read processor D supported = false
- KL: key locker = false
- CLDEMOTE supports cache line demote = false
- MOVDIRI instruction = false
- MOVDIR64B instruction = false
- ENQCMD instruction = false
- SGX_LC: SGX launch config supported = false
- PKS: supervisor protection keys = false
- AVX512_4VNNIW: neural network instrs = false
- AVX512_4FMAPS: multiply acc single prec = false
- fast short REP MOV = false
- UINTR: user interrupts = false
- AVX512_VP2INTERSECT: intersect mask regs = false
- SRBDS mitigation MSR available = false
- VERW MD_CLEAR microcode support = false
- SERIALIZE instruction = false
- hybrid part = false
- TSXLDTRK: TSX suspend load addr tracking = false
- PCONFIG instruction = false
- LBR: architectural last branch records = false
- CET_IBT: CET indirect branch tracking = false
- AMX-BF16: tile bfloat16 support = false
- AVX512_FP16: fp16 support = false
- AMX-TILE: tile architecture support = false
- AMX-INT8: tile 8-bit integer support = false
- IBRS/IBPB: indirect branch restrictions = false
- STIBP: 1 thr indirect branch predictor = false
- L1D_FLUSH: IA32_FLUSH_CMD MSR = false
- IA32_ARCH_CAPABILITIES MSR = false
- IA32_CORE_CAPABILITIES MSR = false
- SSBD: speculative store bypass disable = false
- Direct Cache Access Parameters (9):
- PLATFORM_DCA_CAP MSR bits = 1
- Architecture Performance Monitoring Features (0xa):
- version ID = 0x3 (3)
- number of counters per logical processor = 0x4 (4)
- bit width of counter = 0x30 (48)
- length of EBX bit vector = 0x7 (7)
- core cycle event not available = false
- instruction retired event not available = false
- reference cycles event not available = false
- last-level cache ref event not available = false
- last-level cache miss event not avail = false
- branch inst retired event not available = false
- branch mispred retired event not avail = false
- fixed counter 0 supported = false
- fixed counter 1 supported = false
- fixed counter 2 supported = false
- fixed counter 3 supported = false
- fixed counter 4 supported = false
- fixed counter 5 supported = false
- fixed counter 6 supported = false
- fixed counter 7 supported = false
- fixed counter 8 supported = false
- fixed counter 9 supported = false
- fixed counter 10 supported = false
- fixed counter 11 supported = false
- fixed counter 12 supported = false
- fixed counter 13 supported = false
- fixed counter 14 supported = false
- fixed counter 15 supported = false
- fixed counter 16 supported = false
- fixed counter 17 supported = false
- fixed counter 18 supported = false
- fixed counter 19 supported = false
- fixed counter 20 supported = false
- fixed counter 21 supported = false
- fixed counter 22 supported = false
- fixed counter 23 supported = false
- fixed counter 24 supported = false
- fixed counter 25 supported = false
- fixed counter 26 supported = false
- fixed counter 27 supported = false
- fixed counter 28 supported = false
- fixed counter 29 supported = false
- fixed counter 30 supported = false
- fixed counter 31 supported = false
- number of fixed counters = 0x3 (3)
- bit width of fixed counters = 0x30 (48)
- anythread deprecation = false
- x2APIC features / processor topology (0xb):
- extended APIC ID = 27
- --- level 0 ---
- level number = 0x0 (0)
- level type = thread (1)
- bit width of level = 0x1 (1)
- number of logical processors at level = 0x2 (2)
- --- level 1 ---
- level number = 0x1 (1)
- level type = core (2)
- bit width of level = 0x5 (5)
- number of logical processors at level = 0x18 (24)
- XSAVE features (0xd/0):
- XCR0 lower 32 bits valid bit field mask = 0x00000007
- XCR0 upper 32 bits valid bit field mask = 0x00000000
- XCR0 supported: x87 state = true
- XCR0 supported: SSE state = true
- XCR0 supported: AVX state = true
- XCR0 supported: MPX BNDREGS = false
- XCR0 supported: MPX BNDCSR = false
- XCR0 supported: AVX-512 opmask = false
- XCR0 supported: AVX-512 ZMM_Hi256 = false
- XCR0 supported: AVX-512 Hi16_ZMM = false
- IA32_XSS supported: PT state = false
- XCR0 supported: PKRU state = false
- XCR0 supported: CET_U state = false
- XCR0 supported: CET_S state = false
- IA32_XSS supported: HDC state = false
- IA32_XSS supported: UINTR state = false
- LBR supported = false
- IA32_XSS supported: HWP state = false
- XTILECFG supported = false
- XTILEDATA supported = false
- bytes required by fields in XCR0 = 0x00000340 (832)
- bytes required by XSAVE/XRSTOR area = 0x00000340 (832)
- XSAVE features (0xd/1):
- XSAVEOPT instruction = true
- XSAVEC instruction = false
- XGETBV instruction = false
- XSAVES/XRSTORS instructions = false
- XFD: extended feature disable supported = false
- SAVE area size in bytes = 0x00000000 (0)
- IA32_XSS lower 32 bits valid bit field mask = 0x00000000
- IA32_XSS upper 32 bits valid bit field mask = 0x00000000
- AVX/YMM features (0xd/2):
- AVX/YMM save state byte size = 0x00000100 (256)
- AVX/YMM save state byte offset = 0x00000240 (576)
- supported in IA32_XSS or XCR0 = XCR0 (user state)
- 64-byte alignment in compacted XSAVE = false
- XFD faulting supported = false
- extended feature flags (0x80000001/edx):
- SYSCALL and SYSRET instructions = true
- execution disable = true
- 1-GB large page support = true
- RDTSCP = true
- 64-bit extensions technology available = true
- Intel feature flags (0x80000001/ecx):
- LAHF/SAHF supported in 64-bit mode = true
- LZCNT advanced bit manipulation = false
- 3DNow! PREFETCH/PREFETCHW instructions = false
- brand = " Intel(R) Xeon(R) CPU E5-2696 v2 @ 2.50GHz"
- L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = 0x0 (0)
- data # entries = 0x0 (0)
- data associativity = 0x0 (0)
- L1 data cache information (0x80000005/ecx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L1 instruction cache information (0x80000005/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = 0x0 (0)
- size (KB) = 0x0 (0)
- L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
- instruction # entries = 0x0 (0)
- instruction associativity = L2 off (0)
- data # entries = 0x0 (0)
- data associativity = L2 off (0)
- L2 unified cache information (0x80000006/ecx):
- line size (bytes) = 0x40 (64)
- lines per tag = 0x0 (0)
- associativity = 8-way (6)
- size (KB) = 0x100 (256)
- L3 cache information (0x80000006/edx):
- line size (bytes) = 0x0 (0)
- lines per tag = 0x0 (0)
- associativity = L2 off (0)
- size (in 512KB units) = 0x0 (0)
- RAS Capability (0x80000007/ebx):
- MCA overflow recovery support = false
- SUCCOR support = false
- HWA: hardware assert support = false
- scalable MCA support = false
- Advanced Power Management Features (0x80000007/ecx):
- CmpUnitPwrSampleTimeRatio = 0x0 (0)
- Advanced Power Management Features (0x80000007/edx):
- TS: temperature sensing diode = false
- FID: frequency ID control = false
- VID: voltage ID control = false
- TTP: thermal trip = false
- TM: thermal monitor = false
- STC: software thermal control = false
- 100 MHz multiplier control = false
- hardware P-State control = false
- TscInvariant = true
- CPB: core performance boost = false
- read-only effective frequency interface = false
- processor feedback interface = false
- APM power reporting = false
- connected standby = false
- RAPL: running average power limit = false
- Physical Address and Linear Address Size (0x80000008/eax):
- maximum physical address bits = 0x2e (46)
- maximum linear (virtual) address bits = 0x30 (48)
- maximum guest physical address bits = 0x0 (0)
- Extended Feature Extensions ID (0x80000008/ebx):
- CLZERO instruction = false
- instructions retired count support = false
- always save/restore error pointers = false
- RDPRU instruction = false
- memory bandwidth enforcement = false
- WBNOINVD instruction = false
- IBPB: indirect branch prediction barrier = false
- IBRS: indirect branch restr speculation = false
- STIBP: 1 thr indirect branch predictor = false
- STIBP always on preferred mode = false
- ppin processor id number supported = false
- SSBD: speculative store bypass disable = false
- virtualized SSBD = false
- SSBD fixed in hardware = false
- Size Identifiers (0x80000008/ecx):
- number of CPU cores = 0x1 (1)
- ApicIdCoreIdSize = 0x0 (0)
- performance time-stamp counter size = 0x0 (0)
- Feature Extended Size (0x80000008/edx):
- RDPRU instruction max input support = 0x0 (0)
- (multi-processing synth) = multi-core (c=12), hyper-threaded (t=2)
- (multi-processing method) = Intel leaf 0xb
- (APIC widths synth): CORE_width=5 SMT_width=1
- (APIC synth): PKG_ID=0 CORE_ID=13 SMT_ID=1
- (uarch synth) = Intel Ivy Bridge {Sandy Bridge}, 22nm
- (synth) = Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1) {Sandy Bridge}, 22nm
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