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From: Tom Rix <trix@redhat.com>
To: Tianfei zhang <tianfei.zhang@intel.com>,
	hao.wu@intel.com, mdf@kernel.org, yilun.xu@intel.com,
	linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: corbet@lwn.net, Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: Re: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space.
Date: Tue, 15 Feb 2022 07:05:55 -0800	[thread overview]
Message-ID: <0fdd3d0d-d280-8104-eccc-8fa8d8a992c2@redhat.com> (raw)
In-Reply-To: <20220214112619.219761-4-tianfei.zhang@intel.com>


On 2/14/22 3:26 AM, Tianfei zhang wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
>  From a fpga partial reconfiguration standpoint, a port
> may not be connected any local BAR space.  The port could
> be connected to a different PCIe Physical Function (PF) or
> Virtual Function (VF), in which case another driver instance
> would manage the endpoint.

It is not clear if this is part of iofs or a bug fix.

> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> ---
>   drivers/fpga/dfl-pci.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
> index 4d68719e608f..8abd9b408403 100644
> --- a/drivers/fpga/dfl-pci.c
> +++ b/drivers/fpga/dfl-pci.c
> @@ -243,6 +243,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
>   		v = readq(base + FME_HDR_CAP);
>   		port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
>   
> +		dev_info(&pcidev->dev, "port_num = %d\n", port_num);
>   		WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
>   
>   		for (i = 0; i < port_num; i++) {
> @@ -258,6 +259,13 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
>   			 */
>   			bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
>   			offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
> +			if (bar >= PCI_STD_NUM_BARS) {

Is bar set to a better magic number that pci_std_num_bars ? maybe 0xff's

How do you tell between this case and broken hw ?

Move up a line and skip getting an offset that will not be used.

> +				dev_info(&pcidev->dev, "skipping port without local BAR space %d\n",
> +					 bar);
> +				continue;
> +			} else {
> +				dev_info(&pcidev->dev, "BAR %d offset %u\n", bar, offset);
> +			}
>   			start = pci_resource_start(pcidev, bar) + offset;
>   			len = pci_resource_len(pcidev, bar) - offset;
>   

Is similar logic needed for else-if (port) block below this ?

Tom


  reply	other threads:[~2022-02-15 15:06 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-14 11:26 [PATCH v1 0/7] Add Intel OFS support for DFL driver Tianfei zhang
2022-02-14 11:26 ` [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS Tianfei zhang
2022-02-14 12:18   ` Akira Yokosawa
2022-02-14 17:56     ` Randy Dunlap
2022-02-14 23:27       ` Zhang, Tianfei
2022-02-15 14:32   ` Tom Rix
2022-02-16  3:34   ` Wu, Hao
2022-02-21  7:39     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 2/7] fpga: dfl: check feature type before parse irq info Tianfei zhang
2022-02-15 14:49   ` Tom Rix
2022-02-17  2:38     ` Xu Yilun
2022-02-21  7:54       ` Zhang, Tianfei
2022-02-18  6:53     ` Zhang, Tianfei
2022-02-18 14:29       ` Tom Rix
2022-02-21 12:05         ` Zhang, Tianfei
2022-02-16  3:35   ` Wu, Hao
2022-02-21  7:41     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space Tianfei zhang
2022-02-15 15:05   ` Tom Rix [this message]
2022-02-18  7:31     ` Zhang, Tianfei
2022-02-18 14:49       ` Tom Rix
2022-02-21 17:22         ` matthew.gerlach
2022-02-21 17:51           ` Tom Rix
2022-02-22  9:07             ` Zhang, Tianfei
2022-02-16  3:38   ` Wu, Hao
2022-02-21  7:48     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 4/7] fpga: dfl: fix VF creation when ports have no local BAR space Tianfei zhang
2022-02-15 15:50   ` Tom Rix
2022-02-18  8:14     ` Zhang, Tianfei
2022-02-18 14:55       ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list Tianfei zhang
2022-02-15 15:55   ` Tom Rix
2022-02-18  8:24     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 6/7] fpga: dfl: Handle dfl's starting with AFU Tianfei zhang
2022-02-15 16:09   ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 7/7] fpga: dfl: pci: Add generic OFS PCI PID Tianfei zhang
2022-02-15 16:16   ` Tom Rix
2022-02-18  9:03     ` Zhang, Tianfei
2022-02-18 15:27       ` Tom Rix
2022-02-21 17:50         ` matthew.gerlach
2022-02-21 18:09           ` Tom Rix
2022-02-22  3:11             ` Zhang, Tianfei
2022-02-22 16:11               ` Tom Rix
2022-02-23  1:48                 ` Zhang, Tianfei
2022-02-24 17:54                 ` matthew.gerlach
2022-02-28 10:57                   ` Wu, Hao
2022-03-01  0:25                     ` matthew.gerlach

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