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From: Tianfei zhang <tianfei.zhang@intel.com>
To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org,
	yilun.xu@intel.com, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: corbet@lwn.net, Tianfei Zhang <tianfei.zhang@intel.com>
Subject: [PATCH v1 2/7] fpga: dfl: check feature type before parse irq info
Date: Mon, 14 Feb 2022 06:26:14 -0500	[thread overview]
Message-ID: <20220214112619.219761-3-tianfei.zhang@intel.com> (raw)
In-Reply-To: <20220214112619.219761-1-tianfei.zhang@intel.com>

From: Tianfei Zhang <tianfei.zhang@intel.com>

The feature ID of "Port User Interrupt" and the
"PMCI Subsystem" are identical, 0x12, but one is for FME,
other is for Port. It should check the feature type While
parsing the irq info in parse_feature_irqs().

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
 drivers/fpga/dfl.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 599bb21d86af..26f8cf890700 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -940,9 +940,14 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 {
 	void __iomem *base = binfo->ioaddr + ofst;
 	unsigned int i, ibase, inr = 0;
+	enum dfl_id_type type;
 	int virq;
 	u64 v;
 
+	type = feature_dev_id_type(binfo->feature_dev);
+	if (type >= DFL_ID_MAX)
+		return -EINVAL;
+
 	/*
 	 * Ideally DFL framework should only read info from DFL header, but
 	 * current version DFL only provides mmio resources information for
@@ -959,16 +964,22 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo,
 	 */
 	switch (fid) {
 	case PORT_FEATURE_ID_UINT:
+		if (type != PORT_ID)
+			break;
 		v = readq(base + PORT_UINT_CAP);
 		ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v);
 		inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v);
 		break;
 	case PORT_FEATURE_ID_ERROR:
+		if (type != PORT_ID)
+			break;
 		v = readq(base + PORT_ERROR_CAP);
 		ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v);
 		inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v);
 		break;
 	case FME_FEATURE_ID_GLOBAL_ERR:
+		if (type != FME_ID)
+			break;
 		v = readq(base + FME_ERROR_CAP);
 		ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v);
 		inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v);
-- 
2.17.1


  parent reply	other threads:[~2022-02-14 11:39 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-02-14 11:26 [PATCH v1 0/7] Add Intel OFS support for DFL driver Tianfei zhang
2022-02-14 11:26 ` [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS Tianfei zhang
2022-02-14 12:18   ` Akira Yokosawa
2022-02-14 17:56     ` Randy Dunlap
2022-02-14 23:27       ` Zhang, Tianfei
2022-02-15 14:32   ` Tom Rix
2022-02-16  3:34   ` Wu, Hao
2022-02-21  7:39     ` Zhang, Tianfei
2022-02-14 11:26 ` Tianfei zhang [this message]
2022-02-15 14:49   ` [PATCH v1 2/7] fpga: dfl: check feature type before parse irq info Tom Rix
2022-02-17  2:38     ` Xu Yilun
2022-02-21  7:54       ` Zhang, Tianfei
2022-02-18  6:53     ` Zhang, Tianfei
2022-02-18 14:29       ` Tom Rix
2022-02-21 12:05         ` Zhang, Tianfei
2022-02-16  3:35   ` Wu, Hao
2022-02-21  7:41     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space Tianfei zhang
2022-02-15 15:05   ` Tom Rix
2022-02-18  7:31     ` Zhang, Tianfei
2022-02-18 14:49       ` Tom Rix
2022-02-21 17:22         ` matthew.gerlach
2022-02-21 17:51           ` Tom Rix
2022-02-22  9:07             ` Zhang, Tianfei
2022-02-16  3:38   ` Wu, Hao
2022-02-21  7:48     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 4/7] fpga: dfl: fix VF creation when ports have no local BAR space Tianfei zhang
2022-02-15 15:50   ` Tom Rix
2022-02-18  8:14     ` Zhang, Tianfei
2022-02-18 14:55       ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list Tianfei zhang
2022-02-15 15:55   ` Tom Rix
2022-02-18  8:24     ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 6/7] fpga: dfl: Handle dfl's starting with AFU Tianfei zhang
2022-02-15 16:09   ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 7/7] fpga: dfl: pci: Add generic OFS PCI PID Tianfei zhang
2022-02-15 16:16   ` Tom Rix
2022-02-18  9:03     ` Zhang, Tianfei
2022-02-18 15:27       ` Tom Rix
2022-02-21 17:50         ` matthew.gerlach
2022-02-21 18:09           ` Tom Rix
2022-02-22  3:11             ` Zhang, Tianfei
2022-02-22 16:11               ` Tom Rix
2022-02-23  1:48                 ` Zhang, Tianfei
2022-02-24 17:54                 ` matthew.gerlach
2022-02-28 10:57                   ` Wu, Hao
2022-03-01  0:25                     ` matthew.gerlach

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