[PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

From: Tianfei zhang <tianfei.zhang@intel.com>
To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org,
	yilun.xu@intel.com, linux-fpga@vger.kernel.org,
	linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: corbet@lwn.net, Matthew Gerlach <matthew.gerlach@linux.intel.com>,
	Tianfei Zhang <tianfei.zhang@intel.com>
Subject: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
Date: Mon, 14 Feb 2022 06:26:17 -0500	[thread overview]
Message-ID: <20220214112619.219761-6-tianfei.zhang@intel.com> (raw)
In-Reply-To: <20220214112619.219761-1-tianfei.zhang@intel.com>

From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Not all FPGA designs managed by the DFL driver have a port.
In these cases, don't write the Port Access Control register
when enabling SRIOV.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
 drivers/fpga/dfl.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index cfc539a656f0..a5263ac258c5 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
 	int ret = 0, port_count = 0;
 
 	mutex_lock(&cdev->lock);
+	if (list_empty(&cdev->port_dev_list))
+		goto done;
 
 	list_for_each_entry(pdata, &cdev->port_dev_list, node) {
 		if (pdata->dev)
-- 
2.17.1

