From: Jani Nikula <jani.nikula@intel.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders Date: Tue, 26 Nov 2019 15:42:41 +0200 [thread overview] Message-ID: <1026c6bb4c002fc8caada18fbf4ee9b5948a1d18.1574775655.git.jani.nikula@intel.com> (raw) In-Reply-To: <cover.1574775655.git.jani.nikula@intel.com> Add DSI specific computation and transmission to display of PPS. With hopes that this approach will work for both DP and DSI encoders. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index c53024dfb1ec..7bd727129a8f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,6 +10,7 @@ #include "i915_drv.h" #include "intel_display_types.h" +#include "intel_dsi.h" #include "intel_vdsc.h" enum ROW_INDEX_BPP { @@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, } } +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct mipi_dsi_device *dsi; + struct drm_dsc_picture_parameter_set pps; + enum port port; + + drm_dsc_pps_payload_pack(&pps, vdsc_cfg); + + for_each_dsi_port(port, intel_dsi->ports) { + dsi = intel_dsi->dsi_hosts[port]->device; + + mipi_dsi_picture_parameter_set(dsi, &pps); + mipi_dsi_compression_mode(dsi, true); + } +} + static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_dsc_pps_configure(encoder, crtc_state); - intel_dsc_dp_pps_write(encoder, crtc_state); + if (encoder->type == INTEL_OUTPUT_DSI) + intel_dsc_dsi_pps_write(encoder, crtc_state); + else + intel_dsc_dp_pps_write(encoder, crtc_state); if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { dss_ctl1_reg = DSS_CTL1; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
WARNING: multiple messages have this Message-ID (diff)
From: Jani Nikula <jani.nikula@intel.com> To: intel-gfx@lists.freedesktop.org Cc: jani.nikula@intel.com Subject: [Intel-gfx] [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders Date: Tue, 26 Nov 2019 15:42:41 +0200 [thread overview] Message-ID: <1026c6bb4c002fc8caada18fbf4ee9b5948a1d18.1574775655.git.jani.nikula@intel.com> (raw) Message-ID: <20191126134241.nkbKTJDTrlPqHNGcQI8NtgEn-chmKAlh2-vBVelJQqw@z> (raw) In-Reply-To: <cover.1574775655.git.jani.nikula@intel.com> Add DSI specific computation and transmission to display of PPS. With hopes that this approach will work for both DP and DSI encoders. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 25 ++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index c53024dfb1ec..7bd727129a8f 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,6 +10,7 @@ #include "i915_drv.h" #include "intel_display_types.h" +#include "intel_dsi.h" #include "intel_vdsc.h" enum ROW_INDEX_BPP { @@ -844,6 +845,25 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, } } +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct mipi_dsi_device *dsi; + struct drm_dsc_picture_parameter_set pps; + enum port port; + + drm_dsc_pps_payload_pack(&pps, vdsc_cfg); + + for_each_dsi_port(port, intel_dsi->ports) { + dsi = intel_dsi->dsi_hosts[port]->device; + + mipi_dsi_picture_parameter_set(dsi, &pps); + mipi_dsi_compression_mode(dsi, true); + } +} + static void intel_dsc_dp_pps_write(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { @@ -882,7 +902,10 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_dsc_pps_configure(encoder, crtc_state); - intel_dsc_dp_pps_write(encoder, crtc_state); + if (encoder->type == INTEL_OUTPUT_DSI) + intel_dsc_dsi_pps_write(encoder, crtc_state); + else + intel_dsc_dp_pps_write(encoder, crtc_state); if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { dss_ctl1_reg = DSS_CTL1; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-26 13:43 UTC|newest] Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-11-26 13:42 [PATCH v3 00/13] drm/i915/dsi: enable DSC Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-11-26 13:42 ` [PATCH v3 01/13] drm/i915/bios: pass devdata to parse_ddi_port Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-04 7:52 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 02/13] drm/i915/bios: parse compression parameters block Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-04 8:07 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 03/13] drm/i915/bios: add support for querying DSC details for encoder Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 4:42 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 04/13] drm/i915/dsc: move DP specific compute params to intel_dp.c Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 5:07 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 05/13] drm/i915/dsc: move slice height calculation to encoder Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 5:28 ` Kulkarni, Vandita 2019-11-26 13:42 ` Jani Nikula [this message] 2019-11-26 13:42 ` [Intel-gfx] [PATCH v3 06/13] drm/i915/dsc: add support for computing and writing PPS for DSI encoders Jani Nikula 2019-12-05 5:44 ` Kulkarni, Vandita 2019-12-09 15:43 ` Jani Nikula 2019-11-26 13:42 ` [PATCH v3 07/13] drm/i915/dsi: set pipe_bpp on ICL configure config Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 10:15 ` Kulkarni, Vandita 2019-12-09 15:46 ` Jani Nikula 2019-11-26 13:42 ` [PATCH v3 08/13] drm/i915/dsi: abstract afe_clk calculation Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 8:25 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 09/13] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate() Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 13:06 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 10/13] drm/i915/dsi: take compression into account in afe_clk() Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 14:36 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 11/13] drm/i915/dsi: use compressed pixel format with DSC Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 14:44 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 12/13] drm/i915/dsi: account for DSC in horizontal timings Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 14:52 ` Kulkarni, Vandita 2019-11-26 13:42 ` [PATCH v3 13/13] drm/i915/dsi: add support for DSC Jani Nikula 2019-11-26 13:42 ` [Intel-gfx] " Jani Nikula 2019-12-05 6:14 ` Kulkarni, Vandita 2019-12-09 16:02 ` Jani Nikula 2019-11-26 18:22 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev3) Patchwork 2019-11-26 18:22 ` [Intel-gfx] " Patchwork 2019-11-26 18:52 ` ✗ Fi.CI.BAT: failure " Patchwork 2019-11-26 18:52 ` [Intel-gfx] " Patchwork 2019-11-27 14:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev4) Patchwork 2019-11-27 14:07 ` [Intel-gfx] " Patchwork 2019-11-27 14:30 ` ✓ Fi.CI.BAT: success " Patchwork 2019-11-27 14:30 ` [Intel-gfx] " Patchwork 2019-11-28 14:21 ` ✗ Fi.CI.IGT: failure " Patchwork 2019-11-28 14:21 ` [Intel-gfx] " Patchwork 2019-12-05 15:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC (rev5) Patchwork 2019-12-05 16:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1026c6bb4c002fc8caada18fbf4ee9b5948a1d18.1574775655.git.jani.nikula@intel.com \ --to=jani.nikula@intel.com \ --cc=intel-gfx@lists.freedesktop.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.