[PATCH 00/12] PCI:Add SPEAr13xx PCie support

[PATCH 00/12] PCI:Add SPEAr13xx PCie support

[Mohit Kumar]

First five patches are improvement and fixes for SPEAr13xx support.

Next three patches improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch
 
Mohit Kumar (4):
  SPEAr13xx: Correct dt field name for stmmac phy-addr
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
  MAINTAINERS: Add Synopsis Designware PCIe driver maintainer

Pratyush Anand (8):
  SPEAr13xx: Move SPEAr1340 definitions to header file
  SPEAr13xx: Add SPEAr1310 PCIe register definitions
  SPEAr13xx: Fix static mapping table
  clk: SPEAr13xx: Fix pcie clock name
  pcie: designware: Move register definition to the header file
  pcie: designware: add dw_pcie prefix before cfg_read/write
  pcie: designware: Fix IO transfers
  pcie: SPEAr13xx: Add designware pcie support

 MAINTAINERS                              |   13 +
 arch/arm/boot/dts/spear13xx.dtsi         |   55 +++-
 arch/arm/configs/spear13xx_defconfig     |   15 +
 arch/arm/mach-spear/Kconfig              |    1 +
 arch/arm/mach-spear/include/mach/spear.h |  132 +++++++-
 arch/arm/mach-spear/spear1340.c          |   54 ---
 arch/arm/mach-spear/spear13xx.c          |    2 +-
 drivers/clk/spear/spear1310_clock.c      |    6 +-
 drivers/clk/spear/spear1340_clock.c      |    2 +-
 drivers/pci/host/Kconfig                 |    5 +
 drivers/pci/host/Makefile                |    2 +
 drivers/pci/host/pci-exynos.c            |    5 +-
 drivers/pci/host/pcie-designware.c       |   70 +---
 drivers/pci/host/pcie-designware.h       |   46 +++-
 drivers/pci/host/pcie-spear13xx.c        |  564 ++++++++++++++++++++++++++++++
 15 files changed, 850 insertions(+), 122 deletions(-)
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

[PATCH 00/12] PCI:Add SPEAr13xx PCie support

[Mohit Kumar]

First five patches are improvement and fixes for SPEAr13xx support.

Next three patches improves pcie designware driver and fixes the IO
translation bug. IO translation bug fix leads to the working of PCIe EP devices
connected to RC through switch.

PCIe driver support for SPEAr1310/40 platform board is added.

These patches are tested with SPEAr1310 evaluation board:
	- INTEL PRO 100/100 EP card
	- USB xhci gen2 card
 	- Above cards connected through LeCROY PTC switch
 
Mohit Kumar (4):
  SPEAr13xx: Correct dt field name for stmmac phy-addr
  SPEAr13xx: defconfig: Update
  MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
  MAINTAINERS: Add Synopsis Designware PCIe driver maintainer

Pratyush Anand (8):
  SPEAr13xx: Move SPEAr1340 definitions to header file
  SPEAr13xx: Add SPEAr1310 PCIe register definitions
  SPEAr13xx: Fix static mapping table
  clk: SPEAr13xx: Fix pcie clock name
  pcie: designware: Move register definition to the header file
  pcie: designware: add dw_pcie prefix before cfg_read/write
  pcie: designware: Fix IO transfers
  pcie: SPEAr13xx: Add designware pcie support

 MAINTAINERS                              |   13 +
 arch/arm/boot/dts/spear13xx.dtsi         |   55 +++-
 arch/arm/configs/spear13xx_defconfig     |   15 +
 arch/arm/mach-spear/Kconfig              |    1 +
 arch/arm/mach-spear/include/mach/spear.h |  132 +++++++-
 arch/arm/mach-spear/spear1340.c          |   54 ---
 arch/arm/mach-spear/spear13xx.c          |    2 +-
 drivers/clk/spear/spear1310_clock.c      |    6 +-
 drivers/clk/spear/spear1340_clock.c      |    2 +-
 drivers/pci/host/Kconfig                 |    5 +
 drivers/pci/host/Makefile                |    2 +
 drivers/pci/host/pci-exynos.c            |    5 +-
 drivers/pci/host/pcie-designware.c       |   70 +---
 drivers/pci/host/pcie-designware.h       |   46 +++-
 drivers/pci/host/pcie-spear13xx.c        |  564 ++++++++++++++++++++++++++++++
 15 files changed, 850 insertions(+), 122 deletions(-)
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit Kumar]

DT field name for the phy address changed since kernel 3.10. Set the
snps,phy-addr to 0xffffffff so that the driver probes for the phy.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
---
 arch/arm/boot/dts/spear13xx.dtsi |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3518803 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -155,6 +155,7 @@
 
 		gmac0: eth@e2000000 {
 			compatible = "st,spear600-gmac";
+			snps,phy-addr = <0xffffffff>;
 			reg = <0xe2000000 0x8000>;
 			interrupts = <0 33 0x4
 				      0 34 0x4>;
-- 
1.7.0.1

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit Kumar]

DT field name for the phy address changed since kernel 3.10. Set the
snps,phy-addr to 0xffffffff so that the driver probes for the phy.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
---
 arch/arm/boot/dts/spear13xx.dtsi |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3518803 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -155,6 +155,7 @@
 
 		gmac0: eth at e2000000 {
 			compatible = "st,spear600-gmac";
+			snps,phy-addr = <0xffffffff>;
 			reg = <0xe2000000 0x8000>;
 			interrupts = <0 33 0x4
 				      0 34 0x4>;
-- 
1.7.0.1

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit Kumar]

DT field name for the phy address changed since kernel 3.10. Set the
snps,phy-addr to 0xffffffff so that the driver probes for the phy.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
---
 arch/arm/boot/dts/spear13xx.dtsi |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 4382547..3518803 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -155,6 +155,7 @@
 
 		gmac0: eth@e2000000 {
 			compatible = "st,spear600-gmac";
+			snps,phy-addr = <0xffffffff>;
 			reg = <0xe2000000 0x8000>;
 			interrupts = <0 33 0x4
 				      0 34 0x4>;
-- 
1.7.0.1

Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> DT field name for the phy address changed since kernel 3.10. Set the
> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Pratyush Anand<pratyush.anand@st.com>
> Cc: Viresh Kumar<viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: devicetree@vger.kernel.org
> ---
>   arch/arm/boot/dts/spear13xx.dtsi |    1 +
>   1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
> index 4382547..3518803 100644
> --- a/arch/arm/boot/dts/spear13xx.dtsi
> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> @@ -155,6 +155,7 @@
>
>   		gmac0: eth@e2000000 {
>   			compatible = "st,spear600-gmac";
> +			snps,phy-addr =<0xffffffff>;

Don't you think it should be st,phy-addr =<0xffffffff>, as the 
manufacturer is 'st' as the compatible suggest

~Rajeev


>   			reg =<0xe2000000 0x8000>;
>   			interrupts =<0 33 0x4
>   				      0 34 0x4>;

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> DT field name for the phy address changed since kernel 3.10. Set the
> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Pratyush Anand<pratyush.anand@st.com>
> Cc: Viresh Kumar<viresh.linux@gmail.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: devicetree at vger.kernel.org
> ---
>   arch/arm/boot/dts/spear13xx.dtsi |    1 +
>   1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
> index 4382547..3518803 100644
> --- a/arch/arm/boot/dts/spear13xx.dtsi
> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> @@ -155,6 +155,7 @@
>
>   		gmac0: eth at e2000000 {
>   			compatible = "st,spear600-gmac";
> +			snps,phy-addr =<0xffffffff>;

Don't you think it should be st,phy-addr =<0xffffffff>, as the 
manufacturer is 'st' as the compatible suggest

~Rajeev


>   			reg =<0xe2000000 0x8000>;
>   			interrupts =<0 33 0x4
>   				      0 34 0x4>;

Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

Recheck the subject line, you are not doing any correction.

On 12/11/2013 4:39 PM, Rajeev KUMAR wrote:
> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>> DT field name for the phy address changed since kernel 3.10. Set the
>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>
>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>> Cc: Pratyush Anand<pratyush.anand@st.com>
>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>> Cc: spear-devel@list.st.com
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: devicetree@vger.kernel.org
>> ---
>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
>> index 4382547..3518803 100644
>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>> @@ -155,6 +155,7 @@
>>
>>    		gmac0: eth@e2000000 {
>>    			compatible = "st,spear600-gmac";
>> +			snps,phy-addr =<0xffffffff>;
>
> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> manufacturer is 'st' as the compatible suggest
>
> ~Rajeev
>
>
>>    			reg =<0xe2000000 0x8000>;
>>    			interrupts =<0 33 0x4
>>    				      0 34 0x4>;
>

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

Recheck the subject line, you are not doing any correction.

On 12/11/2013 4:39 PM, Rajeev KUMAR wrote:
> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>> DT field name for the phy address changed since kernel 3.10. Set the
>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>
>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>> Cc: Pratyush Anand<pratyush.anand@st.com>
>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>> Cc: spear-devel at list.st.com
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: devicetree at vger.kernel.org
>> ---
>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
>> index 4382547..3518803 100644
>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>> @@ -155,6 +155,7 @@
>>
>>    		gmac0: eth at e2000000 {
>>    			compatible = "st,spear600-gmac";
>> +			snps,phy-addr =<0xffffffff>;
>
> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> manufacturer is 'st' as the compatible suggest
>
> ~Rajeev
>
>
>>    			reg =<0xe2000000 0x8000>;
>>    			interrupts =<0 33 0x4
>>    				      0 34 0x4>;
>

Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Jingoo Han]

On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> > DT field name for the phy address changed since kernel 3.10. Set the
> > snps,phy-addr to 0xffffffff so that the driver probes for the phy.
> >
> > Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> > Cc: Pratyush Anand<pratyush.anand@st.com>
> > Cc: Viresh Kumar<viresh.linux@gmail.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-arm-kernel@lists.infradead.org
> > Cc: devicetree@vger.kernel.org
> > ---
> >   arch/arm/boot/dts/spear13xx.dtsi |    1 +
> >   1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
> > index 4382547..3518803 100644
> > --- a/arch/arm/boot/dts/spear13xx.dtsi
> > +++ b/arch/arm/boot/dts/spear13xx.dtsi
> > @@ -155,6 +155,7 @@
> >
> >   		gmac0: eth@e2000000 {
> >   			compatible = "st,spear600-gmac";
> > +			snps,phy-addr =<0xffffffff>;
> 
> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> manufacturer is 'st' as the compatible suggest

Hi Rajeev Kumar,

According to the Documentation, it guides to use 'snps' prefix.

In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
not ST specific, 'snps' prefix can be used.

./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr         phy address to connect to.

Best regards,
Jingoo Han

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Jingoo Han]

On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> > DT field name for the phy address changed since kernel 3.10. Set the
> > snps,phy-addr to 0xffffffff so that the driver probes for the phy.
> >
> > Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> > Cc: Pratyush Anand<pratyush.anand@st.com>
> > Cc: Viresh Kumar<viresh.linux@gmail.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-arm-kernel at lists.infradead.org
> > Cc: devicetree at vger.kernel.org
> > ---
> >   arch/arm/boot/dts/spear13xx.dtsi |    1 +
> >   1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
> > index 4382547..3518803 100644
> > --- a/arch/arm/boot/dts/spear13xx.dtsi
> > +++ b/arch/arm/boot/dts/spear13xx.dtsi
> > @@ -155,6 +155,7 @@
> >
> >   		gmac0: eth at e2000000 {
> >   			compatible = "st,spear600-gmac";
> > +			snps,phy-addr =<0xffffffff>;
> 
> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> manufacturer is 'st' as the compatible suggest

Hi Rajeev Kumar,

According to the Documentation, it guides to use 'snps' prefix.

In my humble opinion,
'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
not ST specific, 'snps' prefix can be used.

./Documentation/devicetree/bindings/net/stmmac.txt
- snps,phy-addr         phy address to connect to.

Best regards,
Jingoo Han

Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

On 12/12/2013 6:09 AM, Jingoo Han wrote:
> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>>> DT field name for the phy address changed since kernel 3.10. Set the
>>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>>
>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>>> Cc: Pratyush Anand<pratyush.anand@st.com>
>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>>> Cc: spear-devel@list.st.com
>>> Cc: linux-arm-kernel@lists.infradead.org
>>> Cc: devicetree@vger.kernel.org
>>> ---
>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
>>> index 4382547..3518803 100644
>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>>> @@ -155,6 +155,7 @@
>>>
>>>    		gmac0: eth@e2000000 {
>>>    			compatible = "st,spear600-gmac";
>>> +			snps,phy-addr =<0xffffffff>;
>>
>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
>> manufacturer is 'st' as the compatible suggest
>
> Hi Rajeev Kumar,
>
> According to the Documentation, it guides to use 'snps' prefix.
>
> In my humble opinion,
> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
> not ST specific, 'snps' prefix can be used.
>


Very much true, I raise the point just becuase compatible = 
"st,spear600-gmac". Check the manufacturer name here.

~Rajeev

> ./Documentation/devicetree/bindings/net/stmmac.txt
> - snps,phy-addr         phy address to connect to.
>
> Best regards,
> Jingoo Han
>

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Rajeev kumar]

On 12/12/2013 6:09 AM, Jingoo Han wrote:
> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>>> DT field name for the phy address changed since kernel 3.10. Set the
>>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>>
>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>>> Cc: Pratyush Anand<pratyush.anand@st.com>
>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>>> Cc: spear-devel at list.st.com
>>> Cc: linux-arm-kernel at lists.infradead.org
>>> Cc: devicetree at vger.kernel.org
>>> ---
>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
>>> index 4382547..3518803 100644
>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>>> @@ -155,6 +155,7 @@
>>>
>>>    		gmac0: eth at e2000000 {
>>>    			compatible = "st,spear600-gmac";
>>> +			snps,phy-addr =<0xffffffff>;
>>
>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
>> manufacturer is 'st' as the compatible suggest
>
> Hi Rajeev Kumar,
>
> According to the Documentation, it guides to use 'snps' prefix.
>
> In my humble opinion,
> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
> not ST specific, 'snps' prefix can be used.
>


Very much true, I raise the point just becuase compatible = 
"st,spear600-gmac". Check the manufacturer name here.

~Rajeev

> ./Documentation/devicetree/bindings/net/stmmac.txt
> - snps,phy-addr         phy address to connect to.
>
> Best regards,
> Jingoo Han
>

Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Chen-Yu Tsai]

Hi,

On Thu, Dec 12, 2013 at 11:59 AM, Rajeev kumar <rajeev-dlh.kumar@st.com> wrote:
> On 12/12/2013 6:09 AM, Jingoo Han wrote:
>>
>> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
>>>
>>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>>>>
>>>> DT field name for the phy address changed since kernel 3.10. Set the
>>>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>>>
>>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>>>> Cc: Pratyush Anand<pratyush.anand@st.com>
>>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>>>> Cc: spear-devel@list.st.com
>>>> Cc: linux-arm-kernel@lists.infradead.org
>>>> Cc: devicetree@vger.kernel.org
>>>> ---
>>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
>>>> b/arch/arm/boot/dts/spear13xx.dtsi
>>>> index 4382547..3518803 100644
>>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>>>> @@ -155,6 +155,7 @@
>>>>
>>>>                 gmac0: eth@e2000000 {
>>>>                         compatible = "st,spear600-gmac";
>>>> +                       snps,phy-addr =<0xffffffff>;
>>>
>>>
>>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
>>> manufacturer is 'st' as the compatible suggest
>>
>>
>> Hi Rajeev Kumar,
>>
>> According to the Documentation, it guides to use 'snps' prefix.
>>
>> In my humble opinion,
>> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
>> not ST specific, 'snps' prefix can be used.
>>
>
>
> Very much true, I raise the point just becuase compatible =
> "st,spear600-gmac". Check the manufacturer name here.

As documented, "st,spear600-gmac" is there for backwards
compatibility. It should really be updated to
'"snps,dwmac-<version>", "snps,dwmac"'.




>> ./Documentation/devicetree/bindings/net/stmmac.txt
>> - snps,phy-addr         phy address to connect to.

About the "snps,phy-addr" property, Florian recently raised
the issue that this is !standard. I am currently implementing
proper DT ethernet phy node support for stmmac. Just a
heads up. :)


ChenYu

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Chen-Yu Tsai]

Hi,

On Thu, Dec 12, 2013 at 11:59 AM, Rajeev kumar <rajeev-dlh.kumar@st.com> wrote:
> On 12/12/2013 6:09 AM, Jingoo Han wrote:
>>
>> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
>>>
>>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
>>>>
>>>> DT field name for the phy address changed since kernel 3.10. Set the
>>>> snps,phy-addr to 0xffffffff so that the driver probes for the phy.
>>>>
>>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
>>>> Cc: Pratyush Anand<pratyush.anand@st.com>
>>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
>>>> Cc: spear-devel at list.st.com
>>>> Cc: linux-arm-kernel at lists.infradead.org
>>>> Cc: devicetree at vger.kernel.org
>>>> ---
>>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
>>>>    1 files changed, 1 insertions(+), 0 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
>>>> b/arch/arm/boot/dts/spear13xx.dtsi
>>>> index 4382547..3518803 100644
>>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
>>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
>>>> @@ -155,6 +155,7 @@
>>>>
>>>>                 gmac0: eth at e2000000 {
>>>>                         compatible = "st,spear600-gmac";
>>>> +                       snps,phy-addr =<0xffffffff>;
>>>
>>>
>>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
>>> manufacturer is 'st' as the compatible suggest
>>
>>
>> Hi Rajeev Kumar,
>>
>> According to the Documentation, it guides to use 'snps' prefix.
>>
>> In my humble opinion,
>> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is
>> not ST specific, 'snps' prefix can be used.
>>
>
>
> Very much true, I raise the point just becuase compatible =
> "st,spear600-gmac". Check the manufacturer name here.

As documented, "st,spear600-gmac" is there for backwards
compatibility. It should really be updated to
'"snps,dwmac-<version>", "snps,dwmac"'.




>> ./Documentation/devicetree/bindings/net/stmmac.txt
>> - snps,phy-addr         phy address to connect to.

About the "snps,phy-addr" property, Florian recently raised
the issue that this is !standard. I am currently implementing
proper DT ethernet phy node support for stmmac. Just a
heads up. :)


ChenYu

RE: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit KUMAR DCG]

Hello Shiraz/Viresh,

> -----Original Message-----
> From: wens213@gmail.com [mailto:wens213@gmail.com] On Behalf Of
> Chen-Yu Tsai
> Sent: Thursday, December 12, 2013 9:37 AM
> To: Rajeev KUMAR
> Cc: Jingoo Han; Pratyush ANAND; devicetree@vger.kernel.org; Mohit
> KUMAR DCG; spear-devel; Viresh Kumar; linux-pci@vger.kernel.org; linux-
> arm-kernel@lists.infradead.org; Florian Fainelli
> Subject: Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-
> addr
> 
> Hi,
> 
> On Thu, Dec 12, 2013 at 11:59 AM, Rajeev kumar <rajeev-
> dlh.kumar@st.com> wrote:
> > On 12/12/2013 6:09 AM, Jingoo Han wrote:
> >>
> >> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
> >>>
> >>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> >>>>
> >>>> DT field name for the phy address changed since kernel 3.10. Set
> >>>> the snps,phy-addr to 0xffffffff so that the driver probes for the phy.
> >>>>
> >>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> >>>> Cc: Pratyush Anand<pratyush.anand@st.com>
> >>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
> >>>> Cc: spear-devel@list.st.com
> >>>> Cc: linux-arm-kernel@lists.infradead.org
> >>>> Cc: devicetree@vger.kernel.org
> >>>> ---
> >>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
> >>>>    1 files changed, 1 insertions(+), 0 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> index 4382547..3518803 100644
> >>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> @@ -155,6 +155,7 @@
> >>>>
> >>>>                 gmac0: eth@e2000000 {
> >>>>                         compatible = "st,spear600-gmac";
> >>>> +                       snps,phy-addr =<0xffffffff>;
> >>>
> >>>
> >>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> >>> manufacturer is 'st' as the compatible suggest
> >>
> >>
> >> Hi Rajeev Kumar,
> >>
> >> According to the Documentation, it guides to use 'snps' prefix.
> >>
> >> In my humble opinion,
> >> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST
> >> specific, 'snps' prefix can be used.
> >>
> >
> >
> > Very much true, I raise the point just becuase compatible =
> > "st,spear600-gmac". Check the manufacturer name here.
> 
> As documented, "st,spear600-gmac" is there for backwards compatibility. It
> should really be updated to '"snps,dwmac-<version>", "snps,dwmac"'.
> 
> 
> 
> 
> >> ./Documentation/devicetree/bindings/net/stmmac.txt
> >> - snps,phy-addr         phy address to connect to.
> 
> About the "snps,phy-addr" property, Florian recently raised the issue that
> this is !standard. I am currently implementing proper DT ethernet phy node
> support for stmmac. Just a heads up. :)
> 
- Any comment on this?

Regards
Mohit

[PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit KUMAR DCG]

Hello Shiraz/Viresh,

> -----Original Message-----
> From: wens213 at gmail.com [mailto:wens213 at gmail.com] On Behalf Of
> Chen-Yu Tsai
> Sent: Thursday, December 12, 2013 9:37 AM
> To: Rajeev KUMAR
> Cc: Jingoo Han; Pratyush ANAND; devicetree at vger.kernel.org; Mohit
> KUMAR DCG; spear-devel; Viresh Kumar; linux-pci at vger.kernel.org; linux-
> arm-kernel at lists.infradead.org; Florian Fainelli
> Subject: Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-
> addr
> 
> Hi,
> 
> On Thu, Dec 12, 2013 at 11:59 AM, Rajeev kumar <rajeev-
> dlh.kumar at st.com> wrote:
> > On 12/12/2013 6:09 AM, Jingoo Han wrote:
> >>
> >> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
> >>>
> >>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> >>>>
> >>>> DT field name for the phy address changed since kernel 3.10. Set
> >>>> the snps,phy-addr to 0xffffffff so that the driver probes for the phy.
> >>>>
> >>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> >>>> Cc: Pratyush Anand<pratyush.anand@st.com>
> >>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
> >>>> Cc: spear-devel at list.st.com
> >>>> Cc: linux-arm-kernel at lists.infradead.org
> >>>> Cc: devicetree at vger.kernel.org
> >>>> ---
> >>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
> >>>>    1 files changed, 1 insertions(+), 0 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> index 4382547..3518803 100644
> >>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> @@ -155,6 +155,7 @@
> >>>>
> >>>>                 gmac0: eth at e2000000 {
> >>>>                         compatible = "st,spear600-gmac";
> >>>> +                       snps,phy-addr =<0xffffffff>;
> >>>
> >>>
> >>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> >>> manufacturer is 'st' as the compatible suggest
> >>
> >>
> >> Hi Rajeev Kumar,
> >>
> >> According to the Documentation, it guides to use 'snps' prefix.
> >>
> >> In my humble opinion,
> >> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST
> >> specific, 'snps' prefix can be used.
> >>
> >
> >
> > Very much true, I raise the point just becuase compatible =
> > "st,spear600-gmac". Check the manufacturer name here.
> 
> As documented, "st,spear600-gmac" is there for backwards compatibility. It
> should really be updated to '"snps,dwmac-<version>", "snps,dwmac"'.
> 
> 
> 
> 
> >> ./Documentation/devicetree/bindings/net/stmmac.txt
> >> - snps,phy-addr         phy address to connect to.
> 
> About the "snps,phy-addr" property, Florian recently raised the issue that
> this is !standard. I am currently implementing proper DT ethernet phy node
> support for stmmac. Just a heads up. :)
> 
- Any comment on this?

Regards
Mohit

RE: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-addr

[Mohit KUMAR DCG]

Hello Shiraz/Viresh,

> -----Original Message-----
> From: wens213@gmail.com [mailto:wens213@gmail.com] On Behalf Of
> Chen-Yu Tsai
> Sent: Thursday, December 12, 2013 9:37 AM
> To: Rajeev KUMAR
> Cc: Jingoo Han; Pratyush ANAND; devicetree@vger.kernel.org; Mohit
> KUMAR DCG; spear-devel; Viresh Kumar; linux-pci@vger.kernel.org; linux-
> arm-kernel@lists.infradead.org; Florian Fainelli
> Subject: Re: [PATCH 01/12] SPEAr13xx: Correct dt field name for stmmac phy-
> addr
> 
> Hi,
> 
> On Thu, Dec 12, 2013 at 11:59 AM, Rajeev kumar <rajeev-
> dlh.kumar@st.com> wrote:
> > On 12/12/2013 6:09 AM, Jingoo Han wrote:
> >>
> >> On Wednesday, December 11, 2013 8:09 PM, Rajeev kumar wrote:
> >>>
> >>> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> >>>>
> >>>> DT field name for the phy address changed since kernel 3.10. Set
> >>>> the snps,phy-addr to 0xffffffff so that the driver probes for the phy.
> >>>>
> >>>> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> >>>> Cc: Pratyush Anand<pratyush.anand@st.com>
> >>>> Cc: Viresh Kumar<viresh.linux@gmail.com>
> >>>> Cc: spear-devel@list.st.com
> >>>> Cc: linux-arm-kernel@lists.infradead.org
> >>>> Cc: devicetree@vger.kernel.org
> >>>> ---
> >>>>    arch/arm/boot/dts/spear13xx.dtsi |    1 +
> >>>>    1 files changed, 1 insertions(+), 0 deletions(-)
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> index 4382547..3518803 100644
> >>>> --- a/arch/arm/boot/dts/spear13xx.dtsi
> >>>> +++ b/arch/arm/boot/dts/spear13xx.dtsi
> >>>> @@ -155,6 +155,7 @@
> >>>>
> >>>>                 gmac0: eth@e2000000 {
> >>>>                         compatible = "st,spear600-gmac";
> >>>> +                       snps,phy-addr =<0xffffffff>;
> >>>
> >>>
> >>> Don't you think it should be st,phy-addr =<0xffffffff>, as the
> >>> manufacturer is 'st' as the compatible suggest
> >>
> >>
> >> Hi Rajeev Kumar,
> >>
> >> According to the Documentation, it guides to use 'snps' prefix.
> >>
> >> In my humble opinion,
> >> 'gmac' is a Synopsys based IP. Thus, if 'snps,phy-addr' is not ST
> >> specific, 'snps' prefix can be used.
> >>
> >
> >
> > Very much true, I raise the point just becuase compatible =
> > "st,spear600-gmac". Check the manufacturer name here.
> 
> As documented, "st,spear600-gmac" is there for backwards compatibility. It
> should really be updated to '"snps,dwmac-<version>", "snps,dwmac"'.
> 
> 
> 
> 
> >> ./Documentation/devicetree/bindings/net/stmmac.txt
> >> - snps,phy-addr         phy address to connect to.
> 
> About the "snps,phy-addr" property, Florian recently raised the issue that
> this is !standard. I am currently implementing proper DT ethernet phy node
> support for stmmac. Just a heads up. :)
> 
- Any comment on this?

Regards
Mohit

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Move SPEAr1340 definitions to header files so that theese can be used by
other code too.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |   55 ++++++++++++++++++++++++++++++
 arch/arm/mach-spear/spear1340.c          |   54 -----------------------------
 2 files changed, 55 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..4526f75 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -86,6 +86,61 @@
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE			UART_BASE
 
+/* PCIe/SATA Base addresses */
+#define SPEAR1340_SATA_BASE			UL(0xB1000000)
+#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
+
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
+#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
+#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
+
+#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
+#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
+#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+
 #endif /* SPEAR13XX */
 
 #endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..1b47609 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -22,60 +22,6 @@
 #include <mach/spear.h>
 
 /* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
 /* SATA device registration */
 static int sata_miphy_init(struct device *dev, void __iomem *addr)
 {
-- 
1.7.0.1

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Move SPEAr1340 definitions to header files so that theese can be used by
other code too.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |   55 ++++++++++++++++++++++++++++++
 arch/arm/mach-spear/spear1340.c          |   54 -----------------------------
 2 files changed, 55 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 5cdc53d..4526f75 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -86,6 +86,61 @@
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE			UART_BASE
 
+/* PCIe/SATA Base addresses */
+#define SPEAR1340_SATA_BASE			UL(0xB1000000)
+#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
+
+/* Power Management Registers */
+#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
+#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
+#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
+
+#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
+#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
+#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
+
+/* PCIE - SATA configuration registers */
+#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
+	/* PCIE CFG MASks */
+	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
+	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
+	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
+	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
+	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
+	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
+	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
+			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
+			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
+			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
+			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
+	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
+			SPEAR1340_SATA_CFG_PM_CLK_EN | \
+			SPEAR1340_SATA_CFG_POWERUP_RESET | \
+			SPEAR1340_SATA_CFG_RX_CLK_EN | \
+			SPEAR1340_SATA_CFG_TX_CLK_EN)
+
+#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
+	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
+	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
+	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
+	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
+			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
+
+
 #endif /* SPEAR13XX */
 
 #endif /* __MACH_SPEAR_H */
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c
index 3fb6834..1b47609 100644
--- a/arch/arm/mach-spear/spear1340.c
+++ b/arch/arm/mach-spear/spear1340.c
@@ -22,60 +22,6 @@
 #include <mach/spear.h>
 
 /* FIXME: Move SATA PHY code into a standalone driver */
-
-/* Base addresses */
-#define SPEAR1340_SATA_BASE			UL(0xB1000000)
-
-/* Power Management Registers */
-#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
-#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
-#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
-
-#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
-#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
-#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)
-
-/* PCIE - SATA configuration registers */
-#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
-	/* PCIE CFG MASks */
-	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
-	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
-	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
-	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
-	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
-	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
-	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)
-	#define SPEAR1340_SATA_CFG_PM_CLK_EN		(1 << 1)
-	#define SPEAR1340_PCIE_SATA_SEL_PCIE		(0)
-	#define SPEAR1340_PCIE_SATA_SEL_SATA		(1)
-	#define SPEAR1340_SATA_PCIE_CFG_MASK		0xF1F
-	#define SPEAR1340_PCIE_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_PCIE | \
-			SPEAR1340_PCIE_CFG_AUX_CLK_EN | \
-			SPEAR1340_PCIE_CFG_CORE_CLK_EN | \
-			SPEAR1340_PCIE_CFG_POWERUP_RESET | \
-			SPEAR1340_PCIE_CFG_DEVICE_PRESENT)
-	#define SPEAR1340_SATA_CFG_VAL	(SPEAR1340_PCIE_SATA_SEL_SATA | \
-			SPEAR1340_SATA_CFG_PM_CLK_EN | \
-			SPEAR1340_SATA_CFG_POWERUP_RESET | \
-			SPEAR1340_SATA_CFG_RX_CLK_EN | \
-			SPEAR1340_SATA_CFG_TX_CLK_EN)
-
-#define SPEAR1340_PCIE_MIPHY_CFG		(VA_MISC_BASE + 0x428)
-	#define SPEAR1340_MIPHY_OSC_BYPASS_EXT		(1 << 31)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV2		(1 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV4		(2 << 27)
-	#define SPEAR1340_MIPHY_CLK_REF_DIV8		(3 << 27)
-	#define SPEAR1340_MIPHY_PLL_RATIO_TOP(x)	(x << 0)
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_CLK_REF_DIV2 | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(60))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
-			(SPEAR1340_MIPHY_PLL_RATIO_TOP(120))
-	#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \
-			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
-			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
-
 /* SATA device registration */
 static int sata_miphy_init(struct device *dev, void __iomem *addr)
 {
-- 
1.7.0.1

Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> Move SPEAr1340 definitions to header files so that theese can be used by
> other code too.

This looks like a regression, we intentionally made them private and they
should be moved into a proper driver instead of being globally visible.

> diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
> index 5cdc53d..4526f75 100644
> --- a/arch/arm/mach-spear/include/mach/spear.h
> +++ b/arch/arm/mach-spear/include/mach/spear.h
> @@ -86,6 +86,61 @@
>  /* Debug uart for linux, will be used for debug and uncompress messages */
>  #define SPEAR_DBG_UART_BASE			UART_BASE
>  
> +/* PCIe/SATA Base addresses */
> +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)

These should be in DT only.

> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
> +#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
> +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
> +
> +#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
> +#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
> +#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)

The RST bits should probably go into a drivers/reset driver. Not sure what the
other registers do, but I'm sure we can find a driver for these too, possibly
they should be part of the PHY driver?

> @@ -22,60 +22,6 @@
>  #include <mach/spear.h>
>  
>  /* FIXME: Move SATA PHY code into a standalone driver */
> -
> -
> -/* PCIE - SATA configuration registers */
> -#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
> -	/* PCIE CFG MASks */
> -	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> -	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> -	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> -	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> -	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> -	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> -	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)

You leave the FIXME in place but move away the definitions it talks about.
Please fix the problem instead.

	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> Move SPEAr1340 definitions to header files so that theese can be used by
> other code too.

This looks like a regression, we intentionally made them private and they
should be moved into a proper driver instead of being globally visible.

> diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
> index 5cdc53d..4526f75 100644
> --- a/arch/arm/mach-spear/include/mach/spear.h
> +++ b/arch/arm/mach-spear/include/mach/spear.h
> @@ -86,6 +86,61 @@
>  /* Debug uart for linux, will be used for debug and uncompress messages */
>  #define SPEAR_DBG_UART_BASE			UART_BASE
>  
> +/* PCIe/SATA Base addresses */
> +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)

These should be in DT only.

> +/* Power Management Registers */
> +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE + 0x100)
> +#define SPEAR1340_PCM_WKUP_CFG			(VA_MISC_BASE + 0x104)
> +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE + 0x108)
> +
> +#define SPEAR1340_PERIP1_SW_RST			(VA_MISC_BASE + 0x318)
> +#define SPEAR1340_PERIP2_SW_RST			(VA_MISC_BASE + 0x31C)
> +#define SPEAR1340_PERIP3_SW_RST			(VA_MISC_BASE + 0x320)

The RST bits should probably go into a drivers/reset driver. Not sure what the
other registers do, but I'm sure we can find a driver for these too, possibly
they should be part of the PHY driver?

> @@ -22,60 +22,6 @@
>  #include <mach/spear.h>
>  
>  /* FIXME: Move SATA PHY code into a standalone driver */
> -
> -
> -/* PCIE - SATA configuration registers */
> -#define SPEAR1340_PCIE_SATA_CFG			(VA_MISC_BASE + 0x424)
> -	/* PCIE CFG MASks */
> -	#define SPEAR1340_PCIE_CFG_DEVICE_PRESENT	(1 << 11)
> -	#define SPEAR1340_PCIE_CFG_POWERUP_RESET	(1 << 10)
> -	#define SPEAR1340_PCIE_CFG_CORE_CLK_EN		(1 << 9)
> -	#define SPEAR1340_PCIE_CFG_AUX_CLK_EN		(1 << 8)
> -	#define SPEAR1340_SATA_CFG_TX_CLK_EN		(1 << 4)
> -	#define SPEAR1340_SATA_CFG_RX_CLK_EN		(1 << 3)
> -	#define SPEAR1340_SATA_CFG_POWERUP_RESET	(1 << 2)

You leave the FIXME in place but move away the definitions it talks about.
Please fix the problem instead.

	Arnd

RE: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Thursday, December 12, 2013 4:18 AM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci@vger.kernel.org; Pratyush ANAND; spear-
> devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move SPEAr1340 definitions to header files so that theese can be used
> > by other code too.
> 
> This looks like a regression, we intentionally made them private and they
> should be moved into a proper driver instead of being globally visible.
> 
> > diff --git a/arch/arm/mach-spear/include/mach/spear.h
> > b/arch/arm/mach-spear/include/mach/spear.h
> > index 5cdc53d..4526f75 100644
> > --- a/arch/arm/mach-spear/include/mach/spear.h
> > +++ b/arch/arm/mach-spear/include/mach/spear.h
> > @@ -86,6 +86,61 @@
> >  /* Debug uart for linux, will be used for debug and uncompress messages
> */
> >  #define SPEAR_DBG_UART_BASE			UART_BASE
> >
> > +/* PCIe/SATA Base addresses */
> > +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> > +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
> 
> These should be in DT only.
> 
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE +
> 0x100)
> > +#define SPEAR1340_PCM_WKUP_CFG
> 	(VA_MISC_BASE + 0x104)
> > +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE +
> 0x108)
> > +
> > +#define SPEAR1340_PERIP1_SW_RST
> 	(VA_MISC_BASE + 0x318)
> > +#define SPEAR1340_PERIP2_SW_RST
> 	(VA_MISC_BASE + 0x31C)
> > +#define SPEAR1340_PERIP3_SW_RST
> 	(VA_MISC_BASE + 0x320)
> 	
> The RST bits should probably go into a drivers/reset driver. Not sure what the
> other registers do, but I'm sure we can find a driver for these too, possibly
> they should be part of the PHY driver?

-  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 

Regards
Mohit

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, December 12, 2013 4:18 AM
> To: linux-arm-kernel at lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; spear-
> devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move SPEAr1340 definitions to header files so that theese can be used
> > by other code too.
> 
> This looks like a regression, we intentionally made them private and they
> should be moved into a proper driver instead of being globally visible.
> 
> > diff --git a/arch/arm/mach-spear/include/mach/spear.h
> > b/arch/arm/mach-spear/include/mach/spear.h
> > index 5cdc53d..4526f75 100644
> > --- a/arch/arm/mach-spear/include/mach/spear.h
> > +++ b/arch/arm/mach-spear/include/mach/spear.h
> > @@ -86,6 +86,61 @@
> >  /* Debug uart for linux, will be used for debug and uncompress messages
> */
> >  #define SPEAR_DBG_UART_BASE			UART_BASE
> >
> > +/* PCIe/SATA Base addresses */
> > +#define SPEAR1340_SATA_BASE			UL(0xB1000000)
> > +#define SPEAR1340_PCIE_BASE			UL(0xB1000000)
> 
> These should be in DT only.
> 
> > +/* Power Management Registers */
> > +#define SPEAR1340_PCM_CFG			(VA_MISC_BASE +
> 0x100)
> > +#define SPEAR1340_PCM_WKUP_CFG
> 	(VA_MISC_BASE + 0x104)
> > +#define SPEAR1340_SWITCH_CTR			(VA_MISC_BASE +
> 0x108)
> > +
> > +#define SPEAR1340_PERIP1_SW_RST
> 	(VA_MISC_BASE + 0x318)
> > +#define SPEAR1340_PERIP2_SW_RST
> 	(VA_MISC_BASE + 0x31C)
> > +#define SPEAR1340_PERIP3_SW_RST
> 	(VA_MISC_BASE + 0x320)
> 	
> The RST bits should probably go into a drivers/reset driver. Not sure what the
> other registers do, but I'm sure we can find a driver for these too, possibly
> they should be part of the PHY driver?

-  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 

Regards
Mohit

Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > The RST bits should probably go into a drivers/reset driver. Not sure what the
> > other registers do, but I'm sure we can find a driver for these too, possibly
> > they should be part of the PHY driver?
> 
> -  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
> it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 
> 

Ok, very good.

	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > The RST bits should probably go into a drivers/reset driver. Not sure what the
> > other registers do, but I'm sure we can find a driver for these too, possibly
> > they should be part of the PHY driver?
> 
> -  Perhaps if we implement phy and reset driver then we may not require to move these definitions and
> it will address most of your comments on SPEar13xx pcie driver. I am understanding and working on this.l 
> 

Ok, very good.

	Arnd

RE: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit KUMAR DCG]

Hi Arnd,


> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Sunday, December 15, 2013 12:33 AM
> To: Mohit KUMAR DCG
> Cc: linux-arm-kernel@lists.infradead.org; linux-pci@vger.kernel.org;
> Pratyush ANAND; spear-devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > The RST bits should probably go into a drivers/reset driver. Not
> > > sure what the other registers do, but I'm sure we can find a driver
> > > for these too, possibly they should be part of the PHY driver?
> >
> > -  Perhaps if we implement phy and reset driver then we may not
> > require to move these definitions and it will address most of your
> > comments on SPEar13xx pcie driver. I am understanding and working on
> > this.l
> >

Though we are almost ready with v2. But few concerns:

There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.

We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
The same driver.

Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
Or we keep this new driver in arch/arm/mach-spear only.

Regards
Mohit

> 
> Ok, very good.
> 
> 	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Mohit KUMAR DCG]

Hi Arnd,


> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Sunday, December 15, 2013 12:33 AM
> To: Mohit KUMAR DCG
> Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org;
> Pratyush ANAND; spear-devel; Viresh Kumar
> Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> header file
> 
> On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > The RST bits should probably go into a drivers/reset driver. Not
> > > sure what the other registers do, but I'm sure we can find a driver
> > > for these too, possibly they should be part of the PHY driver?
> >
> > -  Perhaps if we implement phy and reset driver then we may not
> > require to move these definitions and it will address most of your
> > comments on SPEar13xx pcie driver. I am understanding and working on
> > this.l
> >

Though we are almost ready with v2. But few concerns:

There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.

We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
Node this driver's probe is called, which further adds ahci platform driver.
We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
The same driver.

Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
Or we keep this new driver in arch/arm/mach-spear only.

Regards
Mohit

> 
> Ok, very good.
> 
> 	Arnd

Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Pratyush Anand]

On Thu, Jan 16, 2014 at 03:25:41PM +0800, Mohit KUMAR DCG wrote:
> Hi Arnd,
> 
> 
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd@arndb.de]
> > Sent: Sunday, December 15, 2013 12:33 AM
> > To: Mohit KUMAR DCG
> > Cc: linux-arm-kernel@lists.infradead.org; linux-pci@vger.kernel.org;
> > Pratyush ANAND; spear-devel; Viresh Kumar
> > Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> > header file
> > 
> > On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > > The RST bits should probably go into a drivers/reset driver. Not
> > > > sure what the other registers do, but I'm sure we can find a driver
> > > > for these too, possibly they should be part of the PHY driver?
> > >
> > > -  Perhaps if we implement phy and reset driver then we may not
> > > require to move these definitions and it will address most of your
> > > comments on SPEar13xx pcie driver. I am understanding and working on
> > > this.l
> > >
> 
> Though we are almost ready with v2. But few concerns:
> 
> There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> 
> We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> Node this driver's probe is called, which further adds ahci platform driver.
> We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> The same driver.
> 
> Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> Or we keep this new driver in arch/arm/mach-spear only.

I think this misc configuration register block resource should be
passed to syscon (drivers/mfd/syscon.c) driver.

regmap_update_bits should be used to update these registers and hence
to configure pcie/sata settings.

As far as place is concerned, that can be kept into mfd and can be
named as spear13xx-syscon.c

Whats your opinion arnd?

Regards
Pratyush

> 
> Regards
> Mohit
> 
> > 
> > Ok, very good.
> > 
> > 	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Pratyush Anand]

On Thu, Jan 16, 2014 at 03:25:41PM +0800, Mohit KUMAR DCG wrote:
> Hi Arnd,
> 
> 
> > -----Original Message-----
> > From: Arnd Bergmann [mailto:arnd at arndb.de]
> > Sent: Sunday, December 15, 2013 12:33 AM
> > To: Mohit KUMAR DCG
> > Cc: linux-arm-kernel at lists.infradead.org; linux-pci at vger.kernel.org;
> > Pratyush ANAND; spear-devel; Viresh Kumar
> > Subject: Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to
> > header file
> > 
> > On Friday 13 December 2013, Mohit KUMAR DCG wrote:
> > > > The RST bits should probably go into a drivers/reset driver. Not
> > > > sure what the other registers do, but I'm sure we can find a driver
> > > > for these too, possibly they should be part of the PHY driver?
> > >
> > > -  Perhaps if we implement phy and reset driver then we may not
> > > require to move these definitions and it will address most of your
> > > comments on SPEar13xx pcie driver. I am understanding and working on
> > > this.l
> > >
> 
> Though we are almost ready with v2. But few concerns:
> 
> There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> 
> We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> Node this driver's probe is called, which further adds ahci platform driver.
> We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> The same driver.
> 
> Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> Or we keep this new driver in arch/arm/mach-spear only.

I think this misc configuration register block resource should be
passed to syscon (drivers/mfd/syscon.c) driver.

regmap_update_bits should be used to update these registers and hence
to configure pcie/sata settings.

As far as place is concerned, that can be kept into mfd and can be
named as spear13xx-syscon.c

Whats your opinion arnd?

Regards
Pratyush

> 
> Regards
> Mohit
> 
> > 
> > Ok, very good.
> > 
> > 	Arnd

Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Thursday 16 January 2014, Pratyush Anand wrote:
> > Though we are almost ready with v2. But few concerns:
> > 
> > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > 
> > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > Node this driver's probe is called, which further adds ahci platform driver.
> > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > The same driver.
> > 
> > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > Or we keep this new driver in arch/arm/mach-spear only.
> 
> I think this misc configuration register block resource should be
> passed to syscon (drivers/mfd/syscon.c) driver.
> 
> regmap_update_bits should be used to update these registers and hence
> to configure pcie/sata settings.
> 
> As far as place is concerned, that can be kept into mfd and can be
> named as spear13xx-syscon.c
> 
> Whats your opinion arnd?

That sounds exactly like what I would have suggested, thanks!

One question remains, which is what driver should directly use 
syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
and which ones should use a higher-level abstraction from spear13xx-syscon.c.

We can decide this on a case-by-case basis, but in general I would suggest
to have drivers use syscon_regmap_lookup_by_phandle directly as long as
it doesn't cause significant code duplication between drivers.

	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Arnd Bergmann]

On Thursday 16 January 2014, Pratyush Anand wrote:
> > Though we are almost ready with v2. But few concerns:
> > 
> > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > 
> > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > Node this driver's probe is called, which further adds ahci platform driver.
> > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > The same driver.
> > 
> > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > Or we keep this new driver in arch/arm/mach-spear only.
> 
> I think this misc configuration register block resource should be
> passed to syscon (drivers/mfd/syscon.c) driver.
> 
> regmap_update_bits should be used to update these registers and hence
> to configure pcie/sata settings.
> 
> As far as place is concerned, that can be kept into mfd and can be
> named as spear13xx-syscon.c
> 
> Whats your opinion arnd?

That sounds exactly like what I would have suggested, thanks!

One question remains, which is what driver should directly use 
syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
and which ones should use a higher-level abstraction from spear13xx-syscon.c.

We can decide this on a case-by-case basis, but in general I would suggest
to have drivers use syscon_regmap_lookup_by_phandle directly as long as
it doesn't cause significant code duplication between drivers.

	Arnd

Re: [PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Pratyush Anand]

On Thu, Jan 16, 2014 at 07:33:40PM +0800, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Pratyush Anand wrote:
> > > Though we are almost ready with v2. But few concerns:
> > > 
> > > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > > 
> > > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > > Node this driver's probe is called, which further adds ahci platform driver.
> > > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > > The same driver.
> > > 
> > > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > > Or we keep this new driver in arch/arm/mach-spear only.
> > 
> > I think this misc configuration register block resource should be
> > passed to syscon (drivers/mfd/syscon.c) driver.
> > 
> > regmap_update_bits should be used to update these registers and hence
> > to configure pcie/sata settings.
> > 
> > As far as place is concerned, that can be kept into mfd and can be
> > named as spear13xx-syscon.c
> > 
> > Whats your opinion arnd?
> 
> That sounds exactly like what I would have suggested, thanks!
> 
> One question remains, which is what driver should directly use 
> syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
> and which ones should use a higher-level abstraction from spear13xx-syscon.c.
> 
> We can decide this on a case-by-case basis, but in general I would suggest
> to have drivers use syscon_regmap_lookup_by_phandle directly as long as
> it doesn't cause significant code duplication between drivers.

Yes, I think so.

Regards
Pratyush
> 
> 	Arnd

[PATCH 02/12] SPEAr13xx: Move SPEAr1340 definitions to header file

[Pratyush Anand]

On Thu, Jan 16, 2014 at 07:33:40PM +0800, Arnd Bergmann wrote:
> On Thursday 16 January 2014, Pratyush Anand wrote:
> > > Though we are almost ready with v2. But few concerns:
> > > 
> > > There are Spear soc common register used for misc configurations of clock, reset etc  for all ips.  Few of 
> > > registers from the same area are also used for pcie/sata muxing and auxiliary clock configurations.
> > > For example: sata_miphy_init in arch/arm/mach-spear/spear1340.c also uses these registers.
> > > 
> > > We have moved all these sata specific spear1340 configurations in a separate driver.  On the basis of spear-ahci dt 
> > > Node this driver's probe is called, which further adds ahci platform driver.
> > > We plan to put all spear1340/1310_pcie_miphy_init/exit functions of patch 9/12 of this series in
> > > The same driver.
> > > 
> > > Now our concern is, what could be the best place to keep that driver, phy, reset or any other framework?
> > > Or we keep this new driver in arch/arm/mach-spear only.
> > 
> > I think this misc configuration register block resource should be
> > passed to syscon (drivers/mfd/syscon.c) driver.
> > 
> > regmap_update_bits should be used to update these registers and hence
> > to configure pcie/sata settings.
> > 
> > As far as place is concerned, that can be kept into mfd and can be
> > named as spear13xx-syscon.c
> > 
> > Whats your opinion arnd?
> 
> That sounds exactly like what I would have suggested, thanks!
> 
> One question remains, which is what driver should directly use 
> syscon_regmap_lookup_by_phandle() to get the syscon registers themselves,
> and which ones should use a higher-level abstraction from spear13xx-syscon.c.
> 
> We can decide this on a case-by-case basis, but in general I would suggest
> to have drivers use syscon_regmap_lookup_by_phandle directly as long as
> it doesn't cause significant code duplication between drivers.

Yes, I think so.

Regards
Pratyush
> 
> 	Arnd

[PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Add SPEAr1310 Misc register definitions for PCIe.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |   73 ++++++++++++++++++++++++++++++
 1 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 4526f75..c236cef 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -140,6 +140,79 @@
 			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
 			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
 
+#define VA_SPEAR1310_PCIE_SATA_CFG		(VA_MISC_BASE + 0x3A4)
+	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
+	#define SPEAR1310_PCIE_SATA2_SEL_SATA		(1 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_SATA		(1 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_SATA		(1 << 29)
+	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		(1 << 27)
+	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		(1 << 26)
+	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	(1 << 25)
+	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		(1 << 24)
+	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		(1 << 23)
+	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		(1 << 22)
+	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	(1 << 21)
+	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		(1 << 20)
+	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		(1 << 19)
+	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		(1 << 18)
+	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	(1 << 17)
+	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		(1 << 16)
+	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	(1 << 7)
+	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	(1 << 6)
+	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		(1 << 5)
+	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		(1 << 4)
+	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	(1 << 3)
+	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		(1 << 1)
+	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		(1 << 0)
+
+	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+			(1 << (x + 29)))
+	#define SPEAR1310_PCIE_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+	#define SPEAR1310_SATA_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define VA_SPEAR1310_PCIE_MIPHY_CFG_1		(VA_MISC_BASE + 0x3A8)
+	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	(1 << 31)
+	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	(1 << 28)
+	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
+	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	(1 << 15)
+	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	(1 << 12)
+	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define VA_SPEAR1310_PCIE_MIPHY_CFG_2		(VA_MISC_BASE + 0x3AC)
 
 #endif /* SPEAR13XX */
 
-- 
1.7.0.1

[PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Add SPEAr1310 Misc register definitions for PCIe.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |   73 ++++++++++++++++++++++++++++++
 1 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index 4526f75..c236cef 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -140,6 +140,79 @@
 			(SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
 			SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
 
+#define VA_SPEAR1310_PCIE_SATA_CFG		(VA_MISC_BASE + 0x3A4)
+	#define SPEAR1310_PCIE_SATA2_SEL_PCIE		(0 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_PCIE		(0 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_PCIE		(0 << 29)
+	#define SPEAR1310_PCIE_SATA2_SEL_SATA		(1 << 31)
+	#define SPEAR1310_PCIE_SATA1_SEL_SATA		(1 << 30)
+	#define SPEAR1310_PCIE_SATA0_SEL_SATA		(1 << 29)
+	#define SPEAR1310_SATA2_CFG_TX_CLK_EN		(1 << 27)
+	#define SPEAR1310_SATA2_CFG_RX_CLK_EN		(1 << 26)
+	#define SPEAR1310_SATA2_CFG_POWERUP_RESET	(1 << 25)
+	#define SPEAR1310_SATA2_CFG_PM_CLK_EN		(1 << 24)
+	#define SPEAR1310_SATA1_CFG_TX_CLK_EN		(1 << 23)
+	#define SPEAR1310_SATA1_CFG_RX_CLK_EN		(1 << 22)
+	#define SPEAR1310_SATA1_CFG_POWERUP_RESET	(1 << 21)
+	#define SPEAR1310_SATA1_CFG_PM_CLK_EN		(1 << 20)
+	#define SPEAR1310_SATA0_CFG_TX_CLK_EN		(1 << 19)
+	#define SPEAR1310_SATA0_CFG_RX_CLK_EN		(1 << 18)
+	#define SPEAR1310_SATA0_CFG_POWERUP_RESET	(1 << 17)
+	#define SPEAR1310_SATA0_CFG_PM_CLK_EN		(1 << 16)
+	#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT	(1 << 11)
+	#define SPEAR1310_PCIE2_CFG_POWERUP_RESET	(1 << 10)
+	#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN		(1 << 9)
+	#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN		(1 << 8)
+	#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT	(1 << 7)
+	#define SPEAR1310_PCIE1_CFG_POWERUP_RESET	(1 << 6)
+	#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN		(1 << 5)
+	#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN		(1 << 4)
+	#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT	(1 << 3)
+	#define SPEAR1310_PCIE0_CFG_POWERUP_RESET	(1 << 2)
+	#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN		(1 << 1)
+	#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN		(1 << 0)
+
+	#define SPEAR1310_PCIE_CFG_MASK(x) ((0xF << (x * 4)) | (1 << (x + 29)))
+	#define SPEAR1310_SATA_CFG_MASK(x) ((0xF << (x * 4 + 16)) | \
+			(1 << (x + 29)))
+	#define SPEAR1310_PCIE_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \
+			SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \
+			SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT)
+	#define SPEAR1310_SATA_CFG_VAL(x) \
+			(SPEAR1310_PCIE_SATA##x##_SEL_SATA | \
+			SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \
+			SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \
+			SPEAR1310_SATA##x##_CFG_TX_CLK_EN)
+
+#define VA_SPEAR1310_PCIE_MIPHY_CFG_1		(VA_MISC_BASE + 0x3A8)
+	#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT	(1 << 31)
+	#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2	(1 << 28)
+	#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(x)	(x << 16)
+	#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT	(1 << 15)
+	#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2	(1 << 12)
+	#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(x)	(x << 0)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16)
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \
+			(SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120))
+	#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \
+			(SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \
+			SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \
+			SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25))
+
+#define VA_SPEAR1310_PCIE_MIPHY_CFG_2		(VA_MISC_BASE + 0x3AC)
 
 #endif /* SPEAR13XX */
 
-- 
1.7.0.1

Re: [PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
> index 4526f75..c236cef 100644
> --- a/arch/arm/mach-spear/include/mach/spear.h
> +++ b/arch/arm/mach-spear/include/mach/spear.h
> @@ -140,6 +140,79 @@
>                         (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>                         SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>  
> +#define VA_SPEAR1310_PCIE_SATA_CFG             (VA_MISC_BASE + 0x3A4)
> +       #define SPEAR1310_PCIE_SATA2_SEL_PCIE           (0 << 31)
> +       #define SPEAR1310_PCIE_SATA1_SEL_PCIE           (0 << 30)
> +       #define SPEAR1310_PCIE_SATA0_SEL_PCIE           (0 << 29)
> +       #define SPEAR1310_PCIE_SATA2_SEL_SATA           (1 << 31)
> +       #define SPEAR1310_PCIE_SATA1_SEL_SATA           (1 << 30)
> +       #define SPEAR1310_PCIE_SATA0_SEL_SATA           (1 << 29)

These should definitely be part of the PHY driver.

Regarding style, don't use a hardcoded VA_MISC_BASE constant here,
but find the right address in the driver, and instead of shifting
bits, just use hexadecimal notation:

#define SPEAR1310_PCIE_SATA2_SEL_PCIE           0x80000000
#define SPEAR1310_PCIE_SATA1_SEL_PCIE           0x40000000
...

However, if you have a "reset" driver, you can use #reset-cells=<1>
and pass the bit as the reset specifier.

	Arnd

[PATCH 03/12] SPEAr13xx: Add SPEAr1310 PCIe register definitions

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
> index 4526f75..c236cef 100644
> --- a/arch/arm/mach-spear/include/mach/spear.h
> +++ b/arch/arm/mach-spear/include/mach/spear.h
> @@ -140,6 +140,79 @@
>                         (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \
>                         SPEAR1340_MIPHY_PLL_RATIO_TOP(25))
>  
> +#define VA_SPEAR1310_PCIE_SATA_CFG             (VA_MISC_BASE + 0x3A4)
> +       #define SPEAR1310_PCIE_SATA2_SEL_PCIE           (0 << 31)
> +       #define SPEAR1310_PCIE_SATA1_SEL_PCIE           (0 << 30)
> +       #define SPEAR1310_PCIE_SATA0_SEL_PCIE           (0 << 29)
> +       #define SPEAR1310_PCIE_SATA2_SEL_SATA           (1 << 31)
> +       #define SPEAR1310_PCIE_SATA1_SEL_SATA           (1 << 30)
> +       #define SPEAR1310_PCIE_SATA0_SEL_SATA           (1 << 29)

These should definitely be part of the PHY driver.

Regarding style, don't use a hardcoded VA_MISC_BASE constant here,
but find the right address in the driver, and instead of shifting
bits, just use hexadecimal notation:

#define SPEAR1310_PCIE_SATA2_SEL_PCIE           0x80000000
#define SPEAR1310_PCIE_SATA1_SEL_PCIE           0x40000000
...

However, if you have a "reset" driver, you can use #reset-cells=<1>
and pass the bit as the reset specifier.

	Arnd

[PATCH 04/12] SPEAr13xx: Fix static mapping table

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |    4 ++--
 arch/arm/mach-spear/spear13xx.c          |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index c236cef..e7ba122 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
 #ifdef CONFIG_ARCH_SPEAR13XX
 
 #define PERIP_GRP2_BASE				UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE			IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE			IOMEM(0xF9000000)
 #define MCIF_SDHCI_BASE				UL(0xB3000000)
 #define SYSRAM0_BASE				UL(0xB3800000)
-#define VA_SYSRAM0_BASE				IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE				IOMEM(0xF9800000)
 #define SYS_LOCATION				(VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE				UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..20ce885 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)
 /*
  * Following will create 16MB static virtual/physical mappings
  * PHYSICAL		VIRTUAL
- * 0xB3000000		0xFE000000
  * 0xE0000000		0xFD000000
  * 0xEC000000		0xFC000000
  * 0xED000000		0xFB000000
+ * 0xB3000000		0xF9000000
  */
 struct map_desc spear13xx_io_desc[] __initdata = {
 	{
-- 
1.7.0.1

[PATCH 04/12] SPEAr13xx: Fix static mapping table

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

SPEAr13xx was using virtual address space 0xFE000000 to map physical address
space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So
change 0xFE000000 to 0xF9000000.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-spear/include/mach/spear.h |    4 ++--
 arch/arm/mach-spear/spear13xx.c          |    2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-spear/include/mach/spear.h b/arch/arm/mach-spear/include/mach/spear.h
index c236cef..e7ba122 100644
--- a/arch/arm/mach-spear/include/mach/spear.h
+++ b/arch/arm/mach-spear/include/mach/spear.h
@@ -52,10 +52,10 @@
 #ifdef CONFIG_ARCH_SPEAR13XX
 
 #define PERIP_GRP2_BASE				UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE			IOMEM(0xFE000000)
+#define VA_PERIP_GRP2_BASE			IOMEM(0xF9000000)
 #define MCIF_SDHCI_BASE				UL(0xB3000000)
 #define SYSRAM0_BASE				UL(0xB3800000)
-#define VA_SYSRAM0_BASE				IOMEM(0xFE800000)
+#define VA_SYSRAM0_BASE				IOMEM(0xF9800000)
 #define SYS_LOCATION				(VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE				UL(0xE0000000)
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8c..20ce885 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -52,10 +52,10 @@ void __init spear13xx_l2x0_init(void)
 /*
  * Following will create 16MB static virtual/physical mappings
  * PHYSICAL		VIRTUAL
- * 0xB3000000		0xFE000000
  * 0xE0000000		0xFD000000
  * 0xEC000000		0xFC000000
  * 0xED000000		0xFB000000
+ * 0xB3000000		0xF9000000
  */
 struct map_desc spear13xx_io_desc[] __initdata = {
 	{
-- 
1.7.0.1

[PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Follow dt clock naming convention for PCIe clocks.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 drivers/clk/spear/spear1310_clock.c |    6 +++---
 drivers/clk/spear/spear1340_clock.c |    2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.0");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.1");
+	clk_register_clkdev(clk, NULL, "b1800000.pcie");
 	clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.2");
+	clk_register_clkdev(clk, NULL, "b4000000.pcie");
 	clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
-- 
1.7.0.1

[PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Follow dt clock naming convention for PCIe clocks.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/clk/spear/spear1310_clock.c |    6 +++---
 drivers/clk/spear/spear1340_clock.c |    2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 65894f7..4daa597 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
 	clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.0");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.1");
+	clk_register_clkdev(clk, NULL, "b1800000.pcie");
 	clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie.2");
+	clk_register_clkdev(clk, NULL, "b4000000.pcie");
 	clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index fe835c1..5a5c664 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
 	clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
 			0, &_lock);
-	clk_register_clkdev(clk, NULL, "dw_pcie");
+	clk_register_clkdev(clk, NULL, "b1000000.pcie");
 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
-- 
1.7.0.1

Re: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> Follow dt clock naming convention for PCIe clocks.
> 

I think in the future, the spear clocks really need to get
moved into DT representations, as we do for other platforms,
which will get rid of a lot of code in drivers/clk, including
all the clkdev registration.

	Arnd

[PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> Follow dt clock naming convention for PCIe clocks.
> 

I think in the future, the spear clocks really need to get
moved into DT representations, as we do for other platforms,
which will get rid of a lot of code in drivers/clk, including
all the clkdev registration.

	Arnd

RE: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Thursday, December 12, 2013 4:13 AM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci@vger.kernel.org; Pratyush ANAND; spear-
> devel; Viresh Kumar
> Subject: Re: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Follow dt clock naming convention for PCIe clocks.
> >
> 
> I think in the future, the spear clocks really need to get moved into DT
> representations, as we do for other platforms, which will get rid of a lot of
> code in drivers/clk, including all the clkdev registration.
-  Let it be this way for now. May be we will improve it in next cycle.

Thanks
Mohit	

[PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, December 12, 2013 4:13 AM
> To: linux-arm-kernel at lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; spear-
> devel; Viresh Kumar
> Subject: Re: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Follow dt clock naming convention for PCIe clocks.
> >
> 
> I think in the future, the spear clocks really need to get moved into DT
> representations, as we do for other platforms, which will get rid of a lot of
> code in drivers/clk, including all the clkdev registration.
-  Let it be this way for now. May be we will improve it in next cycle.

Thanks
Mohit	

Re: [PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Arnd Bergmann]

On Thursday 12 December 2013, Mohit KUMAR DCG wrote:
> > 
> > I think in the future, the spear clocks really need to get moved into DT
> > representations, as we do for other platforms, which will get rid of a lot of
> > code in drivers/clk, including all the clkdev registration.
>
> -  Let it be this way for now. May be we will improve it in next cycle

Fair enough. This will be a major change that doesn't have to delay the PCIe
driver, just make sure you can address the other comments I made for now.

The clock situation will have to be worked out though before the bindings
can be considered stable, because you will have to add mandatory 'clocks'
properties to a lot of them.

	Arnd

[PATCH 05/12] clk: SPEAr13xx: Fix pcie clock name

[Arnd Bergmann]

On Thursday 12 December 2013, Mohit KUMAR DCG wrote:
> > 
> > I think in the future, the spear clocks really need to get moved into DT
> > representations, as we do for other platforms, which will get rid of a lot of
> > code in drivers/clk, including all the clkdev registration.
>
> -  Let it be this way for now. May be we will improve it in next cycle

Fair enough. This will be a major change that doesn't have to delay the PCIe
driver, just make sure you can address the other comments I made for now.

The clock situation will have to be worked out though before the bindings
can be considered stable, because you will have to add mandatory 'clocks'
properties to a lot of them.

	Arnd

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Move synopsis specific register definition from source file to header
file, so that they can be re-used by other files if needed.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |   42 ------------------------------------
 drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 212b8b6..73aa13c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -23,48 +23,6 @@
 
 #include "pcie-designware.h"
 
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL		0x710
-#define PORT_LINK_MODE_MASK		(0x3f << 16)
-#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
-#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
-#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
-
-#define PCIE_MSI_ADDR_LO		0x820
-#define PCIE_MSI_ADDR_HI		0x824
-#define PCIE_MSI_INTR0_ENABLE		0x828
-#define PCIE_MSI_INTR0_MASK		0x82C
-#define PCIE_MSI_INTR0_STATUS		0x830
-
-#define PCIE_ATU_VIEWPORT		0x900
-#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
-#define PCIE_ATU_CR1			0x904
-#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
-#define PCIE_ATU_TYPE_IO		(0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
-#define PCIE_ATU_CR2			0x908
-#define PCIE_ATU_ENABLE			(0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
-#define PCIE_ATU_LOWER_BASE		0x90C
-#define PCIE_ATU_UPPER_BASE		0x910
-#define PCIE_ATU_LIMIT			0x914
-#define PCIE_ATU_LOWER_TARGET		0x918
-#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET		0x91C
-
 static struct hw_pci dw_pci;
 
 static unsigned long global_io_offset;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_PORT_LINK_CONTROL		0x710
+#define PORT_LINK_MODE_MASK		(0x3f << 16)
+#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
+#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
+#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
+#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
+
+#define PCIE_MSI_ADDR_LO		0x820
+#define PCIE_MSI_ADDR_HI		0x824
+#define PCIE_MSI_INTR0_ENABLE		0x828
+#define PCIE_MSI_INTR0_MASK		0x82C
+#define PCIE_MSI_INTR0_STATUS		0x830
+
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
 #endif /* _PCIE_DESIGNWARE_H */
-- 
1.7.0.1

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

Move synopsis specific register definition from source file to header
file, so that they can be re-used by other files if needed.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel at list.st.com
Cc: linux-pci at vger.kernel.org
---
 drivers/pci/host/pcie-designware.c |   42 ------------------------------------
 drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 212b8b6..73aa13c 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -23,48 +23,6 @@
 
 #include "pcie-designware.h"
 
-/* Synopsis specific PCIE configuration registers */
-#define PCIE_PORT_LINK_CONTROL		0x710
-#define PORT_LINK_MODE_MASK		(0x3f << 16)
-#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
-#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
-#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
-
-#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
-#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
-#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
-#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
-#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
-
-#define PCIE_MSI_ADDR_LO		0x820
-#define PCIE_MSI_ADDR_HI		0x824
-#define PCIE_MSI_INTR0_ENABLE		0x828
-#define PCIE_MSI_INTR0_MASK		0x82C
-#define PCIE_MSI_INTR0_STATUS		0x830
-
-#define PCIE_ATU_VIEWPORT		0x900
-#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
-#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
-#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
-#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
-#define PCIE_ATU_CR1			0x904
-#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
-#define PCIE_ATU_TYPE_IO		(0x2 << 0)
-#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
-#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
-#define PCIE_ATU_CR2			0x908
-#define PCIE_ATU_ENABLE			(0x1 << 31)
-#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
-#define PCIE_ATU_LOWER_BASE		0x90C
-#define PCIE_ATU_UPPER_BASE		0x910
-#define PCIE_ATU_LIMIT			0x914
-#define PCIE_ATU_LOWER_TARGET		0x918
-#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
-#define PCIE_ATU_UPPER_TARGET		0x91C
-
 static struct hw_pci dw_pci;
 
 static unsigned long global_io_offset;
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index c15379b..da1ed35 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
 
+/* Synopsis specific PCIE configuration registers */
+#define PCIE_PORT_LINK_CONTROL		0x710
+#define PORT_LINK_MODE_MASK		(0x3f << 16)
+#define PORT_LINK_MODE_1_LANES		(0x1 << 16)
+#define PORT_LINK_MODE_2_LANES		(0x3 << 16)
+#define PORT_LINK_MODE_4_LANES		(0x7 << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
+#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK	(0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES	(0x4 << 8)
+
+#define PCIE_MSI_ADDR_LO		0x820
+#define PCIE_MSI_ADDR_HI		0x824
+#define PCIE_MSI_INTR0_ENABLE		0x828
+#define PCIE_MSI_INTR0_MASK		0x82C
+#define PCIE_MSI_INTR0_STATUS		0x830
+
+#define PCIE_ATU_VIEWPORT		0x900
+#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
+#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
+#define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
+#define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
+#define PCIE_ATU_CR1			0x904
+#define PCIE_ATU_TYPE_MEM		(0x0 << 0)
+#define PCIE_ATU_TYPE_IO		(0x2 << 0)
+#define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
+#define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
+#define PCIE_ATU_CR2			0x908
+#define PCIE_ATU_ENABLE			(0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
+#define PCIE_ATU_LOWER_BASE		0x90C
+#define PCIE_ATU_UPPER_BASE		0x910
+#define PCIE_ATU_LIMIT			0x914
+#define PCIE_ATU_LOWER_TARGET		0x918
+#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
+#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
+#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
+#define PCIE_ATU_UPPER_TARGET		0x91C
+
 #endif /* _PCIE_DESIGNWARE_H */
-- 
1.7.0.1

Re: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> Move synopsis specific register definition from source file to header
> file, so that they can be re-used by other files if needed.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>  drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 212b8b6..73aa13c 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -23,48 +23,6 @@
>
>  #include "pcie-designware.h"
>
> -/* Synopsis specific PCIE configuration registers */
> -#define PCIE_PORT_LINK_CONTROL         0x710
> -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> -
> -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> -
> -#define PCIE_MSI_ADDR_LO               0x820
> -#define PCIE_MSI_ADDR_HI               0x824
> -#define PCIE_MSI_INTR0_ENABLE          0x828
> -#define PCIE_MSI_INTR0_MASK            0x82C
> -#define PCIE_MSI_INTR0_STATUS          0x830
> -
> -#define PCIE_ATU_VIEWPORT              0x900
> -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> -#define PCIE_ATU_CR1                   0x904
> -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> -#define PCIE_ATU_CR2                   0x908
> -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> -#define PCIE_ATU_LOWER_BASE            0x90C
> -#define PCIE_ATU_UPPER_BASE            0x910
> -#define PCIE_ATU_LIMIT                 0x914
> -#define PCIE_ATU_LOWER_TARGET          0x918
> -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> -#define PCIE_ATU_UPPER_TARGET          0x91C
> -
>  static struct hw_pci dw_pci;
>
>  static unsigned long global_io_offset;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index c15379b..da1ed35 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);
>
> +/* Synopsis specific PCIE configuration registers */
> +#define PCIE_PORT_LINK_CONTROL         0x710
> +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> +
> +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> +
> +#define PCIE_MSI_ADDR_LO               0x820
> +#define PCIE_MSI_ADDR_HI               0x824
> +#define PCIE_MSI_INTR0_ENABLE          0x828
> +#define PCIE_MSI_INTR0_MASK            0x82C
> +#define PCIE_MSI_INTR0_STATUS          0x830
> +
> +#define PCIE_ATU_VIEWPORT              0x900
> +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> +#define PCIE_ATU_CR1                   0x904
> +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> +#define PCIE_ATU_CR2                   0x908
> +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> +#define PCIE_ATU_LOWER_BASE            0x90C
> +#define PCIE_ATU_UPPER_BASE            0x910
> +#define PCIE_ATU_LIMIT                 0x914
> +#define PCIE_ATU_LOWER_TARGET          0x918
> +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> +#define PCIE_ATU_UPPER_TARGET          0x91C
> +
>  #endif /* _PCIE_DESIGNWARE_H */

Seems like none were using these headers except pcie-designware.c - if
ie the case
better to place it same place as before.

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> Move synopsis specific register definition from source file to header
> file, so that they can be re-used by other files if needed.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel at list.st.com
> Cc: linux-pci at vger.kernel.org
> ---
>  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>  drivers/pci/host/pcie-designware.h |   42 ++++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 212b8b6..73aa13c 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -23,48 +23,6 @@
>
>  #include "pcie-designware.h"
>
> -/* Synopsis specific PCIE configuration registers */
> -#define PCIE_PORT_LINK_CONTROL         0x710
> -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> -
> -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> -#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> -
> -#define PCIE_MSI_ADDR_LO               0x820
> -#define PCIE_MSI_ADDR_HI               0x824
> -#define PCIE_MSI_INTR0_ENABLE          0x828
> -#define PCIE_MSI_INTR0_MASK            0x82C
> -#define PCIE_MSI_INTR0_STATUS          0x830
> -
> -#define PCIE_ATU_VIEWPORT              0x900
> -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> -#define PCIE_ATU_CR1                   0x904
> -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> -#define PCIE_ATU_CR2                   0x908
> -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> -#define PCIE_ATU_LOWER_BASE            0x90C
> -#define PCIE_ATU_UPPER_BASE            0x910
> -#define PCIE_ATU_LIMIT                 0x914
> -#define PCIE_ATU_LOWER_TARGET          0x918
> -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> -#define PCIE_ATU_UPPER_TARGET          0x91C
> -
>  static struct hw_pci dw_pci;
>
>  static unsigned long global_io_offset;
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index c15379b..da1ed35 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);
>  void dw_pcie_setup_rc(struct pcie_port *pp);
>  int dw_pcie_host_init(struct pcie_port *pp);
>
> +/* Synopsis specific PCIE configuration registers */
> +#define PCIE_PORT_LINK_CONTROL         0x710
> +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> +
> +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8)
> +#define PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> +
> +#define PCIE_MSI_ADDR_LO               0x820
> +#define PCIE_MSI_ADDR_HI               0x824
> +#define PCIE_MSI_INTR0_ENABLE          0x828
> +#define PCIE_MSI_INTR0_MASK            0x82C
> +#define PCIE_MSI_INTR0_STATUS          0x830
> +
> +#define PCIE_ATU_VIEWPORT              0x900
> +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> +#define PCIE_ATU_CR1                   0x904
> +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> +#define PCIE_ATU_CR2                   0x908
> +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> +#define PCIE_ATU_LOWER_BASE            0x90C
> +#define PCIE_ATU_UPPER_BASE            0x910
> +#define PCIE_ATU_LIMIT                 0x914
> +#define PCIE_ATU_LOWER_TARGET          0x918
> +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> +#define PCIE_ATU_UPPER_TARGET          0x91C
> +
>  #endif /* _PCIE_DESIGNWARE_H */

Seems like none were using these headers except pcie-designware.c - if
ie the case
better to place it same place as before.

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

RE: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit KUMAR DCG]

Hello Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]
> Sent: Wednesday, December 11, 2013 5:09 PM
> To: Mohit KUMAR DCG
> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> Pratyush ANAND; Jingoo Han; spear-devel
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
> wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move synopsis specific register definition from source file to header
> > file, so that they can be re-used by other files if needed.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
> > ---
> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
> >  drivers/pci/host/pcie-designware.h |   42
> ++++++++++++++++++++++++++++++++++++
> >  2 files changed, 42 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 212b8b6..73aa13c 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -23,48 +23,6 @@
> >
> >  #include "pcie-designware.h"
> >
> > -/* Synopsis specific PCIE configuration registers */
> > -#define PCIE_PORT_LINK_CONTROL         0x710
> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > -
> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > -
> > -#define PCIE_MSI_ADDR_LO               0x820
> > -#define PCIE_MSI_ADDR_HI               0x824
> > -#define PCIE_MSI_INTR0_ENABLE          0x828
> > -#define PCIE_MSI_INTR0_MASK            0x82C
> > -#define PCIE_MSI_INTR0_STATUS          0x830
> > -
> > -#define PCIE_ATU_VIEWPORT              0x900
> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > -#define PCIE_ATU_CR1                   0x904
> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > -#define PCIE_ATU_CR2                   0x908
> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > -#define PCIE_ATU_LOWER_BASE            0x90C
> > -#define PCIE_ATU_UPPER_BASE            0x910
> > -#define PCIE_ATU_LIMIT                 0x914
> > -#define PCIE_ATU_LOWER_TARGET          0x918
> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > -#define PCIE_ATU_UPPER_TARGET          0x91C
> > -
> >  static struct hw_pci dw_pci;
> >
> >  static unsigned long global_io_offset; diff --git
> > a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index c15379b..da1ed35 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
> > pcie_port *pp);
> >
> > +/* Synopsis specific PCIE configuration registers */
> > +#define PCIE_PORT_LINK_CONTROL         0x710
> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > +
> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > +
> > +#define PCIE_MSI_ADDR_LO               0x820
> > +#define PCIE_MSI_ADDR_HI               0x824
> > +#define PCIE_MSI_INTR0_ENABLE          0x828
> > +#define PCIE_MSI_INTR0_MASK            0x82C
> > +#define PCIE_MSI_INTR0_STATUS          0x830
> > +
> > +#define PCIE_ATU_VIEWPORT              0x900
> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > +#define PCIE_ATU_CR1                   0x904
> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > +#define PCIE_ATU_CR2                   0x908
> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > +#define PCIE_ATU_LOWER_BASE            0x90C
> > +#define PCIE_ATU_UPPER_BASE            0x910
> > +#define PCIE_ATU_LIMIT                 0x914
> > +#define PCIE_ATU_LOWER_TARGET          0x918
> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > +#define PCIE_ATU_UPPER_TARGET          0x91C
> > +
> >  #endif /* _PCIE_DESIGNWARE_H */
> 
> Seems like none were using these headers except pcie-designware.c - if ie
> the case better to place it same place as before.

- We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
so move these to the separate header  file.

Thanks
Mohit
> 
> --
> Thanks,
> Jagan.
> --------
> Jagannadha Sutradharudu Teki,
> E: jagannadh.teki@gmail.com, P: +91-9676773388 Engineer - System
> Software Hacker U-boot - SPI Custodian and Zynq APSOC
> Ln: http://www.linkedin.com/in/jaganteki

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit KUMAR DCG]

Hello Jagan,

> -----Original Message-----
> From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
> Sent: Wednesday, December 11, 2013 5:09 PM
> To: Mohit KUMAR DCG
> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Pratyush ANAND; Jingoo Han; spear-devel
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
> wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > Move synopsis specific register definition from source file to header
> > file, so that they can be re-used by other files if needed.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-pci at vger.kernel.org
> > ---
> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
> >  drivers/pci/host/pcie-designware.h |   42
> ++++++++++++++++++++++++++++++++++++
> >  2 files changed, 42 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/pci/host/pcie-designware.c
> > b/drivers/pci/host/pcie-designware.c
> > index 212b8b6..73aa13c 100644
> > --- a/drivers/pci/host/pcie-designware.c
> > +++ b/drivers/pci/host/pcie-designware.c
> > @@ -23,48 +23,6 @@
> >
> >  #include "pcie-designware.h"
> >
> > -/* Synopsis specific PCIE configuration registers */
> > -#define PCIE_PORT_LINK_CONTROL         0x710
> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > -
> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > -
> > -#define PCIE_MSI_ADDR_LO               0x820
> > -#define PCIE_MSI_ADDR_HI               0x824
> > -#define PCIE_MSI_INTR0_ENABLE          0x828
> > -#define PCIE_MSI_INTR0_MASK            0x82C
> > -#define PCIE_MSI_INTR0_STATUS          0x830
> > -
> > -#define PCIE_ATU_VIEWPORT              0x900
> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > -#define PCIE_ATU_CR1                   0x904
> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > -#define PCIE_ATU_CR2                   0x908
> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > -#define PCIE_ATU_LOWER_BASE            0x90C
> > -#define PCIE_ATU_UPPER_BASE            0x910
> > -#define PCIE_ATU_LIMIT                 0x914
> > -#define PCIE_ATU_LOWER_TARGET          0x918
> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > -#define PCIE_ATU_UPPER_TARGET          0x91C
> > -
> >  static struct hw_pci dw_pci;
> >
> >  static unsigned long global_io_offset; diff --git
> > a/drivers/pci/host/pcie-designware.h
> > b/drivers/pci/host/pcie-designware.h
> > index c15379b..da1ed35 100644
> > --- a/drivers/pci/host/pcie-designware.h
> > +++ b/drivers/pci/host/pcie-designware.h
> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
> > pcie_port *pp);
> >
> > +/* Synopsis specific PCIE configuration registers */
> > +#define PCIE_PORT_LINK_CONTROL         0x710
> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
> > +
> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
> > +
> > +#define PCIE_MSI_ADDR_LO               0x820
> > +#define PCIE_MSI_ADDR_HI               0x824
> > +#define PCIE_MSI_INTR0_ENABLE          0x828
> > +#define PCIE_MSI_INTR0_MASK            0x82C
> > +#define PCIE_MSI_INTR0_STATUS          0x830
> > +
> > +#define PCIE_ATU_VIEWPORT              0x900
> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
> > +#define PCIE_ATU_CR1                   0x904
> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
> > +#define PCIE_ATU_CR2                   0x908
> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
> > +#define PCIE_ATU_LOWER_BASE            0x90C
> > +#define PCIE_ATU_UPPER_BASE            0x910
> > +#define PCIE_ATU_LIMIT                 0x914
> > +#define PCIE_ATU_LOWER_TARGET          0x918
> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
> > +#define PCIE_ATU_UPPER_TARGET          0x91C
> > +
> >  #endif /* _PCIE_DESIGNWARE_H */
> 
> Seems like none were using these headers except pcie-designware.c - if ie
> the case better to place it same place as before.

- We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
so move these to the separate header  file.

Thanks
Mohit
> 
> --
> Thanks,
> Jagan.
> --------
> Jagannadha Sutradharudu Teki,
> E: jagannadh.teki at gmail.com, P: +91-9676773388 Engineer - System
> Software Hacker U-boot - SPI Custodian and Zynq APSOC
> Ln: http://www.linkedin.com/in/jaganteki

Re: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Jagan Teki]

On Wed, Dec 11, 2013 at 5:25 PM, Mohit KUMAR DCG <Mohit.KUMAR@st.com> wrote:
> Hello Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jagannadh.teki@gmail.com]
>> Sent: Wednesday, December 11, 2013 5:09 PM
>> To: Mohit KUMAR DCG
>> Cc: linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
>> Pratyush ANAND; Jingoo Han; spear-devel
>> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
>> header file
>>
>> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
>> wrote:
>> > From: Pratyush Anand <pratyush.anand@st.com>
>> >
>> > Move synopsis specific register definition from source file to header
>> > file, so that they can be re-used by other files if needed.
>> >
>> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> > Cc: Mohit Kumar <mohit.kumar@st.com>
>> > Cc: Jingoo Han <jg1.han@samsung.com>
>> > Cc: spear-devel@list.st.com
>> > Cc: linux-pci@vger.kernel.org
>> > ---
>> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>> >  drivers/pci/host/pcie-designware.h |   42
>> ++++++++++++++++++++++++++++++++++++
>> >  2 files changed, 42 insertions(+), 42 deletions(-)
>> >
>> > diff --git a/drivers/pci/host/pcie-designware.c
>> > b/drivers/pci/host/pcie-designware.c
>> > index 212b8b6..73aa13c 100644
>> > --- a/drivers/pci/host/pcie-designware.c
>> > +++ b/drivers/pci/host/pcie-designware.c
>> > @@ -23,48 +23,6 @@
>> >
>> >  #include "pcie-designware.h"
>> >
>> > -/* Synopsis specific PCIE configuration registers */
>> > -#define PCIE_PORT_LINK_CONTROL         0x710
>> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > -
>> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > -
>> > -#define PCIE_MSI_ADDR_LO               0x820
>> > -#define PCIE_MSI_ADDR_HI               0x824
>> > -#define PCIE_MSI_INTR0_ENABLE          0x828
>> > -#define PCIE_MSI_INTR0_MASK            0x82C
>> > -#define PCIE_MSI_INTR0_STATUS          0x830
>> > -
>> > -#define PCIE_ATU_VIEWPORT              0x900
>> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > -#define PCIE_ATU_CR1                   0x904
>> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > -#define PCIE_ATU_CR2                   0x908
>> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > -#define PCIE_ATU_LOWER_BASE            0x90C
>> > -#define PCIE_ATU_UPPER_BASE            0x910
>> > -#define PCIE_ATU_LIMIT                 0x914
>> > -#define PCIE_ATU_LOWER_TARGET          0x918
>> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > -#define PCIE_ATU_UPPER_TARGET          0x91C
>> > -
>> >  static struct hw_pci dw_pci;
>> >
>> >  static unsigned long global_io_offset; diff --git
>> > a/drivers/pci/host/pcie-designware.h
>> > b/drivers/pci/host/pcie-designware.h
>> > index c15379b..da1ed35 100644
>> > --- a/drivers/pci/host/pcie-designware.h
>> > +++ b/drivers/pci/host/pcie-designware.h
>> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
>> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
>> > pcie_port *pp);
>> >
>> > +/* Synopsis specific PCIE configuration registers */
>> > +#define PCIE_PORT_LINK_CONTROL         0x710
>> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > +
>> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > +
>> > +#define PCIE_MSI_ADDR_LO               0x820
>> > +#define PCIE_MSI_ADDR_HI               0x824
>> > +#define PCIE_MSI_INTR0_ENABLE          0x828
>> > +#define PCIE_MSI_INTR0_MASK            0x82C
>> > +#define PCIE_MSI_INTR0_STATUS          0x830
>> > +
>> > +#define PCIE_ATU_VIEWPORT              0x900
>> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > +#define PCIE_ATU_CR1                   0x904
>> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > +#define PCIE_ATU_CR2                   0x908
>> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > +#define PCIE_ATU_LOWER_BASE            0x90C
>> > +#define PCIE_ATU_UPPER_BASE            0x910
>> > +#define PCIE_ATU_LIMIT                 0x914
>> > +#define PCIE_ATU_LOWER_TARGET          0x918
>> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > +#define PCIE_ATU_UPPER_TARGET          0x91C
>> > +
>> >  #endif /* _PCIE_DESIGNWARE_H */
>>
>> Seems like none were using these headers except pcie-designware.c - if ie
>> the case better to place it same place as before.
>
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> so move these to the separate header  file.
>

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Jagan Teki]

On Wed, Dec 11, 2013 at 5:25 PM, Mohit KUMAR DCG <Mohit.KUMAR@st.com> wrote:
> Hello Jagan,
>
>> -----Original Message-----
>> From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
>> Sent: Wednesday, December 11, 2013 5:09 PM
>> To: Mohit KUMAR DCG
>> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
>> Pratyush ANAND; Jingoo Han; spear-devel
>> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
>> header file
>>
>> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com>
>> wrote:
>> > From: Pratyush Anand <pratyush.anand@st.com>
>> >
>> > Move synopsis specific register definition from source file to header
>> > file, so that they can be re-used by other files if needed.
>> >
>> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> > Cc: Mohit Kumar <mohit.kumar@st.com>
>> > Cc: Jingoo Han <jg1.han@samsung.com>
>> > Cc: spear-devel at list.st.com
>> > Cc: linux-pci at vger.kernel.org
>> > ---
>> >  drivers/pci/host/pcie-designware.c |   42 ------------------------------------
>> >  drivers/pci/host/pcie-designware.h |   42
>> ++++++++++++++++++++++++++++++++++++
>> >  2 files changed, 42 insertions(+), 42 deletions(-)
>> >
>> > diff --git a/drivers/pci/host/pcie-designware.c
>> > b/drivers/pci/host/pcie-designware.c
>> > index 212b8b6..73aa13c 100644
>> > --- a/drivers/pci/host/pcie-designware.c
>> > +++ b/drivers/pci/host/pcie-designware.c
>> > @@ -23,48 +23,6 @@
>> >
>> >  #include "pcie-designware.h"
>> >
>> > -/* Synopsis specific PCIE configuration registers */
>> > -#define PCIE_PORT_LINK_CONTROL         0x710
>> > -#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > -#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > -#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > -#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > -
>> > -#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > -#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > -#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > -#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) -#define
>> > PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > -
>> > -#define PCIE_MSI_ADDR_LO               0x820
>> > -#define PCIE_MSI_ADDR_HI               0x824
>> > -#define PCIE_MSI_INTR0_ENABLE          0x828
>> > -#define PCIE_MSI_INTR0_MASK            0x82C
>> > -#define PCIE_MSI_INTR0_STATUS          0x830
>> > -
>> > -#define PCIE_ATU_VIEWPORT              0x900
>> > -#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > -#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > -#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > -#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > -#define PCIE_ATU_CR1                   0x904
>> > -#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > -#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > -#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > -#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > -#define PCIE_ATU_CR2                   0x908
>> > -#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > -#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > -#define PCIE_ATU_LOWER_BASE            0x90C
>> > -#define PCIE_ATU_UPPER_BASE            0x910
>> > -#define PCIE_ATU_LIMIT                 0x914
>> > -#define PCIE_ATU_LOWER_TARGET          0x918
>> > -#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > -#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > -#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > -#define PCIE_ATU_UPPER_TARGET          0x91C
>> > -
>> >  static struct hw_pci dw_pci;
>> >
>> >  static unsigned long global_io_offset; diff --git
>> > a/drivers/pci/host/pcie-designware.h
>> > b/drivers/pci/host/pcie-designware.h
>> > index c15379b..da1ed35 100644
>> > --- a/drivers/pci/host/pcie-designware.h
>> > +++ b/drivers/pci/host/pcie-designware.h
>> > @@ -74,4 +74,46 @@ int dw_pcie_link_up(struct pcie_port *pp);  void
>> > dw_pcie_setup_rc(struct pcie_port *pp);  int dw_pcie_host_init(struct
>> > pcie_port *pp);
>> >
>> > +/* Synopsis specific PCIE configuration registers */
>> > +#define PCIE_PORT_LINK_CONTROL         0x710
>> > +#define PORT_LINK_MODE_MASK            (0x3f << 16)
>> > +#define PORT_LINK_MODE_1_LANES         (0x1 << 16)
>> > +#define PORT_LINK_MODE_2_LANES         (0x3 << 16)
>> > +#define PORT_LINK_MODE_4_LANES         (0x7 << 16)
>> > +
>> > +#define PCIE_LINK_WIDTH_SPEED_CONTROL  0x80C
>> > +#define PORT_LOGIC_SPEED_CHANGE                (0x1 << 17)
>> > +#define PORT_LOGIC_LINK_WIDTH_MASK     (0x1ff << 8)
>> > +#define PORT_LOGIC_LINK_WIDTH_1_LANES  (0x1 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_2_LANES  (0x2 << 8) #define
>> > +PORT_LOGIC_LINK_WIDTH_4_LANES  (0x4 << 8)
>> > +
>> > +#define PCIE_MSI_ADDR_LO               0x820
>> > +#define PCIE_MSI_ADDR_HI               0x824
>> > +#define PCIE_MSI_INTR0_ENABLE          0x828
>> > +#define PCIE_MSI_INTR0_MASK            0x82C
>> > +#define PCIE_MSI_INTR0_STATUS          0x830
>> > +
>> > +#define PCIE_ATU_VIEWPORT              0x900
>> > +#define PCIE_ATU_REGION_INBOUND                (0x1 << 31)
>> > +#define PCIE_ATU_REGION_OUTBOUND       (0x0 << 31)
>> > +#define PCIE_ATU_REGION_INDEX1         (0x1 << 0)
>> > +#define PCIE_ATU_REGION_INDEX0         (0x0 << 0)
>> > +#define PCIE_ATU_CR1                   0x904
>> > +#define PCIE_ATU_TYPE_MEM              (0x0 << 0)
>> > +#define PCIE_ATU_TYPE_IO               (0x2 << 0)
>> > +#define PCIE_ATU_TYPE_CFG0             (0x4 << 0)
>> > +#define PCIE_ATU_TYPE_CFG1             (0x5 << 0)
>> > +#define PCIE_ATU_CR2                   0x908
>> > +#define PCIE_ATU_ENABLE                        (0x1 << 31)
>> > +#define PCIE_ATU_BAR_MODE_ENABLE       (0x1 << 30)
>> > +#define PCIE_ATU_LOWER_BASE            0x90C
>> > +#define PCIE_ATU_UPPER_BASE            0x910
>> > +#define PCIE_ATU_LIMIT                 0x914
>> > +#define PCIE_ATU_LOWER_TARGET          0x918
>> > +#define PCIE_ATU_BUS(x)                        (((x) & 0xff) << 24)
>> > +#define PCIE_ATU_DEV(x)                        (((x) & 0x1f) << 19)
>> > +#define PCIE_ATU_FUNC(x)               (((x) & 0x7) << 16)
>> > +#define PCIE_ATU_UPPER_TARGET          0x91C
>> > +
>> >  #endif /* _PCIE_DESIGNWARE_H */
>>
>> Seems like none were using these headers except pcie-designware.c - if ie
>> the case better to place it same place as before.
>
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> so move these to the separate header  file.
>

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

Re: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > 
> > Seems like none were using these headers except pcie-designware.c - if ie
> > the case better to place it same place as before.
> 
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
> so move these to the separate header  file.

I think it's better not to touch any of the registers from a platform-specific
driver. Better make a high-level function in the common code that the
spear driver can call to change this register.

	Arnd

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > 
> > Seems like none were using these headers except pcie-designware.c - if ie
> > the case better to place it same place as before.
> 
> - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, 
> so move these to the separate header  file.

I think it's better not to touch any of the registers from a platform-specific
driver. Better make a high-level function in the common code that the
spear driver can call to change this register.

	Arnd

Re: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Jingoo Han]

On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > >
> > > Seems like none were using these headers except pcie-designware.c - if ie
> > > the case better to place it same place as before.
> >
> > - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> > so move these to the separate header  file.
> 
> I think it's better not to touch any of the registers from a platform-specific
> driver. Better make a high-level function in the common code that the
> spear driver can call to change this register.

I also agree with Arnd's opinion.

Best regards,
Jingoo Han

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Jingoo Han]

On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > >
> > > Seems like none were using these headers except pcie-designware.c - if ie
> > > the case better to place it same place as before.
> >
> > - We have include these and used few like ' PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform,
> > so move these to the separate header  file.
> 
> I think it's better not to touch any of the registers from a platform-specific
> driver. Better make a high-level function in the common code that the
> spear driver can call to change this register.

I also agree with Arnd's opinion.

Best regards,
Jingoo Han

RE: [PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Jingoo Han [mailto:jg1.han@samsung.com]
> Sent: Thursday, December 12, 2013 4:19 AM
> To: Mohit KUMAR DCG; 'Arnd Bergmann'
> Cc: linux-arm-kernel@lists.infradead.org; 'Jagan Teki'; linux-
> pci@vger.kernel.org; spear-devel; Pratyush ANAND; 'Jingoo Han'
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> > On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > > >
> > > > Seems like none were using these headers except pcie-designware.c
> > > > - if ie the case better to place it same place as before.
> > >
> > > - We have include these and used few like '
> > > PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, so move
> these to the separate header  file.
> >
> > I think it's better not to touch any of the registers from a
> > platform-specific driver. Better make a high-level function in the
> > common code that the spear driver can call to change this register.
> 
> I also agree with Arnd's opinion.

- As suggested, I will implement required functions in dw driver and hence no need to move register definitions.

Regards
Mohit 

[PATCH 06/12] pcie: designware: Move register definition to the header file

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Jingoo Han [mailto:jg1.han at samsung.com]
> Sent: Thursday, December 12, 2013 4:19 AM
> To: Mohit KUMAR DCG; 'Arnd Bergmann'
> Cc: linux-arm-kernel at lists.infradead.org; 'Jagan Teki'; linux-
> pci at vger.kernel.org; spear-devel; Pratyush ANAND; 'Jingoo Han'
> Subject: Re: [PATCH 06/12] pcie: designware: Move register definition to the
> header file
> 
> On Thursday, December 12, 2013 6:32 AM, Arnd Bergmann wrote:
> > On Wednesday 11 December 2013, Mohit KUMAR DCG wrote:
> > > >
> > > > Seems like none were using these headers except pcie-designware.c
> > > > - if ie the case better to place it same place as before.
> > >
> > > - We have include these and used few like '
> > > PCIE_LINK_WIDTH_SPEED_CONTROL '  for SPEAr13xx platform, so move
> these to the separate header  file.
> >
> > I think it's better not to touch any of the registers from a
> > platform-specific driver. Better make a high-level function in the
> > common code that the spear driver can call to change this register.
> 
> I also agree with Arnd's opinion.

- As suggested, I will implement required functions in dw driver and hence no need to move register definitions.

Regards
Mohit 

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

cfg_read/write function are designware pcie specific. Add dw_pcie prefix
to avoid collision in global name space.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 drivers/pci/host/pci-exynos.c      |    5 +++--
 drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
 drivers/pci/host/pcie-designware.h |    4 ++--
 3 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 24beed3..3de6bfb 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 	int ret;
 
 	exynos_pcie_sideband_dbi_r_mode(pp, true);
-	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
 	exynos_pcie_sideband_dbi_r_mode(pp, false);
 	return ret;
 }
@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	int ret;
 
 	exynos_pcie_sideband_dbi_w_mode(pp, true);
-	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+			where, size, val);
 	exynos_pcie_sideband_dbi_w_mode(pp, false);
 	return ret;
 }
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 73aa13c..be6ce30 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
 	return sys->private_data;
 }
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val)
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
 	*val = readl(addr);
 
@@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int cfg_write(void __iomem *addr, int where, int size, u32 val)
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
 {
 	if (size == 4)
 		writel(val, addr);
@@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 	if (pp->ops->rd_own_conf)
 		ret = pp->ops->rd_own_conf(pp, where, size, val);
 	else
-		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
+				size, val);
 
 	return ret;
 }
@@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	if (pp->ops->wr_own_conf)
 		ret = pp->ops->wr_own_conf(pp, where, size, val);
 	else
-		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
-				val);
+		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
+				size, val);
 
 	return ret;
 }
@@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 
@@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index da1ed35..afb1734 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -66,8 +66,8 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 };
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int cfg_write(void __iomem *addr, int where, int size, u32 val);
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
 void dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
-- 
1.7.0.1

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

cfg_read/write function are designware pcie specific. Add dw_pcie prefix
to avoid collision in global name space.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: spear-devel at list.st.com
Cc: linux-pci at vger.kernel.org
---
 drivers/pci/host/pci-exynos.c      |    5 +++--
 drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
 drivers/pci/host/pcie-designware.h |    4 ++--
 3 files changed, 19 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 24beed3..3de6bfb 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 	int ret;
 
 	exynos_pcie_sideband_dbi_r_mode(pp, true);
-	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
 	exynos_pcie_sideband_dbi_r_mode(pp, false);
 	return ret;
 }
@@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	int ret;
 
 	exynos_pcie_sideband_dbi_w_mode(pp, true);
-	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
+	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
+			where, size, val);
 	exynos_pcie_sideband_dbi_w_mode(pp, false);
 	return ret;
 }
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 73aa13c..be6ce30 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
 	return sys->private_data;
 }
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val)
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
 {
 	*val = readl(addr);
 
@@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int cfg_write(void __iomem *addr, int where, int size, u32 val)
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
 {
 	if (size == 4)
 		writel(val, addr);
@@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
 	if (pp->ops->rd_own_conf)
 		ret = pp->ops->rd_own_conf(pp, where, size, val);
 	else
-		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
+		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
+				size, val);
 
 	return ret;
 }
@@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	if (pp->ops->wr_own_conf)
 		ret = pp->ops->wr_own_conf(pp, where, size, val);
 	else
-		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
-				val);
+		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
+				size, val);
 
 	return ret;
 }
@@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 
@@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 
 	if (bus->parent->number == pp->root_bus_nr) {
 		dw_pcie_prog_viewport_cfg0(pp, busdev);
-		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_mem_outbound(pp);
 	} else {
 		dw_pcie_prog_viewport_cfg1(pp, busdev);
-		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
+		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
+				val);
 		dw_pcie_prog_viewport_io_outbound(pp);
 	}
 
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index da1ed35..afb1734 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -66,8 +66,8 @@ struct pcie_host_ops {
 	void (*host_init)(struct pcie_port *pp);
 };
 
-int cfg_read(void __iomem *addr, int where, int size, u32 *val);
-int cfg_write(void __iomem *addr, int where, int size, u32 val);
+int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
+int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
 void dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
 int dw_pcie_link_up(struct pcie_port *pp);
-- 
1.7.0.1

Re: [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org
> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 24beed3..3de6bfb 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>         int ret;
>
>         exynos_pcie_sideband_dbi_r_mode(pp, true);
> -       ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +       ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
>         exynos_pcie_sideband_dbi_r_mode(pp, false);
>         return ret;
>  }
> @@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>         int ret;
>
>         exynos_pcie_sideband_dbi_w_mode(pp, true);
> -       ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
> +       ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
> +                       where, size, val);
>         exynos_pcie_sideband_dbi_w_mode(pp, false);
>         return ret;
>  }
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 73aa13c..be6ce30 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>         return sys->private_data;
>  }
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  {
>         *val = readl(addr);
>
> @@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
>         return PCIBIOS_SUCCESSFUL;
>  }
>
> -int cfg_write(void __iomem *addr, int where, int size, u32 val)
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
>  {
>         if (size == 4)
>                 writel(val, addr);
> @@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>         if (pp->ops->rd_own_conf)
>                 ret = pp->ops->rd_own_conf(pp, where, size, val);
>         else
> -               ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +               ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> +                               size, val);
>
>         return ret;
>  }
> @@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>         if (pp->ops->wr_own_conf)
>                 ret = pp->ops->wr_own_conf(pp, where, size, val);
>         else
> -               ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
> -                               val);
> +               ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
> +                               size, val);
>
>         return ret;
>  }
> @@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
>         if (bus->parent->number == pp->root_bus_nr) {
>                 dw_pcie_prog_viewport_cfg0(pp, busdev);
> -               ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
> +               ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_mem_outbound(pp);
>         } else {
>                 dw_pcie_prog_viewport_cfg1(pp, busdev);
> -               ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
> +               ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_io_outbound(pp);
>         }
>
> @@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
>         if (bus->parent->number == pp->root_bus_nr) {
>                 dw_pcie_prog_viewport_cfg0(pp, busdev);
> -               ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
> +               ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_mem_outbound(pp);
>         } else {
>                 dw_pcie_prog_viewport_cfg1(pp, busdev);
> -               ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
> +               ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_io_outbound(pp);
>         }
>
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index da1ed35..afb1734 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -66,8 +66,8 @@ struct pcie_host_ops {
>         void (*host_init)(struct pcie_port *pp);
>  };
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val);
> -int cfg_write(void __iomem *addr, int where, int size, u32 val);
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  void dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
>
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel at list.st.com
> Cc: linux-pci at vger.kernel.org
> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 24beed3..3de6bfb 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>         int ret;
>
>         exynos_pcie_sideband_dbi_r_mode(pp, true);
> -       ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +       ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
>         exynos_pcie_sideband_dbi_r_mode(pp, false);
>         return ret;
>  }
> @@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>         int ret;
>
>         exynos_pcie_sideband_dbi_w_mode(pp, true);
> -       ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
> +       ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
> +                       where, size, val);
>         exynos_pcie_sideband_dbi_w_mode(pp, false);
>         return ret;
>  }
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 73aa13c..be6ce30 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>         return sys->private_data;
>  }
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  {
>         *val = readl(addr);
>
> @@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
>         return PCIBIOS_SUCCESSFUL;
>  }
>
> -int cfg_write(void __iomem *addr, int where, int size, u32 val)
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
>  {
>         if (size == 4)
>                 writel(val, addr);
> @@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>         if (pp->ops->rd_own_conf)
>                 ret = pp->ops->rd_own_conf(pp, where, size, val);
>         else
> -               ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +               ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> +                               size, val);
>
>         return ret;
>  }
> @@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>         if (pp->ops->wr_own_conf)
>                 ret = pp->ops->wr_own_conf(pp, where, size, val);
>         else
> -               ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
> -                               val);
> +               ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
> +                               size, val);
>
>         return ret;
>  }
> @@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
>         if (bus->parent->number == pp->root_bus_nr) {
>                 dw_pcie_prog_viewport_cfg0(pp, busdev);
> -               ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
> +               ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_mem_outbound(pp);
>         } else {
>                 dw_pcie_prog_viewport_cfg1(pp, busdev);
> -               ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
> +               ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_io_outbound(pp);
>         }
>
> @@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>
>         if (bus->parent->number == pp->root_bus_nr) {
>                 dw_pcie_prog_viewport_cfg0(pp, busdev);
> -               ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
> +               ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_mem_outbound(pp);
>         } else {
>                 dw_pcie_prog_viewport_cfg1(pp, busdev);
> -               ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
> +               ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
> +                               val);
>                 dw_pcie_prog_viewport_io_outbound(pp);
>         }
>
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index da1ed35..afb1734 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -66,8 +66,8 @@ struct pcie_host_ops {
>         void (*host_init)(struct pcie_port *pp);
>  };
>
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val);
> -int cfg_write(void __iomem *addr, int where, int size, u32 val);
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  void dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
> --
> 1.7.0.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

Re: [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jingoo Han]

On Wednesday, December 11, 2013 8:40 PM, Jagan Teki wrote:
> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> > to avoid collision in global name space.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: spear-devel@list.st.com
> > Cc: linux-pci@vger.kernel.org
> > ---
> >  drivers/pci/host/pci-exynos.c      |    5 +++--
> >  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
> >  drivers/pci/host/pcie-designware.h |    4 ++--

[....]

> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Please use ' Reviewed-by', instead of 'Acked-by'.
It will apply to other patches, too.

According to the ./Documentation/SubmittingPatches,

Acked-by: is often used by the maintainer of the affected code when that
maintainer neither contributed to nor forwarded the patch.

Reviewed-by:, instead, indicates that the patch has been reviewed and found
acceptable according to the Reviewer's Statement:

Best regards,
Jingoo Han

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jingoo Han]

On Wednesday, December 11, 2013 8:40 PM, Jagan Teki wrote:
> On Wed, Dec 11, 2013 at 3:08 PM, Mohit Kumar <mohit.kumar@st.com> wrote:
> > From: Pratyush Anand <pratyush.anand@st.com>
> >
> > cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> > to avoid collision in global name space.
> >
> > Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> > Cc: Mohit Kumar <mohit.kumar@st.com>
> > Cc: Jingoo Han <jg1.han@samsung.com>
> > Cc: spear-devel at list.st.com
> > Cc: linux-pci at vger.kernel.org
> > ---
> >  drivers/pci/host/pci-exynos.c      |    5 +++--
> >  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
> >  drivers/pci/host/pcie-designware.h |    4 ++--

[....]

> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Please use ' Reviewed-by', instead of 'Acked-by'.
It will apply to other patches, too.

According to the ./Documentation/SubmittingPatches,

Acked-by: is often used by the maintainer of the affected code when that
maintainer neither contributed to nor forwarded the patch.

Reviewed-by:, instead, indicates that the patch has been reviewed and found
acceptable according to the Reviewer's Statement:

Best regards,
Jingoo Han

Re: [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> 
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org

Acked-by: Jingoo Han <jg1.han@samsung.com>

It looks good. Also, I tested this patch on Exynos platform.

Best regards,
Jingoo Han

> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> 
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel at list.st.com
> Cc: linux-pci at vger.kernel.org

Acked-by: Jingoo Han <jg1.han@samsung.com>

It looks good. Also, I tested this patch on Exynos platform.

Best regards,
Jingoo Han

> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)

Re: [PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Bjorn Helgaas]

On Wed, Dec 11, 2013 at 03:08:32PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel@list.st.com
> Cc: linux-pci@vger.kernel.org

Applied to pci/host-designware for v3.14, with these acks:

    Tested-by: Jingoo Han <jg1.han@samsung.com>
    Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
    Acked-by: Jingoo Han <jg1.han@samsung.com>

Thanks!

> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 24beed3..3de6bfb 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>  	int ret;
>  
>  	exynos_pcie_sideband_dbi_r_mode(pp, true);
> -	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
>  	exynos_pcie_sideband_dbi_r_mode(pp, false);
>  	return ret;
>  }
> @@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>  	int ret;
>  
>  	exynos_pcie_sideband_dbi_w_mode(pp, true);
> -	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
> +	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
> +			where, size, val);
>  	exynos_pcie_sideband_dbi_w_mode(pp, false);
>  	return ret;
>  }
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 73aa13c..be6ce30 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>  	return sys->private_data;
>  }
>  
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  {
>  	*val = readl(addr);
>  
> @@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  	return PCIBIOS_SUCCESSFUL;
>  }
>  
> -int cfg_write(void __iomem *addr, int where, int size, u32 val)
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
>  {
>  	if (size == 4)
>  		writel(val, addr);
> @@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>  	if (pp->ops->rd_own_conf)
>  		ret = pp->ops->rd_own_conf(pp, where, size, val);
>  	else
> -		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> +				size, val);
>  
>  	return ret;
>  }
> @@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>  	if (pp->ops->wr_own_conf)
>  		ret = pp->ops->wr_own_conf(pp, where, size, val);
>  	else
> -		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
> -				val);
> +		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
> +				size, val);
>  
>  	return ret;
>  }
> @@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  
>  	if (bus->parent->number == pp->root_bus_nr) {
>  		dw_pcie_prog_viewport_cfg0(pp, busdev);
> -		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
> +		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_mem_outbound(pp);
>  	} else {
>  		dw_pcie_prog_viewport_cfg1(pp, busdev);
> -		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
> +		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_io_outbound(pp);
>  	}
>  
> @@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  
>  	if (bus->parent->number == pp->root_bus_nr) {
>  		dw_pcie_prog_viewport_cfg0(pp, busdev);
> -		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
> +		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_mem_outbound(pp);
>  	} else {
>  		dw_pcie_prog_viewport_cfg1(pp, busdev);
> -		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
> +		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_io_outbound(pp);
>  	}
>  
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index da1ed35..afb1734 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -66,8 +66,8 @@ struct pcie_host_ops {
>  	void (*host_init)(struct pcie_port *pp);
>  };
>  
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val);
> -int cfg_write(void __iomem *addr, int where, int size, u32 val);
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  void dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 07/12] pcie: designware: add dw_pcie prefix before cfg_read/write

[Bjorn Helgaas]

On Wed, Dec 11, 2013 at 03:08:32PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> cfg_read/write function are designware pcie specific. Add dw_pcie prefix
> to avoid collision in global name space.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit Kumar <mohit.kumar@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: spear-devel at list.st.com
> Cc: linux-pci at vger.kernel.org

Applied to pci/host-designware for v3.14, with these acks:

    Tested-by: Jingoo Han <jg1.han@samsung.com>
    Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
    Acked-by: Jingoo Han <jg1.han@samsung.com>

Thanks!

> ---
>  drivers/pci/host/pci-exynos.c      |    5 +++--
>  drivers/pci/host/pcie-designware.c |   23 ++++++++++++++---------
>  drivers/pci/host/pcie-designware.h |    4 ++--
>  3 files changed, 19 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 24beed3..3de6bfb 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -468,7 +468,7 @@ static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>  	int ret;
>  
>  	exynos_pcie_sideband_dbi_r_mode(pp, true);
> -	ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +	ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
>  	exynos_pcie_sideband_dbi_r_mode(pp, false);
>  	return ret;
>  }
> @@ -479,7 +479,8 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>  	int ret;
>  
>  	exynos_pcie_sideband_dbi_w_mode(pp, true);
> -	ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val);
> +	ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3),
> +			where, size, val);
>  	exynos_pcie_sideband_dbi_w_mode(pp, false);
>  	return ret;
>  }
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 73aa13c..be6ce30 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -32,7 +32,7 @@ static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
>  	return sys->private_data;
>  }
>  
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val)
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  {
>  	*val = readl(addr);
>  
> @@ -46,7 +46,7 @@ int cfg_read(void __iomem *addr, int where, int size, u32 *val)
>  	return PCIBIOS_SUCCESSFUL;
>  }
>  
> -int cfg_write(void __iomem *addr, int where, int size, u32 val)
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
>  {
>  	if (size == 4)
>  		writel(val, addr);
> @@ -84,7 +84,8 @@ static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
>  	if (pp->ops->rd_own_conf)
>  		ret = pp->ops->rd_own_conf(pp, where, size, val);
>  	else
> -		ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
> +		ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
> +				size, val);
>  
>  	return ret;
>  }
> @@ -97,8 +98,8 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
>  	if (pp->ops->wr_own_conf)
>  		ret = pp->ops->wr_own_conf(pp, where, size, val);
>  	else
> -		ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
> -				val);
> +		ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
> +				size, val);
>  
>  	return ret;
>  }
> @@ -534,11 +535,13 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  
>  	if (bus->parent->number == pp->root_bus_nr) {
>  		dw_pcie_prog_viewport_cfg0(pp, busdev);
> -		ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
> +		ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_mem_outbound(pp);
>  	} else {
>  		dw_pcie_prog_viewport_cfg1(pp, busdev);
> -		ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
> +		ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_io_outbound(pp);
>  	}
>  
> @@ -557,11 +560,13 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  
>  	if (bus->parent->number == pp->root_bus_nr) {
>  		dw_pcie_prog_viewport_cfg0(pp, busdev);
> -		ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
> +		ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_mem_outbound(pp);
>  	} else {
>  		dw_pcie_prog_viewport_cfg1(pp, busdev);
> -		ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
> +		ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
> +				val);
>  		dw_pcie_prog_viewport_io_outbound(pp);
>  	}
>  
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index da1ed35..afb1734 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -66,8 +66,8 @@ struct pcie_host_ops {
>  	void (*host_init)(struct pcie_port *pp);
>  };
>  
> -int cfg_read(void __iomem *addr, int where, int size, u32 *val);
> -int cfg_write(void __iomem *addr, int where, int size, u32 val);
> +int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val);
> +int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val);
>  void dw_handle_msi_irq(struct pcie_port *pp);
>  void dw_pcie_msi_init(struct pcie_port *pp);
>  int dw_pcie_link_up(struct pcie_port *pp);
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 08/12] pcie: designware: Fix IO transfers

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

pp->io_base which is the input of the outbound IO address translation
unit should be the cpu address, it was programmed wrongly to realio
address.

We should pass global_io_offset rather than sys->io_offset to
pci_ioremap_io, so we map the new window into the first available spot
in the Linux view of the I/O space.

We must also pass cpu address instead  of realio address to
pci_ioremap_io.

This patch fixes above issue. It has been tested with Lecroy PTC in AIC
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
otherwise.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
Cc: linux-pci@vger.kernel.org
Cc: spear-devel@list.st.com
---
 drivers/pci/host/pcie-designware.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index be6ce30..071ebc0 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 					   + global_io_offset);
 			pp->config.io_size = resource_size(&pp->io);
 			pp->config.io_bus_addr = range.pci_addr;
+			pp->io_base = range.cpu_addr;
 		}
 		if (restype == IORESOURCE_MEM) {
 			of_pci_range_to_resource(&range, np, &pp->mem);
@@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 
 	pp->cfg0_base = pp->cfg.start;
 	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
-	pp->io_base = pp->io.start;
 	pp->mem_base = pp->mem.start;
 
 	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 	return ret;
 }
 
-
 static int dw_pcie_valid_config(struct pcie_port *pp,
 				struct pci_bus *bus, int dev)
 {
@@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
 
 	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
 		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
-		pci_ioremap_io(sys->io_offset, pp->io.start);
+		pci_ioremap_io(global_io_offset, pp->io_base);
 		global_io_offset += SZ_64K;
 		pci_add_resource_offset(&sys->resources, &pp->io,
 					sys->io_offset);
-- 
1.7.0.1

[PATCH 08/12] pcie: designware: Fix IO transfers

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

pp->io_base which is the input of the outbound IO address translation
unit should be the cpu address, it was programmed wrongly to realio
address.

We should pass global_io_offset rather than sys->io_offset to
pci_ioremap_io, so we map the new window into the first available spot
in the Linux view of the I/O space.

We must also pass cpu address instead  of realio address to
pci_ioremap_io.

This patch fixes above issue. It has been tested with Lecroy PTC in AIC
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
otherwise.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
Cc: linux-pci at vger.kernel.org
Cc: spear-devel at list.st.com
---
 drivers/pci/host/pcie-designware.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index be6ce30..071ebc0 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 					   + global_io_offset);
 			pp->config.io_size = resource_size(&pp->io);
 			pp->config.io_bus_addr = range.pci_addr;
+			pp->io_base = range.cpu_addr;
 		}
 		if (restype == IORESOURCE_MEM) {
 			of_pci_range_to_resource(&range, np, &pp->mem);
@@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
 
 	pp->cfg0_base = pp->cfg.start;
 	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
-	pp->io_base = pp->io.start;
 	pp->mem_base = pp->mem.start;
 
 	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
@@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 	return ret;
 }
 
-
 static int dw_pcie_valid_config(struct pcie_port *pp,
 				struct pci_bus *bus, int dev)
 {
@@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
 
 	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
 		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
-		pci_ioremap_io(sys->io_offset, pp->io.start);
+		pci_ioremap_io(global_io_offset, pp->io_base);
 		global_io_offset += SZ_64K;
 		pci_add_resource_offset(&sys->resources, &pp->io,
 					sys->io_offset);
-- 
1.7.0.1

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Marek Vasut]

On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

[PATCH 08/12] pcie: designware: Fix IO transfers

[Marek Vasut]

On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci at vger.kernel.org
> Cc: spear-devel at list.st.com

Acked-by: Marek Vasut <marex@denx.de>

Best regards,
Marek Vasut

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
>> From: Pratyush Anand <pratyush.anand@st.com>
>>
>> pp->io_base which is the input of the outbound IO address translation
>> unit should be the cpu address, it was programmed wrongly to realio
>> address.
>>
>> We should pass global_io_offset rather than sys->io_offset to
>> pci_ioremap_io, so we map the new window into the first available spot
>> in the Linux view of the I/O space.
>>
>> We must also pass cpu address instead  of realio address to
>> pci_ioremap_io.
>>
>> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
>> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
>> otherwise.
>>
>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>> Tested-by: Tim Harvey <tharvey@gateworks.com>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Marek Vasut <marex@denx.de>
>> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
>> Cc: linux-pci@vger.kernel.org
>> Cc: spear-devel@list.st.com
>
> Acked-by: Marek Vasut <marex@denx.de>
>
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki@gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

[PATCH 08/12] pcie: designware: Fix IO transfers

[Jagan Teki]

On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
>> From: Pratyush Anand <pratyush.anand@st.com>
>>
>> pp->io_base which is the input of the outbound IO address translation
>> unit should be the cpu address, it was programmed wrongly to realio
>> address.
>>
>> We should pass global_io_offset rather than sys->io_offset to
>> pci_ioremap_io, so we map the new window into the first available spot
>> in the Linux view of the I/O space.
>>
>> We must also pass cpu address instead  of realio address to
>> pci_ioremap_io.
>>
>> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
>> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
>> otherwise.
>>
>> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
>> Tested-by: Mohit Kumar <mohit.kumar@st.com>
>> Tested-by: Tim Harvey <tharvey@gateworks.com>
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Cc: Marek Vasut <marex@denx.de>
>> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
>> Cc: linux-pci at vger.kernel.org
>> Cc: spear-devel at list.st.com
>
> Acked-by: Marek Vasut <marex@denx.de>
>
> Best regards,
> Marek Vasut
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

-- 
Thanks,
Jagan.
--------
Jagannadha Sutradharudu Teki,
E: jagannadh.teki at gmail.com, P: +91-9676773388
Engineer - System Software Hacker
U-boot - SPI Custodian and Zynq APSOC
Ln: http://www.linkedin.com/in/jaganteki

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Jingoo Han]

On Wednesday, December 11, 2013 8:30 PM, Jagan Teki wrote:
> On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> > On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> >> From: Pratyush Anand <pratyush.anand@st.com>
> >>
> >> pp->io_base which is the input of the outbound IO address translation
> >> unit should be the cpu address, it was programmed wrongly to realio
> >> address.
> >>
> >> We should pass global_io_offset rather than sys->io_offset to
> >> pci_ioremap_io, so we map the new window into the first available spot
> >> in the Linux view of the I/O space.
> >>
> >> We must also pass cpu address instead  of realio address to
> >> pci_ioremap_io.
> >>
> >> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> >> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> >> otherwise.
> >>
> >> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> >> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> >> Tested-by: Tim Harvey <tharvey@gateworks.com>
> >> Cc: Arnd Bergmann <arnd@arndb.de>
> >> Cc: Marek Vasut <marex@denx.de>
> >> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> >> Cc: linux-pci@vger.kernel.org
> >> Cc: spear-devel@list.st.com
> >
> > Acked-by: Marek Vasut <marex@denx.de>
> >
> > Best regards,
> > Marek Vasut
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > the body of a message to majordomo@vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

As I said, please use 'Reviewed-by' instead of 'Acked-by'.

Best regards,
Jingoo Han

[PATCH 08/12] pcie: designware: Fix IO transfers

[Jingoo Han]

On Wednesday, December 11, 2013 8:30 PM, Jagan Teki wrote:
> On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> > On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> >> From: Pratyush Anand <pratyush.anand@st.com>
> >>
> >> pp->io_base which is the input of the outbound IO address translation
> >> unit should be the cpu address, it was programmed wrongly to realio
> >> address.
> >>
> >> We should pass global_io_offset rather than sys->io_offset to
> >> pci_ioremap_io, so we map the new window into the first available spot
> >> in the Linux view of the I/O space.
> >>
> >> We must also pass cpu address instead  of realio address to
> >> pci_ioremap_io.
> >>
> >> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> >> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> >> otherwise.
> >>
> >> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> >> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> >> Tested-by: Tim Harvey <tharvey@gateworks.com>
> >> Cc: Arnd Bergmann <arnd@arndb.de>
> >> Cc: Marek Vasut <marex@denx.de>
> >> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> >> Cc: linux-pci at vger.kernel.org
> >> Cc: spear-devel at list.st.com
> >
> > Acked-by: Marek Vasut <marex@denx.de>
> >
> > Best regards,
> > Marek Vasut
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

As I said, please use 'Reviewed-by' instead of 'Acked-by'.

Best regards,
Jingoo Han

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Pratyush Anand]

Hi Bjorn,

On Thu, Dec 12, 2013 at 09:17:19AM +0800, Jingoo Han wrote:
> On Wednesday, December 11, 2013 8:30 PM, Jagan Teki wrote:
> > On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> > > On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> > >> From: Pratyush Anand <pratyush.anand@st.com>

May be you can apply this patch along with 07/12 of this series.
V2 of other patches might get delayed because of vacations.

Regards
Pratyush

[PATCH 08/12] pcie: designware: Fix IO transfers

[Pratyush Anand]

Hi Bjorn,

On Thu, Dec 12, 2013 at 09:17:19AM +0800, Jingoo Han wrote:
> On Wednesday, December 11, 2013 8:30 PM, Jagan Teki wrote:
> > On Wed, Dec 11, 2013 at 3:33 PM, Marek Vasut <marex@denx.de> wrote:
> > > On Wednesday, December 11, 2013 at 10:38:33 AM, Mohit Kumar wrote:
> > >> From: Pratyush Anand <pratyush.anand@st.com>

May be you can apply this patch along with 07/12 of this series.
V2 of other patches might get delayed because of vacations.

Regards
Pratyush

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com

Acked-by: Arnd Bergmann <arnd@arndb.de>

[PATCH 08/12] pcie: designware: Fix IO transfers

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci at vger.kernel.org
> Cc: spear-devel at list.st.com

Acked-by: Arnd Bergmann <arnd@arndb.de>

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com

Acked-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> ---
>  drivers/pci/host/pcie-designware.c |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)

[PATCH 08/12] pcie: designware: Fix IO transfers

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci at vger.kernel.org
> Cc: spear-devel at list.st.com

Acked-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> ---
>  drivers/pci/host/pcie-designware.c |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)

Re: [PATCH 08/12] pcie: designware: Fix IO transfers

[Bjorn Helgaas]

On Wed, Dec 11, 2013 at 03:08:33PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci@vger.kernel.org
> Cc: spear-devel@list.st.com

Applied to pci/host-designware for v3.14, with these acks:

    Reviewed-by: Marek Vasut <marex@denx.de
    Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
    Acked-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Jingoo Han <jg1.han@samsung.com>

Thanks!

> ---
>  drivers/pci/host/pcie-designware.c |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index be6ce30..071ebc0 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  					   + global_io_offset);
>  			pp->config.io_size = resource_size(&pp->io);
>  			pp->config.io_bus_addr = range.pci_addr;
> +			pp->io_base = range.cpu_addr;
>  		}
>  		if (restype == IORESOURCE_MEM) {
>  			of_pci_range_to_resource(&range, np, &pp->mem);
> @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  
>  	pp->cfg0_base = pp->cfg.start;
>  	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> -	pp->io_base = pp->io.start;
>  	pp->mem_base = pp->mem.start;
>  
>  	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> @@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  	return ret;
>  }
>  
> -
>  static int dw_pcie_valid_config(struct pcie_port *pp,
>  				struct pci_bus *bus, int dev)
>  {
> @@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
>  
>  	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
>  		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> -		pci_ioremap_io(sys->io_offset, pp->io.start);
> +		pci_ioremap_io(global_io_offset, pp->io_base);
>  		global_io_offset += SZ_64K;
>  		pci_add_resource_offset(&sys->resources, &pp->io,
>  					sys->io_offset);
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 08/12] pcie: designware: Fix IO transfers

[Bjorn Helgaas]

On Wed, Dec 11, 2013 at 03:08:33PM +0530, Mohit Kumar wrote:
> From: Pratyush Anand <pratyush.anand@st.com>
> 
> pp->io_base which is the input of the outbound IO address translation
> unit should be the cpu address, it was programmed wrongly to realio
> address.
> 
> We should pass global_io_offset rather than sys->io_offset to
> pci_ioremap_io, so we map the new window into the first available spot
> in the Linux view of the I/O space.
> 
> We must also pass cpu address instead  of realio address to
> pci_ioremap_io.
> 
> This patch fixes above issue. It has been tested with Lecroy PTC in AIC
> mode and Pericom PI7C9X2G303EL PCIe switch, which does not work
> otherwise.
> 
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Tested-by: Mohit Kumar <mohit.kumar@st.com>
> Tested-by: Tim Harvey <tharvey@gateworks.com>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
> Cc: linux-pci at vger.kernel.org
> Cc: spear-devel at list.st.com

Applied to pci/host-designware for v3.14, with these acks:

    Reviewed-by: Marek Vasut <marex at denx.de
    Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
    Acked-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Jingoo Han <jg1.han@samsung.com>

Thanks!

> ---
>  drivers/pci/host/pcie-designware.c |    5 ++---
>  1 files changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index be6ce30..071ebc0 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  					   + global_io_offset);
>  			pp->config.io_size = resource_size(&pp->io);
>  			pp->config.io_bus_addr = range.pci_addr;
> +			pp->io_base = range.cpu_addr;
>  		}
>  		if (restype == IORESOURCE_MEM) {
>  			of_pci_range_to_resource(&range, np, &pp->mem);
> @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp)
>  
>  	pp->cfg0_base = pp->cfg.start;
>  	pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
> -	pp->io_base = pp->io.start;
>  	pp->mem_base = pp->mem.start;
>  
>  	pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
> @@ -573,7 +573,6 @@ static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  	return ret;
>  }
>  
> -
>  static int dw_pcie_valid_config(struct pcie_port *pp,
>  				struct pci_bus *bus, int dev)
>  {
> @@ -667,7 +666,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
>  
>  	if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
>  		sys->io_offset = global_io_offset - pp->config.io_bus_addr;
> -		pci_ioremap_io(sys->io_offset, pp->io.start);
> +		pci_ioremap_io(global_io_offset, pp->io_base);
>  		global_io_offset += SZ_64K;
>  		pci_add_resource_offset(&sys->resources, &pp->io,
>  					sys->io_offset);
> -- 
> 1.7.0.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.

SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie from respective
evb dtsi file.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
 arch/arm/boot/dts/spear13xx.dtsi  |   54 ++++-
 arch/arm/mach-spear/Kconfig       |    1 +
 drivers/pci/host/Kconfig          |    5 +
 drivers/pci/host/Makefile         |    2 +
 drivers/pci/host/pcie-spear13xx.c |  564 +++++++++++++++++++++++++++++++++++++
 5 files changed, 623 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3518803..aad232e 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0x50000000 0x50000000 0x10000000
-			  0xb0000000 0xb0000000 0x10000000
-			  0xd0000000 0xd0000000 0x02000000
+			  0x80000000 0x80000000 0x20000000
+			  0xb0000000 0xb0000000 0x22000000
 			  0xd8000000 0xd8000000 0x01000000
 			  0xe0000000 0xe0000000 0x10000000>;
 
@@ -210,7 +210,54 @@
 			usbh1_id = <1>;
 			status = "disabled";
 		};
-
+		pcie@b1000000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb1000000 0x4000
+				0xeb800000 0x1000>;
+			interrupts = <0 68 0x4>;
+			pcie_id = <0>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+		pcie@b1800000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb1800000 0x4000
+				0xeb804000 0x1000>;
+			interrupts = <0 69 0x4>;
+			pcie_id = <1>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+		pcie@b4000000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb4000000 0x4000
+				0xeb808000 0x1000>;
+			interrupts = <0 70 0x4>;
+			pcie_id = <2>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -334,6 +381,7 @@
 				reg = <0xe07008c4 0x4>;
 				thermal_flags = <0x7000>;
 			};
+
 		};
 	};
 };
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..d269c2b 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,7 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select PCI
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..df52fad 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2
 	  There are 3 internal PCI controllers available with a single
 	  built-in EHCI/OHCI host controller present on each one.
 
+config PCIE_SPEAR13XX
+	bool "STMicroelectronics SPEAr PCIe controller"
+	depends on ARCH_SPEAR13XX
+	select PCIEPORTBUS
+	select PCIE_DW
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..d6b3d37 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+ccflags-$(CONFIG_PCIE_SPEAR13XX) := -Iarch/arm/mach-spear/include/
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..f01890a
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,564 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2013 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <mach/spear.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+	void __iomem		*phy_base;
+	void __iomem		*app_base;
+	struct clk		*clk;
+	struct pcie_port	pp;
+	int			id;
+	int			is_gen1;
+};
+
+struct pcie_app_reg {
+	u32	app_ctrl_0;		/*cr0*/
+	u32	app_ctrl_1;		/*cr1*/
+	u32	app_status_0;		/*cr2*/
+	u32	app_status_1;		/*cr3*/
+	u32	msg_status;		/*cr4*/
+	u32	msg_payload;		/*cr5*/
+	u32	int_sts;		/*cr6*/
+	u32	int_clr;		/*cr7*/
+	u32	int_mask;		/*cr8*/
+	u32	mst_bmisc;		/*cr9*/
+	u32	phy_ctrl;		/*cr10*/
+	u32	phy_status;		/*cr11*/
+	u32	cxpl_debug_info_0;	/*cr12*/
+	u32	cxpl_debug_info_1;	/*cr13*/
+	u32	ven_msg_ctrl_0;		/*cr14*/
+	u32	ven_msg_ctrl_1;		/*cr15*/
+	u32	ven_msg_data_0;		/*cr16*/
+	u32	ven_msg_data_1;		/*cr17*/
+	u32	ven_msi_0;		/*cr18*/
+	u32	ven_msi_1;		/*cr19*/
+	u32	mst_rmisc;		/*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID			0
+#define TX_LANE_FLIP_EN_ID			1
+#define SYS_AUX_PWR_DET_ID			2
+#define APP_LTSSM_ENABLE_ID			3
+#define SYS_ATTEN_BUTTON_PRESSED_ID		4
+#define SYS_MRL_SENSOR_STATE_ID			5
+#define SYS_PWR_FAULT_DET_ID			6
+#define SYS_MRL_SENSOR_CHGED_ID			7
+#define SYS_PRE_DET_CHGED_ID			8
+#define SYS_CMD_CPLED_INT_ID			9
+#define APP_INIT_RST_0_ID			11
+#define APP_REQ_ENTR_L1_ID			12
+#define APP_READY_ENTR_L23_ID			13
+#define APP_REQ_EXIT_L1_ID			14
+#define DEVICE_TYPE_EP				(0 << 25)
+#define DEVICE_TYPE_LEP				(1 << 25)
+#define DEVICE_TYPE_RC				(4 << 25)
+#define SYS_INT_ID				29
+#define MISCTRL_EN_ID				30
+#define REG_TRANSLATION_ENABLE			31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID			2
+#define APPS_PM_XMT_PME_ID			5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
+#define XMLH_LTSSM_STATE_L0			0x11
+#define XMLH_LTSSM_STATE_L0S			0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define XMLH_LTSSM_STATE_L1_IDLE		0x14
+#define XMLH_LTSSM_STATE_L2_IDLE		0x15
+#define XMLH_LTSSM_STATE_L2_WAKE		0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
+#define XMLH_LTSSM_STATE_DISABLED		0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
+#define XMLH_LTSSM_STATE_MASK			0x3F
+#define XMLH_LINK_UP				(1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID				18
+
+/*CR6*/
+#define INTA_CTRL_INT				(1 << 7)
+#define INTB_CTRL_INT				(1 << 8)
+#define INTC_CTRL_INT				(1 << 9)
+#define INTD_CTRL_INT				(1 << 10)
+#define MSI_CTRL_INT				(1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID				11
+#define VEN_MSI_FUN_NUM_ID			8
+#define VEN_MSI_TC_ID				5
+#define VEN_MSI_VECTOR_ID			0
+#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET			0x70
+
+#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
+
+static int workaround_linkup_spear1340(struct spear13xx_pcie *spear13xx_pcie)
+{
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	int count = 0;
+	u32 vala;
+	u8 valm;
+
+	vala = readl(&app_reg->app_status_1);
+	/* till ltsmm state is not L0 */
+	while ((vala & XMLH_LTSSM_STATE_MASK) != XMLH_LTSSM_STATE_L0) {
+		while (((vala & XMLH_LTSSM_STATE_MASK)
+					== XMLH_LTSSM_STATE_DETECT_QUIET) ||
+				((vala & XMLH_LTSSM_STATE_MASK)
+					== XMLH_LTSSM_STATE_DETECT_ACT)) {
+			valm = readb(spear13xx_pcie->phy_base + 0x20);
+			valm &= ~0x3;
+			writeb(valm, spear13xx_pcie->phy_base + 0x20);
+
+			writeb(0, spear13xx_pcie->phy_base + 0x21);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x16);
+			valm &= ~(1 << 3);
+			writeb(valm, spear13xx_pcie->phy_base + 0x16);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x12);
+			valm &= ~0x3;
+			writeb(valm, spear13xx_pcie->phy_base + 0x12);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x10);
+			valm |= 0x1;
+			writeb(valm, spear13xx_pcie->phy_base + 0x10);
+
+			count++;
+			if (count > 5000)
+				return -ECONNRESET;
+
+			udelay(1);
+			vala = readl(&app_reg->app_status_1);
+		}
+		valm = readb(spear13xx_pcie->phy_base + 0x10);
+		valm &= ~0x1;
+		writeb(valm, spear13xx_pcie->phy_base + 0x10);
+
+		vala = readl(&app_reg->app_status_1);
+	}
+
+	return 0;
+}
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+	u32 val;
+	int count = 0;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+	if (dw_pcie_link_up(pp)) {
+		dev_err(pp->dev, "Link already up\n");
+		return 0;
+	}
+
+	/* setup root complex */
+	dw_pcie_setup_rc(pp);
+
+	/*
+	 * this controller support only 128 bytes read size, however its
+	 * default value in capability register is 512 bytes. So force
+	 * it to 128 here.
+	 */
+	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+	val &= ~PCI_EXP_DEVCTL_READRQ;
+	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+	/* program vid and did for RC */
+	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+	/*
+	 * if is_gen1 is set then handle it, so that some buggy card
+	 * also works
+	 */
+	if (spear13xx_pcie->is_gen1) {
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCAP, 4, val);
+		}
+
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCTL2, 4, val);
+		}
+	} else {
+		dw_pcie_cfg_read(pp->dbi_base, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,
+				&val);
+		val |= PORT_LOGIC_SPEED_CHANGE;
+		dw_pcie_cfg_write(pp->dbi_base, PCIE_LINK_WIDTH_SPEED_CONTROL,
+				4, val);
+	}
+
+	/* txdetectrx workaround for SPEAr1310 */
+	if (of_machine_is_compatible("st,spear1310"))
+		writeb(0x00, spear13xx_pcie->phy_base + 0x16);
+
+	/* enable ltssm */
+	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+			| (1 << APP_LTSSM_ENABLE_ID)
+			| ((u32)1 << REG_TRANSLATION_ENABLE),
+			&app_reg->app_ctrl_0);
+
+	/* linkup workaround for SPEAr1340 */
+	if (of_machine_is_compatible("st,spear1340")) {
+		if (workaround_linkup_spear1340(spear13xx_pcie)) {
+			dev_err(pp->dev, "Link Fail\n");
+			return -EINVAL;
+
+		} else {
+			/* check if the link is up or not */
+			while (!dw_pcie_link_up(pp)) {
+				mdelay(100);
+				count++;
+				if (count == 10) {
+					dev_err(pp->dev, "Link Fail\n");
+					return -EINVAL;
+				}
+			}
+			dev_info(pp->dev, "Link up\n");
+		}
+	}
+
+	return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+	struct pcie_port *pp = arg;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	unsigned int status;
+
+	status = readl(&app_reg->int_sts);
+
+	if (status & MSI_CTRL_INT) {
+		if (!IS_ENABLED(CONFIG_PCI_MSI))
+			BUG();
+		dw_handle_msi_irq(pp);
+	}
+
+	writel(status, &app_reg->int_clr);
+
+	return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	/* Enable MSI interrupt */
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		dw_pcie_msi_init(pp);
+		writel(readl(&app_reg->int_mask) |
+				MSI_CTRL_INT, &app_reg->int_mask);
+	}
+
+	return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+		return 1;
+
+	return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+	spear13xx_pcie_establish_link(pp);
+	spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+	.link_up = spear13xx_pcie_link_up,
+	.host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+	int ret;
+
+	pp->irq = platform_get_irq(pdev, 0);
+	if (!pp->irq) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+	ret = devm_request_irq(&pdev->dev, pp->irq, spear13xx_pcie_irq_handler,
+				IRQF_SHARED, "spear13xx-pcie", pp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		return ret;
+	}
+
+	pp->root_bus_nr = -1;
+	pp->ops = &spear13xx_pcie_host_ops;
+
+	spin_lock_init(&pp->conf_lock);
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void spear1340_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE,
+			SPEAR1340_PCIE_MIPHY_CFG);
+	writel(SPEAR1340_PCIE_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+}
+
+static void spear1340_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	writel(0, SPEAR1340_PCIE_SATA_CFG);
+	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+}
+
+static int spear1310_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	u32 temp;
+
+	temp = readl(VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+	temp &= ~SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK;
+	temp |= SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE;
+
+	writel(temp, VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+
+	temp = readl(VA_SPEAR1310_PCIE_SATA_CFG);
+
+	switch (spear13xx_pcie->id) {
+	case 0:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(0);
+		temp |= SPEAR1310_PCIE_CFG_VAL(0);
+		break;
+	case 1:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(1);
+		temp |= SPEAR1310_PCIE_CFG_VAL(1);
+		break;
+	case 2:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(2);
+		temp |= SPEAR1310_PCIE_CFG_VAL(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+	writel(temp, VA_SPEAR1310_PCIE_SATA_CFG);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	u32 temp;
+
+	temp = readl(VA_SPEAR1310_PCIE_SATA_CFG);
+
+	switch (spear13xx_pcie->id) {
+	case 0:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(0);
+		break;
+	case 1:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(1);
+		break;
+	case 2:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(2);
+		break;
+	}
+
+	writel(temp, VA_SPEAR1310_PCIE_SATA_CFG);
+	writel(~SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+			VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+
+	return 0;
+}
+
+static void spear_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	if (of_machine_is_compatible("st,spear1340"))
+		spear1340_pcie_miphy_init(spear13xx_pcie);
+	else if (of_machine_is_compatible("st,spear1310"))
+		spear1310_pcie_miphy_init(spear13xx_pcie);
+}
+
+static void spear_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	if (of_machine_is_compatible("st,spear1340"))
+		spear1340_pcie_miphy_exit(spear13xx_pcie);
+	else if (of_machine_is_compatible("st,spear1310"))
+		spear1310_pcie_miphy_exit(spear13xx_pcie);
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie;
+	struct pcie_port *pp;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *dbi_base;
+	struct resource *phy_base;
+	int ret;
+
+	spear13xx_pcie = devm_kzalloc(&pdev->dev, sizeof(*spear13xx_pcie),
+				GFP_KERNEL);
+	if (!spear13xx_pcie) {
+		dev_err(&pdev->dev, "no memory for SPEAr13xx pcie\n");
+		return -ENOMEM;
+	}
+
+	spear_pcie_miphy_init(spear13xx_pcie);
+
+	spear13xx_pcie->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(spear13xx_pcie->clk)) {
+		dev_err(&pdev->dev, "couldn't get clk for pcie\n");
+		return PTR_ERR(spear13xx_pcie->clk);
+	}
+	ret = clk_prepare_enable(spear13xx_pcie->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "couldn't enable clk for pcie\n");
+		return ret;
+	}
+
+	pp = &spear13xx_pcie->pp;
+
+	pp->dev = &pdev->dev;
+
+	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
+	if (IS_ERR(pp->dbi_base)) {
+		dev_err(&pdev->dev, "couldn't remap dbi base\n");
+		ret = PTR_ERR(pp->dbi_base);
+		goto fail_clk;
+	}
+	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	spear13xx_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
+	if (IS_ERR(spear13xx_pcie->phy_base)) {
+		dev_err(&pdev->dev, "couldn't remap phy base\n");
+		ret = PTR_ERR(spear13xx_pcie->phy_base);
+		goto fail_clk;
+	}
+
+	of_property_read_u32(np, "pcie_is_gen1", &spear13xx_pcie->is_gen1);
+	of_property_read_u32(np, "pcie_id", &spear13xx_pcie->id);
+
+	ret = add_pcie_port(pp, pdev);
+	if (ret < 0)
+		goto fail_clk;
+
+	platform_set_drvdata(pdev, spear13xx_pcie);
+	return 0;
+
+fail_clk:
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	spear_pcie_miphy_exit(spear13xx_pcie);
+
+	return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+	{ .compatible = "st,spear13xx-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+	.remove		= __exit_p(spear13xx_pcie_remove),
+	.driver = {
+		.name	= "spear-pcie",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+	},
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+
+	return platform_driver_probe(&spear13xx_pcie_driver,
+				spear13xx_pcie_probe);
+}
+subsys_initcall(pcie_init);
+
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
-- 
1.7.0.1

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Mohit Kumar]

From: Pratyush Anand <pratyush.anand@st.com>

SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add
SPEAr13xx PCIe driver based on designware controller driver.

SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed
with ahci/sata pins. By default evaluation board of both controller
works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the
necessary modifications on board and enable (okay) pcie from respective
evb dtsi file.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-pci at vger.kernel.org
---
 arch/arm/boot/dts/spear13xx.dtsi  |   54 ++++-
 arch/arm/mach-spear/Kconfig       |    1 +
 drivers/pci/host/Kconfig          |    5 +
 drivers/pci/host/Makefile         |    2 +
 drivers/pci/host/pcie-spear13xx.c |  564 +++++++++++++++++++++++++++++++++++++
 5 files changed, 623 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pci/host/pcie-spear13xx.c

diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 3518803..aad232e 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -83,8 +83,8 @@
 		#size-cells = <1>;
 		compatible = "simple-bus";
 		ranges = <0x50000000 0x50000000 0x10000000
-			  0xb0000000 0xb0000000 0x10000000
-			  0xd0000000 0xd0000000 0x02000000
+			  0x80000000 0x80000000 0x20000000
+			  0xb0000000 0xb0000000 0x22000000
 			  0xd8000000 0xd8000000 0x01000000
 			  0xe0000000 0xe0000000 0x10000000>;
 
@@ -210,7 +210,54 @@
 			usbh1_id = <1>;
 			status = "disabled";
 		};
-
+		pcie at b1000000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb1000000 0x4000
+				0xeb800000 0x1000>;
+			interrupts = <0 68 0x4>;
+			pcie_id = <0>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+		pcie at b1800000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb1800000 0x4000
+				0xeb804000 0x1000>;
+			interrupts = <0 69 0x4>;
+			pcie_id = <1>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
+		pcie at b4000000 {
+			compatible = "st,spear13xx-pcie", "snps,dw-pcie";
+			reg = <0xb4000000 0x4000
+				0xeb808000 0x1000>;
+			interrupts = <0 70 0x4>;
+			pcie_id = <2>;
+			pcie_is_gen1 = <0>;
+			num-lanes = <1>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */
+				0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */
+				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
+			status = "disabled";
+		};
 		apb {
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -334,6 +381,7 @@
 				reg = <0xe07008c4 0x4>;
 				thermal_flags = <0x7000>;
 			};
+
 		};
 	};
 };
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index ac1710e..d269c2b 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -26,6 +26,7 @@ config ARCH_SPEAR13XX
 	select MIGHT_HAVE_CACHE_L2X0
 	select PINCTRL
 	select USE_OF
+	select PCI
 	help
 	  Supports for ARM's SPEAR13XX family
 
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 47d46c6..df52fad 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2
 	  There are 3 internal PCI controllers available with a single
 	  built-in EHCI/OHCI host controller present on each one.
 
+config PCIE_SPEAR13XX
+	bool "STMicroelectronics SPEAr PCIe controller"
+	depends on ARCH_SPEAR13XX
+	select PCIEPORTBUS
+	select PCIE_DW
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 13fb333..d6b3d37 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -4,3 +4,5 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
+ccflags-$(CONFIG_PCIE_SPEAR13XX) := -Iarch/arm/mach-spear/include/
+obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/host/pcie-spear13xx.c b/drivers/pci/host/pcie-spear13xx.c
new file mode 100644
index 0000000..f01890a
--- /dev/null
+++ b/drivers/pci/host/pcie-spear13xx.c
@@ -0,0 +1,564 @@
+/*
+ * PCIe host controller driver for ST Microelectronics SPEAr13xx SoCs
+ *
+ * SPEAr13xx PCIe Glue Layer Source Code
+ *
+ * Copyright (C) 2010-2013 ST Microelectronics
+ * Pratyush Anand <pratyush.anand@st.com>
+ *
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <mach/spear.h>
+
+#include "pcie-designware.h"
+
+struct spear13xx_pcie {
+	void __iomem		*phy_base;
+	void __iomem		*app_base;
+	struct clk		*clk;
+	struct pcie_port	pp;
+	int			id;
+	int			is_gen1;
+};
+
+struct pcie_app_reg {
+	u32	app_ctrl_0;		/*cr0*/
+	u32	app_ctrl_1;		/*cr1*/
+	u32	app_status_0;		/*cr2*/
+	u32	app_status_1;		/*cr3*/
+	u32	msg_status;		/*cr4*/
+	u32	msg_payload;		/*cr5*/
+	u32	int_sts;		/*cr6*/
+	u32	int_clr;		/*cr7*/
+	u32	int_mask;		/*cr8*/
+	u32	mst_bmisc;		/*cr9*/
+	u32	phy_ctrl;		/*cr10*/
+	u32	phy_status;		/*cr11*/
+	u32	cxpl_debug_info_0;	/*cr12*/
+	u32	cxpl_debug_info_1;	/*cr13*/
+	u32	ven_msg_ctrl_0;		/*cr14*/
+	u32	ven_msg_ctrl_1;		/*cr15*/
+	u32	ven_msg_data_0;		/*cr16*/
+	u32	ven_msg_data_1;		/*cr17*/
+	u32	ven_msi_0;		/*cr18*/
+	u32	ven_msi_1;		/*cr19*/
+	u32	mst_rmisc;		/*cr 20*/
+};
+
+/*CR0 ID*/
+#define RX_LANE_FLIP_EN_ID			0
+#define TX_LANE_FLIP_EN_ID			1
+#define SYS_AUX_PWR_DET_ID			2
+#define APP_LTSSM_ENABLE_ID			3
+#define SYS_ATTEN_BUTTON_PRESSED_ID		4
+#define SYS_MRL_SENSOR_STATE_ID			5
+#define SYS_PWR_FAULT_DET_ID			6
+#define SYS_MRL_SENSOR_CHGED_ID			7
+#define SYS_PRE_DET_CHGED_ID			8
+#define SYS_CMD_CPLED_INT_ID			9
+#define APP_INIT_RST_0_ID			11
+#define APP_REQ_ENTR_L1_ID			12
+#define APP_READY_ENTR_L23_ID			13
+#define APP_REQ_EXIT_L1_ID			14
+#define DEVICE_TYPE_EP				(0 << 25)
+#define DEVICE_TYPE_LEP				(1 << 25)
+#define DEVICE_TYPE_RC				(4 << 25)
+#define SYS_INT_ID				29
+#define MISCTRL_EN_ID				30
+#define REG_TRANSLATION_ENABLE			31
+
+/*CR1 ID*/
+#define APPS_PM_XMT_TURNOFF_ID			2
+#define APPS_PM_XMT_PME_ID			5
+
+/*CR3 ID*/
+#define XMLH_LTSSM_STATE_DETECT_QUIET		0x00
+#define XMLH_LTSSM_STATE_DETECT_ACT		0x01
+#define XMLH_LTSSM_STATE_POLL_ACTIVE		0x02
+#define XMLH_LTSSM_STATE_POLL_COMPLIANCE	0x03
+#define XMLH_LTSSM_STATE_POLL_CONFIG		0x04
+#define XMLH_LTSSM_STATE_PRE_DETECT_QUIET	0x05
+#define XMLH_LTSSM_STATE_DETECT_WAIT		0x06
+#define XMLH_LTSSM_STATE_CFG_LINKWD_START	0x07
+#define XMLH_LTSSM_STATE_CFG_LINKWD_ACEPT	0x08
+#define XMLH_LTSSM_STATE_CFG_LANENUM_WAIT	0x09
+#define XMLH_LTSSM_STATE_CFG_LANENUM_ACEPT	0x0A
+#define XMLH_LTSSM_STATE_CFG_COMPLETE		0x0B
+#define XMLH_LTSSM_STATE_CFG_IDLE		0x0C
+#define XMLH_LTSSM_STATE_RCVRY_LOCK		0x0D
+#define XMLH_LTSSM_STATE_RCVRY_SPEED		0x0E
+#define XMLH_LTSSM_STATE_RCVRY_RCVRCFG		0x0F
+#define XMLH_LTSSM_STATE_RCVRY_IDLE		0x10
+#define XMLH_LTSSM_STATE_L0			0x11
+#define XMLH_LTSSM_STATE_L0S			0x12
+#define XMLH_LTSSM_STATE_L123_SEND_EIDLE	0x13
+#define XMLH_LTSSM_STATE_L1_IDLE		0x14
+#define XMLH_LTSSM_STATE_L2_IDLE		0x15
+#define XMLH_LTSSM_STATE_L2_WAKE		0x16
+#define XMLH_LTSSM_STATE_DISABLED_ENTRY		0x17
+#define XMLH_LTSSM_STATE_DISABLED_IDLE		0x18
+#define XMLH_LTSSM_STATE_DISABLED		0x19
+#define XMLH_LTSSM_STATE_LPBK_ENTRY		0x1A
+#define XMLH_LTSSM_STATE_LPBK_ACTIVE		0x1B
+#define XMLH_LTSSM_STATE_LPBK_EXIT		0x1C
+#define XMLH_LTSSM_STATE_LPBK_EXIT_TIMEOUT	0x1D
+#define XMLH_LTSSM_STATE_HOT_RESET_ENTRY	0x1E
+#define XMLH_LTSSM_STATE_HOT_RESET		0x1F
+#define XMLH_LTSSM_STATE_MASK			0x3F
+#define XMLH_LINK_UP				(1 << 6)
+
+/*CR4 ID*/
+#define CFG_MSI_EN_ID				18
+
+/*CR6*/
+#define INTA_CTRL_INT				(1 << 7)
+#define INTB_CTRL_INT				(1 << 8)
+#define INTC_CTRL_INT				(1 << 9)
+#define INTD_CTRL_INT				(1 << 10)
+#define MSI_CTRL_INT				(1 << 26)
+
+/*CR19 ID*/
+#define VEN_MSI_REQ_ID				11
+#define VEN_MSI_FUN_NUM_ID			8
+#define VEN_MSI_TC_ID				5
+#define VEN_MSI_VECTOR_ID			0
+#define VEN_MSI_REQ_EN		((u32)0x1 << VEN_MSI_REQ_ID)
+#define VEN_MSI_FUN_NUM_MASK	((u32)0x7 << VEN_MSI_FUN_NUM_ID)
+#define VEN_MSI_TC_MASK		((u32)0x7 << VEN_MSI_TC_ID)
+#define VEN_MSI_VECTOR_MASK	((u32)0x1F << VEN_MSI_VECTOR_ID)
+
+#define PCI_CAP_ID_EXP_OFFSET			0x70
+
+#define to_spear13xx_pcie(x)	container_of(x, struct spear13xx_pcie, pp)
+
+static int workaround_linkup_spear1340(struct spear13xx_pcie *spear13xx_pcie)
+{
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	int count = 0;
+	u32 vala;
+	u8 valm;
+
+	vala = readl(&app_reg->app_status_1);
+	/* till ltsmm state is not L0 */
+	while ((vala & XMLH_LTSSM_STATE_MASK) != XMLH_LTSSM_STATE_L0) {
+		while (((vala & XMLH_LTSSM_STATE_MASK)
+					== XMLH_LTSSM_STATE_DETECT_QUIET) ||
+				((vala & XMLH_LTSSM_STATE_MASK)
+					== XMLH_LTSSM_STATE_DETECT_ACT)) {
+			valm = readb(spear13xx_pcie->phy_base + 0x20);
+			valm &= ~0x3;
+			writeb(valm, spear13xx_pcie->phy_base + 0x20);
+
+			writeb(0, spear13xx_pcie->phy_base + 0x21);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x16);
+			valm &= ~(1 << 3);
+			writeb(valm, spear13xx_pcie->phy_base + 0x16);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x12);
+			valm &= ~0x3;
+			writeb(valm, spear13xx_pcie->phy_base + 0x12);
+
+			valm = readb(spear13xx_pcie->phy_base + 0x10);
+			valm |= 0x1;
+			writeb(valm, spear13xx_pcie->phy_base + 0x10);
+
+			count++;
+			if (count > 5000)
+				return -ECONNRESET;
+
+			udelay(1);
+			vala = readl(&app_reg->app_status_1);
+		}
+		valm = readb(spear13xx_pcie->phy_base + 0x10);
+		valm &= ~0x1;
+		writeb(valm, spear13xx_pcie->phy_base + 0x10);
+
+		vala = readl(&app_reg->app_status_1);
+	}
+
+	return 0;
+}
+
+static int spear13xx_pcie_establish_link(struct pcie_port *pp)
+{
+	u32 val;
+	int count = 0;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	u32 exp_cap_off = PCI_CAP_ID_EXP_OFFSET;
+
+	if (dw_pcie_link_up(pp)) {
+		dev_err(pp->dev, "Link already up\n");
+		return 0;
+	}
+
+	/* setup root complex */
+	dw_pcie_setup_rc(pp);
+
+	/*
+	 * this controller support only 128 bytes read size, however its
+	 * default value in capability register is 512 bytes. So force
+	 * it to 128 here.
+	 */
+	dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, &val);
+	val &= ~PCI_EXP_DEVCTL_READRQ;
+	dw_pcie_cfg_write(pp->dbi_base, exp_cap_off + PCI_EXP_DEVCTL, 4, val);
+
+	/* program vid and did for RC */
+	dw_pcie_cfg_write(pp->dbi_base, PCI_VENDOR_ID, 2, 0x104A);
+	dw_pcie_cfg_write(pp->dbi_base, PCI_DEVICE_ID, 2, 0xCD80);
+
+	/*
+	 * if is_gen1 is set then handle it, so that some buggy card
+	 * also works
+	 */
+	if (spear13xx_pcie->is_gen1) {
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCAP, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCAP, 4, val);
+		}
+
+		dw_pcie_cfg_read(pp->dbi_base, exp_cap_off + PCI_EXP_LNKCTL2, 4,
+				&val);
+		if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
+			val &= ~((u32)PCI_EXP_LNKCAP_SLS);
+			val |= PCI_EXP_LNKCAP_SLS_2_5GB;
+			dw_pcie_cfg_write(pp->dbi_base, exp_cap_off +
+					PCI_EXP_LNKCTL2, 4, val);
+		}
+	} else {
+		dw_pcie_cfg_read(pp->dbi_base, PCIE_LINK_WIDTH_SPEED_CONTROL, 4,
+				&val);
+		val |= PORT_LOGIC_SPEED_CHANGE;
+		dw_pcie_cfg_write(pp->dbi_base, PCIE_LINK_WIDTH_SPEED_CONTROL,
+				4, val);
+	}
+
+	/* txdetectrx workaround for SPEAr1310 */
+	if (of_machine_is_compatible("st,spear1310"))
+		writeb(0x00, spear13xx_pcie->phy_base + 0x16);
+
+	/* enable ltssm */
+	writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
+			| (1 << APP_LTSSM_ENABLE_ID)
+			| ((u32)1 << REG_TRANSLATION_ENABLE),
+			&app_reg->app_ctrl_0);
+
+	/* linkup workaround for SPEAr1340 */
+	if (of_machine_is_compatible("st,spear1340")) {
+		if (workaround_linkup_spear1340(spear13xx_pcie)) {
+			dev_err(pp->dev, "Link Fail\n");
+			return -EINVAL;
+
+		} else {
+			/* check if the link is up or not */
+			while (!dw_pcie_link_up(pp)) {
+				mdelay(100);
+				count++;
+				if (count == 10) {
+					dev_err(pp->dev, "Link Fail\n");
+					return -EINVAL;
+				}
+			}
+			dev_info(pp->dev, "Link up\n");
+		}
+	}
+
+	return 0;
+}
+
+static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
+{
+	struct pcie_port *pp = arg;
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+	unsigned int status;
+
+	status = readl(&app_reg->int_sts);
+
+	if (status & MSI_CTRL_INT) {
+		if (!IS_ENABLED(CONFIG_PCI_MSI))
+			BUG();
+		dw_handle_msi_irq(pp);
+	}
+
+	writel(status, &app_reg->int_clr);
+
+	return IRQ_HANDLED;
+}
+
+static void spear13xx_pcie_enable_interrupts(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	/* Enable MSI interrupt */
+	if (IS_ENABLED(CONFIG_PCI_MSI)) {
+		dw_pcie_msi_init(pp);
+		writel(readl(&app_reg->int_mask) |
+				MSI_CTRL_INT, &app_reg->int_mask);
+	}
+
+	return;
+}
+
+static int spear13xx_pcie_link_up(struct pcie_port *pp)
+{
+	struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pp);
+	struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
+
+	if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
+		return 1;
+
+	return 0;
+}
+
+static void spear13xx_pcie_host_init(struct pcie_port *pp)
+{
+	spear13xx_pcie_establish_link(pp);
+	spear13xx_pcie_enable_interrupts(pp);
+}
+
+static struct pcie_host_ops spear13xx_pcie_host_ops = {
+	.link_up = spear13xx_pcie_link_up,
+	.host_init = spear13xx_pcie_host_init,
+};
+
+static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev)
+{
+	int ret;
+
+	pp->irq = platform_get_irq(pdev, 0);
+	if (!pp->irq) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+	ret = devm_request_irq(&pdev->dev, pp->irq, spear13xx_pcie_irq_handler,
+				IRQF_SHARED, "spear13xx-pcie", pp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		return ret;
+	}
+
+	pp->root_bus_nr = -1;
+	pp->ops = &spear13xx_pcie_host_ops;
+
+	spin_lock_init(&pp->conf_lock);
+	ret = dw_pcie_host_init(pp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to initialize host\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void spear1340_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE,
+			SPEAR1340_PCIE_MIPHY_CFG);
+	writel(SPEAR1340_PCIE_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+}
+
+static void spear1340_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	writel(0, SPEAR1340_PCIE_SATA_CFG);
+	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+}
+
+static int spear1310_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	u32 temp;
+
+	temp = readl(VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+	temp &= ~SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK;
+	temp |= SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE;
+
+	writel(temp, VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+
+	temp = readl(VA_SPEAR1310_PCIE_SATA_CFG);
+
+	switch (spear13xx_pcie->id) {
+	case 0:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(0);
+		temp |= SPEAR1310_PCIE_CFG_VAL(0);
+		break;
+	case 1:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(1);
+		temp |= SPEAR1310_PCIE_CFG_VAL(1);
+		break;
+	case 2:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(2);
+		temp |= SPEAR1310_PCIE_CFG_VAL(2);
+		break;
+	default:
+		return -EINVAL;
+	}
+	writel(temp, VA_SPEAR1310_PCIE_SATA_CFG);
+
+	return 0;
+}
+
+static int spear1310_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	u32 temp;
+
+	temp = readl(VA_SPEAR1310_PCIE_SATA_CFG);
+
+	switch (spear13xx_pcie->id) {
+	case 0:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(0);
+		break;
+	case 1:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(1);
+		break;
+	case 2:
+		temp &= ~SPEAR1310_PCIE_CFG_MASK(2);
+		break;
+	}
+
+	writel(temp, VA_SPEAR1310_PCIE_SATA_CFG);
+	writel(~SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK,
+			VA_SPEAR1310_PCIE_MIPHY_CFG_1);
+
+	return 0;
+}
+
+static void spear_pcie_miphy_init(struct spear13xx_pcie *spear13xx_pcie)
+{
+	if (of_machine_is_compatible("st,spear1340"))
+		spear1340_pcie_miphy_init(spear13xx_pcie);
+	else if (of_machine_is_compatible("st,spear1310"))
+		spear1310_pcie_miphy_init(spear13xx_pcie);
+}
+
+static void spear_pcie_miphy_exit(struct spear13xx_pcie *spear13xx_pcie)
+{
+	if (of_machine_is_compatible("st,spear1340"))
+		spear1340_pcie_miphy_exit(spear13xx_pcie);
+	else if (of_machine_is_compatible("st,spear1310"))
+		spear1310_pcie_miphy_exit(spear13xx_pcie);
+}
+
+static int __init spear13xx_pcie_probe(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie;
+	struct pcie_port *pp;
+	struct device_node *np = pdev->dev.of_node;
+	struct resource *dbi_base;
+	struct resource *phy_base;
+	int ret;
+
+	spear13xx_pcie = devm_kzalloc(&pdev->dev, sizeof(*spear13xx_pcie),
+				GFP_KERNEL);
+	if (!spear13xx_pcie) {
+		dev_err(&pdev->dev, "no memory for SPEAr13xx pcie\n");
+		return -ENOMEM;
+	}
+
+	spear_pcie_miphy_init(spear13xx_pcie);
+
+	spear13xx_pcie->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(spear13xx_pcie->clk)) {
+		dev_err(&pdev->dev, "couldn't get clk for pcie\n");
+		return PTR_ERR(spear13xx_pcie->clk);
+	}
+	ret = clk_prepare_enable(spear13xx_pcie->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "couldn't enable clk for pcie\n");
+		return ret;
+	}
+
+	pp = &spear13xx_pcie->pp;
+
+	pp->dev = &pdev->dev;
+
+	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);
+	if (IS_ERR(pp->dbi_base)) {
+		dev_err(&pdev->dev, "couldn't remap dbi base\n");
+		ret = PTR_ERR(pp->dbi_base);
+		goto fail_clk;
+	}
+	spear13xx_pcie->app_base = pp->dbi_base + 0x2000;
+
+	phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	spear13xx_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
+	if (IS_ERR(spear13xx_pcie->phy_base)) {
+		dev_err(&pdev->dev, "couldn't remap phy base\n");
+		ret = PTR_ERR(spear13xx_pcie->phy_base);
+		goto fail_clk;
+	}
+
+	of_property_read_u32(np, "pcie_is_gen1", &spear13xx_pcie->is_gen1);
+	of_property_read_u32(np, "pcie_id", &spear13xx_pcie->id);
+
+	ret = add_pcie_port(pp, pdev);
+	if (ret < 0)
+		goto fail_clk;
+
+	platform_set_drvdata(pdev, spear13xx_pcie);
+	return 0;
+
+fail_clk:
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	return ret;
+}
+
+static int __exit spear13xx_pcie_remove(struct platform_device *pdev)
+{
+	struct spear13xx_pcie *spear13xx_pcie = platform_get_drvdata(pdev);
+
+	clk_disable_unprepare(spear13xx_pcie->clk);
+
+	spear_pcie_miphy_exit(spear13xx_pcie);
+
+	return 0;
+}
+
+static const struct of_device_id spear13xx_pcie_of_match[] = {
+	{ .compatible = "st,spear13xx-pcie", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, spear13xx_pcie_of_match);
+
+static struct platform_driver spear13xx_pcie_driver = {
+	.remove		= __exit_p(spear13xx_pcie_remove),
+	.driver = {
+		.name	= "spear-pcie",
+		.owner	= THIS_MODULE,
+		.of_match_table = of_match_ptr(spear13xx_pcie_of_match),
+	},
+};
+
+/* SPEAr13xx PCIe driver does not allow module unload */
+
+static int __init pcie_init(void)
+{
+
+	return platform_driver_probe(&spear13xx_pcie_driver,
+				spear13xx_pcie_probe);
+}
+subsys_initcall(pcie_init);
+
+MODULE_AUTHOR("Pratyush Anand <pratyush.anand@st.com>");
+MODULE_DESCRIPTION("ST Microelectronics SPEAr13xx PCIe host controller driver");
-- 
1.7.0.1

Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +#include <mach/spear.h>

This won't actually build: you cannot access mach/*.h header files
from outside of mach-spear!

> +struct spear13xx_pcie {
> +	void __iomem		*phy_base;
> +	void __iomem		*app_base;
> +	struct clk		*clk;
> +	struct pcie_port	pp;
> +	int			id;
> +	int			is_gen1;
> +};

The pcie driver shouldn't have direct access to the phy registers,
use a phy driver for that.

> +static int workaround_linkup_spear1340(struct spear13xx_pcie *spear13xx_pcie)
> +{
> 
> +}
> +
> +static int spear13xx_pcie_establish_link(struct pcie_port *pp)
> +{

These should move into the phy driver.

> +	/* txdetectrx workaround for SPEAr1310 */
> +	if (of_machine_is_compatible("st,spear1310"))
> +		writeb(0x00, spear13xx_pcie->phy_base + 0x16);

Don't use of_machine_is_compatible() to test for features or bugs of a
particular device. Instead use a binary property in the specific
device node, or key it off of the device's "compatible" value if
there are a lot of differences. You seem to have a couple of these
to test for one or the other PHY implementation, those will
go away when you have a proper driver for them.

	Arnd

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Arnd Bergmann]

On Wednesday 11 December 2013, Mohit Kumar wrote:
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +#include <mach/spear.h>

This won't actually build: you cannot access mach/*.h header files
from outside of mach-spear!

> +struct spear13xx_pcie {
> +	void __iomem		*phy_base;
> +	void __iomem		*app_base;
> +	struct clk		*clk;
> +	struct pcie_port	pp;
> +	int			id;
> +	int			is_gen1;
> +};

The pcie driver shouldn't have direct access to the phy registers,
use a phy driver for that.

> +static int workaround_linkup_spear1340(struct spear13xx_pcie *spear13xx_pcie)
> +{
> 
> +}
> +
> +static int spear13xx_pcie_establish_link(struct pcie_port *pp)
> +{

These should move into the phy driver.

> +	/* txdetectrx workaround for SPEAr1310 */
> +	if (of_machine_is_compatible("st,spear1310"))
> +		writeb(0x00, spear13xx_pcie->phy_base + 0x16);

Don't use of_machine_is_compatible() to test for features or bugs of a
particular device. Instead use a binary property in the specific
device node, or key it off of the device's "compatible" value if
there are a lot of differences. You seem to have a couple of these
to test for one or the other PHY implementation, those will
go away when you have a proper driver for them.

	Arnd

RE: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Thursday, December 12, 2013 4:31 AM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci@vger.kernel.org; Pratyush ANAND; Jingoo
> Han; Viresh Kumar; spear-devel
> Subject: Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +#include <mach/spear.h>
> 
> This won't actually build: you cannot access mach/*.h header files from
> outside of mach-spear!

- OK, will fix it.

> 
> > +struct spear13xx_pcie {
> > +	void __iomem		*phy_base;
> > +	void __iomem		*app_base;
> > +	struct clk		*clk;
> > +	struct pcie_port	pp;
> > +	int			id;
> > +	int			is_gen1;
> > +};
> 
> The pcie driver shouldn't have direct access to the phy registers, use a phy
> driver for that.

- OK. In few workarounds we have to access controller as well as phy registers,
How we should handle such cases if we separate out phy driver from here? Should it be
through phy global functions called from pcie driver?

Thanks
Mohit

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Mohit KUMAR DCG]

Hello Arnd,

> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd at arndb.de]
> Sent: Thursday, December 12, 2013 4:31 AM
> To: linux-arm-kernel at lists.infradead.org
> Cc: Mohit KUMAR DCG; linux-pci at vger.kernel.org; Pratyush ANAND; Jingoo
> Han; Viresh Kumar; spear-devel
> Subject: Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support
> 
> On Wednesday 11 December 2013, Mohit Kumar wrote:
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +#include <mach/spear.h>
> 
> This won't actually build: you cannot access mach/*.h header files from
> outside of mach-spear!

- OK, will fix it.

> 
> > +struct spear13xx_pcie {
> > +	void __iomem		*phy_base;
> > +	void __iomem		*app_base;
> > +	struct clk		*clk;
> > +	struct pcie_port	pp;
> > +	int			id;
> > +	int			is_gen1;
> > +};
> 
> The pcie driver shouldn't have direct access to the phy registers, use a phy
> driver for that.

- OK. In few workarounds we have to access controller as well as phy registers,
How we should handle such cases if we separate out phy driver from here? Should it be
through phy global functions called from pcie driver?

Thanks
Mohit

Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Jingoo Han]

On Friday, December 13, 2013 1:30 PM, Mohit KUMAR DCG wrote:
> On Thursday, December 12, 2013 4:31 AM, Arnd Bergmann wrote:
> > On Wednesday 11 December 2013, Mohit Kumar wrote:

[.....]

> > > +struct spear13xx_pcie {
> > > +	void __iomem		*phy_base;
> > > +	void __iomem		*app_base;
> > > +	struct clk		*clk;
> > > +	struct pcie_port	pp;
> > > +	int			id;
> > > +	int			is_gen1;
> > > +};
> >
> > The pcie driver shouldn't have direct access to the phy registers, use a phy
> > driver for that.
> 
> - OK. In few workarounds we have to access controller as well as phy registers,
> How we should handle such cases if we separate out phy driver from here? Should it be
> through phy global functions called from pcie driver?

Arnd, do you mean the following?

1. Implement Spear PCIe PHY driver using General PHY framework.
  ./drivers/phy/phy-spear13xx-pcie.c

2. Call General PHY APIs
  ./drivers/pci/host/pcie-spear13xx.c
  #include <linux/phy/phy.h>

  pp->phy = devm_phy_get(pp->dev, ...);

  phy_power_on(pp->phy);

  phy_power_off(pp->phy);


Best regards,
Jingoo Han

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Jingoo Han]

On Friday, December 13, 2013 1:30 PM, Mohit KUMAR DCG wrote:
> On Thursday, December 12, 2013 4:31 AM, Arnd Bergmann wrote:
> > On Wednesday 11 December 2013, Mohit Kumar wrote:

[.....]

> > > +struct spear13xx_pcie {
> > > +	void __iomem		*phy_base;
> > > +	void __iomem		*app_base;
> > > +	struct clk		*clk;
> > > +	struct pcie_port	pp;
> > > +	int			id;
> > > +	int			is_gen1;
> > > +};
> >
> > The pcie driver shouldn't have direct access to the phy registers, use a phy
> > driver for that.
> 
> - OK. In few workarounds we have to access controller as well as phy registers,
> How we should handle such cases if we separate out phy driver from here? Should it be
> through phy global functions called from pcie driver?

Arnd, do you mean the following?

1. Implement Spear PCIe PHY driver using General PHY framework.
  ./drivers/phy/phy-spear13xx-pcie.c

2. Call General PHY APIs
  ./drivers/pci/host/pcie-spear13xx.c
  #include <linux/phy/phy.h>

  pp->phy = devm_phy_get(pp->dev, ...);

  phy_power_on(pp->phy);

  phy_power_off(pp->phy);


Best regards,
Jingoo Han

Re: [PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Arnd Bergmann]

On Friday 13 December 2013, Jingoo Han wrote:
> Arnd, do you mean the following?
> 
> 1. Implement Spear PCIe PHY driver using General PHY framework.
>   ./drivers/phy/phy-spear13xx-pcie.c
> 
> 2. Call General PHY APIs
>   ./drivers/pci/host/pcie-spear13xx.c
>   #include <linux/phy/phy.h>
> 
>   pp->phy = devm_phy_get(pp->dev, ...);
> 
>   phy_power_on(pp->phy);
> 
>   phy_power_off(pp->phy);

Yes, exactly.

Of course if the phy driver is licensed from some other company such as
designware as well, or if it can handle more than just pcie, the
implementation of the phy driver and the binding should reflect that.

	Arnd

[PATCH 09/12] pcie: SPEAr13xx: Add designware pcie support

[Arnd Bergmann]

On Friday 13 December 2013, Jingoo Han wrote:
> Arnd, do you mean the following?
> 
> 1. Implement Spear PCIe PHY driver using General PHY framework.
>   ./drivers/phy/phy-spear13xx-pcie.c
> 
> 2. Call General PHY APIs
>   ./drivers/pci/host/pcie-spear13xx.c
>   #include <linux/phy/phy.h>
> 
>   pp->phy = devm_phy_get(pp->dev, ...);
> 
>   phy_power_on(pp->phy);
> 
>   phy_power_off(pp->phy);

Yes, exactly.

Of course if the phy driver is licensed from some other company such as
designware as well, or if it can handle more than just pcie, the
implementation of the phy driver and the binding should reflect that.

	Arnd

[PATCH 10/12] SPEAr13xx: defconfig: Update

[Mohit Kumar]

Enable EABI, OEABI, VFP and NFS configs in default configuration file for
SPEAr13xx.

Enable PCIe support for SPEAr13xx.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel@list.st.com
Cc: linux-arm-kernel@lists.infradead.org
---
 arch/arm/configs/spear13xx_defconfig |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..83882c0 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
 CONFIG_SMP=y
 # CONFIG_SMP_ON_UP is not set
 # CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SPEAR=y
@@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
-- 
1.7.0.1

[PATCH 10/12] SPEAr13xx: defconfig: Update

[Mohit Kumar]

Enable EABI, OEABI, VFP and NFS configs in default configuration file for
SPEAr13xx.

Enable PCIe support for SPEAr13xx.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: spear-devel at list.st.com
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/configs/spear13xx_defconfig |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
index 82eaa55..83882c0 100644
--- a/arch/arm/configs/spear13xx_defconfig
+++ b/arch/arm/configs/spear13xx_defconfig
@@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 # CONFIG_SWP_EMULATE is not set
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_SPEAR13XX=y
 CONFIG_SMP=y
 # CONFIG_SMP_ON_UP is not set
 # CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
 CONFIG_BINFMT_MISC=y
 CONFIG_NET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_NET_IPIP=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_OF_PARTS=y
@@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_FSMC=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 # CONFIG_SATA_PMP is not set
 CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +78,7 @@ CONFIG_USB=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SPEAR=y
@@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_DEFAULT="utf8"
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=m
-- 
1.7.0.1

Re: [PATCH 10/12] SPEAr13xx: defconfig: Update

[Rajeev kumar]

On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> Enable EABI, OEABI, VFP and NFS configs in default configuration file for
> SPEAr13xx.
>
> Enable PCIe support for SPEAr13xx.
>
> Signed-off-by: Pratyush Anand<pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Mohit Kumar<mohit.kumar@st.com>
> Cc: Viresh Kumar<viresh.linux@gmail.com>
> Cc: spear-devel@list.st.com
> Cc: linux-arm-kernel@lists.infradead.org
> ---
>   arch/arm/configs/spear13xx_defconfig |   15 +++++++++++++++
>   1 files changed, 15 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
> index 82eaa55..83882c0 100644
> --- a/arch/arm/configs/spear13xx_defconfig
> +++ b/arch/arm/configs/spear13xx_defconfig
> @@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
>   CONFIG_MACH_SPEAR1310=y
>   CONFIG_MACH_SPEAR1340=y
>   # CONFIG_SWP_EMULATE is not set
> +CONFIG_PCI_MSI=y
> +CONFIG_PCIE_SPEAR13XX=y
>   CONFIG_SMP=y
>   # CONFIG_SMP_ON_UP is not set
>   # CONFIG_ARM_CPU_TOPOLOGY is not set
> +CONFIG_AEABI=y
> +CONFIG_OABI_COMPAT=y
>   CONFIG_ARM_APPENDED_DTB=y
>   CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_VFP=y
>   CONFIG_BINFMT_MISC=y
>   CONFIG_NET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_NET_IPIP=y
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>   CONFIG_MTD=y
>   CONFIG_MTD_OF_PARTS=y
> @@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
>   CONFIG_MTD_NAND_FSMC=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=16384
> +CONFIG_BLK_DEV_SD=y
>   CONFIG_ATA=y
>   # CONFIG_SATA_PMP is not set
>   CONFIG_SATA_AHCI_PLATFORM=y
> @@ -66,6 +78,7 @@ CONFIG_USB=y
>   # CONFIG_USB_DEVICE_CLASS is not set
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_STORAGE=y
>   CONFIG_MMC=y
>   CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_SPEAR=y
> @@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m
>   CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
>   CONFIG_TMPFS=y
>   CONFIG_JFFS2_FS=y
> +CONFIG_NFS_FS=y
> +CONFIG_ROOT_NFS=y

Its better to enable CONFIG_FUSE_FS also in case you want to work with 
fully functional NFS in userspace.

~Rajeev

>   CONFIG_NLS_DEFAULT="utf8"
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_ASCII=m

[PATCH 10/12] SPEAr13xx: defconfig: Update

[Rajeev kumar]

On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> Enable EABI, OEABI, VFP and NFS configs in default configuration file for
> SPEAr13xx.
>
> Enable PCIe support for SPEAr13xx.
>
> Signed-off-by: Pratyush Anand<pratyush.anand@st.com>
> Signed-off-by: Mohit Kumar<mohit.kumar@st.com>
> Cc: Mohit Kumar<mohit.kumar@st.com>
> Cc: Viresh Kumar<viresh.linux@gmail.com>
> Cc: spear-devel at list.st.com
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>   arch/arm/configs/spear13xx_defconfig |   15 +++++++++++++++
>   1 files changed, 15 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
> index 82eaa55..83882c0 100644
> --- a/arch/arm/configs/spear13xx_defconfig
> +++ b/arch/arm/configs/spear13xx_defconfig
> @@ -11,13 +11,24 @@ CONFIG_ARCH_SPEAR13XX=y
>   CONFIG_MACH_SPEAR1310=y
>   CONFIG_MACH_SPEAR1340=y
>   # CONFIG_SWP_EMULATE is not set
> +CONFIG_PCI_MSI=y
> +CONFIG_PCIE_SPEAR13XX=y
>   CONFIG_SMP=y
>   # CONFIG_SMP_ON_UP is not set
>   # CONFIG_ARM_CPU_TOPOLOGY is not set
> +CONFIG_AEABI=y
> +CONFIG_OABI_COMPAT=y
>   CONFIG_ARM_APPENDED_DTB=y
>   CONFIG_ARM_ATAG_DTB_COMPAT=y
> +CONFIG_VFP=y
>   CONFIG_BINFMT_MISC=y
>   CONFIG_NET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_NET_IPIP=y
>   CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
>   CONFIG_MTD=y
>   CONFIG_MTD_OF_PARTS=y
> @@ -27,6 +38,7 @@ CONFIG_MTD_NAND=y
>   CONFIG_MTD_NAND_FSMC=y
>   CONFIG_BLK_DEV_RAM=y
>   CONFIG_BLK_DEV_RAM_SIZE=16384
> +CONFIG_BLK_DEV_SD=y
>   CONFIG_ATA=y
>   # CONFIG_SATA_PMP is not set
>   CONFIG_SATA_AHCI_PLATFORM=y
> @@ -66,6 +78,7 @@ CONFIG_USB=y
>   # CONFIG_USB_DEVICE_CLASS is not set
>   CONFIG_USB_EHCI_HCD=y
>   CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_STORAGE=y
>   CONFIG_MMC=y
>   CONFIG_MMC_SDHCI=y
>   CONFIG_MMC_SDHCI_SPEAR=y
> @@ -84,6 +97,8 @@ CONFIG_VFAT_FS=m
>   CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
>   CONFIG_TMPFS=y
>   CONFIG_JFFS2_FS=y
> +CONFIG_NFS_FS=y
> +CONFIG_ROOT_NFS=y

Its better to enable CONFIG_FUSE_FS also in case you want to work with 
fully functional NFS in userspace.

~Rajeev

>   CONFIG_NLS_DEFAULT="utf8"
>   CONFIG_NLS_CODEPAGE_437=y
>   CONFIG_NLS_ASCII=m

RE: [PATCH 10/12] SPEAr13xx: defconfig: Update

[Mohit KUMAR DCG]

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aW4gdXNlcnNwYWNlLg0KDQotIE9LLCB3aWxsIGVuYWJsZSB0aGlzIG9wdGlvbi4NCg0KVGhhbmtz
DQpNb2hpdA0K

[PATCH 10/12] SPEAr13xx: defconfig: Update

[Mohit KUMAR DCG]

Hello Rajeev,

> -----Original Message-----
> From: Rajeev KUMAR
> Sent: Wednesday, December 11, 2013 4:17 PM
> To: Mohit KUMAR DCG
> Cc: linux-pci at vger.kernel.org; linux-arm-kernel at lists.infradead.org;
> Pratyush ANAND; Viresh Kumar; spear-devel
> Subject: Re: [PATCH 10/12] SPEAr13xx: defconfig: Update
> 
> On 12/11/2013 3:08 PM, Mohit KUMAR wrote:
> > Enable EABI, OEABI, VFP and NFS configs in default configuration file
> > for SPEAr13xx.
> >
> > Enable PCIe support for SPEAr13xx.

[...]
> >   CONFIG_JFFS2_FS=y
> > +CONFIG_NFS_FS=y
> > +CONFIG_ROOT_NFS=y
> 
> Its better to enable CONFIG_FUSE_FS also in case you want to work with
> fully functional NFS in userspace.

- OK, will enable this option.

Thanks
Mohit

[PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Mohit Kumar]

Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
 MAINTAINERS |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4..fd03da6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6462,6 +6462,12 @@ L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/pci-exynos.c
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:	Mohit Kumar <mohit.kumar@st.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-spear13xx.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia@lists.infradead.org
-- 
1.7.0.1

[PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Mohit Kumar]

Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci at vger.kernel.org
---
 MAINTAINERS |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8285ed4..fd03da6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6462,6 +6462,12 @@ L:	linux-pci at vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/pci-exynos.c
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:	Mohit Kumar <mohit.kumar@st.com>
+L:	linux-pci at vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-spear13xx.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia at lists.infradead.org
-- 
1.7.0.1

Re: [PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> 
> Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
> 
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: linux-pci@vger.kernel.org

Acked-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> ---
>  MAINTAINERS |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8285ed4..fd03da6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6462,6 +6462,12 @@ L:	linux-pci@vger.kernel.org
>  S:	Maintained
>  F:	drivers/pci/host/pci-exynos.c
> 
> +PCIE DRIVER FOR ST SPEAR13XX
> +M:	Mohit Kumar <mohit.kumar@st.com>
> +L:	linux-pci@vger.kernel.org
> +S:	Maintained
> +F:	drivers/pci/host/pcie-spear13xx.c
> +
>  PCMCIA SUBSYSTEM
>  P:	Linux PCMCIA Team
>  L:	linux-pcmcia@lists.infradead.org
> --
> 1.7.0.1

[PATCH 11/12] MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer

[Jingoo Han]

On Wednesday, December 11, 2013 6:39 PM, Mohit Kumar wrote:
> 
> Add Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
> 
> Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
> Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
> Cc: Jingoo Han <jg1.han@samsung.com>
> Cc: linux-pci at vger.kernel.org

Acked-by: Jingoo Han <jg1.han@samsung.com>

Best regards,
Jingoo Han

> ---
>  MAINTAINERS |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 8285ed4..fd03da6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -6462,6 +6462,12 @@ L:	linux-pci at vger.kernel.org
>  S:	Maintained
>  F:	drivers/pci/host/pci-exynos.c
> 
> +PCIE DRIVER FOR ST SPEAR13XX
> +M:	Mohit Kumar <mohit.kumar@st.com>
> +L:	linux-pci at vger.kernel.org
> +S:	Maintained
> +F:	drivers/pci/host/pcie-spear13xx.c
> +
>  PCMCIA SUBSYSTEM
>  P:	Linux PCMCIA Team
>  L:	linux-pcmcia at lists.infradead.org
> --
> 1.7.0.1

[PATCH 12/12] MAINTAINERS: Add Synopsis Designware PCIe driver maintainer

[Mohit Kumar]

Add Mohit Kumar and Jingoo Han as maintainer for Synopsis Designware PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci@vger.kernel.org
---
 MAINTAINERS |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd03da6..3ec2a36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6468,6 +6468,13 @@ L:	linux-pci@vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/pcie-spear13xx.c
 
+PCIE DRIVER FOR SYNOPSIS DESIGNWARE CONTROLLER
+M:	Mohit Kumar <mohit.kumar@st.com>
+M:	Jingoo Han <jg1.han@samsung.com>
+L:	linux-pci@vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-designware.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia@lists.infradead.org
-- 
1.7.0.1

[PATCH 12/12] MAINTAINERS: Add Synopsis Designware PCIe driver maintainer

[Mohit Kumar]

Add Mohit Kumar and Jingoo Han as maintainer for Synopsis Designware PCIe driver.

Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: linux-pci at vger.kernel.org
---
 MAINTAINERS |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fd03da6..3ec2a36 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6468,6 +6468,13 @@ L:	linux-pci at vger.kernel.org
 S:	Maintained
 F:	drivers/pci/host/pcie-spear13xx.c
 
+PCIE DRIVER FOR SYNOPSIS DESIGNWARE CONTROLLER
+M:	Mohit Kumar <mohit.kumar@st.com>
+M:	Jingoo Han <jg1.han@samsung.com>
+L:	linux-pci at vger.kernel.org
+S:	Maintained
+F:	drivers/pci/host/pcie-designware.c
+
 PCMCIA SUBSYSTEM
 P:	Linux PCMCIA Team
 L:	linux-pcmcia at lists.infradead.org
-- 
1.7.0.1