* R: Re: PCI device not working
@ 2012-10-04 12:24 Davide Viti
2012-10-04 13:14 ` Kumar Gala
0 siblings, 1 reply; 9+ messages in thread
From: Davide Viti @ 2012-10-04 12:24 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
Hi,
it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), the=
=20
devide behind the second controller is detected by the Linux kernel.
Would=20
you suggest any particular patch I should apply to fix this (I'm using kern=
el=20
2.6.34)
thanx alot in advance
Davide
[1] http://permalink.gmane.org/gmane.
linux.ports.ppc.embedded/20140
>----Messaggio originale----
>Da:=20
zinosat@tiscali.it
>Data: 28/09/2012 16.48
>A: <galak@kernel.crashing.org>
>Cc:=20
<linuxppc-dev@lists.ozlabs.org>
>Ogg: R: Re: PCI device not working
>
>Hi=20
Kumar,
>
>>
>>It was, can you figure out in u-boot what exact config read on=20
>the bus would return the correct thing.
>>
>>The fact that when we probe the=20
>device at 0001:03 we should get back something like cfg_data=3D0xabba1b65
>>
>
>here=20
>follow some details about what is going on inside u-boot; verbosity=20
increases=20
>from [1] to [3]
>
> [1] PCI printouts when the board come up
> [2]=20
output of "pci=20
>[0-3] long" u-boot command
> [3] same as [1] but with debug=20
print inside=20
>indirect_read_config_##size() [drivers/pci/pci_indirect.c]
>
>if=20
you were curious=20
>about our u-boot board settings, please refer to:
>http:
//www.mail-archive.
>com/linuxppc-dev@lists.ozlabs.org/msg62007.html
>
>thanx=20
alot,
>Davide
>
>
>
>*************
>* [1] *
>*************
> PCIE1=20
used as Root Complex (base=20
>addr ffe09000)
> Scanning PCI bus 01
> 01 00 1b65 abba =20
>0280 00
> cfg_addr:ffe09000 cfg_data:
ffe09004 indirect_type:0
> =20
>PCIE1 on bus 00 - 01
>
>
> PCIE2 used as=20
Root Complex (base addr ffe0a000)
>
> Scanning PCI bus 03
> 03 00 1b65 abba 0280 00
> =20
>cfg_addr:ffe0a000 cfg_data:
ffe0a004 indirect_type:0
> PCIE2 on bus 02 - 03
>
>
>*************
>* =20
[2] *
>*************
>
>=3D> pci 0 long
>Scanning PCI devices=20
>on bus 0
>
>Found PCI device 00.00.00:
> vendor ID =3D 0x1957
> =20
>device=20
ID =3D 0x0100
> command register =3D 0x0006
> =20
>status register =3D 0x0010
> revision ID =3D 0x11
> =20
>class code =3D 0x0b (Processor)
> sub class code=20
=3D =20
>0x20
> programming interface =3D 0x00
> cache line=20
=3D 0x08
>
> latency time =3D 0x00
> header type=20
=3D 0x01
> =20
>BIST =3D 0x00
> base address=20
0 =3D 0xfff00000
> =20
>base address 1 =3D 0x00000000
> =20
primary bus number =3D 0x00
> =20
>secondary bus number =3D 0x01
> =20
subordinate bus number =3D 0x01
> =20
>secondary latency timer =3D 0x00
> =20
IO base =3D 0x00
> IO=20
>limit =3D 0x00
> =20
secondary status =3D 0x0000
> memory=20
>base =3D 0xa000
> memory limit =3D 0xa000
> prefetch=20
>memory base =3D =20
0x1001
> prefetch memory limit =3D 0x0001
> prefetch=20
>memory base upper=20
=3D 0x00000000
> prefetch memory limit upper =3D 0x00000000
> IO=20
>base upper 16=20
bits =3D 0x0000
> IO limit upper 16 bits =3D 0x0000
> =20
>expansion ROM=20
base address =3D 0x00000000
> interrupt line =3D 0x00
> =20
>interrupt=20
pin =3D 0x00
> bridge control =3D 0x0000
>
>=3D>=20
>pci 1=20
long
>Scanning PCI devices on bus 1
>
>Found PCI device 01.00.00:kk
> vendor=20
>ID =3D 0x1b65
> device ID =3D 0xabba
> =20
command=20
>register =3D 0x0006
> status register =3D 0x0010
> revision=20
>ID =3D 0x01
> class code =3D 0x02=20
(Network=20
>controller)
> sub class code =3D 0x80
> programming=20
interface=20
>=3D 0x00
> cache line =3D 0x08
> latency time=20
>=3D 0x00
> header type =3D 0x00
> BIST=20
>=3D 0x00
> base address 0 =3D 0xa0000000
> =20
base=20
>address 1 =3D 0xa0010000
> base address 2 =3D =20
0x00000000
>
> base address 3 =3D 0x00000000
> base address 4=20
=3D =20
>0x00000000
> base address 5 =3D 0x00000000
> =20
cardBus CIS pointer=20
>=3D 0x00000000
> sub system vendor ID =3D =20
0x0000
> sub system ID=20
>=3D 0x0000
> expansion ROM base address=20
=3D 0x00000000
> interrupt=20
>line =3D 0x00
> interrupt pin=20
=3D 0x01
> min Grant=20
>=3D 0x00
> max Latency=20
=3D 0x00
>
>=3D> pci 2 long
>
>Scanning PCI devices on bus 2
>
>Found PCI device 02.00.00:
> vendor ID=20
>=3D 0x1957
> device=20
ID =3D 0x0100
> command=20
>register =3D 0x0006
> =20
status register =3D 0x0010
> revision=20
>ID =3D 0x11
> =20
class code =3D 0x0b (Processor)
> =20
>sub class code=20
=3D 0x20
> programming interface =3D 0x00
> cache=20
>line=20
=3D 0x08
> latency time =3D 0x00
> header type=20
>=3D 0x01
> BIST =3D 0x00
> base address=20
0=20
>=3D 0xfff00000
> base address 1 =3D 0x00000000
> =20
primary=20
>bus number =3D 0x00
> secondary bus number =3D 0x01
> =20
subordinate=20
>bus number =3D 0x01
> secondary latency timer =3D 0x00
> =20
IO base=20
>=3D 0x00
> IO limit =3D 0x00
> =20
secondary=20
>status =3D 0x0000
> memory base =3D 0xb000
> memory=20
>limit =3D 0xb000
> prefetch memory base =3D =20
0x1001
> prefetch=20
>memory limit =3D 0x0001
> prefetch memory base upper=20
=3D 0x00000000
> =20
>prefetch memory limit upper =3D 0x00000000
> IO base upper 16=20
bits =3D 0x0000
>
> IO limit upper 16 bits =3D 0x0000
> expansion ROM=20
base address =3D =20
>0x00000000
> interrupt line =3D 0x00
> interrupt=20
pin =3D =20
>0x00
> bridge control =3D 0x0000
>
>=3D> pci 3=20
long
>Scanning PCI devices=20
>on bus 3
>
>Found PCI device 03.00.00:
> vendor=20
ID =3D 0x1b65
> =20
>device ID =3D 0xabba
> =20
command register =3D 0x0006
> =20
>status register =3D 0x0010
> revision ID =3D 0x01
> =20
>class code =3D 0x02=20
(Network controller)
> sub class code=20
>=3D 0x80
> programming=20
interface =3D 0x00
> cache line=20
>=3D 0x08
> latency time=20
=3D 0x00
> header type=20
>=3D 0x00
> BIST=20
=3D 0x00
> base address 0=20
>=3D 0xb0000000
> =20
base address 1 =3D 0xb0010000
> base=20
>address 2 =3D =20
0x00000000
> base address 3 =3D 0x00000000
>
> base address 4=20
=3D 0x00000000
> base address 5 =3D =20
>0x00000000
> =20
cardBus CIS pointer =3D 0x00000000
> sub system vendor ID=20
>=3D =20
0x0000
> sub system ID =3D 0x0000
> expansion ROM base=20
>address=20
=3D 0x00000000
> interrupt line =3D 0x00
> interrupt pin=20
>=3D 0x01
> min Grant =3D 0x00
> max Latency=20
>=3D 0x00
>
>
>*************
>* [3] *
>*************
>
> =20
PCIE1=20
>used as Root Complex (base addr ffe09000)
>b=3D0 d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0=20
>cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D10 mask=3D0
>...
> Scanning=20
>PCI bus 01
>b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0=20
cfg_adr=3Dffe09000 cfg_data=3Dffe09004)=20
>ofs=3De mask=3D3
>...
>b=3D1 d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0 cfg_adr=3Dffe09000=20
>cfg_data=3Dffe09004) ofs=3D3c mask=3D3
> 01 00 =20
1b65 abba 0280 00
>b=3D1 d=3D1=20
>f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000=20
cfg_data=3Dffe09004) ofs=3De mask=3D3
>b=3D1 d=3D1=20
>f=3D0 (fbusno=3D0 itype=3D0=20
cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D0 mask=3D2
>...
>b=3D0=20
>d=3D0 f=3D0 (fbusno=3D0=20
itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D9 mask=3D3
> =20
>PCIE1 on bus 00=20
- 01
>
> PCIE2 used as Root Complex (base addr ffe0a000)
>b=3D0=20
>d=3D0 f=3D0=20
(fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D10 mask=
=3D0
>b=3D0=20
>d=3D0=20
f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D1=
0 mask=3D0
>...
>
>b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0=
a004) ofs=3D9 mask=3D3
>
> Scanning PCI bus 03
>b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
>cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3De mask=3D3
>b=3D1 d=3D0 f=3D0 (fbusno=3D2=20
itype=3D0=20
>cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D0 mask=3D2
>...
>b=3D1 d=3D0 f=3D0=20
(fbusno=3D2=20
>itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D3c mask=3D3
> =20
03 00 1b65 =20
>abba 0280 00
> cfg_addr:ffe0a000 cfg_data:ffe0a004 =20
indirect_type:0
>
>b=3D1 d=3D1 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000=20
cfg_data=3Dffe0a004) ofs=3De mask=3D3
>
>...
>b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D9=20
>mask=3D3
> PCIE2 on bus 02 - 03
>
>
>
>Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9=20
di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio per te e =
per lui! Un=20
amico al mese e parli e navighi sempre gratis: http://freelosophy.tiscali.i=
t/
Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9 di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio pe=
r te e per lui! Un amico al mese e parli e navighi sempre gratis: http://fr=
eelosophy.tiscali.it/
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: PCI device not working
2012-10-04 12:24 R: Re: PCI device not working Davide Viti
@ 2012-10-04 13:14 ` Kumar Gala
[not found] ` <CAKpAL0m3YnsbbGxL+ejfyE4zfGE5LD9Qxb7oobHVaAZGE1_Jnw@mail.gmail.com>
0 siblings, 1 reply; 9+ messages in thread
From: Kumar Gala @ 2012-10-04 13:14 UTC (permalink / raw)
To: Davide Viti; +Cc: linuxppc-dev
On Oct 4, 2012, at 7:24 AM, Davide Viti wrote:
> Hi,
> it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), =
the=20
> devide behind the second controller is detected by the Linux kernel.
>=20
> Would=20
> you suggest any particular patch I should apply to fix this (I'm using =
kernel=20
> 2.6.34)
>=20
> thanx alot in advance
> Davide
>=20
> [1] http://permalink.gmane.org/gmane.
> linux.ports.ppc.embedded/20140
My suggestion would be to try and dump all the controller registers =
between the case that works and doesn't and compare. There's some minor =
setting difference that I'm guessing is causing issues.
- k
>=20
>> ----Messaggio originale----
>> Da:=20
> zinosat@tiscali.it
>> Data: 28/09/2012 16.48
>> A: <galak@kernel.crashing.org>
>> Cc:=20
> <linuxppc-dev@lists.ozlabs.org>
>> Ogg: R: Re: PCI device not working
>>=20
>> Hi=20
> Kumar,
>>=20
>>>=20
>>> It was, can you figure out in u-boot what exact config read on=20
>=20
>> the bus would return the correct thing.
>>>=20
>>> The fact that when we probe the=20
>=20
>> device at 0001:03 we should get back something like =
cfg_data=3D0xabba1b65
>>>=20
>>=20
>=20
>> here=20
>> follow some details about what is going on inside u-boot; verbosity=20=
> increases=20
>> from [1] to [3]
>>=20
>> [1] PCI printouts when the board come up
>> [2]=20
> output of "pci=20
>> [0-3] long" u-boot command
>> [3] same as [1] but with debug=20
> print inside=20
>> indirect_read_config_##size() [drivers/pci/pci_indirect.c]
>>=20
>> if=20
> you were curious=20
>> about our u-boot board settings, please refer to:
>> http:
> //www.mail-archive.
>> com/linuxppc-dev@lists.ozlabs.org/msg62007.html
>>=20
>> thanx=20
> alot,
>> Davide
>>=20
>>=20
>>=20
>> *************
>> * [1] *
>> *************
>> PCIE1=20
> used as Root Complex (base=20
>> addr ffe09000)
>> Scanning PCI bus 01
>=20
>> 01 00 1b65 abba =20
>> 0280 00
>> cfg_addr:ffe09000 cfg_data:
> ffe09004 indirect_type:0
>>=20
>> PCIE1 on bus 00 - 01
>>=20
>>=20
>> PCIE2 used as=20
> Root Complex (base addr ffe0a000)
>>=20
>> Scanning PCI bus 03
>=20
>> 03 00 1b65 abba 0280 00
>>=20
>> cfg_addr:ffe0a000 cfg_data:
> ffe0a004 indirect_type:0
>> PCIE2 on bus 02 - 03
>>=20
>>=20
>> *************
>> * =20
> [2] *
>> *************
>>=20
>> =3D> pci 0 long
>> Scanning PCI devices=20
>> on bus 0
>>=20
>=20
>> Found PCI device 00.00.00:
>> vendor ID =3D 0x1957
>>=20
>> device=20
> ID =3D 0x0100
>> command register =3D 0x0006
>>=20
>=20
>> status register =3D 0x0010
>> revision ID =3D 0x11
>>=20
>=20
>> class code =3D 0x0b (Processor)
>> sub class code=20
> =3D =20
>> 0x20
>> programming interface =3D 0x00
>> cache line=20
> =3D 0x08
>>=20
>> latency time =3D 0x00
>> header type=20
> =3D 0x01
>>=20
>> BIST =3D 0x00
>> base address=20
> 0 =3D 0xfff00000
>>=20
>> base address 1 =3D 0x00000000
>>=20
> primary bus number =3D 0x00
>>=20
>> secondary bus number =3D 0x01
>>=20
> subordinate bus number =3D 0x01
>>=20
>> secondary latency timer =3D 0x00
>>=20
> IO base =3D 0x00
>> IO=20
>> limit =3D 0x00
>>=20
> secondary status =3D 0x0000
>> memory=20
>> base =3D 0xa000
>=20
>> memory limit =3D 0xa000
>> prefetch=20
>> memory base =3D =20
> 0x1001
>> prefetch memory limit =3D 0x0001
>> prefetch=20
>> memory base upper=20
> =3D 0x00000000
>> prefetch memory limit upper =3D 0x00000000
>> IO=20
>> base upper 16=20
> bits =3D 0x0000
>> IO limit upper 16 bits =3D 0x0000
>>=20
>> expansion ROM=20
> base address =3D 0x00000000
>> interrupt line =3D 0x00
>>=20
>> interrupt=20
> pin =3D 0x00
>> bridge control =3D 0x0000
>>=20
>> =3D>=20
>> pci 1=20
> long
>> Scanning PCI devices on bus 1
>>=20
>> Found PCI device 01.00.00:kk
>> vendor=20
>=20
>> ID =3D 0x1b65
>> device ID =3D 0xabba
>>=20
> command=20
>> register =3D 0x0006
>> status register =3D 0x0010
>=20
>> revision=20
>> ID =3D 0x01
>> class code =3D 0x02=20
> (Network=20
>> controller)
>> sub class code =3D 0x80
>> programming=20
> interface=20
>> =3D 0x00
>> cache line =3D 0x08
>> latency time=20
>=20
>> =3D 0x00
>> header type =3D 0x00
>> BIST=20
>=20
>> =3D 0x00
>> base address 0 =3D 0xa0000000
>>=20
> base=20
>> address 1 =3D 0xa0010000
>> base address 2 =3D =20
> 0x00000000
>>=20
>> base address 3 =3D 0x00000000
>> base address 4=20
> =3D =20
>> 0x00000000
>> base address 5 =3D 0x00000000
>>=20
> cardBus CIS pointer=20
>> =3D 0x00000000
>> sub system vendor ID =3D =20
> 0x0000
>> sub system ID=20
>> =3D 0x0000
>> expansion ROM base address=20
> =3D 0x00000000
>> interrupt=20
>> line =3D 0x00
>> interrupt pin=20
> =3D 0x01
>> min Grant=20
>> =3D 0x00
>> max Latency=20
> =3D 0x00
>>=20
>> =3D> pci 2 long
>>=20
>> Scanning PCI devices on bus 2
>>=20
>=20
>> Found PCI device 02.00.00:
>> vendor ID=20
>> =3D 0x1957
>> device=20
> ID =3D 0x0100
>> command=20
>> register =3D 0x0006
>>=20
> status register =3D 0x0010
>> revision=20
>> ID =3D 0x11
>>=20
> class code =3D 0x0b (Processor)
>>=20
>> sub class code=20
> =3D 0x20
>> programming interface =3D 0x00
>> cache=20
>> line=20
> =3D 0x08
>> latency time =3D 0x00
>> header type=20
>=20
>> =3D 0x01
>> BIST =3D 0x00
>> base address=20
> 0=20
>> =3D 0xfff00000
>> base address 1 =3D 0x00000000
>>=20
> primary=20
>> bus number =3D 0x00
>> secondary bus number =3D 0x01
>>=20
> subordinate=20
>> bus number =3D 0x01
>> secondary latency timer =3D 0x00
>>=20
> IO base=20
>> =3D 0x00
>> IO limit =3D 0x00
>>=20
> secondary=20
>> status =3D 0x0000
>> memory base =3D 0xb000
>=20
>> memory=20
>> limit =3D 0xb000
>> prefetch memory base =3D =20
> 0x1001
>> prefetch=20
>> memory limit =3D 0x0001
>> prefetch memory base upper=20
> =3D 0x00000000
>>=20
>> prefetch memory limit upper =3D 0x00000000
>> IO base upper 16=20
> bits =3D 0x0000
>>=20
>> IO limit upper 16 bits =3D 0x0000
>> expansion ROM=20
> base address =3D =20
>> 0x00000000
>> interrupt line =3D 0x00
>> interrupt=20
> pin =3D =20
>> 0x00
>> bridge control =3D 0x0000
>>=20
>> =3D> pci 3=20
> long
>> Scanning PCI devices=20
>> on bus 3
>>=20
>> Found PCI device 03.00.00:
>> vendor=20
> ID =3D 0x1b65
>>=20
>> device ID =3D 0xabba
>>=20
> command register =3D 0x0006
>>=20
>> status register =3D 0x0010
>=20
>> revision ID =3D 0x01
>>=20
>> class code =3D 0x02=20
> (Network controller)
>> sub class code=20
>> =3D 0x80
>> programming=20
> interface =3D 0x00
>> cache line=20
>> =3D 0x08
>> latency time=20
> =3D 0x00
>> header type=20
>> =3D 0x00
>> BIST=20
> =3D 0x00
>> base address 0=20
>> =3D 0xb0000000
>>=20
> base address 1 =3D 0xb0010000
>> base=20
>> address 2 =3D =20
> 0x00000000
>> base address 3 =3D 0x00000000
>>=20
>> base address 4=20
> =3D 0x00000000
>> base address 5 =3D =20
>> 0x00000000
>>=20
> cardBus CIS pointer =3D 0x00000000
>> sub system vendor ID=20
>> =3D =20
> 0x0000
>> sub system ID =3D 0x0000
>> expansion ROM base=20
>> address=20
> =3D 0x00000000
>> interrupt line =3D 0x00
>> interrupt pin=20
>=20
>> =3D 0x01
>> min Grant =3D 0x00
>> max Latency=20
>=20
>> =3D 0x00
>>=20
>>=20
>> *************
>> * [3] *
>> *************
>>=20
>>=20
> PCIE1=20
>> used as Root Complex (base addr ffe09000)
>> b=3D0 d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0=20
>> cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D10 mask=3D0
>> ...
>=20
>> Scanning=20
>> PCI bus 01
>> b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0=20
> cfg_adr=3Dffe09000 cfg_data=3Dffe09004)=20
>> ofs=3De mask=3D3
>> ...
>> b=3D1 d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0 cfg_adr=3Dffe09000=20
>> cfg_data=3Dffe09004) ofs=3D3c mask=3D3
>> 01 00 =20
> 1b65 abba 0280 00
>> b=3D1 d=3D1=20
>> f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000=20
> cfg_data=3Dffe09004) ofs=3De mask=3D3
>> b=3D1 d=3D1=20
>> f=3D0 (fbusno=3D0 itype=3D0=20
> cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D0 mask=3D2
>> ...
>> b=3D0=20
>> d=3D0 f=3D0 (fbusno=3D0=20
> itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D9 mask=3D3
>>=20
>> PCIE1 on bus 00=20
> - 01
>>=20
>> PCIE2 used as Root Complex (base addr ffe0a000)
>> b=3D0=20
>> d=3D0 f=3D0=20
> (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D10 =
mask=3D0
>> b=3D0=20
>> d=3D0=20
> f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) =
ofs=3D10 mask=3D0
>> ...
>>=20
>=20
>> b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 =
cfg_data=3Dffe0a004) ofs=3D9 mask=3D3
>=20
>>=20
>> Scanning PCI bus 03
>> b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
>=20
>> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3De mask=3D3
>> b=3D1 d=3D0 f=3D0 (fbusno=3D2=20
> itype=3D0=20
>> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D0 mask=3D2
>> ...
>> b=3D1 d=3D0 f=3D0=20
> (fbusno=3D2=20
>> itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D3c mask=3D3
>>=20
> 03 00 1b65 =20
>> abba 0280 00
>> cfg_addr:ffe0a000 cfg_data:ffe0a004 =20
> indirect_type:0
>>=20
>> b=3D1 d=3D1 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000=20
> cfg_data=3Dffe0a004) ofs=3De mask=3D3
>>=20
>> ...
>> b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
> cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D9=20
>> mask=3D3
>> PCIE2 on bus 02 - 03
>>=20
>=20
>>=20
>>=20
>> Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico =
vale pi=F9=20
> di uno spot in TV. Per ogni nuovo abbonato 30 =80 di premio per te e =
per lui! Un=20
> amico al mese e parli e navighi sempre gratis: =
http://freelosophy.tiscali.it/
>=20
>=20
>=20
> Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale =
pi=F9 di uno spot in TV. Per ogni nuovo abbonato 30 =80 di premio per te =
e per lui! Un amico al mese e parli e navighi sempre gratis: =
http://freelosophy.tiscali.it/
^ permalink raw reply [flat|nested] 9+ messages in thread
* Fwd: PCI device not working
[not found] ` <CAKpAL0m3YnsbbGxL+ejfyE4zfGE5LD9Qxb7oobHVaAZGE1_Jnw@mail.gmail.com>
@ 2012-10-05 8:54 ` Davide Viti
2012-10-05 12:47 ` Kumar Gala
0 siblings, 1 reply; 9+ messages in thread
From: Davide Viti @ 2012-10-05 8:54 UTC (permalink / raw)
To: linuxppc-dev
(just realized I did not send this to the mailing list: sorry for the noise)
Hi Kumar,
2012/10/4 Kumar Gala <galak@kernel.crashing.org>:
>
> On Oct 4, 2012, at 7:24 AM, Davide Viti wrote:
>
>> Hi,
>> it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), the
>> device behind the second controller is detected by the Linux kernel.
>>
>> Would
>> you suggest any particular patch I should apply to fix this (I'm using kernel
>> 2.6.34)
>>
>> thanx alot in advance
>> Davide
>>
>> [1] http://permalink.gmane.org/gmane.linux.ports.ppc.embedded/20140
>
> My suggestion would be to try and dump all the controller registers between the case that works and doesn't and compare. There's some minor setting difference that I'm guessing is causing issues.
>
> - k
Here's a diff for the configurations for the controller, obtained via
hexdump -C /sys/bus/pci/devices/0001\:02\:00.0/config
--- cfg0_2_NOK.txt 2012-10-05 09:37:44.854607000 +0200
+++ cfg0_2_OK.txt 2012-10-05 09:36:58.337399000 +0200
00000400 00 00 00 00 16 00 00 00 e2 04 00 00 00 00 00 00 |................|
00000410 04 00 00 00 01 00 00 00 00 00 00 00 40 40 00 00 |............@@..|
00000420 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
-00000430 00 00 00 00 00 00 00 00 21 81 9e 00 1a 90 01 00 |........!.......|
+00000430 00 00 00 00 00 00 00 00 21 81 9e 00 83 20 08 00 |........!.... ..|
00000440 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000450 ce d7 14 00 20 1e fc 01 00 00 00 00 5c 0c 00 00 |.... .......\...|
00000460 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000470 57 19 00 01 11 00 20 0b 00 00 00 00 01 00 00 00 |W..... .........|
00000480 44 3d 00 00 00 00 00 00 f0 07 00 00 00 00 00 00 |D=..............|
00000490 c0 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
-000004a0 00 00 00 00 00 00 00 00 00 00 00 00 3c 01 00 00 |............<...|
+000004a0 00 00 00 00 00 00 00 00 00 00 00 00 7e 01 00 00 |............~...|
000004b0 00 00 00 00 00 00 00 00 28 04 01 80 85 20 00 00 |........(.... ..|
000004c0 ff 00 00 00 00 00 00 00 00 00 00 00 11 00 00 00 |................|
000004d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
000004e0 00 00 00 00 01 01 00 00 01 01 00 00 00 00 00 00 |................|
-000004f0 0a 00 00 00 01 00 20 04 00 00 00 00 79 47 0e eb |...... .....yG..|
+000004f0 4a 00 00 01 03 00 00 04 00 00 00 00 01 00 01 00 |J...............|
00000500 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000510 00 00 00 00 00 00 00 00 21 01 00 00 00 00 00 00 |........!.......|
00000520 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
Hope this mail client will not screw up the text...
Just in case,
I've pasted the entire register dumps to [1].
thank you so much for your time,
D.
[1] http://pastebin.com/zzAtzCeS
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: PCI device not working
2012-10-05 8:54 ` Fwd: " Davide Viti
@ 2012-10-05 12:47 ` Kumar Gala
2012-10-25 8:21 ` Davide
2012-10-31 8:52 ` Davide
0 siblings, 2 replies; 9+ messages in thread
From: Kumar Gala @ 2012-10-05 12:47 UTC (permalink / raw)
To: Davide Viti; +Cc: linuxppc-dev
On Oct 5, 2012, at 3:54 AM, Davide Viti wrote:
> (just realized I did not send this to the mailing list: sorry for the =
noise)
>=20
> Hi Kumar,
>=20
> 2012/10/4 Kumar Gala <galak@kernel.crashing.org>:
>>=20
>> On Oct 4, 2012, at 7:24 AM, Davide Viti wrote:
>>=20
>>> Hi,
>>> it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per =
[1]), the
>>> device behind the second controller is detected by the Linux =
kernel.
>>>=20
>>> Would
>>> you suggest any particular patch I should apply to fix this (I'm =
using kernel
>>> 2.6.34)
>>>=20
>>> thanx alot in advance
>>> Davide
>>>=20
>>> [1] http://permalink.gmane.org/gmane.linux.ports.ppc.embedded/20140
>>=20
>> My suggestion would be to try and dump all the controller registers =
between the case that works and doesn't and compare. There's some minor =
setting difference that I'm guessing is causing issues.
>>=20
>> - k
When I said controller registers, I meant the FSL PCI controller and the =
CCSR registers not the PCI cfg register space
- k=
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: PCI device not working
2012-10-05 12:47 ` Kumar Gala
@ 2012-10-25 8:21 ` Davide
2012-10-31 8:52 ` Davide
1 sibling, 0 replies; 9+ messages in thread
From: Davide @ 2012-10-25 8:21 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
Hi Kumar,
On Fri, Oct 05, 2012 at 07:47:24AM -0500, Kumar Gala wrote:
>
> On Oct 5, 2012, at 3:54 AM, Davide Viti wrote:
>
> >> On Oct 4, 2012, at 7:24 AM, Davide Viti wrote:
> >>
> >>> Hi,
> >>> it turns out that if define CONFIG_PCI_NOSCAN in u-boot (as per [1]), the
> >>> device behind the second controller is detected by the Linux kernel.
> >>>
> >>> Would
> >>> you suggest any particular patch I should apply to fix this (I'm using kernel
> >>> 2.6.34)
> >>>
> >>> thanx alot in advance
> >>> Davide
> >>>
> >>> [1] http://permalink.gmane.org/gmane.linux.ports.ppc.embedded/20140
> >>
> >> My suggestion would be to try and dump all the controller registers between the case that works and doesn't and compare. There's some minor setting difference that I'm guessing is causing issues.
> >>
> >> - k
>
> When I said controller registers, I meant the FSL PCI controller and the CCSR registers not the PCI cfg register space
>
I've collected a complete dump of the registers in the working and not working cases
0x9000: 0x80000048 (not working) -> 0x8003007c (ok)
0x9004: 0x00000000 (not working) -> 0x08000000 (ok)
According to the p1020 manual, the register fall in the PCI Express controller 2 area,
in particular:
0x9000 PEX_CONFIG_ADDR—PCI Express configuration address register
0x9004 PEX_CONFIG_DATA—PCI Express configuration data register
does that ring any bell?
thank you in advance
Davide
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: PCI device not working
2012-10-05 12:47 ` Kumar Gala
2012-10-25 8:21 ` Davide
@ 2012-10-31 8:52 ` Davide
1 sibling, 0 replies; 9+ messages in thread
From: Davide @ 2012-10-31 8:52 UTC (permalink / raw)
To: Kumar Gala; +Cc: linuxppc-dev
Hi Kumar,
I try to summarize the problem in the hope to fix it for good:
Linux Kernel (2.6.34-6) did not detect one of the two pci devices
that instead u-boot could "see".
This was worakounded by defining CONFIG_PCI_NOSCAN in u-boot as per [1]
To find out the root cause of the problem, you've suggested to dump all
the controller registers between the case that works and doesn't and
see what changes.
Te following registers have different values in the faulty situation (u-boot
compiled without CONFIG_PCI_NOSCAN definition) vs the working case (u-boot
compiled with CONFIG_PCI_NOSCAN defined):
0x9000: 0x80000048 (not working) -> 0x8003007c (ok)
0x9004: 0x00000000 (not working) -> 0x08000000 (ok)
The register values were obtained with the devmem utility.
Thanx very much for your help,
Davide
[1] http://permalink.gmane.org/gmane.linux.ports.ppc.embedded/20140
^ permalink raw reply [flat|nested] 9+ messages in thread
* R: Re: PCI device not working
@ 2012-09-28 14:48 Davide Viti
0 siblings, 0 replies; 9+ messages in thread
From: Davide Viti @ 2012-09-28 14:48 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
Hi Kumar,
>
>It was, can you figure out in u-boot what exact config read on=20
the bus would return the correct thing.
>
>The fact that when we probe the=20
device at 0001:03 we should get back something like cfg_data=3D0xabba1b65
>
here=20
follow some details about what is going on inside u-boot; verbosity increas=
es=20
from [1] to [3]
[1] PCI printouts when the board come up
[2] output of "pci=20
[0-3] long" u-boot command
[3] same as [1] but with debug print inside=20
indirect_read_config_##size() [drivers/pci/pci_indirect.c]
if you were curious=20
about our u-boot board settings, please refer to:
http://www.mail-archive.
com/linuxppc-dev@lists.ozlabs.org/msg62007.html
thanx alot,
Davide
*************
* [1] *
*************
PCIE1 used as Root Complex (base=20
addr ffe09000)
Scanning PCI bus 01
01 00 1b65 abba =20
0280 00
cfg_addr:ffe09000 cfg_data:ffe09004 indirect_type:0
=20
PCIE1 on bus 00 - 01
PCIE2 used as Root Complex (base addr ffe0a000)
Scanning PCI bus 03
03 00 1b65 abba 0280 00
=20
cfg_addr:ffe0a000 cfg_data:ffe0a004 indirect_type:0
PCIE2 on bus 02 - 03
*************
* [2] *
*************
=3D> pci 0 long
Scanning PCI devices=20
on bus 0
Found PCI device 00.00.00:
vendor ID =3D 0x1957
=20
device ID =3D 0x0100
command register =3D 0x0006
=20
status register =3D 0x0010
revision ID =3D 0x11
=20
class code =3D 0x0b (Processor)
sub class code =3D =20
0x20
programming interface =3D 0x00
cache line =3D 0x08
latency time =3D 0x00
header type =3D 0x01
=20
BIST =3D 0x00
base address 0 =3D 0xfff00000
=20
base address 1 =3D 0x00000000
primary bus number =3D 0x00
=20
secondary bus number =3D 0x01
subordinate bus number =3D 0x01
=20
secondary latency timer =3D 0x00
IO base =3D 0x00
IO=20
limit =3D 0x00
secondary status =3D 0x0000
memory=20
base =3D 0xa000
memory limit =3D 0xa000
prefetch=20
memory base =3D 0x1001
prefetch memory limit =3D 0x0001
prefetch=20
memory base upper =3D 0x00000000
prefetch memory limit upper =3D 0x00000000
IO=20
base upper 16 bits =3D 0x0000
IO limit upper 16 bits =3D 0x0000
=20
expansion ROM base address =3D 0x00000000
interrupt line =3D 0x00
=20
interrupt pin =3D 0x00
bridge control =3D 0x0000
=3D>=20
pci 1 long
Scanning PCI devices on bus 1
Found PCI device 01.00.00:kk
vendor=20
ID =3D 0x1b65
device ID =3D 0xabba
command=20
register =3D 0x0006
status register =3D 0x0010
revision=20
ID =3D 0x01
class code =3D 0x02 (Network=20
controller)
sub class code =3D 0x80
programming interface=20
=3D 0x00
cache line =3D 0x08
latency time=20
=3D 0x00
header type =3D 0x00
BIST=20
=3D 0x00
base address 0 =3D 0xa0000000
base=20
address 1 =3D 0xa0010000
base address 2 =3D 0x00000000
base address 3 =3D 0x00000000
base address 4 =3D =20
0x00000000
base address 5 =3D 0x00000000
cardBus CIS pointer=20
=3D 0x00000000
sub system vendor ID =3D 0x0000
sub system ID=20
=3D 0x0000
expansion ROM base address =3D 0x00000000
interrupt=20
line =3D 0x00
interrupt pin =3D 0x01
min Grant=20
=3D 0x00
max Latency =3D 0x00
=3D> pci 2 long
Scanning PCI devices on bus 2
Found PCI device 02.00.00:
vendor ID=20
=3D 0x1957
device ID =3D 0x0100
command=20
register =3D 0x0006
status register =3D 0x0010
revision=20
ID =3D 0x11
class code =3D 0x0b (Processor)
=20
sub class code =3D 0x20
programming interface =3D 0x00
cache=20
line =3D 0x08
latency time =3D 0x00
header type=20
=3D 0x01
BIST =3D 0x00
base address 0=20
=3D 0xfff00000
base address 1 =3D 0x00000000
primary=20
bus number =3D 0x00
secondary bus number =3D 0x01
subordinate=20
bus number =3D 0x01
secondary latency timer =3D 0x00
IO base=20
=3D 0x00
IO limit =3D 0x00
secondary=20
status =3D 0x0000
memory base =3D 0xb000
memory=20
limit =3D 0xb000
prefetch memory base =3D 0x1001
prefetch=20
memory limit =3D 0x0001
prefetch memory base upper =3D 0x00000000
=20
prefetch memory limit upper =3D 0x00000000
IO base upper 16 bits =3D 0x0000
IO limit upper 16 bits =3D 0x0000
expansion ROM base address =3D =20
0x00000000
interrupt line =3D 0x00
interrupt pin =3D =20
0x00
bridge control =3D 0x0000
=3D> pci 3 long
Scanning PCI devices=20
on bus 3
Found PCI device 03.00.00:
vendor ID =3D 0x1b65
=20
device ID =3D 0xabba
command register =3D 0x0006
=20
status register =3D 0x0010
revision ID =3D 0x01
=20
class code =3D 0x02 (Network controller)
sub class code=20
=3D 0x80
programming interface =3D 0x00
cache line=20
=3D 0x08
latency time =3D 0x00
header type=20
=3D 0x00
BIST =3D 0x00
base address 0=20
=3D 0xb0000000
base address 1 =3D 0xb0010000
base=20
address 2 =3D 0x00000000
base address 3 =3D 0x00000000
base address 4 =3D 0x00000000
base address 5 =3D =20
0x00000000
cardBus CIS pointer =3D 0x00000000
sub system vendor ID=20
=3D 0x0000
sub system ID =3D 0x0000
expansion ROM base=20
address =3D 0x00000000
interrupt line =3D 0x00
interrupt pin=20
=3D 0x01
min Grant =3D 0x00
max Latency=20
=3D 0x00
*************
* [3] *
*************
PCIE1=20
used as Root Complex (base addr ffe09000)
b=3D0 d=3D0 f=3D0 (fbusno=3D0 itype=3D0=20
cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D10 mask=3D0
...
Scanning=20
PCI bus 01
b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09=
004)=20
ofs=3De mask=3D3
...
b=3D1 d=3D0 f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000=20
cfg_data=3Dffe09004) ofs=3D3c mask=3D3
01 00 1b65 abba 0280 00
b=3D1 d=3D1=20
f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3De=
mask=3D3
b=3D1 d=3D1=20
f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) ofs=3D0=
mask=3D2
...
b=3D0=20
d=3D0 f=3D0 (fbusno=3D0 itype=3D0 cfg_adr=3Dffe09000 cfg_data=3Dffe09004) o=
fs=3D9 mask=3D3
=20
PCIE1 on bus 00 - 01
PCIE2 used as Root Complex (base addr ffe0a000)
b=3D0=20
d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) o=
fs=3D10 mask=3D0
b=3D0=20
d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) o=
fs=3D10 mask=3D0
...
b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a=
004) ofs=3D9 mask=3D3
Scanning PCI bus 03
b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3De mask=3D3
b=3D1 d=3D0 f=3D0 (fbusno=3D2 itype=3D0=20
cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D0 mask=3D2
...
b=3D1 d=3D0 f=3D0 (fbusno=3D2=20
itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a004) ofs=3D3c mask=3D3
03 00 1b65 =20
abba 0280 00
cfg_addr:ffe0a000 cfg_data:ffe0a004 indirect_type:0
b=3D1 d=3D1 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a=
004) ofs=3De mask=3D3
...
b=3D0 d=3D0 f=3D0 (fbusno=3D2 itype=3D0 cfg_adr=3Dffe0a000 cfg_data=3Dffe0a=
004) ofs=3D9=20
mask=3D3
PCIE2 on bus 02 - 03
Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9 di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio pe=
r te e per lui! Un amico al mese e parli e navighi sempre gratis: http://fr=
eelosophy.tiscali.it/
^ permalink raw reply [flat|nested] 9+ messages in thread
* R: Re: PCI device not working
@ 2012-09-27 13:14 Davide Viti
0 siblings, 0 replies; 9+ messages in thread
From: Davide Viti @ 2012-09-27 13:14 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
Hi Kumar,
>----Messaggio originale----
>Da: galak@kernel.crashing.org
>Data:=20
27/09/2012 14.27
>A: "Davide Viti"<zinosat@tiscali.it>
>Cc: <linuxppc-dev@lists.
ozlabs.org>
>Ogg: Re: PCI device not working
>
...
>Can you see what bus_no=20
actually gets set to in the case we scan 0001:03 ?
>
>If its set to 03, can you=20
try hack it to 1.
is this what you mean?
---=20
a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
bus_no =3D (bus->number =3D=3D hose->first_busno) ?
=20
hose->self_busno : bus->number;
+ if (bus_no =3D=3D 3) {
+ printk
("*** force bus_no 3 -> 1 ***\n");
+ bus_no =3D 1;
+ }
+
I've=20
tested a kernel with the above patch and this is what is printed on the log=
:
pci_bus 0001:03: scanning bus
-> ind_r_config - [/pcie@ffe0a000] devfn=3D0x0=20
offset=3D0x0 len=3D0x4 hose->indirect_type=3D0x16 hose->first_busno=3D0x2 b=
us-
>number=3D0x3
*** force bus_no 3 -> 1 ***
-> ind_r_config [/pcie@ffe0a000] -=20
(bus_no=3D0x1 reg=3D0x0 cfg_data=3D0xff7eb004 len=3D0x4 hose->cfg_addr=3D0x=
ff7eb000)=20
val=3D0xffffffff PCIBIOS_SUCCESSFUL
the entire log (132Kb) is available in [1]=20
and [2]
thanx for your help,
Davide
[1] http://pastebin.com/3mcbDzwY
[2] http:
//paste2.org/p/2274032
Invita i tuoi amici e Tiscali ti premia! Il consiglio di un amico vale pi=
=C3=B9 di uno spot in TV. Per ogni nuovo abbonato 30 =E2=82=AC di premio pe=
r te e per lui! Un amico al mese e parli e navighi sempre gratis: http://fr=
eelosophy.tiscali.it/
^ permalink raw reply [flat|nested] 9+ messages in thread
* R: Re: PCI device not working
@ 2012-09-27 11:43 Davide Viti
0 siblings, 0 replies; 9+ messages in thread
From: Davide Viti @ 2012-09-27 11:43 UTC (permalink / raw)
To: galak; +Cc: linuxppc-dev
Hi,
>So its odd that scanning of the second bus didn't report any devices. Do=
=20
you have code that implements ppc_md.pci_exclude_device ?
not that I'm aware=20
of
>You might also want to put some code in the indirect PCI ops (indirect.c)=
=20
to see what actual values you are getting from various indirect_read_config=
()=20
calls.
To make sure that ppc_md.pci_exclude_device is not implemented, I've=20
put some printouts inside indirect_read_config(): I print various paramete=
rs=20
when the function is called, and when it returns and note that:
1.=20
indirect_read_config() is called 422 times:=20
174 times for=20
[/pcie@ffe0a000] (controller where the device is not detected)
248 times=20
for [/pcie@ffe09000]=20
2. ppc_md.pci_exclude_device is always NULL
3. the=20
function always returns with PCIBIOS_SUCCESSFUL
4. the only call to =20
indirect_read_config() inside which bus_no=3D0x3, returns with the followi=
ng=20
log:
pci_bus 0001:03: scanning bus
-> ind_r_config - [/pcie@ffe0a000]=20
devfn=3D0x0 len=3D0x4 hose->indirect_type=3D0x16 hose->first_busno=3D0x2 bu=
s-
>number=3D0x3
-> ind_r_config [/pcie@ffe0a000] - (bus_no=3D0x3 reg=3D0x0=20
cfg_data=3D0xffffffff len=3D0xff7eb004) val=3D0x4 PCIBIOS_SUCCESSFUL =20
the entire=20
log is about 116Kb and is available in [1] or [2] (didn't feel like pasting=
so=20
much data on the ML)
thanx alot,
Davide
[1] http://pastebin.com/JaPGmmfs
[2]=20
http://paste2.org/p/2273728
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2012-10-31 8:53 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-10-04 12:24 R: Re: PCI device not working Davide Viti
2012-10-04 13:14 ` Kumar Gala
[not found] ` <CAKpAL0m3YnsbbGxL+ejfyE4zfGE5LD9Qxb7oobHVaAZGE1_Jnw@mail.gmail.com>
2012-10-05 8:54 ` Fwd: " Davide Viti
2012-10-05 12:47 ` Kumar Gala
2012-10-25 8:21 ` Davide
2012-10-31 8:52 ` Davide
-- strict thread matches above, loose matches on Subject: below --
2012-09-28 14:48 R: " Davide Viti
2012-09-27 13:14 Davide Viti
2012-09-27 11:43 Davide Viti
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