From: Stefan Wahren <stefan.wahren@i2se.com> To: Juergen Borleis <juergen@kreuzholzen.de> Cc: dbaryshkov@gmail.com, rjw@rjwysocki.net, kernel@pengutronix.de, pawel.moll@arm.com, lgirdwood@gmail.com, ijc+devicetree@hellion.org.uk, robh+dt@kernel.org, galak@codeaurora.org, shawn.guo@linaro.org, sre@kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, fabio.estevam@freescale.com, dwmw2@infradead.org, Lucas Stach <l.stach@pengutronix.de>, viresh.kumar@linaro.org, mark.rutland@arm.com, sebastien.szymanski@armadeus.com, broonie@kernel.org, marex@denx.de, devicetree@vger.kernel.org Subject: Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28 Date: Sun, 29 Mar 2015 21:09:08 +0200 (CEST) [thread overview] Message-ID: <1275326545.964987.1427656148956.JavaMail.open-xchange@oxbaltgw00.schlund.de> (raw) In-Reply-To: <201503291640.56538.juergen@kreuzholzen.de> Hi Juergen, > Juergen Borleis <juergen@kreuzholzen.de> hat am 29. März 2015 um 16:40 > geschrieben: > > > Hi Stefan, > > Stefan Wahren wrote: > > > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. März 2015 um 21:45 > > > geschrieben: > > > > > > Stefan Wahren wrote: > > > > [...] > > > > diff --git a/arch/arm/boot/dts/imx28.dtsi > > > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644 > > > > --- a/arch/arm/boot/dts/imx28.dtsi > > > > +++ b/arch/arm/boot/dts/imx28.dtsi > > > > @@ -38,12 +38,23 @@ > > > > }; > > > > > > > > cpus { > > > > - #address-cells = <0>; > > > > + #address-cells = <1>; > > > > #size-cells = <0>; > > > > > > > > - cpu { > > > > + cpu@0 { > > > > compatible = "arm,arm926ej-s"; > > > > device_type = "cpu"; > > > > + reg = <0x0>; > > > > + operating-points = < > > > > + /* kHz uV */ > > > > + 261819 1350000 > > > > + 360000 1350000 > > > > + 392728 1450000 > > > > + 454737 1550000 > > > > + >; > > > > + clocks = <&clks 4>; > > > > + clock-latency = <61036>; /* two CLK32 periods */ > > > > + cpu-supply = <®_vddd>; > > > > }; > > > > }; > > > > > > Maybe you should take into account not to reduce VDD below 1.55 V if the > > > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these > > > restrictions. VDD powers the SDRAM controller as well. From the datasheet > > > the table "Frequency versus Voltage for EMICLK" shows: > > > > > > EMICLK Fmax (MHz) > > > VDDD (V) DDR2 mDDR > > > -------------------------------- > > > 1.550 205.71 205.71 > > > 1.450 196.36 196.36 > > > 1.350 196.36 196.36 > > > > > > jbe > > > > > > [1] > > > i.MX28 Applications > > > Processors for Consumer > > > Products > > > Silicon Version 1.2 > > > > > > Document Number: IMX28CEC > > > Rev. 3, 07/2012 > > > > the only chance that i see to meet this constraint without introducing a > > new cpufreq driver is to change clock ref_cpu > > and ref_emi. > > > > Do you think this solution of a virtual clock [1] can be applied here, too? > > This would imply we can change the SDRAM timing at run-time on the fly. IMHO > that is not possible (at least not easy). it's possible since the cpufreq driver in the FSL can do it. But the code isn't nice and contains some workarounds. > I think when the driver detects the SDRAM controller runs above 196 MHz the > clock for the CPU core can still be > changed, but VDD must be kept at 1.55 V. The cpufreq-dt doesn't know anything about SDRAM controller and i think it isn't necessary if we use 1.55 V for all operating points. > > Juergen Stefan
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From: stefan.wahren@i2se.com (Stefan Wahren) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28 Date: Sun, 29 Mar 2015 21:09:08 +0200 (CEST) [thread overview] Message-ID: <1275326545.964987.1427656148956.JavaMail.open-xchange@oxbaltgw00.schlund.de> (raw) In-Reply-To: <201503291640.56538.juergen@kreuzholzen.de> Hi Juergen, > Juergen Borleis <juergen@kreuzholzen.de> hat am 29. M?rz 2015 um 16:40 > geschrieben: > > > Hi Stefan, > > Stefan Wahren wrote: > > > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. M?rz 2015 um 21:45 > > > geschrieben: > > > > > > Stefan Wahren wrote: > > > > [...] > > > > diff --git a/arch/arm/boot/dts/imx28.dtsi > > > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644 > > > > --- a/arch/arm/boot/dts/imx28.dtsi > > > > +++ b/arch/arm/boot/dts/imx28.dtsi > > > > @@ -38,12 +38,23 @@ > > > > }; > > > > > > > > cpus { > > > > - #address-cells = <0>; > > > > + #address-cells = <1>; > > > > #size-cells = <0>; > > > > > > > > - cpu { > > > > + cpu at 0 { > > > > compatible = "arm,arm926ej-s"; > > > > device_type = "cpu"; > > > > + reg = <0x0>; > > > > + operating-points = < > > > > + /* kHz uV */ > > > > + 261819 1350000 > > > > + 360000 1350000 > > > > + 392728 1450000 > > > > + 454737 1550000 > > > > + >; > > > > + clocks = <&clks 4>; > > > > + clock-latency = <61036>; /* two CLK32 periods */ > > > > + cpu-supply = <®_vddd>; > > > > }; > > > > }; > > > > > > Maybe you should take into account not to reduce VDD below 1.55 V if the > > > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these > > > restrictions. VDD powers the SDRAM controller as well. From the datasheet > > > the table "Frequency versus Voltage for EMICLK" shows: > > > > > > EMICLK Fmax (MHz) > > > VDDD (V) DDR2 mDDR > > > -------------------------------- > > > 1.550 205.71 205.71 > > > 1.450 196.36 196.36 > > > 1.350 196.36 196.36 > > > > > > jbe > > > > > > [1] > > > i.MX28 Applications > > > Processors for Consumer > > > Products > > > Silicon Version 1.2 > > > > > > Document Number: IMX28CEC > > > Rev. 3, 07/2012 > > > > the only chance that i see to meet this constraint without introducing a > > new cpufreq driver is to change clock ref_cpu > > and ref_emi. > > > > Do you think this solution of a virtual clock [1] can be applied here, too? > > This would imply we can change the SDRAM timing at run-time on the fly. IMHO > that is not possible (at least not easy). it's possible since the cpufreq driver in the FSL can do it. But the code isn't nice and contains some workarounds. > I think when the driver detects the SDRAM controller runs above 196 MHz the > clock for the CPU core can still be > changed, but VDD must be kept at 1.55 V. The cpufreq-dt doesn't know anything about SDRAM controller and i think it isn't necessary if we use 1.55 V for all operating points. > > Juergen Stefan
next prev parent reply other threads:[~2015-03-29 19:09 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-03-28 17:53 [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28 Stefan Wahren 2015-03-29 14:40 ` Juergen Borleis 2015-03-29 14:40 ` Juergen Borleis 2015-03-29 19:09 ` Stefan Wahren [this message] 2015-03-29 19:09 ` Stefan Wahren -- strict thread matches above, loose matches on Subject: below -- 2015-03-22 0:29 [PATCH 0/7] power: enable cpufreq-dt support " Stefan Wahren 2015-03-22 0:30 ` [PATCH 7/7] ARM: dts: add OPPs " Stefan Wahren 2015-03-22 0:30 ` Stefan Wahren 2015-03-24 20:45 ` Juergen Borleis 2015-03-24 20:45 ` Juergen Borleis [not found] ` <201503242145.26370.juergen-vozXLyro3r7AVMDmWPUVSw@public.gmane.org> 2015-03-25 20:20 ` Stefan Wahren 2015-03-25 20:20 ` Stefan Wahren
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