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* Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-28 17:53 Stefan Wahren
  2015-03-29 14:40   ` Juergen Borleis
  0 siblings, 1 reply; 11+ messages in thread
From: Stefan Wahren @ 2015-03-28 17:53 UTC (permalink / raw)
  To: Juergen Borleis, viresh.kumar, Lucas Stach
  Cc: kernel, rjw, dbaryshkov, pawel.moll, galak, robh+dt,
	ijc+devicetree, lgirdwood, shawn.guo, sre, linux-pm,
	fabio.estevam, dwmw2, mark.rutland, sebastien.szymanski, broonie,
	marex, devicetree, linux-arm-kernel

Hi,

> Juergen Borleis <juergen@kreuzholzen.de> hat am 24. März 2015 um 21:45
> geschrieben:
>
>
> Stefan Wahren wrote:
> > [...]
> > diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> > index 98c1be6..21c1921 100644
> > --- a/arch/arm/boot/dts/imx28.dtsi
> > +++ b/arch/arm/boot/dts/imx28.dtsi
> > @@ -38,12 +38,23 @@
> > };
> >
> > cpus {
> > - #address-cells = <0>;
> > + #address-cells = <1>;
> > #size-cells = <0>;
> >
> > - cpu {
> > + cpu@0 {
> > compatible = "arm,arm926ej-s";
> > device_type = "cpu";
> > + reg = <0x0>;
> > + operating-points = <
> > + /* kHz uV */
> > + 261819 1350000
> > + 360000 1350000
> > + 392728 1450000
> > + 454737 1550000
> > + >;
> > + clocks = <&clks 4>;
> > + clock-latency = <61036>; /* two CLK32 periods */
> > + cpu-supply = <&reg_vddd>;
> > };
> > };
>
> Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM
> controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> restrictions. VDD powers the SDRAM controller as well. From the datasheet the
> table "Frequency versus Voltage for EMICLK" shows:
>
> EMICLK Fmax (MHz)
> VDDD (V) DDR2 mDDR
> --------------------------------
> 1.550 205.71 205.71
> 1.450 196.36 196.36
> 1.350 196.36 196.36
>
> jbe
>
> [1]
> i.MX28 Applications
> Processors for Consumer
> Products
> Silicon Version 1.2
>
> Document Number: IMX28CEC
> Rev. 3, 07/2012

the only chance that i see to meet this constraint without introducing a new
cpufreq driver is to change clock ref_cpu
and ref_emi.

Do you think this solution of a virtual clock [1] can be applied here, too?

Best regards
Stefan

[1] -
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-September/290822.html

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
  2015-03-28 17:53 [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28 Stefan Wahren
@ 2015-03-29 14:40   ` Juergen Borleis
  0 siblings, 0 replies; 11+ messages in thread
From: Juergen Borleis @ 2015-03-29 14:40 UTC (permalink / raw)
  To: Stefan Wahren
  Cc: viresh.kumar, Lucas Stach, kernel, rjw, dbaryshkov, pawel.moll,
	galak, robh+dt, ijc+devicetree, lgirdwood, shawn.guo, sre,
	linux-pm, fabio.estevam, dwmw2, mark.rutland,
	sebastien.szymanski, broonie, marex, devicetree,
	linux-arm-kernel

Hi Stefan,

Stefan Wahren wrote:
> > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. März 2015 um 21:45
> > geschrieben:
> >
> > Stefan Wahren wrote:
> > > [...]
> > > diff --git a/arch/arm/boot/dts/imx28.dtsi
> > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644
> > > --- a/arch/arm/boot/dts/imx28.dtsi
> > > +++ b/arch/arm/boot/dts/imx28.dtsi
> > > @@ -38,12 +38,23 @@
> > > };
> > >
> > > cpus {
> > > - #address-cells = <0>;
> > > + #address-cells = <1>;
> > > #size-cells = <0>;
> > >
> > > - cpu {
> > > + cpu@0 {
> > > compatible = "arm,arm926ej-s";
> > > device_type = "cpu";
> > > + reg = <0x0>;
> > > + operating-points = <
> > > + /* kHz uV */
> > > + 261819 1350000
> > > + 360000 1350000
> > > + 392728 1450000
> > > + 454737 1550000
> > > + >;
> > > + clocks = <&clks 4>;
> > > + clock-latency = <61036>; /* two CLK32 periods */
> > > + cpu-supply = <&reg_vddd>;
> > > };
> > > };
> >
> > Maybe you should take into account not to reduce VDD below 1.55 V if the
> > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> > restrictions. VDD powers the SDRAM controller as well. From the datasheet
> > the table "Frequency versus Voltage for EMICLK" shows:
> >
> > EMICLK Fmax (MHz)
> > VDDD (V) DDR2 mDDR
> > --------------------------------
> > 1.550 205.71 205.71
> > 1.450 196.36 196.36
> > 1.350 196.36 196.36
> >
> > jbe
> >
> > [1]
> > i.MX28 Applications
> > Processors for Consumer
> > Products
> > Silicon Version 1.2
> >
> > Document Number: IMX28CEC
> > Rev. 3, 07/2012
>
> the only chance that i see to meet this constraint without introducing a
> new cpufreq driver is to change clock ref_cpu
> and ref_emi.
>
> Do you think this solution of a virtual clock [1] can be applied here, too?

This would imply we can change the SDRAM timing at run-time on the fly. IMHO 
that is not possible (at least not easy). I think when the driver detects the 
SDRAM controller runs above 196 MHz the clock for the CPU core can still be 
changed, but VDD must be kept at 1.55 V.

Juergen

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-29 14:40   ` Juergen Borleis
  0 siblings, 0 replies; 11+ messages in thread
From: Juergen Borleis @ 2015-03-29 14:40 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Stefan,

Stefan Wahren wrote:
> > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. M?rz 2015 um 21:45
> > geschrieben:
> >
> > Stefan Wahren wrote:
> > > [...]
> > > diff --git a/arch/arm/boot/dts/imx28.dtsi
> > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644
> > > --- a/arch/arm/boot/dts/imx28.dtsi
> > > +++ b/arch/arm/boot/dts/imx28.dtsi
> > > @@ -38,12 +38,23 @@
> > > };
> > >
> > > cpus {
> > > - #address-cells = <0>;
> > > + #address-cells = <1>;
> > > #size-cells = <0>;
> > >
> > > - cpu {
> > > + cpu at 0 {
> > > compatible = "arm,arm926ej-s";
> > > device_type = "cpu";
> > > + reg = <0x0>;
> > > + operating-points = <
> > > + /* kHz uV */
> > > + 261819 1350000
> > > + 360000 1350000
> > > + 392728 1450000
> > > + 454737 1550000
> > > + >;
> > > + clocks = <&clks 4>;
> > > + clock-latency = <61036>; /* two CLK32 periods */
> > > + cpu-supply = <&reg_vddd>;
> > > };
> > > };
> >
> > Maybe you should take into account not to reduce VDD below 1.55 V if the
> > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> > restrictions. VDD powers the SDRAM controller as well. From the datasheet
> > the table "Frequency versus Voltage for EMICLK" shows:
> >
> > EMICLK Fmax (MHz)
> > VDDD (V) DDR2 mDDR
> > --------------------------------
> > 1.550 205.71 205.71
> > 1.450 196.36 196.36
> > 1.350 196.36 196.36
> >
> > jbe
> >
> > [1]
> > i.MX28 Applications
> > Processors for Consumer
> > Products
> > Silicon Version 1.2
> >
> > Document Number: IMX28CEC
> > Rev. 3, 07/2012
>
> the only chance that i see to meet this constraint without introducing a
> new cpufreq driver is to change clock ref_cpu
> and ref_emi.
>
> Do you think this solution of a virtual clock [1] can be applied here, too?

This would imply we can change the SDRAM timing at run-time on the fly. IMHO 
that is not possible (at least not easy). I think when the driver detects the 
SDRAM controller runs above 196 MHz the clock for the CPU core can still be 
changed, but VDD must be kept at 1.55 V.

Juergen

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
  2015-03-29 14:40   ` Juergen Borleis
@ 2015-03-29 19:09     ` Stefan Wahren
  -1 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-29 19:09 UTC (permalink / raw)
  To: Juergen Borleis
  Cc: dbaryshkov, rjw, kernel, pawel.moll, lgirdwood, ijc+devicetree,
	robh+dt, galak, shawn.guo, sre, linux-pm, linux-arm-kernel,
	fabio.estevam, dwmw2, Lucas Stach, viresh.kumar, mark.rutland,
	sebastien.szymanski, broonie, marex, devicetree

Hi Juergen,

> Juergen Borleis <juergen@kreuzholzen.de> hat am 29. März 2015 um 16:40
> geschrieben:
>
>
> Hi Stefan,
>
> Stefan Wahren wrote:
> > > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. März 2015 um 21:45
> > > geschrieben:
> > >
> > > Stefan Wahren wrote:
> > > > [...]
> > > > diff --git a/arch/arm/boot/dts/imx28.dtsi
> > > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644
> > > > --- a/arch/arm/boot/dts/imx28.dtsi
> > > > +++ b/arch/arm/boot/dts/imx28.dtsi
> > > > @@ -38,12 +38,23 @@
> > > > };
> > > >
> > > > cpus {
> > > > - #address-cells = <0>;
> > > > + #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > - cpu {
> > > > + cpu@0 {
> > > > compatible = "arm,arm926ej-s";
> > > > device_type = "cpu";
> > > > + reg = <0x0>;
> > > > + operating-points = <
> > > > + /* kHz uV */
> > > > + 261819 1350000
> > > > + 360000 1350000
> > > > + 392728 1450000
> > > > + 454737 1550000
> > > > + >;
> > > > + clocks = <&clks 4>;
> > > > + clock-latency = <61036>; /* two CLK32 periods */
> > > > + cpu-supply = <&reg_vddd>;
> > > > };
> > > > };
> > >
> > > Maybe you should take into account not to reduce VDD below 1.55 V if the
> > > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> > > restrictions. VDD powers the SDRAM controller as well. From the datasheet
> > > the table "Frequency versus Voltage for EMICLK" shows:
> > >
> > > EMICLK Fmax (MHz)
> > > VDDD (V) DDR2 mDDR
> > > --------------------------------
> > > 1.550 205.71 205.71
> > > 1.450 196.36 196.36
> > > 1.350 196.36 196.36
> > >
> > > jbe
> > >
> > > [1]
> > > i.MX28 Applications
> > > Processors for Consumer
> > > Products
> > > Silicon Version 1.2
> > >
> > > Document Number: IMX28CEC
> > > Rev. 3, 07/2012
> >
> > the only chance that i see to meet this constraint without introducing a
> > new cpufreq driver is to change clock ref_cpu
> > and ref_emi.
> >
> > Do you think this solution of a virtual clock [1] can be applied here, too?
>
> This would imply we can change the SDRAM timing at run-time on the fly. IMHO
> that is not possible (at least not easy).

it's possible since the cpufreq driver in the FSL can do it. But the code isn't
nice and contains some workarounds.

> I think when the driver detects the SDRAM controller runs above 196 MHz the
> clock for the CPU core can still be
> changed, but VDD must be kept at 1.55 V.

The cpufreq-dt doesn't know anything about SDRAM controller and i think it isn't
necessary if we use 1.55 V for all
operating points.

>
> Juergen

Stefan

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-29 19:09     ` Stefan Wahren
  0 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-29 19:09 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Juergen,

> Juergen Borleis <juergen@kreuzholzen.de> hat am 29. M?rz 2015 um 16:40
> geschrieben:
>
>
> Hi Stefan,
>
> Stefan Wahren wrote:
> > > Juergen Borleis <juergen@kreuzholzen.de> hat am 24. M?rz 2015 um 21:45
> > > geschrieben:
> > >
> > > Stefan Wahren wrote:
> > > > [...]
> > > > diff --git a/arch/arm/boot/dts/imx28.dtsi
> > > > b/arch/arm/boot/dts/imx28.dtsi index 98c1be6..21c1921 100644
> > > > --- a/arch/arm/boot/dts/imx28.dtsi
> > > > +++ b/arch/arm/boot/dts/imx28.dtsi
> > > > @@ -38,12 +38,23 @@
> > > > };
> > > >
> > > > cpus {
> > > > - #address-cells = <0>;
> > > > + #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > - cpu {
> > > > + cpu at 0 {
> > > > compatible = "arm,arm926ej-s";
> > > > device_type = "cpu";
> > > > + reg = <0x0>;
> > > > + operating-points = <
> > > > + /* kHz uV */
> > > > + 261819 1350000
> > > > + 360000 1350000
> > > > + 392728 1450000
> > > > + 454737 1550000
> > > > + >;
> > > > + clocks = <&clks 4>;
> > > > + clock-latency = <61036>; /* two CLK32 periods */
> > > > + cpu-supply = <&reg_vddd>;
> > > > };
> > > > };
> > >
> > > Maybe you should take into account not to reduce VDD below 1.55 V if the
> > > SDRAM controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> > > restrictions. VDD powers the SDRAM controller as well. From the datasheet
> > > the table "Frequency versus Voltage for EMICLK" shows:
> > >
> > > EMICLK Fmax (MHz)
> > > VDDD (V) DDR2 mDDR
> > > --------------------------------
> > > 1.550 205.71 205.71
> > > 1.450 196.36 196.36
> > > 1.350 196.36 196.36
> > >
> > > jbe
> > >
> > > [1]
> > > i.MX28 Applications
> > > Processors for Consumer
> > > Products
> > > Silicon Version 1.2
> > >
> > > Document Number: IMX28CEC
> > > Rev. 3, 07/2012
> >
> > the only chance that i see to meet this constraint without introducing a
> > new cpufreq driver is to change clock ref_cpu
> > and ref_emi.
> >
> > Do you think this solution of a virtual clock [1] can be applied here, too?
>
> This would imply we can change the SDRAM timing at run-time on the fly. IMHO
> that is not possible (at least not easy).

it's possible since the cpufreq driver in the FSL can do it. But the code isn't
nice and contains some workarounds.

> I think when the driver detects the SDRAM controller runs above 196 MHz the
> clock for the CPU core can still be
> changed, but VDD must be kept at 1.55 V.

The cpufreq-dt doesn't know anything about SDRAM controller and i think it isn't
necessary if we use 1.55 V for all
operating points.

>
> Juergen

Stefan

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
  2015-03-24 20:45     ` Juergen Borleis
@ 2015-03-25 20:20         ` Stefan Wahren
  -1 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-25 20:20 UTC (permalink / raw)
  To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Juergen Borleis
  Cc: kernel-bIcnvbaLZ9MEGnE8C9+IrQ, rjw-LthD3rsA81gm4RdzfppkhA,
	dbaryshkov-Re5JQEeQqe8AvxtiuMwx3w, pawel.moll-5wv7dgnIgG8,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
	shawn.guo-QSEj5FYQhm4dnm+yROfE0A, sre-DgEjT+Ai2ygdnm+yROfE0A,
	linux-pm-u79uwXL29TY76Z2rM5mHXA,
	fabio.estevam-KZfg59tc24xl57MIdRCFDg,
	dwmw2-wEGCiKHe2LqWVfeAwA7xHQ,
	viresh.kumar-QSEj5FYQhm4dnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	sebastien.szymanski-d2DlULPkwbNWk0Htik3J/w,
	broonie-DgEjT+Ai2ygdnm+yROfE0A, marex-ynQEQJNshbs,
	devicetree-u79uwXL29TY76Z2rM5mHXA

Hi Juergen,

> Juergen Borleis <juergen-vozXLyro3r7AVMDmWPUVSw@public.gmane.org> hat am 24. März 2015 um 21:45
> geschrieben:
>
>
> Stefan Wahren wrote:
> > [...]
> 
> Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM
> controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> restrictions. VDD powers the SDRAM controller as well. From the datasheet the
> table "Frequency versus Voltage for EMICLK" shows:
>
> EMICLK Fmax (MHz)
> VDDD (V) DDR2 mDDR
> --------------------------------
> 1.550 205.71 205.71
> 1.450 196.36 196.36
> 1.350 196.36 196.36
>
> jbe
>
> [1]
> i.MX28 Applications
> Processors for Consumer
> Products
> Silicon Version 1.2
>
> Document Number: IMX28CEC
> Rev. 3, 07/2012

thanks for pointing out. I will take care of it.

Stefan
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^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-25 20:20         ` Stefan Wahren
  0 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-25 20:20 UTC (permalink / raw)
  To: linux-arm-kernel

Hi Juergen,

> Juergen Borleis <juergen@kreuzholzen.de> hat am 24. M?rz 2015 um 21:45
> geschrieben:
>
>
> Stefan Wahren wrote:
> > [...]
> 
> Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM
> controller runs above 196 MHz. The i.MX28 datasheet[1] lists these
> restrictions. VDD powers the SDRAM controller as well. From the datasheet the
> table "Frequency versus Voltage for EMICLK" shows:
>
> EMICLK Fmax (MHz)
> VDDD (V) DDR2 mDDR
> --------------------------------
> 1.550 205.71 205.71
> 1.450 196.36 196.36
> 1.350 196.36 196.36
>
> jbe
>
> [1]
> i.MX28 Applications
> Processors for Consumer
> Products
> Silicon Version 1.2
>
> Document Number: IMX28CEC
> Rev. 3, 07/2012

thanks for pointing out. I will take care of it.

Stefan

^ permalink raw reply	[flat|nested] 11+ messages in thread
* Re: [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
  2015-03-22  0:30   ` Stefan Wahren
@ 2015-03-24 20:45     ` Juergen Borleis
  -1 siblings, 0 replies; 11+ messages in thread
From: Juergen Borleis @ 2015-03-24 20:45 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Stefan Wahren, mark.rutland, marex, fabio.estevam, pawel.moll,
	ijc+devicetree, dbaryshkov, viresh.kumar, linux-pm, rjw, sre,
	robh+dt, lgirdwood, devicetree, broonie, kernel, galak,
	sebastien.szymanski, shawn.guo, dwmw2

Stefan Wahren wrote:
> [...]
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 98c1be6..21c1921 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -38,12 +38,23 @@
>  	};
>
>  	cpus {
> -		#address-cells = <0>;
> +		#address-cells = <1>;
>  		#size-cells = <0>;
>
> -		cpu {
> +		cpu@0 {
>  			compatible = "arm,arm926ej-s";
>  			device_type = "cpu";
> +			reg = <0x0>;
> +			operating-points = <
> +				/* kHz	uV */
> +				261819  1350000
> +				360000  1350000
> +				392728  1450000
> +				454737  1550000
> +			>;
> +			clocks = <&clks 4>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			cpu-supply = <&reg_vddd>;
>  		};
>  	};

Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM 
controller runs above 196 MHz. The i.MX28 datasheet[1] lists these 
restrictions. VDD powers the SDRAM controller as well. From the datasheet the 
table "Frequency versus Voltage for EMICLK" shows:
                     
             EMICLK Fmax (MHz)
VDDD (V)      DDR2       mDDR
--------------------------------
 1.550       205.71     205.71
 1.450       196.36     196.36
 1.350       196.36     196.36

jbe

[1]
  i.MX28 Applications
Processors for Consumer
     Products
  Silicon Version 1.2

Document Number: IMX28CEC
   Rev. 3, 07/2012

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-24 20:45     ` Juergen Borleis
  0 siblings, 0 replies; 11+ messages in thread
From: Juergen Borleis @ 2015-03-24 20:45 UTC (permalink / raw)
  To: linux-arm-kernel

Stefan Wahren wrote:
> [...]
> diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
> index 98c1be6..21c1921 100644
> --- a/arch/arm/boot/dts/imx28.dtsi
> +++ b/arch/arm/boot/dts/imx28.dtsi
> @@ -38,12 +38,23 @@
>  	};
>
>  	cpus {
> -		#address-cells = <0>;
> +		#address-cells = <1>;
>  		#size-cells = <0>;
>
> -		cpu {
> +		cpu at 0 {
>  			compatible = "arm,arm926ej-s";
>  			device_type = "cpu";
> +			reg = <0x0>;
> +			operating-points = <
> +				/* kHz	uV */
> +				261819  1350000
> +				360000  1350000
> +				392728  1450000
> +				454737  1550000
> +			>;
> +			clocks = <&clks 4>;
> +			clock-latency = <61036>; /* two CLK32 periods */
> +			cpu-supply = <&reg_vddd>;
>  		};
>  	};

Maybe you should take into account not to reduce VDD below 1.55 V if the SDRAM 
controller runs above 196 MHz. The i.MX28 datasheet[1] lists these 
restrictions. VDD powers the SDRAM controller as well. From the datasheet the 
table "Frequency versus Voltage for EMICLK" shows:
                     
             EMICLK Fmax (MHz)
VDDD (V)      DDR2       mDDR
--------------------------------
 1.550       205.71     205.71
 1.450       196.36     196.36
 1.350       196.36     196.36

jbe

[1]
  i.MX28 Applications
Processors for Consumer
     Products
  Silicon Version 1.2

Document Number: IMX28CEC
   Rev. 3, 07/2012

^ permalink raw reply	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
  2015-03-22  0:29 [PATCH 0/7] power: enable cpufreq-dt support " Stefan Wahren
@ 2015-03-22  0:30   ` Stefan Wahren
  0 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-22  0:30 UTC (permalink / raw)
  To: shawn.guo, sre, dbaryshkov, dwmw2, broonie, lgirdwood,
	mark.rutland, pawel.moll, ijc+devicetree, robh+dt, galak
  Cc: fabio.estevam, marex, devicetree, viresh.kumar, linux-pm, rjw,
	Stefan Wahren, kernel, sebastien.szymanski, linux-arm-kernel

This patch adds the OPPs for i.MX23/i.MX28 which are necessary
for cpufreq support.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
 arch/arm/boot/dts/imx23.dtsi |   15 +++++++++++++--
 arch/arm/boot/dts/imx28.dtsi |   15 +++++++++++++--
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index be0aee8..885c79c 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -27,12 +27,23 @@
 	};
 
 	cpus {
-		#address-cells = <0>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu {
+		cpu@0 {
 			compatible = "arm,arm926ej-s";
 			device_type = "cpu";
+			reg = <0x0>;
+			operating-points = <
+				/* kHz	uV */
+				261819  1350000
+				360000  1350000
+				392728  1450000
+				454737  1550000
+			>;
+			clocks = <&clks 2>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			cpu-supply = <&reg_vddd>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 98c1be6..21c1921 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -38,12 +38,23 @@
 	};
 
 	cpus {
-		#address-cells = <0>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu {
+		cpu@0 {
 			compatible = "arm,arm926ej-s";
 			device_type = "cpu";
+			reg = <0x0>;
+			operating-points = <
+				/* kHz	uV */
+				261819  1350000
+				360000  1350000
+				392728  1450000
+				454737  1550000
+			>;
+			clocks = <&clks 4>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			cpu-supply = <&reg_vddd>;
 		};
 	};
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28
@ 2015-03-22  0:30   ` Stefan Wahren
  0 siblings, 0 replies; 11+ messages in thread
From: Stefan Wahren @ 2015-03-22  0:30 UTC (permalink / raw)
  To: linux-arm-kernel

This patch adds the OPPs for i.MX23/i.MX28 which are necessary
for cpufreq support.

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
 arch/arm/boot/dts/imx23.dtsi |   15 +++++++++++++--
 arch/arm/boot/dts/imx28.dtsi |   15 +++++++++++++--
 2 files changed, 26 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index be0aee8..885c79c 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -27,12 +27,23 @@
 	};
 
 	cpus {
-		#address-cells = <0>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu {
+		cpu at 0 {
 			compatible = "arm,arm926ej-s";
 			device_type = "cpu";
+			reg = <0x0>;
+			operating-points = <
+				/* kHz	uV */
+				261819  1350000
+				360000  1350000
+				392728  1450000
+				454737  1550000
+			>;
+			clocks = <&clks 2>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			cpu-supply = <&reg_vddd>;
 		};
 	};
 
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 98c1be6..21c1921 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -38,12 +38,23 @@
 	};
 
 	cpus {
-		#address-cells = <0>;
+		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu {
+		cpu at 0 {
 			compatible = "arm,arm926ej-s";
 			device_type = "cpu";
+			reg = <0x0>;
+			operating-points = <
+				/* kHz	uV */
+				261819  1350000
+				360000  1350000
+				392728  1450000
+				454737  1550000
+			>;
+			clocks = <&clks 4>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			cpu-supply = <&reg_vddd>;
 		};
 	};
 
-- 
1.7.9.5

^ permalink raw reply related	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-03-29 19:09 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-28 17:53 [PATCH 7/7] ARM: dts: add OPPs for i.MX23/i.MX28 Stefan Wahren
2015-03-29 14:40 ` Juergen Borleis
2015-03-29 14:40   ` Juergen Borleis
2015-03-29 19:09   ` Stefan Wahren
2015-03-29 19:09     ` Stefan Wahren
  -- strict thread matches above, loose matches on Subject: below --
2015-03-22  0:29 [PATCH 0/7] power: enable cpufreq-dt support " Stefan Wahren
2015-03-22  0:30 ` [PATCH 7/7] ARM: dts: add OPPs " Stefan Wahren
2015-03-22  0:30   ` Stefan Wahren
2015-03-24 20:45   ` Juergen Borleis
2015-03-24 20:45     ` Juergen Borleis
     [not found]     ` <201503242145.26370.juergen-vozXLyro3r7AVMDmWPUVSw@public.gmane.org>
2015-03-25 20:20       ` Stefan Wahren
2015-03-25 20:20         ` Stefan Wahren

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