From: Chris Wilson <chris@chris-wilson.co.uk> To: Ivan Bulatovic <combuster@gmx.com> Cc: Chris Wilson <chris@chris-wilson.co.uk>, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, jbarnes@virtuousgeek.org, eric@anholt.net, penberg@kernel.org Subject: [PATCH] drm/i915/tv: Flush register writes before sleeping. Date: Tue, 24 Aug 2010 10:21:17 +0100 [thread overview] Message-ID: <1282641677-27378-1-git-send-email-chris@chris-wilson.co.uk> (raw) In-Reply-To: <1282641126.2259.15.camel@localhost.localdomain> Ivan, can you try this patch? Linus is going to make some more snide comments if he sees just how many of these trivial-ish patches that I have pending... --- If we need to wait until the next vblank for the register to be updated and to take effect, make sure the write is actually flushed to the register prior to sleeping. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_tv.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index d2029ef..19b9739 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1157,10 +1157,13 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); /* Wait for vblank for the disable to take effect */ - if (!IS_I9XX(dev)) + if (!IS_I9XX(dev)) { + POSTING_READ(dspbase_reg); intel_wait_for_vblank(dev, intel_crtc->pipe); + } I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE); + POSTING_READ(pipeconf_reg); /* Wait for vblank for the disable to take effect. */ intel_wait_for_vblank(dev, intel_crtc->pipe); @@ -1268,11 +1271,15 @@ intel_tv_detect_type (struct intel_tv *intel_tv) DAC_C_0_7_V); I915_WRITE(TV_CTL, tv_ctl); I915_WRITE(TV_DAC, tv_dac); + POSTING_READ(TV_DAC); intel_wait_for_vblank(dev, intel_crtc->pipe); + tv_dac = I915_READ(TV_DAC); I915_WRITE(TV_DAC, save_tv_dac); I915_WRITE(TV_CTL, save_tv_ctl); + POSTING_READ(TV_CTL); intel_wait_for_vblank(dev, intel_crtc->pipe); + /* * A B C * 0 1 1 Composite -- 1.7.1
WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk> To: Ivan Bulatovic <combuster@gmx.com> Cc: linux-kernel@vger.kernel.org, penberg@kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH] drm/i915/tv: Flush register writes before sleeping. Date: Tue, 24 Aug 2010 10:21:17 +0100 [thread overview] Message-ID: <1282641677-27378-1-git-send-email-chris@chris-wilson.co.uk> (raw) In-Reply-To: <1282641126.2259.15.camel@localhost.localdomain> Ivan, can you try this patch? Linus is going to make some more snide comments if he sees just how many of these trivial-ish patches that I have pending... --- If we need to wait until the next vblank for the register to be updated and to take effect, make sure the write is actually flushed to the register prior to sleeping. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/intel_tv.c | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index d2029ef..19b9739 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1157,10 +1157,13 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, I915_WRITE(dspbase_reg, I915_READ(dspbase_reg)); /* Wait for vblank for the disable to take effect */ - if (!IS_I9XX(dev)) + if (!IS_I9XX(dev)) { + POSTING_READ(dspbase_reg); intel_wait_for_vblank(dev, intel_crtc->pipe); + } I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE); + POSTING_READ(pipeconf_reg); /* Wait for vblank for the disable to take effect. */ intel_wait_for_vblank(dev, intel_crtc->pipe); @@ -1268,11 +1271,15 @@ intel_tv_detect_type (struct intel_tv *intel_tv) DAC_C_0_7_V); I915_WRITE(TV_CTL, tv_ctl); I915_WRITE(TV_DAC, tv_dac); + POSTING_READ(TV_DAC); intel_wait_for_vblank(dev, intel_crtc->pipe); + tv_dac = I915_READ(TV_DAC); I915_WRITE(TV_DAC, save_tv_dac); I915_WRITE(TV_CTL, save_tv_ctl); + POSTING_READ(TV_CTL); intel_wait_for_vblank(dev, intel_crtc->pipe); + /* * A B C * 0 1 1 Composite -- 1.7.1
next prev parent reply other threads:[~2010-08-24 9:59 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2010-08-24 1:00 i915: 2.6.36-rc2 wrong resolution on gdm start Ivan Bulatovic 2010-08-24 7:49 ` Chris Wilson 2010-08-24 7:49 ` Chris Wilson 2010-08-24 8:35 ` Ivan Bulatovic 2010-08-24 8:50 ` Chris Wilson 2010-08-24 8:50 ` Chris Wilson 2010-08-24 9:12 ` Ivan Bulatovic 2010-08-24 9:21 ` Chris Wilson [this message] 2010-08-24 9:21 ` [PATCH] drm/i915/tv: Flush register writes before sleeping Chris Wilson 2010-08-24 11:03 ` Ivan Bulatovic 2010-08-24 15:11 ` [PATCH] drm/i915/tv: After disabling the pipe, use wait_for_vblank_off() Chris Wilson 2010-08-24 21:08 ` Ivan Bulatovic 2010-08-24 21:52 ` Chris Wilson 2010-08-24 23:00 ` Ivan Bulatovic 2010-08-24 23:04 ` Ivan Bulatovic 2010-08-24 23:05 ` Jesse Barnes 2010-08-24 23:06 ` Ivan Bulatovic 2010-08-25 8:15 ` Sitsofe Wheeler 2010-08-25 9:17 ` Ivan Bulatovic 2010-08-25 9:31 ` Ivan Bulatovic 2010-08-25 9:51 ` Kan-Ru Chen 2010-08-29 11:29 ` i915: 2.6.36-rc2 wrong resolution on gdm start Pekka Enberg 2010-08-29 13:37 ` Sitsofe Wheeler 2010-08-24 8:54 ` Pekka Enberg 2010-08-24 8:54 ` Pekka Enberg 2010-08-29 12:59 ` Maciej Rutecki 2010-08-29 12:59 ` Maciej Rutecki -- strict thread matches above, loose matches on Subject: below -- 2010-08-15 14:56 [PATCH] drm/i915/tv: Flush register writes before sleeping Chris Wilson
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