From: Stepan Moskovchenko <stepanm@codeaurora.org> To: dwalker@codeaurora.org Cc: davidb@codeaurora.org, bryanh@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stepan Moskovchenko <stepanm@codeaurora.org> Subject: [PATCH 12/14] msm: iommu: Definitions for extended memory attributes Date: Fri, 12 Nov 2010 19:29:58 -0800 [thread overview] Message-ID: <1289619000-13167-13-git-send-email-stepanm@codeaurora.org> (raw) In-Reply-To: <1289619000-13167-1-git-send-email-stepanm@codeaurora.org> Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> --- arch/arm/mach-msm/include/mach/iommu.h | 11 +++++++++++ arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | 22 +++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 17fc79f..bfc80c8 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -20,6 +20,17 @@ #include <linux/interrupt.h> +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + + /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect * performance, but there is a practical limit on how many distinct MIDs may diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3..c2c3da9 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -54,6 +54,7 @@ do { \ #define NUM_FL_PTE 4096 #define NUM_SL_PTE 256 +#define NUM_TEX_CLASS 8 /* First-level page table bits */ #define FL_BASE_MASK 0xFFFFFC00 @@ -63,6 +64,9 @@ do { \ #define FL_AP_WRITE (1 << 10) #define FL_AP_READ (1 << 11) #define FL_SHARED (1 << 16) +#define FL_BUFFERABLE (1 << 2) +#define FL_CACHEABLE (1 << 3) +#define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) /* Second-level page table bits */ @@ -73,8 +77,20 @@ do { \ #define SL_AP0 (1 << 4) #define SL_AP1 (2 << 4) #define SL_SHARED (1 << 10) +#define SL_BUFFERABLE (1 << 2) +#define SL_CACHEABLE (1 << 3) +#define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +/* Memory type and cache policy attributes */ +#define MT_SO 0 +#define MT_DEV 1 +#define MT_NORMAL 2 +#define CP_NONCACHED 0 +#define CP_WB_WA 1 +#define CP_WT 2 +#define CP_WB_NWA 3 + /* Global register setters / getters */ #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) @@ -706,7 +722,9 @@ do { \ #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) - +#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) +#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ + ((n) * 2 + 16)) /* PAR */ #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) @@ -750,6 +768,8 @@ do { \ #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) +#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) +#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) /* RESUME */ -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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From: stepanm@codeaurora.org (Stepan Moskovchenko) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 12/14] msm: iommu: Definitions for extended memory attributes Date: Fri, 12 Nov 2010 19:29:58 -0800 [thread overview] Message-ID: <1289619000-13167-13-git-send-email-stepanm@codeaurora.org> (raw) In-Reply-To: <1289619000-13167-1-git-send-email-stepanm@codeaurora.org> Add the register field definitions and memory attribute definitions that will be needed to support IOMMU transactions with cache-coherent memory access. Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org> --- arch/arm/mach-msm/include/mach/iommu.h | 11 +++++++++++ arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h | 22 +++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 17fc79f..bfc80c8 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -20,6 +20,17 @@ #include <linux/interrupt.h> +/* Sharability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NON_SH 0x0 +#define MSM_IOMMU_ATTR_SH 0x4 + +/* Cacheability attributes of MSM IOMMU mappings */ +#define MSM_IOMMU_ATTR_NONCACHED 0x0 +#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 +#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 +#define MSM_IOMMU_ATTR_CACHED_WT 0x3 + + /* Maximum number of Machine IDs that we are allowing to be mapped to the same * context bank. The number of MIDs mapped to the same CB does not affect * performance, but there is a practical limit on how many distinct MIDs may diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h index f9386d3..c2c3da9 100644 --- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h +++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h @@ -54,6 +54,7 @@ do { \ #define NUM_FL_PTE 4096 #define NUM_SL_PTE 256 +#define NUM_TEX_CLASS 8 /* First-level page table bits */ #define FL_BASE_MASK 0xFFFFFC00 @@ -63,6 +64,9 @@ do { \ #define FL_AP_WRITE (1 << 10) #define FL_AP_READ (1 << 11) #define FL_SHARED (1 << 16) +#define FL_BUFFERABLE (1 << 2) +#define FL_CACHEABLE (1 << 3) +#define FL_TEX0 (1 << 12) #define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20) /* Second-level page table bits */ @@ -73,8 +77,20 @@ do { \ #define SL_AP0 (1 << 4) #define SL_AP1 (2 << 4) #define SL_SHARED (1 << 10) +#define SL_BUFFERABLE (1 << 2) +#define SL_CACHEABLE (1 << 3) +#define SL_TEX0 (1 << 6) #define SL_OFFSET(va) (((va) & 0xFF000) >> 12) +/* Memory type and cache policy attributes */ +#define MT_SO 0 +#define MT_DEV 1 +#define MT_NORMAL 2 +#define CP_NONCACHED 0 +#define CP_WB_WA 1 +#define CP_WT 2 +#define CP_WB_NWA 3 + /* Global register setters / getters */ #define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v)) #define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v)) @@ -706,7 +722,9 @@ do { \ #define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5) #define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6) #define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7) - +#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2)) +#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \ + ((n) * 2 + 16)) /* PAR */ #define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT) @@ -750,6 +768,8 @@ do { \ #define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5) #define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6) #define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7) +#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0) +#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2))) /* RESUME */ -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
next prev parent reply other threads:[~2010-11-13 3:30 UTC|newest] Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top 2010-11-13 3:29 [PATCH 00/14] Improvements to the MSM IOMMU driver Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 01/14] msm: iommu: Increase maximum MID size to 5 bits Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 02/14] msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 03/14] msm: iommu: Use more consistent naming in platform data Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 04/14] msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 05/14] msm: iommu: Revise GFX2D0 " Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 06/14] msm: iommu: Support for the 2nd GFX core's IOMMU Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 07/14] msm: iommu: Mark functions with the right section names Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 08/14] msm: iommu: Don't flush page tables if no devices attached Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 09/14] msm: iommu: Kconfig option for cacheable page tables Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-14 20:17 ` Daniel Walker 2010-11-14 20:17 ` Daniel Walker 2010-11-15 2:56 ` Stepan Moskovchenko 2010-11-15 2:56 ` Stepan Moskovchenko 2010-11-15 2:56 ` Stepan Moskovchenko 2010-11-15 18:20 ` Daniel Walker 2010-11-15 18:20 ` Daniel Walker 2010-11-15 18:20 ` Daniel Walker 2010-11-16 1:47 ` Stepan Moskovchenko 2010-11-16 1:47 ` Stepan Moskovchenko 2010-11-16 1:47 ` Stepan Moskovchenko 2010-11-16 1:46 ` [PATCH 09/14 v2] msm: iommu: Kconfig item " Stepan Moskovchenko 2010-11-16 1:46 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 10/14] msm: iommu: Check if device is already attached Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 11/14] msm: iommu: Kconfig dependency for the IOMMU API Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko [this message] 2010-11-13 3:29 ` [PATCH 12/14] msm: iommu: Definitions for extended memory attributes Stepan Moskovchenko 2010-11-16 2:19 ` [PATCH 12/14 v2] " Stepan Moskovchenko 2010-11-16 2:19 ` Stepan Moskovchenko 2010-11-13 3:29 ` [PATCH 13/14] msm: iommu: Support cache-coherent memory access Stepan Moskovchenko 2010-11-13 3:29 ` Stepan Moskovchenko 2010-11-16 2:20 ` [PATCH 13/14 v2] " Stepan Moskovchenko 2010-11-16 2:20 ` Stepan Moskovchenko 2010-11-13 3:30 ` [PATCH 14/14] msm: iommu: Miscellaneous code cleanup Stepan Moskovchenko 2010-11-13 3:30 ` Stepan Moskovchenko 2010-11-16 0:25 ` Daniel Walker 2010-11-16 0:25 ` Daniel Walker 2010-11-16 1:16 ` Stepan Moskovchenko 2010-11-16 1:16 ` Stepan Moskovchenko 2010-11-16 20:45 ` Daniel Walker 2010-11-16 20:45 ` Daniel Walker
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