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From: Andi Kleen <andi@firstfloor.org>
To: a.p.zijlstra@chello.nl
Cc: eranian@google.com, linux-kernel@vger.kernel.org, x86@kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 2/4] perf: Document enhanced event encoding for OFFCORE_MSR
Date: Thu, 18 Nov 2010 11:47:32 +0100	[thread overview]
Message-ID: <1290077254-12165-3-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1290077254-12165-1-git-send-email-andi@firstfloor.org>

From: Andi Kleen <ak@linux.intel.com>

Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
 tools/perf/Documentation/perf-list.txt |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
index 399751b..700afd7 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -58,6 +58,13 @@ raw encoding of 0x1A8 can be used:
  perf stat -e r1a8 -a sleep 1
  perf record -e r1a8 ...
 
+Some special events on x86 encode additional data in the normally unused 
+[32;63] bits of the raw value. This is particularly used for 
+the OFFCORE_RESPONSE events on Intel Core i7.  The 16bit 
+mask in the OFFCORE_RESPONSE register is put into bits [32;48].
+For example the OFFCORE_RESPONSE_0.ANY_DATA.ANY_CACHE_DRAM event
+is encoded as r00007f11004301b7.
+
 You should refer to the processor specific documentation for getting these
 details. Some of them are referenced in the SEE ALSO section below.
 
-- 
1.7.1


  parent reply	other threads:[~2010-11-18 10:47 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-18 10:47 perf offcore patchkit for merge Andi Kleen
2010-11-18 10:47 ` [PATCH 1/4] x86: set cpu masks before calling CPU_STARTING notifiers Andi Kleen
2010-11-18 11:52   ` Thomas Gleixner
2010-11-18 13:39     ` Andi Kleen
2010-11-26 15:05   ` [tip:perf/core] x86: Set " tip-bot for Andi Kleen
2010-11-18 10:47 ` Andi Kleen [this message]
2010-11-18 10:47 ` [PATCH 3/4] perf-events: Add support for supplementary event registers v3 Andi Kleen
2010-11-18 11:12   ` Peter Zijlstra
2010-11-18 11:16     ` Andi Kleen
2010-11-18 11:46       ` Peter Zijlstra
2010-11-26 15:28         ` Peter Zijlstra
2010-11-26 15:30           ` Peter Zijlstra
2010-11-18 12:07   ` Peter Zijlstra
2010-11-22 12:23   ` Lin Ming
2010-11-22 12:47     ` Stephane Eranian
2010-11-22 13:01       ` Lin Ming
2010-12-01 14:27   ` Peter Zijlstra
2010-12-01 16:19     ` Peter Zijlstra
2010-11-18 10:47 ` [PATCH 4/4] perf-events: Fix LLC-* events on Intel Nehalem/Westmere v2 Andi Kleen

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