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From: Peter Zijlstra <a.p.zijlstra@chello.nl>
To: Andi Kleen <andi@firstfloor.org>
Cc: eranian@google.com, linux-kernel@vger.kernel.org, x86@kernel.org,
	Andi Kleen <ak@linux.intel.com>
Subject: Re: [PATCH 3/4] perf-events: Add support for supplementary event registers v3
Date: Wed, 01 Dec 2010 15:27:11 +0100	[thread overview]
Message-ID: <1291213631.32004.1563.camel@laptop> (raw)
In-Reply-To: <1290077254-12165-4-git-send-email-andi@firstfloor.org>

On Thu, 2010-11-18 at 11:47 +0100, Andi Kleen wrote:
> @@ -876,6 +944,8 @@ static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
>                                           u64 enable_mask)
>  {
>         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
> +       if (hwc->extra_reg)
> +               wrmsrl(hwc->extra_reg, hwc->extra_config);
>  } 

I thought we agreed it made more sense to program the extra msr before
enabling the counter.

  parent reply	other threads:[~2010-12-01 14:26 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-11-18 10:47 perf offcore patchkit for merge Andi Kleen
2010-11-18 10:47 ` [PATCH 1/4] x86: set cpu masks before calling CPU_STARTING notifiers Andi Kleen
2010-11-18 11:52   ` Thomas Gleixner
2010-11-18 13:39     ` Andi Kleen
2010-11-26 15:05   ` [tip:perf/core] x86: Set " tip-bot for Andi Kleen
2010-11-18 10:47 ` [PATCH 2/4] perf: Document enhanced event encoding for OFFCORE_MSR Andi Kleen
2010-11-18 10:47 ` [PATCH 3/4] perf-events: Add support for supplementary event registers v3 Andi Kleen
2010-11-18 11:12   ` Peter Zijlstra
2010-11-18 11:16     ` Andi Kleen
2010-11-18 11:46       ` Peter Zijlstra
2010-11-26 15:28         ` Peter Zijlstra
2010-11-26 15:30           ` Peter Zijlstra
2010-11-18 12:07   ` Peter Zijlstra
2010-11-22 12:23   ` Lin Ming
2010-11-22 12:47     ` Stephane Eranian
2010-11-22 13:01       ` Lin Ming
2010-12-01 14:27   ` Peter Zijlstra [this message]
2010-12-01 16:19     ` Peter Zijlstra
2010-11-18 10:47 ` [PATCH 4/4] perf-events: Fix LLC-* events on Intel Nehalem/Westmere v2 Andi Kleen

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