From: Meador Inge <meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org Cc: openmcapi-dev-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, devicetree-discuss-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org, Hollis Blanchard <hollis_blanchard-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> Subject: [PATCH 1/2] powerpc: document the FSL MPIC message register binding Date: Tue, 19 Apr 2011 11:59:34 -0500 [thread overview] Message-ID: <1303232375-25014-2-git-send-email-meador_inge@mentor.com> (raw) In-Reply-To: <1303232375-25014-1-git-send-email-meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> This binding documents how the message register blocks found in some FSL MPIC implementations shall be represented in a device tree. Signed-off-by: Meador Inge <meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> Cc: Hollis Blanchard <hollis_blanchard-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> Cc: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org> Cc: Benjamin Herrenschmidt <benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org> --- .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 71 ++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt new file mode 100644 index 0000000..41f1965 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt @@ -0,0 +1,71 @@ +* FSL MPIC Message Registers + +This binding specifies what properties must be available in the device tree +representation of the message register blocks found in some FSL MPIC +implementations. + +Required properties: + + - compatible: Specifies the compatibility list for the message register + block. The type shall be <string> and the value shall be of the form + "fsl,mpic-v<version>-msgr", where <version> is the version number of + the MPIC containing the message registers. + + - reg: Specifies the base physical address(s) and size(s) of the + message register block's addressable register space. The type shall be + <prop-encoded-array>. + + - interrupts: Specifies a list of interrupt source and level-sense pairs. + The type shall be <prop-encoded-array>. The length shall be equal to + the number of bits set in the 'msg-receive-mask' property value. + + - interrupt-parent: Specifies the interrupt parent of the message register + block. The type shall be a <phandle> and the value of that <phandle> + shall point to the interrupt parent. + +Optional properties: + + - msg-receive-mask: Specifies what registers in the containing block are + allowed to receive interrupts. The value is a bit mask where a set bit + at bit 'n' indicates that message register 'n' can receive interrupts. + The type shall be <prop-encoded-array>. The default value shall be + all a string of consecutive ones where the length of the run is equal + to the number of registers in the block. For example, a block with + four registers shall default to 0xF. + +Required alias: + + In order for a message register block to be discovered it *must* define + an alias in the 'aliases' node. Aliases are of the form 'msgr-block<n>', + where <n> is an integer specifying the block's number. Numbers shall start + at 0. + +Example: + + /* The aliases needed to define an order on the message register blocks. + */ + aliases { + msgr-block0 = &msgr_block0; + msgr-block1 = &msgr_block1; + }; + + msgr_block0: msgr-block@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb0 and 0xb2, respectively. + interrupts = <0xb0 2 0xb2 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + + msgr_block1: msgr-block@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb4 and 0xb6, respectively. + interrupts = <0xb4 2 0xb6 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + -- 1.6.3.3
WARNING: multiple messages have this Message-ID (diff)
From: Meador Inge <meador_inge@mentor.com> To: linuxppc-dev@lists.ozlabs.org Cc: openmcapi-dev@googlegroups.com, devicetree-discuss@lists.ozlabs.org, Hollis Blanchard <hollis_blanchard@mentor.com> Subject: [PATCH 1/2] powerpc: document the FSL MPIC message register binding Date: Tue, 19 Apr 2011 11:59:34 -0500 [thread overview] Message-ID: <1303232375-25014-2-git-send-email-meador_inge@mentor.com> (raw) In-Reply-To: <1303232375-25014-1-git-send-email-meador_inge@mentor.com> This binding documents how the message register blocks found in some FSL MPIC implementations shall be represented in a device tree. Signed-off-by: Meador Inge <meador_inge@mentor.com> Cc: Hollis Blanchard <hollis_blanchard@mentor.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> --- .../devicetree/bindings/powerpc/fsl/mpic-msgr.txt | 71 ++++++++++++++++++++ 1 files changed, 71 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt new file mode 100644 index 0000000..41f1965 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/mpic-msgr.txt @@ -0,0 +1,71 @@ +* FSL MPIC Message Registers + +This binding specifies what properties must be available in the device tree +representation of the message register blocks found in some FSL MPIC +implementations. + +Required properties: + + - compatible: Specifies the compatibility list for the message register + block. The type shall be <string> and the value shall be of the form + "fsl,mpic-v<version>-msgr", where <version> is the version number of + the MPIC containing the message registers. + + - reg: Specifies the base physical address(s) and size(s) of the + message register block's addressable register space. The type shall be + <prop-encoded-array>. + + - interrupts: Specifies a list of interrupt source and level-sense pairs. + The type shall be <prop-encoded-array>. The length shall be equal to + the number of bits set in the 'msg-receive-mask' property value. + + - interrupt-parent: Specifies the interrupt parent of the message register + block. The type shall be a <phandle> and the value of that <phandle> + shall point to the interrupt parent. + +Optional properties: + + - msg-receive-mask: Specifies what registers in the containing block are + allowed to receive interrupts. The value is a bit mask where a set bit + at bit 'n' indicates that message register 'n' can receive interrupts. + The type shall be <prop-encoded-array>. The default value shall be + all a string of consecutive ones where the length of the run is equal + to the number of registers in the block. For example, a block with + four registers shall default to 0xF. + +Required alias: + + In order for a message register block to be discovered it *must* define + an alias in the 'aliases' node. Aliases are of the form 'msgr-block<n>', + where <n> is an integer specifying the block's number. Numbers shall start + at 0. + +Example: + + /* The aliases needed to define an order on the message register blocks. + */ + aliases { + msgr-block0 = &msgr_block0; + msgr-block1 = &msgr_block1; + }; + + msgr_block0: msgr-block@41400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x41400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb0 and 0xb2, respectively. + interrupts = <0xb0 2 0xb2 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + + msgr_block1: msgr-block@42400 { + compatible = "fsl,mpic-v3.1-msgr"; + reg = <0x42400 0x200>; + // Message registers 0 and 3 in this block can receive interrupts on + // sources 0xb4 and 0xb6, respectively. + interrupts = <0xb4 2 0xb6 2>; + msg-receive-mask = <0x5>; + interrupt-parent = <&mpic>; + }; + -- 1.6.3.3
next prev parent reply other threads:[~2011-04-19 16:59 UTC|newest] Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top 2011-04-19 16:59 [PATCH 0/2] powerpc: define and implement MPIC message register support Meador Inge 2011-04-19 16:59 ` Meador Inge [not found] ` <1303232375-25014-1-git-send-email-meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> 2011-04-19 16:59 ` Meador Inge [this message] 2011-04-19 16:59 ` [PATCH 1/2] powerpc: document the FSL MPIC message register binding Meador Inge [not found] ` <1303232375-25014-2-git-send-email-meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> 2011-04-19 17:52 ` Scott Wood 2011-04-19 17:52 ` Scott Wood 2011-04-19 18:26 ` Meador Inge 2011-04-19 18:33 ` Scott Wood [not found] ` <20110419133336.46d8566f-1MYqz8GpK7RekFaExTCHk1jVikpgYyvb5NbjCUgZEJk@public.gmane.org> 2011-04-21 19:26 ` Meador Inge 2011-04-21 19:26 ` Meador Inge [not found] ` <4DB084F6.4060103-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> 2011-04-21 19:35 ` Scott Wood 2011-04-21 19:35 ` Scott Wood 2011-04-19 16:59 ` [PATCH 2/2] powerpc: add support for MPIC message register API Meador Inge 2011-04-19 16:59 ` Meador Inge [not found] ` <1303232375-25014-3-git-send-email-meador_inge-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> 2011-04-29 5:00 ` Kushwaha Prabhakar-B32579 2011-04-29 5:00 ` Kushwaha Prabhakar-B32579 2011-04-29 16:54 ` Hollis Blanchard 2011-04-29 17:27 ` Kushwaha Prabhakar-B32579 2011-04-29 17:27 ` Kushwaha Prabhakar-B32579 [not found] ` <071A08F2C6A57E4E94D980ECA553F8741967EC-TcFNo7jSaXM0vywKSws3iq4g8xLGJsHaLnY5E4hWTkheoWH0uzbU5w@public.gmane.org> 2011-04-29 17:30 ` Scott Wood 2011-04-29 17:30 ` Scott Wood [not found] ` <20110429123051.4ed1ca01-1MYqz8GpK7RekFaExTCHk1jVikpgYyvb5NbjCUgZEJk@public.gmane.org> 2011-05-02 3:41 ` Kushwaha Prabhakar-B32579 2011-05-02 3:41 ` Kushwaha Prabhakar-B32579 2011-05-02 16:03 ` Hollis Blanchard [not found] ` <4DBED5E9.2070201-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org> 2011-05-03 15:19 ` Scott Wood 2011-05-03 15:19 ` Scott Wood 2011-05-05 21:41 ` Meador Inge 2011-05-06 19:29 ` Scott Wood [not found] ` <20110506142937.77e7a10f-1MYqz8GpK7RekFaExTCHk1jVikpgYyvb5NbjCUgZEJk@public.gmane.org> 2011-05-06 23:51 ` Meador Inge 2011-05-06 23:51 ` Meador Inge 2012-02-17 2:49 [PATCH 1/2] powerpc: document the FSL MPIC message register binding Jia Hongtao
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