[Qemu-devel] [PATCH 0/3] make endian-independent unaligned memory access functions available in libhw

[Qemu-devel] [PATCH 0/3] make endian-independent unaligned memory access functions available in libhw

[Paolo Bonzini]

Functions like ldl_be_p and ldl_le_p are currently used only as building
blocks for {ld,st}XX_p.  As such, they are in cpu-all.h even though they
have absolutely no dependency on the target.

In order to make them globally available, this series moves them to
bswap.h instead.

An interesting part of this is that there are functions also for floating
point values.  Leaving them in cpu-all.h would be possible but untidy.
In fact handling these is easy, but it requires to split out the few
target-dependent parts of softfloat.h.  This is what patch 2 does.

Paolo Bonzini (3):
  move WORDS_ALIGNED to qemu-common.h
  softfloat: extract softfloat-target.h
  move unaligned memory access functions to bswap.h

 Makefile.hw            |    2 +-
 bswap.h                |  481 ++++++++++++++++++++++++++++++++++++++++++++++++
 configure              |    7 +-
 cpu-all.h              |  453 +---------------------------------------------
 cpu-common.h           |    4 -
 fpu/softfloat-target.h |  119 ++++++++++++
 fpu/softfloat.c        |   11 +-
 fpu/softfloat.h        |   70 +-------
 qemu-common.h          |    4 +
 target-arm/helper.c    |    1 +
 10 files changed, 619 insertions(+), 533 deletions(-)
 create mode 100644 fpu/softfloat-target.h

-- 
1.7.4.4

[Qemu-devel] [PATCH 1/3] move WORDS_ALIGNED to qemu-common.h

[Paolo Bonzini]

This is not a CPU interface.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 cpu-common.h  |    4 ----
 qemu-common.h |    4 ++++
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/cpu-common.h b/cpu-common.h
index 151c32c..3a148b8 100644
--- a/cpu-common.h
+++ b/cpu-common.h
@@ -3,10 +3,6 @@
 
 /* CPU interfaces that are target indpendent.  */
 
-#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
-#define WORDS_ALIGNED
-#endif
-
 #ifdef TARGET_PHYS_ADDR_BITS
 #include "targphys.h"
 #endif
diff --git a/qemu-common.h b/qemu-common.h
index bba8dfe..f7beb0f 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -4,6 +4,10 @@
 
 #include "config-host.h"
 
+#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
+#define WORDS_ALIGNED
+#endif
+
 #define QEMU_NORETURN __attribute__ ((__noreturn__))
 #ifdef CONFIG_GCC_ATTRIBUTE_WARN_UNUSED_RESULT
 #define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
-- 
1.7.4.4

[Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Paolo Bonzini]

Most definitions in softfloat.h are really target-independent.  Split
the few that stand out as target-dependent, to allow including
softfloat.h from files that are not compiled per-target.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 fpu/softfloat-target.h |  119 ++++++++++++++++++++++++++++++++++++++++++++++++
 fpu/softfloat.c        |   11 +++-
 fpu/softfloat.h        |   70 +----------------------------
 target-arm/helper.c    |    1 +
 4 files changed, 129 insertions(+), 72 deletions(-)
 create mode 100644 fpu/softfloat-target.h

diff --git a/fpu/softfloat-target.h b/fpu/softfloat-target.h
new file mode 100644
index 0000000..513542c
--- /dev/null
+++ b/fpu/softfloat-target.h
@@ -0,0 +1,119 @@
+/*
+ * QEMU float support
+ *
+ * Derived from SoftFloat.
+ */
+
+/*============================================================================
+
+This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
+Package, Release 2b.
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+#ifndef SOFTFLOAT_TARGET_H
+#define SOFTFLOAT_TARGET_H
+
+#include "softfloat.h"
+#include "config-target.h"
+
+#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
+#define SNAN_BIT_IS_ONE		1
+#else
+#define SNAN_BIT_IS_ONE		0
+#endif
+
+#ifdef CONFIG_SOFTFLOAT
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated half-precision NaN.
+*----------------------------------------------------------------------------*/
+#if defined(TARGET_ARM)
+#define float16_default_nan make_float16(0x7E00)
+#elif SNAN_BIT_IS_ONE
+#define float16_default_nan make_float16(0x7DFF)
+#else
+#define float16_default_nan make_float16(0xFE00)
+#endif
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated single-precision NaN.
+*----------------------------------------------------------------------------*/
+#if defined(TARGET_SPARC)
+#define float32_default_nan make_float32(0x7FFFFFFF)
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#define float32_default_nan make_float32(0x7FC00000)
+#elif SNAN_BIT_IS_ONE
+#define float32_default_nan make_float32(0x7FBFFFFF)
+#else
+#define float32_default_nan make_float32(0xFFC00000)
+#endif
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated double-precision NaN.
+*----------------------------------------------------------------------------*/
+#if defined(TARGET_SPARC)
+#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
+#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
+#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
+#elif SNAN_BIT_IS_ONE
+#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
+#else
+#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
+#endif
+
+#ifdef FLOATX80
+
+#if SNAN_BIT_IS_ONE
+#define floatx80_default_nan_high 0x7FFF
+#define floatx80_default_nan_low  LIT64( 0xBFFFFFFFFFFFFFFF )
+#else
+#define floatx80_default_nan_high 0xFFFF
+#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )
+#endif
+
+#endif
+
+#ifdef FLOAT128
+
+/*----------------------------------------------------------------------------
+| The pattern for a default generated quadruple-precision NaN.  The `high' and
+| `low' values hold the most- and least-significant bits, respectively.
+*----------------------------------------------------------------------------*/
+#if SNAN_BIT_IS_ONE
+#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
+#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
+#else
+#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
+#define float128_default_nan_low  LIT64( 0x0000000000000000 )
+#endif
+
+#endif
+
+#endif /* !CONFIG_SOFTFLOAT */
+
+#endif /* !SOFTFLOAT_TARGET_H */
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index baba1dc..72aefc5 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -45,12 +45,17 @@ these four paragraphs for those parts of this code that are retained.
 #include "softfloat-macros.h"
 
 /*----------------------------------------------------------------------------
+| Public functions and definitions for the default generated quiet NaNs.
+| This is target-specific.
+*----------------------------------------------------------------------------*/
+#include "softfloat-target.h"
+
+/*----------------------------------------------------------------------------
 | Functions and definitions to determine:  (1) whether tininess for underflow
 | is detected before or after rounding by default, (2) what (if anything)
 | happens when exceptions are raised, (3) how signaling NaNs are distinguished
-| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs
-| are propagated from function inputs to output.  These details are target-
-| specific.
+| from quiet NaNs, and (4) how NaNs are propagated from function inputs to
+| output.  These details are target-specific.
 *----------------------------------------------------------------------------*/
 #include "softfloat-specialize.h"
 
diff --git a/fpu/softfloat.h b/fpu/softfloat.h
index 5eff085..c9e4446 100644
--- a/fpu/softfloat.h
+++ b/fpu/softfloat.h
@@ -43,7 +43,7 @@ these four paragraphs for those parts of this code that are retained.
 #endif
 
 #include <inttypes.h>
-#include "config.h"
+#include "config-host.h"
 
 /*----------------------------------------------------------------------------
 | Each of the following `typedef's defines the most convenient type that holds
@@ -68,12 +68,6 @@ typedef int64_t int64;
 #define LIT64( a ) a##LL
 #define INLINE static inline
 
-#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
-#define SNAN_BIT_IS_ONE		1
-#else
-#define SNAN_BIT_IS_ONE		0
-#endif
-
 /*----------------------------------------------------------------------------
 | The macro `FLOATX80' must be defined to enable the extended double-precision
 | floating-point format `floatx80'.  If this macro is not defined, the
@@ -280,17 +274,6 @@ int float16_is_signaling_nan( float16 );
 float16 float16_maybe_silence_nan( float16 );
 
 /*----------------------------------------------------------------------------
-| The pattern for a default generated half-precision NaN.
-*----------------------------------------------------------------------------*/
-#if defined(TARGET_ARM)
-#define float16_default_nan make_float16(0x7E00)
-#elif SNAN_BIT_IS_ONE
-#define float16_default_nan make_float16(0x7DFF)
-#else
-#define float16_default_nan make_float16(0xFE00)
-#endif
-
-/*----------------------------------------------------------------------------
 | Software IEC/IEEE single-precision conversion routines.
 *----------------------------------------------------------------------------*/
 int16 float32_to_int16_round_to_zero( float32 STATUS_PARAM );
@@ -393,19 +376,6 @@ INLINE float32 float32_set_sign(float32 a, int sign)
 
 
 /*----------------------------------------------------------------------------
-| The pattern for a default generated single-precision NaN.
-*----------------------------------------------------------------------------*/
-#if defined(TARGET_SPARC)
-#define float32_default_nan make_float32(0x7FFFFFFF)
-#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
-#define float32_default_nan make_float32(0x7FC00000)
-#elif SNAN_BIT_IS_ONE
-#define float32_default_nan make_float32(0x7FBFFFFF)
-#else
-#define float32_default_nan make_float32(0xFFC00000)
-#endif
-
-/*----------------------------------------------------------------------------
 | Software IEC/IEEE double-precision conversion routines.
 *----------------------------------------------------------------------------*/
 int16 float64_to_int16_round_to_zero( float64 STATUS_PARAM );
@@ -504,19 +474,6 @@ INLINE float64 float64_set_sign(float64 a, int sign)
 #define float64_half make_float64(0x3fe0000000000000LL)
 #define float64_infinity make_float64(0x7ff0000000000000LL)
 
-/*----------------------------------------------------------------------------
-| The pattern for a default generated double-precision NaN.
-*----------------------------------------------------------------------------*/
-#if defined(TARGET_SPARC)
-#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
-#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
-#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
-#elif SNAN_BIT_IS_ONE
-#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
-#else
-#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
-#endif
-
 #ifdef FLOATX80
 
 /*----------------------------------------------------------------------------
@@ -596,19 +553,6 @@ INLINE int floatx80_is_any_nan(floatx80 a)
 #define floatx80_half make_floatx80(0x3ffe, 0x8000000000000000LL)
 #define floatx80_infinity make_floatx80(0x7fff, 0x8000000000000000LL)
 
-/*----------------------------------------------------------------------------
-| The pattern for a default generated extended double-precision NaN.  The
-| `high' and `low' values hold the most- and least-significant bits,
-| respectively.
-*----------------------------------------------------------------------------*/
-#if SNAN_BIT_IS_ONE
-#define floatx80_default_nan_high 0x7FFF
-#define floatx80_default_nan_low  LIT64( 0xBFFFFFFFFFFFFFFF )
-#else
-#define floatx80_default_nan_high 0xFFFF
-#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )
-#endif
-
 #endif
 
 #ifdef FLOAT128
@@ -684,18 +628,6 @@ INLINE int float128_is_any_nan(float128 a)
         ((a.low != 0) || ((a.high & 0xffffffffffffLL) != 0));
 }
 
-/*----------------------------------------------------------------------------
-| The pattern for a default generated quadruple-precision NaN.  The `high' and
-| `low' values hold the most- and least-significant bits, respectively.
-*----------------------------------------------------------------------------*/
-#if SNAN_BIT_IS_ONE
-#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
-#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
-#else
-#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
-#define float128_default_nan_low  LIT64( 0x0000000000000000 )
-#endif
-
 #endif
 
 #else /* CONFIG_SOFTFLOAT */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 62ae72e..0f15cf3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -8,6 +8,7 @@
 #include "helper.h"
 #include "qemu-common.h"
 #include "host-utils.h"
+#include "softfloat-target.h"
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-- 
1.7.4.4

[Qemu-devel] [PATCH 3/3] move unaligned memory access functions to bswap.h

[Paolo Bonzini]

This is just code movement, and moving the fpu/ include path from
target-dependent to target-independent Make variables.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 Makefile.hw |    2 +-
 bswap.h     |  481 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 configure   |    7 +-
 cpu-all.h   |  453 +-------------------------------------------------------
 4 files changed, 486 insertions(+), 457 deletions(-)

diff --git a/Makefile.hw b/Makefile.hw
index b9181ab..659e441 100644
--- a/Makefile.hw
+++ b/Makefile.hw
@@ -9,7 +9,7 @@ include $(SRC_PATH)/rules.mak
 
 $(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw)
 
-QEMU_CFLAGS+=-I.. -I$(SRC_PATH)/fpu
+QEMU_CFLAGS+=-I..
 
 include $(SRC_PATH)/Makefile.objs
 
diff --git a/bswap.h b/bswap.h
index 82a7951..17de018 100644
--- a/bswap.h
+++ b/bswap.h
@@ -11,6 +11,8 @@
 #include <machine/bswap.h>
 #else
 
+#include "softfloat.h"
+
 #ifdef CONFIG_BYTESWAP_H
 #include <byteswap.h>
 #else
@@ -237,4 +239,483 @@ static inline uint32_t qemu_bswap_len(uint32_t value, int len)
     return bswap32(value) >> (32 - 8 * len);
 }
 
+typedef union {
+    float32 f;
+    uint32_t l;
+} CPU_FloatU;
+
+/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
+   endian ! */
+typedef union {
+    float64 d;
+#if defined(HOST_WORDS_BIGENDIAN) \
+    || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
+    struct {
+        uint32_t upper;
+        uint32_t lower;
+    } l;
+#else
+    struct {
+        uint32_t lower;
+        uint32_t upper;
+    } l;
+#endif
+    uint64_t ll;
+} CPU_DoubleU;
+
+#if defined(FLOATX80)
+typedef union {
+     floatx80 d;
+     struct {
+         uint64_t lower;
+         uint16_t upper;
+     } l;
+} CPU_LDoubleU;
+#endif
+
+#if defined(CONFIG_SOFTFLOAT)
+typedef union {
+    float128 q;
+#if defined(HOST_WORDS_BIGENDIAN)
+    struct {
+        uint32_t upmost;
+        uint32_t upper;
+        uint32_t lower;
+        uint32_t lowest;
+    } l;
+    struct {
+        uint64_t upper;
+        uint64_t lower;
+    } ll;
+#else
+    struct {
+        uint32_t lowest;
+        uint32_t lower;
+        uint32_t upper;
+        uint32_t upmost;
+    } l;
+    struct {
+        uint64_t lower;
+        uint64_t upper;
+    } ll;
+#endif
+} CPU_QuadU;
+#endif
+
+/* unaligned/endian-independent pointer access */
+
+/*
+ * the generic syntax is:
+ *
+ * load: ld{type}{sign}{size}{endian}_p(ptr)
+ *
+ * store: st{type}{size}{endian}_p(ptr, val)
+ *
+ * Note there are small differences with the softmmu access API!
+ *
+ * type is:
+ * (empty): integer access
+ *   f    : float access
+ *
+ * sign is:
+ * (empty): for floats or 32 bit size
+ *   u    : unsigned
+ *   s    : signed
+ *
+ * size is:
+ *   b: 8 bits
+ *   w: 16 bits
+ *   l: 32 bits
+ *   q: 64 bits
+ *
+ * endian is:
+ * (empty): 8 bit access
+ *   be   : big endian
+ *   le   : little endian
+ */
+static inline int ldub_p(const void *ptr)
+{
+    return *(uint8_t *)ptr;
+}
+
+static inline int ldsb_p(const void *ptr)
+{
+    return *(int8_t *)ptr;
+}
+
+static inline void stb_p(void *ptr, int v)
+{
+    *(uint8_t *)ptr = v;
+}
+
+/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
+   kernel handles unaligned load/stores may give better results, but
+   it is a system wide setting : bad */
+#if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
+
+/* conservative code for little endian unaligned accesses */
+static inline int lduw_le_p(const void *ptr)
+{
+#ifdef _ARCH_PPC
+    int val;
+    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
+    return val;
+#else
+    const uint8_t *p = ptr;
+    return p[0] | (p[1] << 8);
+#endif
+}
+
+static inline int ldsw_le_p(const void *ptr)
+{
+#ifdef _ARCH_PPC
+    int val;
+    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
+    return (int16_t)val;
+#else
+    const uint8_t *p = ptr;
+    return (int16_t)(p[0] | (p[1] << 8));
+#endif
+}
+
+static inline int ldl_le_p(const void *ptr)
+{
+#ifdef _ARCH_PPC
+    int val;
+    __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
+    return val;
+#else
+    const uint8_t *p = ptr;
+    return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
+#endif
+}
+
+static inline uint64_t ldq_le_p(const void *ptr)
+{
+    const uint8_t *p = ptr;
+    uint32_t v1, v2;
+    v1 = ldl_le_p(p);
+    v2 = ldl_le_p(p + 4);
+    return v1 | ((uint64_t)v2 << 32);
+}
+
+static inline void stw_le_p(void *ptr, int v)
+{
+#ifdef _ARCH_PPC
+    __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
+#else
+    uint8_t *p = ptr;
+    p[0] = v;
+    p[1] = v >> 8;
+#endif
+}
+
+static inline void stl_le_p(void *ptr, int v)
+{
+#ifdef _ARCH_PPC
+    __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
+#else
+    uint8_t *p = ptr;
+    p[0] = v;
+    p[1] = v >> 8;
+    p[2] = v >> 16;
+    p[3] = v >> 24;
+#endif
+}
+
+static inline void stq_le_p(void *ptr, uint64_t v)
+{
+    uint8_t *p = ptr;
+    stl_le_p(p, (uint32_t)v);
+    stl_le_p(p + 4, v >> 32);
+}
+
+/* float access */
+
+static inline float32 ldfl_le_p(const void *ptr)
+{
+    union {
+        float32 f;
+        uint32_t i;
+    } u;
+    u.i = ldl_le_p(ptr);
+    return u.f;
+}
+
+static inline void stfl_le_p(void *ptr, float32 v)
+{
+    union {
+        float32 f;
+        uint32_t i;
+    } u;
+    u.f = v;
+    stl_le_p(ptr, u.i);
+}
+
+static inline float64 ldfq_le_p(const void *ptr)
+{
+    CPU_DoubleU u;
+    u.l.lower = ldl_le_p(ptr);
+    u.l.upper = ldl_le_p(ptr + 4);
+    return u.d;
+}
+
+static inline void stfq_le_p(void *ptr, float64 v)
+{
+    CPU_DoubleU u;
+    u.d = v;
+    stl_le_p(ptr, u.l.lower);
+    stl_le_p(ptr + 4, u.l.upper);
+}
+
+#else
+
+static inline int lduw_le_p(const void *ptr)
+{
+    return *(uint16_t *)ptr;
+}
+
+static inline int ldsw_le_p(const void *ptr)
+{
+    return *(int16_t *)ptr;
+}
+
+static inline int ldl_le_p(const void *ptr)
+{
+    return *(uint32_t *)ptr;
+}
+
+static inline uint64_t ldq_le_p(const void *ptr)
+{
+    return *(uint64_t *)ptr;
+}
+
+static inline void stw_le_p(void *ptr, int v)
+{
+    *(uint16_t *)ptr = v;
+}
+
+static inline void stl_le_p(void *ptr, int v)
+{
+    *(uint32_t *)ptr = v;
+}
+
+static inline void stq_le_p(void *ptr, uint64_t v)
+{
+    *(uint64_t *)ptr = v;
+}
+
+/* float access */
+
+static inline float32 ldfl_le_p(const void *ptr)
+{
+    return *(float32 *)ptr;
+}
+
+static inline float64 ldfq_le_p(const void *ptr)
+{
+    return *(float64 *)ptr;
+}
+
+static inline void stfl_le_p(void *ptr, float32 v)
+{
+    *(float32 *)ptr = v;
+}
+
+static inline void stfq_le_p(void *ptr, float64 v)
+{
+    *(float64 *)ptr = v;
+}
+#endif
+
+#if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
+
+static inline int lduw_be_p(const void *ptr)
+{
+#if defined(__i386__)
+    int val;
+    asm volatile ("movzwl %1, %0\n"
+                  "xchgb %b0, %h0\n"
+                  : "=q" (val)
+                  : "m" (*(uint16_t *)ptr));
+    return val;
+#else
+    const uint8_t *b = ptr;
+    return ((b[0] << 8) | b[1]);
+#endif
+}
+
+static inline int ldsw_be_p(const void *ptr)
+{
+#if defined(__i386__)
+    int val;
+    asm volatile ("movzwl %1, %0\n"
+                  "xchgb %b0, %h0\n"
+                  : "=q" (val)
+                  : "m" (*(uint16_t *)ptr));
+    return (int16_t)val;
+#else
+    const uint8_t *b = ptr;
+    return (int16_t)((b[0] << 8) | b[1]);
+#endif
+}
+
+static inline int ldl_be_p(const void *ptr)
+{
+#if defined(__i386__) || defined(__x86_64__)
+    int val;
+    asm volatile ("movl %1, %0\n"
+                  "bswap %0\n"
+                  : "=r" (val)
+                  : "m" (*(uint32_t *)ptr));
+    return val;
+#else
+    const uint8_t *b = ptr;
+    return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
+#endif
+}
+
+static inline uint64_t ldq_be_p(const void *ptr)
+{
+    uint32_t a,b;
+    a = ldl_be_p(ptr);
+    b = ldl_be_p((uint8_t *)ptr + 4);
+    return (((uint64_t)a<<32)|b);
+}
+
+static inline void stw_be_p(void *ptr, int v)
+{
+#if defined(__i386__)
+    asm volatile ("xchgb %b0, %h0\n"
+                  "movw %w0, %1\n"
+                  : "=q" (v)
+                  : "m" (*(uint16_t *)ptr), "0" (v));
+#else
+    uint8_t *d = (uint8_t *) ptr;
+    d[0] = v >> 8;
+    d[1] = v;
+#endif
+}
+
+static inline void stl_be_p(void *ptr, int v)
+{
+#if defined(__i386__) || defined(__x86_64__)
+    asm volatile ("bswap %0\n"
+                  "movl %0, %1\n"
+                  : "=r" (v)
+                  : "m" (*(uint32_t *)ptr), "0" (v));
+#else
+    uint8_t *d = (uint8_t *) ptr;
+    d[0] = v >> 24;
+    d[1] = v >> 16;
+    d[2] = v >> 8;
+    d[3] = v;
+#endif
+}
+
+static inline void stq_be_p(void *ptr, uint64_t v)
+{
+    stl_be_p(ptr, v >> 32);
+    stl_be_p((uint8_t *)ptr + 4, v);
+}
+
+/* float access */
+
+static inline float32 ldfl_be_p(const void *ptr)
+{
+    union {
+        float32 f;
+        uint32_t i;
+    } u;
+    u.i = ldl_be_p(ptr);
+    return u.f;
+}
+
+static inline void stfl_be_p(void *ptr, float32 v)
+{
+    union {
+        float32 f;
+        uint32_t i;
+    } u;
+    u.f = v;
+    stl_be_p(ptr, u.i);
+}
+
+static inline float64 ldfq_be_p(const void *ptr)
+{
+    CPU_DoubleU u;
+    u.l.upper = ldl_be_p(ptr);
+    u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
+    return u.d;
+}
+
+static inline void stfq_be_p(void *ptr, float64 v)
+{
+    CPU_DoubleU u;
+    u.d = v;
+    stl_be_p(ptr, u.l.upper);
+    stl_be_p((uint8_t *)ptr + 4, u.l.lower);
+}
+
+#else
+
+static inline int lduw_be_p(const void *ptr)
+{
+    return *(uint16_t *)ptr;
+}
+
+static inline int ldsw_be_p(const void *ptr)
+{
+    return *(int16_t *)ptr;
+}
+
+static inline int ldl_be_p(const void *ptr)
+{
+    return *(uint32_t *)ptr;
+}
+
+static inline uint64_t ldq_be_p(const void *ptr)
+{
+    return *(uint64_t *)ptr;
+}
+
+static inline void stw_be_p(void *ptr, int v)
+{
+    *(uint16_t *)ptr = v;
+}
+
+static inline void stl_be_p(void *ptr, int v)
+{
+    *(uint32_t *)ptr = v;
+}
+
+static inline void stq_be_p(void *ptr, uint64_t v)
+{
+    *(uint64_t *)ptr = v;
+}
+
+/* float access */
+
+static inline float32 ldfl_be_p(const void *ptr)
+{
+    return *(float32 *)ptr;
+}
+
+static inline float64 ldfq_be_p(const void *ptr)
+{
+    return *(float64 *)ptr;
+}
+
+static inline void stfl_be_p(void *ptr, float32 v)
+{
+    *(float32 *)ptr = v;
+}
+
+static inline void stfq_be_p(void *ptr, float64 v)
+{
+    *(float64 *)ptr = v;
+}
+
+#endif
+
 #endif /* BSWAP_H */
diff --git a/configure b/configure
index d7dba5d..6897d94 100755
--- a/configure
+++ b/configure
@@ -233,7 +233,7 @@ QEMU_CFLAGS="-Wall -Wundef -Wendif-labels -Wwrite-strings -Wmissing-prototypes $
 QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS"
 QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE $QEMU_CFLAGS"
 QEMU_CFLAGS="-D_FORTIFY_SOURCE=2 $QEMU_CFLAGS"
-QEMU_INCLUDES="-I. -I\$(SRC_PATH)"
+QEMU_INCLUDES="-I. -I\$(SRC_PATH) -I\$(SRC_PATH)/fpu"
 LDFLAGS="-g $LDFLAGS"
 
 # make source path absolute
@@ -2985,6 +2985,8 @@ if test "$posix_madvise" = "yes" ; then
   echo "CONFIG_POSIX_MADVISE=y" >> $config_host_mak
 fi
 
+echo "CONFIG_SOFTFLOAT=y" >> $config_host_mak
+
 if test "$spice" = "yes" ; then
   echo "CONFIG_SPICE=y" >> $config_host_mak
 fi
@@ -3382,8 +3384,6 @@ if test ! -z "$gdb_xml_files" ; then
   echo "TARGET_XML_FILES=$list" >> $config_target_mak
 fi
 
-echo "CONFIG_SOFTFLOAT=y" >> $config_target_mak
-
 if test "$target_user_only" = "yes" -a "$bflt" = "yes"; then
   echo "TARGET_HAS_BFLT=y" >> $config_target_mak
 fi
@@ -3414,7 +3414,6 @@ else
   includes="-I\$(SRC_PATH)/tcg/\$(ARCH) $includes"
 fi
 includes="-I\$(SRC_PATH)/tcg $includes"
-includes="-I\$(SRC_PATH)/fpu $includes"
 
 if test "$target_user_only" = "yes" ; then
     libdis_config_mak=libdis-user/config.mak
diff --git a/cpu-all.h b/cpu-all.h
index 54df1d3..9bc1aff 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -35,8 +35,6 @@
  * TARGET_WORDS_BIGENDIAN : same for target cpu
  */
 
-#include "softfloat.h"
-
 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
 #define BSWAP_NEEDED
 #endif
@@ -114,71 +112,6 @@ static inline void tswap64s(uint64_t *s)
 #define bswaptls(s) bswap64s(s)
 #endif
 
-typedef union {
-    float32 f;
-    uint32_t l;
-} CPU_FloatU;
-
-/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
-   endian ! */
-typedef union {
-    float64 d;
-#if defined(HOST_WORDS_BIGENDIAN) \
-    || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
-    struct {
-        uint32_t upper;
-        uint32_t lower;
-    } l;
-#else
-    struct {
-        uint32_t lower;
-        uint32_t upper;
-    } l;
-#endif
-    uint64_t ll;
-} CPU_DoubleU;
-
-#if defined(FLOATX80)
-typedef union {
-     floatx80 d;
-     struct {
-         uint64_t lower;
-         uint16_t upper;
-     } l;
-} CPU_LDoubleU;
-#endif
-
-#if defined(CONFIG_SOFTFLOAT)
-typedef union {
-    float128 q;
-#if defined(HOST_WORDS_BIGENDIAN)
-    struct {
-        uint32_t upmost;
-        uint32_t upper;
-        uint32_t lower;
-        uint32_t lowest;
-    } l;
-    struct {
-        uint64_t upper;
-        uint64_t lower;
-    } ll;
-#else
-    struct {
-        uint32_t lowest;
-        uint32_t lower;
-        uint32_t upper;
-        uint32_t upmost;
-    } l;
-    struct {
-        uint64_t lower;
-        uint64_t upper;
-    } ll;
-#endif
-} CPU_QuadU;
-#endif
-
-/* CPU memory access without any memory or io remapping */
-
 /*
  * the generic syntax for the memory accesses is:
  *
@@ -212,392 +145,8 @@ typedef union {
  *   user   : user mode access using soft MMU
  *   kernel : kernel mode access using soft MMU
  */
-static inline int ldub_p(const void *ptr)
-{
-    return *(uint8_t *)ptr;
-}
-
-static inline int ldsb_p(const void *ptr)
-{
-    return *(int8_t *)ptr;
-}
-
-static inline void stb_p(void *ptr, int v)
-{
-    *(uint8_t *)ptr = v;
-}
-
-/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
-   kernel handles unaligned load/stores may give better results, but
-   it is a system wide setting : bad */
-#if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
-
-/* conservative code for little endian unaligned accesses */
-static inline int lduw_le_p(const void *ptr)
-{
-#ifdef _ARCH_PPC
-    int val;
-    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
-    return val;
-#else
-    const uint8_t *p = ptr;
-    return p[0] | (p[1] << 8);
-#endif
-}
-
-static inline int ldsw_le_p(const void *ptr)
-{
-#ifdef _ARCH_PPC
-    int val;
-    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
-    return (int16_t)val;
-#else
-    const uint8_t *p = ptr;
-    return (int16_t)(p[0] | (p[1] << 8));
-#endif
-}
-
-static inline int ldl_le_p(const void *ptr)
-{
-#ifdef _ARCH_PPC
-    int val;
-    __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
-    return val;
-#else
-    const uint8_t *p = ptr;
-    return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
-#endif
-}
-
-static inline uint64_t ldq_le_p(const void *ptr)
-{
-    const uint8_t *p = ptr;
-    uint32_t v1, v2;
-    v1 = ldl_le_p(p);
-    v2 = ldl_le_p(p + 4);
-    return v1 | ((uint64_t)v2 << 32);
-}
-
-static inline void stw_le_p(void *ptr, int v)
-{
-#ifdef _ARCH_PPC
-    __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
-#else
-    uint8_t *p = ptr;
-    p[0] = v;
-    p[1] = v >> 8;
-#endif
-}
-
-static inline void stl_le_p(void *ptr, int v)
-{
-#ifdef _ARCH_PPC
-    __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
-#else
-    uint8_t *p = ptr;
-    p[0] = v;
-    p[1] = v >> 8;
-    p[2] = v >> 16;
-    p[3] = v >> 24;
-#endif
-}
-
-static inline void stq_le_p(void *ptr, uint64_t v)
-{
-    uint8_t *p = ptr;
-    stl_le_p(p, (uint32_t)v);
-    stl_le_p(p + 4, v >> 32);
-}
-
-/* float access */
-
-static inline float32 ldfl_le_p(const void *ptr)
-{
-    union {
-        float32 f;
-        uint32_t i;
-    } u;
-    u.i = ldl_le_p(ptr);
-    return u.f;
-}
-
-static inline void stfl_le_p(void *ptr, float32 v)
-{
-    union {
-        float32 f;
-        uint32_t i;
-    } u;
-    u.f = v;
-    stl_le_p(ptr, u.i);
-}
-
-static inline float64 ldfq_le_p(const void *ptr)
-{
-    CPU_DoubleU u;
-    u.l.lower = ldl_le_p(ptr);
-    u.l.upper = ldl_le_p(ptr + 4);
-    return u.d;
-}
-
-static inline void stfq_le_p(void *ptr, float64 v)
-{
-    CPU_DoubleU u;
-    u.d = v;
-    stl_le_p(ptr, u.l.lower);
-    stl_le_p(ptr + 4, u.l.upper);
-}
-
-#else
-
-static inline int lduw_le_p(const void *ptr)
-{
-    return *(uint16_t *)ptr;
-}
-
-static inline int ldsw_le_p(const void *ptr)
-{
-    return *(int16_t *)ptr;
-}
-
-static inline int ldl_le_p(const void *ptr)
-{
-    return *(uint32_t *)ptr;
-}
-
-static inline uint64_t ldq_le_p(const void *ptr)
-{
-    return *(uint64_t *)ptr;
-}
-
-static inline void stw_le_p(void *ptr, int v)
-{
-    *(uint16_t *)ptr = v;
-}
-
-static inline void stl_le_p(void *ptr, int v)
-{
-    *(uint32_t *)ptr = v;
-}
-
-static inline void stq_le_p(void *ptr, uint64_t v)
-{
-    *(uint64_t *)ptr = v;
-}
-
-/* float access */
-
-static inline float32 ldfl_le_p(const void *ptr)
-{
-    return *(float32 *)ptr;
-}
-
-static inline float64 ldfq_le_p(const void *ptr)
-{
-    return *(float64 *)ptr;
-}
-
-static inline void stfl_le_p(void *ptr, float32 v)
-{
-    *(float32 *)ptr = v;
-}
-
-static inline void stfq_le_p(void *ptr, float64 v)
-{
-    *(float64 *)ptr = v;
-}
-#endif
-
-#if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
-
-static inline int lduw_be_p(const void *ptr)
-{
-#if defined(__i386__)
-    int val;
-    asm volatile ("movzwl %1, %0\n"
-                  "xchgb %b0, %h0\n"
-                  : "=q" (val)
-                  : "m" (*(uint16_t *)ptr));
-    return val;
-#else
-    const uint8_t *b = ptr;
-    return ((b[0] << 8) | b[1]);
-#endif
-}
-
-static inline int ldsw_be_p(const void *ptr)
-{
-#if defined(__i386__)
-    int val;
-    asm volatile ("movzwl %1, %0\n"
-                  "xchgb %b0, %h0\n"
-                  : "=q" (val)
-                  : "m" (*(uint16_t *)ptr));
-    return (int16_t)val;
-#else
-    const uint8_t *b = ptr;
-    return (int16_t)((b[0] << 8) | b[1]);
-#endif
-}
-
-static inline int ldl_be_p(const void *ptr)
-{
-#if defined(__i386__) || defined(__x86_64__)
-    int val;
-    asm volatile ("movl %1, %0\n"
-                  "bswap %0\n"
-                  : "=r" (val)
-                  : "m" (*(uint32_t *)ptr));
-    return val;
-#else
-    const uint8_t *b = ptr;
-    return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
-#endif
-}
-
-static inline uint64_t ldq_be_p(const void *ptr)
-{
-    uint32_t a,b;
-    a = ldl_be_p(ptr);
-    b = ldl_be_p((uint8_t *)ptr + 4);
-    return (((uint64_t)a<<32)|b);
-}
-
-static inline void stw_be_p(void *ptr, int v)
-{
-#if defined(__i386__)
-    asm volatile ("xchgb %b0, %h0\n"
-                  "movw %w0, %1\n"
-                  : "=q" (v)
-                  : "m" (*(uint16_t *)ptr), "0" (v));
-#else
-    uint8_t *d = (uint8_t *) ptr;
-    d[0] = v >> 8;
-    d[1] = v;
-#endif
-}
-
-static inline void stl_be_p(void *ptr, int v)
-{
-#if defined(__i386__) || defined(__x86_64__)
-    asm volatile ("bswap %0\n"
-                  "movl %0, %1\n"
-                  : "=r" (v)
-                  : "m" (*(uint32_t *)ptr), "0" (v));
-#else
-    uint8_t *d = (uint8_t *) ptr;
-    d[0] = v >> 24;
-    d[1] = v >> 16;
-    d[2] = v >> 8;
-    d[3] = v;
-#endif
-}
-
-static inline void stq_be_p(void *ptr, uint64_t v)
-{
-    stl_be_p(ptr, v >> 32);
-    stl_be_p((uint8_t *)ptr + 4, v);
-}
-
-/* float access */
-
-static inline float32 ldfl_be_p(const void *ptr)
-{
-    union {
-        float32 f;
-        uint32_t i;
-    } u;
-    u.i = ldl_be_p(ptr);
-    return u.f;
-}
-
-static inline void stfl_be_p(void *ptr, float32 v)
-{
-    union {
-        float32 f;
-        uint32_t i;
-    } u;
-    u.f = v;
-    stl_be_p(ptr, u.i);
-}
-
-static inline float64 ldfq_be_p(const void *ptr)
-{
-    CPU_DoubleU u;
-    u.l.upper = ldl_be_p(ptr);
-    u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
-    return u.d;
-}
-
-static inline void stfq_be_p(void *ptr, float64 v)
-{
-    CPU_DoubleU u;
-    u.d = v;
-    stl_be_p(ptr, u.l.upper);
-    stl_be_p((uint8_t *)ptr + 4, u.l.lower);
-}
-
-#else
-
-static inline int lduw_be_p(const void *ptr)
-{
-    return *(uint16_t *)ptr;
-}
-
-static inline int ldsw_be_p(const void *ptr)
-{
-    return *(int16_t *)ptr;
-}
-
-static inline int ldl_be_p(const void *ptr)
-{
-    return *(uint32_t *)ptr;
-}
-
-static inline uint64_t ldq_be_p(const void *ptr)
-{
-    return *(uint64_t *)ptr;
-}
-
-static inline void stw_be_p(void *ptr, int v)
-{
-    *(uint16_t *)ptr = v;
-}
-
-static inline void stl_be_p(void *ptr, int v)
-{
-    *(uint32_t *)ptr = v;
-}
-
-static inline void stq_be_p(void *ptr, uint64_t v)
-{
-    *(uint64_t *)ptr = v;
-}
-
-/* float access */
-
-static inline float32 ldfl_be_p(const void *ptr)
-{
-    return *(float32 *)ptr;
-}
-
-static inline float64 ldfq_be_p(const void *ptr)
-{
-    return *(float64 *)ptr;
-}
-
-static inline void stfl_be_p(void *ptr, float32 v)
-{
-    *(float32 *)ptr = v;
-}
-
-static inline void stfq_be_p(void *ptr, float64 v)
-{
-    *(float64 *)ptr = v;
-}
-
-#endif
 
-/* target CPU memory access functions */
+/* target-endianness CPU memory access functions */
 #if defined(TARGET_WORDS_BIGENDIAN)
 #define lduw_p(p) lduw_be_p(p)
 #define ldsw_p(p) ldsw_be_p(p)
-- 
1.7.4.4

Re: [Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Blue Swirl]

On Thu, May 19, 2011 at 4:47 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> Most definitions in softfloat.h are really target-independent.  Split
> the few that stand out as target-dependent, to allow including
> softfloat.h from files that are not compiled per-target.

Maybe the next step should be (or in place of this patch) to move the
various defines to target-xyz/cpu.h?

Re: [Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Paolo Bonzini]

On 05/20/2011 09:38 PM, Blue Swirl wrote:
> On Thu, May 19, 2011 at 4:47 PM, Paolo Bonzini<pbonzini@redhat.com>  wrote:
> >  Most definitions in softfloat.h are really target-independent.  Split
> >  the few that stand out as target-dependent, to allow including
> >  softfloat.h from files that are not compiled per-target.
>
> Maybe the next step should be (or in place of this patch) to move the
> various defines to target-xyz/cpu.h?

Not sure...  Adding (or increasing, I haven't checked) the dependency of 
softfloat on */cpu.h is bad, but a new file 
target-xyz/softfloat-target.h would be feasible.  You'd miss the 
classification in the two big groups (sNAN sign bit = 0/1), but that's 
not a big deal.

Regarding "in place of this patch" however I disagree, since this patch 
is a naive split of a file in two big pieces, while your proposal 
requires more thought.

Paolo

Re: [Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Blue Swirl]

On Fri, May 20, 2011 at 10:45 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 05/20/2011 09:38 PM, Blue Swirl wrote:
>>
>> On Thu, May 19, 2011 at 4:47 PM, Paolo Bonzini<pbonzini@redhat.com>
>>  wrote:
>> >  Most definitions in softfloat.h are really target-independent.  Split
>> >  the few that stand out as target-dependent, to allow including
>> >  softfloat.h from files that are not compiled per-target.
>>
>> Maybe the next step should be (or in place of this patch) to move the
>> various defines to target-xyz/cpu.h?
>
> Not sure...  Adding (or increasing, I haven't checked) the dependency of
> softfloat on */cpu.h is bad, but a new file target-xyz/softfloat-target.h
> would be feasible.  You'd miss the classification in the two big groups
> (sNAN sign bit = 0/1), but that's not a big deal.
>
> Regarding "in place of this patch" however I disagree, since this patch is a
> naive split of a file in two big pieces, while your proposal requires more
> thought.

OK. Overall, a nice series.

Re: [Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Aurelien Jarno]

On Thu, May 19, 2011 at 03:47:00PM +0200, Paolo Bonzini wrote:
> Most definitions in softfloat.h are really target-independent.  Split
> the few that stand out as target-dependent, to allow including
> softfloat.h from files that are not compiled per-target.

Looks ok in principle, but I wonder if we should really create a new
header for that. softfloat-specialize.h is already supposed to contain
the target specific functions, so it's probably a good idea to move them
there instead.

Also please note that this will conflict with the patch series I sent
recently about removing softfloat-native (most of the patches have been
acked, I'll send a new series soon).

> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>  fpu/softfloat-target.h |  119 ++++++++++++++++++++++++++++++++++++++++++++++++
>  fpu/softfloat.c        |   11 +++-
>  fpu/softfloat.h        |   70 +----------------------------
>  target-arm/helper.c    |    1 +
>  4 files changed, 129 insertions(+), 72 deletions(-)
>  create mode 100644 fpu/softfloat-target.h
> 
> diff --git a/fpu/softfloat-target.h b/fpu/softfloat-target.h
> new file mode 100644
> index 0000000..513542c
> --- /dev/null
> +++ b/fpu/softfloat-target.h
> @@ -0,0 +1,119 @@
> +/*
> + * QEMU float support
> + *
> + * Derived from SoftFloat.
> + */
> +
> +/*============================================================================
> +
> +This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
> +Package, Release 2b.
> +
> +Written by John R. Hauser.  This work was made possible in part by the
> +International Computer Science Institute, located at Suite 600, 1947 Center
> +Street, Berkeley, California 94704.  Funding was partially provided by the
> +National Science Foundation under grant MIP-9311980.  The original version
> +of this code was written as part of a project to build a fixed-point vector
> +processor in collaboration with the University of California at Berkeley,
> +overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
> +is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
> +arithmetic/SoftFloat.html'.
> +
> +THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
> +been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
> +RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
> +AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
> +COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
> +EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
> +INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
> +OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
> +
> +Derivative works are acceptable, even for commercial purposes, so long as
> +(1) the source code for the derivative work includes prominent notice that
> +the work is derivative, and (2) the source code includes prominent notice with
> +these four paragraphs for those parts of this code that are retained.
> +
> +=============================================================================*/
> +
> +#ifndef SOFTFLOAT_TARGET_H
> +#define SOFTFLOAT_TARGET_H
> +
> +#include "softfloat.h"
> +#include "config-target.h"
> +
> +#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
> +#define SNAN_BIT_IS_ONE		1
> +#else
> +#define SNAN_BIT_IS_ONE		0
> +#endif
> +
> +#ifdef CONFIG_SOFTFLOAT
> +
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated half-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_ARM)
> +#define float16_default_nan make_float16(0x7E00)
> +#elif SNAN_BIT_IS_ONE
> +#define float16_default_nan make_float16(0x7DFF)
> +#else
> +#define float16_default_nan make_float16(0xFE00)
> +#endif
> +
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated single-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_SPARC)
> +#define float32_default_nan make_float32(0x7FFFFFFF)
> +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> +#define float32_default_nan make_float32(0x7FC00000)
> +#elif SNAN_BIT_IS_ONE
> +#define float32_default_nan make_float32(0x7FBFFFFF)
> +#else
> +#define float32_default_nan make_float32(0xFFC00000)
> +#endif
> +
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated double-precision NaN.
> +*----------------------------------------------------------------------------*/
> +#if defined(TARGET_SPARC)
> +#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
> +#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> +#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
> +#elif SNAN_BIT_IS_ONE
> +#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
> +#else
> +#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
> +#endif
> +
> +#ifdef FLOATX80
> +
> +#if SNAN_BIT_IS_ONE
> +#define floatx80_default_nan_high 0x7FFF
> +#define floatx80_default_nan_low  LIT64( 0xBFFFFFFFFFFFFFFF )
> +#else
> +#define floatx80_default_nan_high 0xFFFF
> +#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )
> +#endif
> +
> +#endif
> +
> +#ifdef FLOAT128
> +
> +/*----------------------------------------------------------------------------
> +| The pattern for a default generated quadruple-precision NaN.  The `high' and
> +| `low' values hold the most- and least-significant bits, respectively.
> +*----------------------------------------------------------------------------*/
> +#if SNAN_BIT_IS_ONE
> +#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
> +#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
> +#else
> +#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
> +#define float128_default_nan_low  LIT64( 0x0000000000000000 )
> +#endif
> +
> +#endif
> +
> +#endif /* !CONFIG_SOFTFLOAT */
> +
> +#endif /* !SOFTFLOAT_TARGET_H */
> diff --git a/fpu/softfloat.c b/fpu/softfloat.c
> index baba1dc..72aefc5 100644
> --- a/fpu/softfloat.c
> +++ b/fpu/softfloat.c
> @@ -45,12 +45,17 @@ these four paragraphs for those parts of this code that are retained.
>  #include "softfloat-macros.h"
>  
>  /*----------------------------------------------------------------------------
> +| Public functions and definitions for the default generated quiet NaNs.
> +| This is target-specific.
> +*----------------------------------------------------------------------------*/
> +#include "softfloat-target.h"
> +
> +/*----------------------------------------------------------------------------
>  | Functions and definitions to determine:  (1) whether tininess for underflow
>  | is detected before or after rounding by default, (2) what (if anything)
>  | happens when exceptions are raised, (3) how signaling NaNs are distinguished
> -| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs
> -| are propagated from function inputs to output.  These details are target-
> -| specific.
> +| from quiet NaNs, and (4) how NaNs are propagated from function inputs to
> +| output.  These details are target-specific.
>  *----------------------------------------------------------------------------*/
>  #include "softfloat-specialize.h"
>  
> diff --git a/fpu/softfloat.h b/fpu/softfloat.h
> index 5eff085..c9e4446 100644
> --- a/fpu/softfloat.h
> +++ b/fpu/softfloat.h
> @@ -43,7 +43,7 @@ these four paragraphs for those parts of this code that are retained.
>  #endif
>  
>  #include <inttypes.h>
> -#include "config.h"
> +#include "config-host.h"
>  
>  /*----------------------------------------------------------------------------
>  | Each of the following `typedef's defines the most convenient type that holds
> @@ -68,12 +68,6 @@ typedef int64_t int64;
>  #define LIT64( a ) a##LL
>  #define INLINE static inline
>  
> -#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
> -#define SNAN_BIT_IS_ONE		1
> -#else
> -#define SNAN_BIT_IS_ONE		0
> -#endif
> -
>  /*----------------------------------------------------------------------------
>  | The macro `FLOATX80' must be defined to enable the extended double-precision
>  | floating-point format `floatx80'.  If this macro is not defined, the
> @@ -280,17 +274,6 @@ int float16_is_signaling_nan( float16 );
>  float16 float16_maybe_silence_nan( float16 );
>  
>  /*----------------------------------------------------------------------------
> -| The pattern for a default generated half-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_ARM)
> -#define float16_default_nan make_float16(0x7E00)
> -#elif SNAN_BIT_IS_ONE
> -#define float16_default_nan make_float16(0x7DFF)
> -#else
> -#define float16_default_nan make_float16(0xFE00)
> -#endif
> -
> -/*----------------------------------------------------------------------------
>  | Software IEC/IEEE single-precision conversion routines.
>  *----------------------------------------------------------------------------*/
>  int16 float32_to_int16_round_to_zero( float32 STATUS_PARAM );
> @@ -393,19 +376,6 @@ INLINE float32 float32_set_sign(float32 a, int sign)
>  
>  
>  /*----------------------------------------------------------------------------
> -| The pattern for a default generated single-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_SPARC)
> -#define float32_default_nan make_float32(0x7FFFFFFF)
> -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> -#define float32_default_nan make_float32(0x7FC00000)
> -#elif SNAN_BIT_IS_ONE
> -#define float32_default_nan make_float32(0x7FBFFFFF)
> -#else
> -#define float32_default_nan make_float32(0xFFC00000)
> -#endif
> -
> -/*----------------------------------------------------------------------------
>  | Software IEC/IEEE double-precision conversion routines.
>  *----------------------------------------------------------------------------*/
>  int16 float64_to_int16_round_to_zero( float64 STATUS_PARAM );
> @@ -504,19 +474,6 @@ INLINE float64 float64_set_sign(float64 a, int sign)
>  #define float64_half make_float64(0x3fe0000000000000LL)
>  #define float64_infinity make_float64(0x7ff0000000000000LL)
>  
> -/*----------------------------------------------------------------------------
> -| The pattern for a default generated double-precision NaN.
> -*----------------------------------------------------------------------------*/
> -#if defined(TARGET_SPARC)
> -#define float64_default_nan make_float64(LIT64( 0x7FFFFFFFFFFFFFFF ))
> -#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA)
> -#define float64_default_nan make_float64(LIT64( 0x7FF8000000000000 ))
> -#elif SNAN_BIT_IS_ONE
> -#define float64_default_nan make_float64(LIT64( 0x7FF7FFFFFFFFFFFF ))
> -#else
> -#define float64_default_nan make_float64(LIT64( 0xFFF8000000000000 ))
> -#endif
> -
>  #ifdef FLOATX80
>  
>  /*----------------------------------------------------------------------------
> @@ -596,19 +553,6 @@ INLINE int floatx80_is_any_nan(floatx80 a)
>  #define floatx80_half make_floatx80(0x3ffe, 0x8000000000000000LL)
>  #define floatx80_infinity make_floatx80(0x7fff, 0x8000000000000000LL)
>  
> -/*----------------------------------------------------------------------------
> -| The pattern for a default generated extended double-precision NaN.  The
> -| `high' and `low' values hold the most- and least-significant bits,
> -| respectively.
> -*----------------------------------------------------------------------------*/
> -#if SNAN_BIT_IS_ONE
> -#define floatx80_default_nan_high 0x7FFF
> -#define floatx80_default_nan_low  LIT64( 0xBFFFFFFFFFFFFFFF )
> -#else
> -#define floatx80_default_nan_high 0xFFFF
> -#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )
> -#endif
> -
>  #endif
>  
>  #ifdef FLOAT128
> @@ -684,18 +628,6 @@ INLINE int float128_is_any_nan(float128 a)
>          ((a.low != 0) || ((a.high & 0xffffffffffffLL) != 0));
>  }
>  
> -/*----------------------------------------------------------------------------
> -| The pattern for a default generated quadruple-precision NaN.  The `high' and
> -| `low' values hold the most- and least-significant bits, respectively.
> -*----------------------------------------------------------------------------*/
> -#if SNAN_BIT_IS_ONE
> -#define float128_default_nan_high LIT64( 0x7FFF7FFFFFFFFFFF )
> -#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
> -#else
> -#define float128_default_nan_high LIT64( 0xFFFF800000000000 )
> -#define float128_default_nan_low  LIT64( 0x0000000000000000 )
> -#endif
> -
>  #endif
>  
>  #else /* CONFIG_SOFTFLOAT */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 62ae72e..0f15cf3 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -8,6 +8,7 @@
>  #include "helper.h"
>  #include "qemu-common.h"
>  #include "host-utils.h"
> +#include "softfloat-target.h"
>  #if !defined(CONFIG_USER_ONLY)
>  #include "hw/loader.h"
>  #endif
> -- 
> 1.7.4.4
> 
> 
> 
> 

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 2/3] softfloat: extract softfloat-target.h

[Paolo Bonzini]

On 05/23/2011 11:11 PM, Aurelien Jarno wrote:
> Looks ok in principle, but I wonder if we should really create a new
> header for that. softfloat-specialize.h is already supposed to contain
> the target specific functions, so it's probably a good idea to move them
> there instead.

I was wondering about that too... I was thinking of separating _private_ 
target-specific functions and a public interface that is target-specific 
just because we go for macros rather than extern variables.

In fact, using const variables is another way to solve the problem, 
without introducing a new header.  I'll probably do that for v2.

> Also please note that this will conflict with the patch series I sent
> recently about removing softfloat-native (most of the patches have been
> acked, I'll send a new series soon).

Yes, no problem.

Paolo