[U-Boot] resend patches to replace previous 3/7, 6/7, 7/7

[U-Boot] resend patches to replace previous 3/7, 6/7, 7/7

[York Sun]

Kumar,

These two patches replace previous 3/7, 6/7, 7/7

[PATCH 3/7] powerpc/mpc8xxx: Enable calculation for fixed DDR chips
[PATCH 6/7] powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
[PATCH 7/7] powerpc/mpc8xxx: change raw timing function call parameters

York

[U-Boot] [Patch v2 1/2] powerpc/mpc8xxx: Enable calculation for fixed DDR chips

[York Sun]

We used to have fixed parameters for soldered DDR chips. This patch introduces
CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR
chip datasheet, implemneted in board-specific files or header files.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 README                                |    6 ++++++
 arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
 arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    9 +++++++++
 arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
 5 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/README b/README
index 8bb9c8d..c1ddfd0 100644
--- a/README
+++ b/README
@@ -2930,6 +2930,12 @@ Low Level (hardware related) configuration options:
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
 
+- CONFIG_SYS_DDR_RAW_TIMING
+		Get DDR timing information from other than SPD. Common with
+		soldered DDR chips onboard without SPD. DDR raw timing
+		parameters are extracted from datasheet and hard-coded into
+		header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index f863f4a..53f0887 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -336,7 +336,9 @@ phys_size_t initdram(int board_type)
 	}
 #endif
 
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if	defined(CONFIG_SPD_EEPROM)	|| \
+	defined(CONFIG_DDR_SPD)		|| \
+	defined(CONFIG_SYS_DDR_RAW_TIMING)
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
index 4a5a785..d1b4c4b 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile
@@ -12,15 +12,24 @@ LIB	= $(obj)libddr.o
 
 COBJS-$(CONFIG_FSL_DDR1)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
+endif
+
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
index 1e866fe..220fdc4 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
@@ -14,6 +14,7 @@
 
 #include "common_timing_params.h"
 
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
  * Bind the main DDR setup driver's generic names
  * to this specific DDR technology.
@@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
 {
 	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
 }
+#endif
 
 /*
  * Data Structures
@@ -80,4 +82,11 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
+
+/* board specific function */
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
+#endif	/* CONFIG_SYS_DDR_RAW_TIMING */
 #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 62a73dd..3c49fa9 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -325,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 	switch (start_step) {
 	case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 		/* STEP 1:  Gather all DIMM SPD data */
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
@@ -356,6 +357,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			}
 		}
 
+#else
+	case STEP_COMPUTE_DIMM_PARMS:
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				dimm_params_t *pdimm =
+					&(pinfo->dimm_params[i][j]);
+				fsl_ddr_get_dimm_params(pdimm, i, j);
+			}
+		}
+		debug("Filling dimm parameters from board specific file\n");
+#endif
 	case STEP_COMPUTE_COMMON_PARMS:
 		/*
 		 * STEP 3: Compute a common set of timing parameters
-- 
1.7.0.4

[U-Boot] [Patch v2 2/2] powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

[York Sun]

In case of empty SPD or checksum error, fallback to raw timing on
supported boards.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 3c49fa9..249fd7d 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->dimm_params[i][j]);
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+				if (retval != 0) {
+					printf("SPD error! Trying fallback to "
+					"raw timing calculation\n");
+					fsl_ddr_get_dimm_params(pdimm, i, j);
+				}
+#else
 				if (retval == 2) {
 					printf("Error: compute_dimm_parameters"
 					" non-zero returned FATAL value "
 					"for memctl=%u dimm=%u\n", i, j);
 					return 0;
 				}
+#endif
 				if (retval) {
 					debug("Warning: compute_dimm_parameters"
 					" non-zero return value for memctl=%u "
-- 
1.7.0.4

[U-Boot] [Patch v2 1/2] powerpc/mpc8xxx: Enable calculation for fixed DDR chips

[Kumar Gala]

On Jun 6, 2011, at 8:42 PM, York Sun wrote:

> We used to have fixed parameters for soldered DDR chips. This patch introduces
> CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR
> chip datasheet, implemneted in board-specific files or header files.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> README                                |    6 ++++++
> arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
> arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
> arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    9 +++++++++
> arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
> 5 files changed, 41 insertions(+), 3 deletions(-)
> 
> diff --git a/README b/README
> index 8bb9c8d..c1ddfd0 100644
> --- a/README
> +++ b/README
> @@ -2930,6 +2930,12 @@ Low Level (hardware related) configuration options:
> 		one, specify here. Note that the value must resolve
> 		to something your driver can deal with.
> 
> +- CONFIG_SYS_DDR_RAW_TIMING
> +		Get DDR timing information from other than SPD. Common with
> +		soldered DDR chips onboard without SPD. DDR raw timing
> +		parameters are extracted from datasheet and hard-coded into
> +		header files or board specific files.
> +

How is this not just !CONFIG_SPD ?

> - CONFIG_SYS_83XX_DDR_USES_CS0
> 		Only for 83xx systems. If specified, then DDR should
> 		be configured using CS0 and CS1 instead of CS2 and CS3.

> 
> 
> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> index 1e866fe..220fdc4 100644
> --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
> @@ -14,6 +14,7 @@
> 
> #include "common_timing_params.h"
> 
> +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
> /*
>  * Bind the main DDR setup driver's generic names
>  * to this specific DDR technology.
> @@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
> {
> 	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
> }
> +#endif
> 
> /*
>  * Data Structures
> @@ -80,4 +82,11 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
> extern unsigned int mclk_to_picos(unsigned int mclk);
> extern unsigned int get_memory_clk_period_ps(void);
> extern unsigned int picos_to_mclk(unsigned int picos);
> +
> +/* board specific function */
> +#ifdef CONFIG_SYS_DDR_RAW_TIMING
> +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
> +			unsigned int controller_number,
> +			unsigned int dimm_number);

where is this code?

> +#endif	/* CONFIG_SYS_DDR_RAW_TIMING */
> #endif
> diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> index 62a73dd..3c49fa9 100644
> --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
> @@ -325,6 +325,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
> 
> 	switch (start_step) {
> 	case STEP_GET_SPD:
> +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
> 		/* STEP 1:  Gather all DIMM SPD data */
> 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
> 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
> @@ -356,6 +357,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
> 			}
> 		}
> 
> +#else
> +	case STEP_COMPUTE_DIMM_PARMS:
> +		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
> +			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
> +				dimm_params_t *pdimm =
> +					&(pinfo->dimm_params[i][j]);
> +				fsl_ddr_get_dimm_params(pdimm, i, j);
> +			}
> +		}
> +		debug("Filling dimm parameters from board specific file\n");
> +#endif
> 	case STEP_COMPUTE_COMMON_PARMS:
> 		/*
> 		 * STEP 3: Compute a common set of timing parameters
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [Patch v2 1/2] powerpc/mpc8xxx: Enable calculation for fixed DDR chips

[York Sun]

On Tue, 2011-06-07 at 08:35 -0500, Kumar Gala wrote:
> > +- CONFIG_SYS_DDR_RAW_TIMING
> > +		Get DDR timing information from other than SPD. Common with
> > +		soldered DDR chips onboard without SPD. DDR raw timing
> > +		parameters are extracted from datasheet and hard-coded into
> > +		header files or board specific files.
> > +
> 
> How is this not just !CONFIG_SPD ?

There are boards with fixed DDR in the past. They didn't use SPD.

> > +/* board specific function */
> > +#ifdef CONFIG_SYS_DDR_RAW_TIMING
> > +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
> > +			unsigned int controller_number,
> > +			unsigned int dimm_number);
> 
> where is this code?

This code is in board ddr.c file. It is board specific.

York

[U-Boot] [Patch v2 1/2] powerpc/mpc8xxx: Enable calculation for fixed DDR chips

[Kumar Gala]

On Jun 6, 2011, at 8:42 PM, York Sun wrote:

> We used to have fixed parameters for soldered DDR chips. This patch introduces
> CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR
> chip datasheet, implemneted in board-specific files or header files.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> README                                |    6 ++++++
> arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
> arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
> arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    9 +++++++++
> arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
> 5 files changed, 41 insertions(+), 3 deletions(-)

applied to 85xx

- k

[U-Boot] [Patch v2 2/2] powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

[Kumar Gala]

On Jun 6, 2011, at 8:42 PM, York Sun wrote:

> In case of empty SPD or checksum error, fallback to raw timing on
> supported boards.
> 
> Signed-off-by: York Sun <yorksun@freescale.com>
> ---
> arch/powerpc/cpu/mpc8xxx/ddr/main.c |    8 ++++++++
> 1 files changed, 8 insertions(+), 0 deletions(-)

applied to 85xx

- k