* [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X
@ 2011-07-15 9:09 Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5 Michael Jones
` (8 more replies)
0 siblings, 9 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Add support for the Matrix Vision mvBlueLYNX-X, an OMAP3-based
intelligent camera.
These patches were created on top of v2011.06, but they also apply cleanly to
master and u-boot-arm/master. What should I use as base to submit such a patch?
Howard D. Gray (1):
Add 37xx ESx revision numbers.
Michael Jones (5):
fpga: support FPP Cyclone configuration
mmc: rescan fails on empty slot
mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE
ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in
i2c_write
mvblx: Initial support for mvBlueLYNX-X
MAINTAINERS | 4 +
MAKEALL | 1 +
arch/arm/cpu/armv7/omap3/sys_info.c | 13 +-
arch/arm/include/asm/arch-omap3/omap3.h | 10 +
board/matrix_vision/common/mv_common.c | 2 +
board/matrix_vision/mvblx/Makefile | 53 ++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 222 +++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 171 +++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 ++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 396 +++++++++++++++++++++++++++++++
boards.cfg | 1 +
common/cmd_mmc.c | 6 +-
doc/README.omap3 | 5 +
drivers/fpga/cyclon2.c | 10 +
drivers/i2c/omap24xx_i2c.c | 134 +++++------
include/configs/omap3_mvblx.h | 312 ++++++++++++++++++++++++
18 files changed, 1686 insertions(+), 81 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-28 14:46 ` Wolfgang Denk
2011-07-15 9:09 ` [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration Michael Jones
` (7 subsequent siblings)
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
include/ACEX1K.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/ACEX1K.h b/include/ACEX1K.h
index ae20164..2bb9226 100644
--- a/include/ACEX1K.h
+++ b/include/ACEX1K.h
@@ -76,6 +76,7 @@ typedef struct {
#define Altera_EP2C8_SIZE 247942
#define Altera_EP2C20_SIZE 586562
#define Altera_EP2C35_SIZE 883905
+#define Altera_EP3C5_SIZE 368011 /* .rbf size in bytes */
/* Descriptor Macros
*********************************************************************/
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5 Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-28 14:47 ` Wolfgang Denk
2011-07-15 9:09 ` [U-Boot] [PATCH 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers Michael Jones
` (6 subsequent siblings)
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Support FPGAs which use Fast Passive Parallel configuration
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
drivers/fpga/cyclon2.c | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c
index 4622b4e..567099e 100644
--- a/drivers/fpga/cyclon2.c
+++ b/drivers/fpga/cyclon2.c
@@ -63,6 +63,16 @@ int CYC2_load (Altera_desc * desc, void *buf, size_t bsize)
ret_val = CYC2_ps_load (desc, buf, bsize);
break;
+ case fast_passive_parallel:
+ /* Fast Passive Parallel (FPP) and PS only differ in what is
+ * done in the write() callback. Use the existing PS load
+ * function for FPP, too.
+ */
+ PRINTF ("%s: Launching Fast Passive Parallel Loader\n",
+ __FUNCTION__);
+ ret_val = CYC2_ps_load(desc, buf, bsize);
+ break;
+
/* Add new interface types here */
default:
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers.
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5 Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-18 14:36 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot Michael Jones
` (5 subsequent siblings)
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
From: "Howard D. Gray" <howard.gray@matrix-vision.de>
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
arch/arm/cpu/armv7/omap3/sys_info.c | 13 ++++++++++++-
arch/arm/include/asm/arch-omap3/omap3.h | 10 ++++++++++
2 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19..8f1e74a 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -43,6 +43,12 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
"UNKNOWN",
"3.1.2"};
+/* this is the revision table for 37xx CPUs */
+static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
+ "1.0",
+ "1.1",
+ "1.2"};
+
/*****************************************************************
* dieid_num_r(void) - read and set die ID
*****************************************************************/
@@ -344,7 +350,12 @@ int print_cpuinfo (void)
sec_s = "?";
}
- printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ if (CPU_OMAP36XX == get_cpu_family())
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ cpu_family_s, cpu_s, sec_s,
+ rev_s_37xx[get_cpu_rev()], max_clk);
+ else
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
cpu_family_s, cpu_s, sec_s,
rev_s[get_cpu_rev()], max_clk);
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index cc2b541..63340af 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -193,6 +193,16 @@ struct gpio {
#define CPU_3XX_ES312 7
#define CPU_3XX_MAX_REV 8
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10 0
+#define CPU_37XX_ES11 1
+#define CPU_37XX_ES12 2
+#define CPU_37XX_MAX_REV 3
+
#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
--
1.7.5.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (2 preceding siblings ...)
2011-07-15 9:09 ` [U-Boot] [PATCH 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-18 14:40 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-19 2:06 ` [U-Boot] [PATCH " Jaehoon Chung
2011-07-15 9:09 ` [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE Michael Jones
` (4 subsequent siblings)
8 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Fail in 'mmc rescan' if mmc_init() returns error
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
common/cmd_mmc.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 176646d..28918f6 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
mmc->has_init = 0;
- mmc_init(mmc);
- return 0;
+ if (mmc_init(mmc))
+ return 1;
+ else
+ return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
block_dev_desc_t *mmc_dev;
struct mmc *mmc = find_mmc_device(curr_device);
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (3 preceding siblings ...)
2011-07-15 9:09 ` [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-18 14:45 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-18 17:39 ` [U-Boot] [PATCH " Mike Frysinger
2011-07-15 9:09 ` [U-Boot] [PATCH 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Michael Jones
` (3 subsequent siblings)
8 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Doesn't make sense to provide this function to boards which defined
CONFIG_ENV_IS_NOWHERE. Such a board gets a linking error because
common/env_nowhere.c doesn't define saveenv().
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
board/matrix_vision/common/mv_common.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
index 0afc535..404c8b4 100644
--- a/board/matrix_vision/common/mv_common.c
+++ b/board/matrix_vision/common/mv_common.c
@@ -38,6 +38,7 @@ static char* entries_to_keep[] = {
#define MV_MAX_ENV_ENTRY_LENGTH 64
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
+#ifndef CONFIG_ENV_IS_NOWHERE
void mv_reset_environment(void)
{
int i;
@@ -67,6 +68,7 @@ void mv_reset_environment(void)
saveenv();
}
+#endif
int mv_load_fpga(void)
{
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (4 preceding siblings ...)
2011-07-15 9:09 ` [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-18 14:58 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X Michael Jones
` (2 subsequent siblings)
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
This allows the EEPROM layer to send a single i2c write command
per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
i2c write commands.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
drivers/i2c/omap24xx_i2c.c | 134 ++++++++++++++++++-------------------------
1 files changed, 56 insertions(+), 78 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 966ffc4..4ae03bc 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -216,77 +216,6 @@ read_exit:
return i2c_error;
}
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- writew (2, &i2c_base->cnt);
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send register offset */
- writeb(regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
- /* send data */
- writeb(value, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
- break;
-#else
- /* send out two bytes */
- writew((value << 8) + regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-#endif
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
- wait_for_bb();
-
- status = readw(&i2c_base->stat);
- if (status & I2C_STAT_NACK)
- i2c_error = 1;
-
-write_exit:
- flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
- return i2c_error;
-}
-
static void flush_fifo(void)
{ u16 stat;
@@ -372,26 +301,75 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
int i;
+ u16 status;
+ int i2c_error = 0;
if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
+ printf("I2C write: address 0x%x + 0x%x out of range\n");
return 1;
}
+ /* wait until bus not busy */
+ wait_for_bb();
+
+ /* start address phase - will write regoffset + len bytes data */
+ /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+ writew(alen+len, &i2c_base->cnt);
+ /* set slave address */
+ writew(chip, &i2c_base->sa);
+ /* stop bit needed here */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con);
+
+ /* Send address byte */
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(addr & 0xFF, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ /* address phase is over, now write data */
for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n",
+ __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(buffer[i], &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("%s:%d i=%d error status=0x%x\n",
+ __func__, __LINE__, i, status);
+ goto write_exit;
}
}
- return 0;
+write_exit:
+ flush_fifo();
+ writew(0xFFFF, &i2c_base->stat);
+ return i2c_error;
}
static void wait_for_bb (void)
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (5 preceding siblings ...)
2011-07-15 9:09 ` [U-Boot] [PATCH 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Michael Jones
@ 2011-07-15 9:09 ` Michael Jones
2011-07-18 15:00 ` [U-Boot] [PATCH v2 " Michael Jones
2011-08-17 8:55 ` [U-Boot] [PATCH v4] " Michael Jones
2011-10-05 15:08 ` [U-Boot] [PATCH v5] " Michael Jones
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-15 9:09 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 171 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 312 +++++++++++++++++++++++++
12 files changed, 1591 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2bba7b4..866f75a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -678,6 +678,10 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/MAKEALL b/MAKEALL
index 51db13e..fc06e86 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -434,6 +434,7 @@ LIST_ARMV7=" \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
+ omap3_mvblx \
omap4_panda \
omap4_sdp4430 \
s5p_goni \
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..9ad83d8
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/arch/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (omap_request_gpio(GPIO_DCLK) ||
+ omap_request_gpio(GPIO_nSTATUS) ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_request_gpio(GPIO_CONF_DONE) ||
+#endif
+ omap_request_gpio(GPIO_nCONFIG) ||
+ omap_request_gpio(GPIO_DATA0) ||
+ omap_request_gpio(GPIO_DATA1) ||
+ omap_request_gpio(GPIO_DATA2) ||
+ omap_request_gpio(GPIO_DATA3) ||
+ omap_request_gpio(GPIO_DATA4) ||
+ omap_request_gpio(GPIO_DATA5) ||
+ omap_request_gpio(GPIO_DATA6) ||
+ omap_request_gpio(GPIO_DATA7)) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ omap_set_gpio_direction(GPIO_DCLK, 0);
+ omap_set_gpio_direction(GPIO_nCONFIG, 0);
+ omap_set_gpio_direction(GPIO_DATA0, 0);
+ omap_set_gpio_direction(GPIO_DATA1, 0);
+ omap_set_gpio_direction(GPIO_DATA2, 0);
+ omap_set_gpio_direction(GPIO_DATA3, 0);
+ omap_set_gpio_direction(GPIO_DATA4, 0);
+ omap_set_gpio_direction(GPIO_DATA5, 0);
+ omap_set_gpio_direction(GPIO_DATA6, 0);
+ omap_set_gpio_direction(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ */
+
+ /* set up inputs */
+ omap_set_gpio_direction(GPIO_nSTATUS, 1);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_set_gpio_direction(GPIO_CONF_DONE, 1);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ omap_set_gpio_dataout(GPIO_nCONFIG, !assert);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (omap_get_gpio_datain(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ omap_free_gpio(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = omap_get_gpio_datain(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ /* TODO it takes ~7s to call this routine 368,011 times
+ * even when the udelay() calls are removed completely.
+ * Where does all this time come from?
+ */
+ omap_set_gpio_dataout(GPIO_DATA0, byte & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA1, (byte >> 1) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA2, (byte >> 2) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA3, (byte >> 3) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA4, (byte >> 4) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA5, (byte >> 5) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA6, (byte >> 6) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ omap_set_gpio_dataout(GPIO_DCLK, 1);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..e117e84
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..1b8a005
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,171 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_MVBLX;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..4c0fc49
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+/* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+/*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..029cf20
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index dfefc3f..3c8b762 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -151,6 +151,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 460950d..b0d875c 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..eb41b12
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,312 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers.
2011-07-15 9:09 ` [U-Boot] [PATCH 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers Michael Jones
@ 2011-07-18 14:36 ` Michael Jones
0 siblings, 0 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-18 14:36 UTC (permalink / raw)
To: u-boot
From: "Howard D. Gray" <howard.gray@matrix-vision.de>
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
arch/arm/cpu/armv7/omap3/sys_info.c | 13 ++++++++++++-
arch/arm/include/asm/arch-omap3/omap3.h | 10 ++++++++++
2 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19..8f1e74a 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -43,6 +43,12 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
"UNKNOWN",
"3.1.2"};
+/* this is the revision table for 37xx CPUs */
+static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
+ "1.0",
+ "1.1",
+ "1.2"};
+
/*****************************************************************
* dieid_num_r(void) - read and set die ID
*****************************************************************/
@@ -344,7 +350,12 @@ int print_cpuinfo (void)
sec_s = "?";
}
- printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ if (CPU_OMAP36XX == get_cpu_family())
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
+ cpu_family_s, cpu_s, sec_s,
+ rev_s_37xx[get_cpu_rev()], max_clk);
+ else
+ printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
cpu_family_s, cpu_s, sec_s,
rev_s[get_cpu_rev()], max_clk);
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index cc2b541..63340af 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -193,6 +193,16 @@ struct gpio {
#define CPU_3XX_ES312 7
#define CPU_3XX_MAX_REV 8
+/*
+ * 37xx real hardware:
+ * ES1.0 onwards, the value maps to contents of IDCODE register [31:28].
+ */
+
+#define CPU_37XX_ES10 0
+#define CPU_37XX_ES11 1
+#define CPU_37XX_ES12 2
+#define CPU_37XX_MAX_REV 3
+
#define CPU_3XX_ID_SHIFT 28
#define WIDTH_8BIT 0x0000
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 4/7] mmc: rescan fails on empty slot
2011-07-15 9:09 ` [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot Michael Jones
@ 2011-07-18 14:40 ` Michael Jones
2011-08-17 2:15 ` Andy Fleming
2011-07-19 2:06 ` [U-Boot] [PATCH " Jaehoon Chung
1 sibling, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-18 14:40 UTC (permalink / raw)
To: u-boot
Fail in 'mmc rescan' if mmc_init() returns error
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
common/cmd_mmc.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 176646d..28918f6 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
}
mmc->has_init = 0;
- mmc_init(mmc);
- return 0;
+ if (mmc_init(mmc))
+ return 1;
+ else
+ return 0;
} else if (strncmp(argv[1], "part", 4) == 0) {
block_dev_desc_t *mmc_dev;
struct mmc *mmc = find_mmc_device(curr_device);
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE
2011-07-15 9:09 ` [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE Michael Jones
@ 2011-07-18 14:45 ` Michael Jones
2011-07-28 14:49 ` Wolfgang Denk
2011-07-18 17:39 ` [U-Boot] [PATCH " Mike Frysinger
1 sibling, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-18 14:45 UTC (permalink / raw)
To: u-boot
Doesn't make sense to provide this function to boards which defined
CONFIG_ENV_IS_NOWHERE. Such a board gets a linking error because
common/env_nowhere.c doesn't define saveenv().
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
board/matrix_vision/common/mv_common.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
index 0afc535..404c8b4 100644
--- a/board/matrix_vision/common/mv_common.c
+++ b/board/matrix_vision/common/mv_common.c
@@ -38,6 +38,7 @@ static char* entries_to_keep[] = {
#define MV_MAX_ENV_ENTRY_LENGTH 64
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
+#ifndef CONFIG_ENV_IS_NOWHERE
void mv_reset_environment(void)
{
int i;
@@ -67,6 +68,7 @@ void mv_reset_environment(void)
saveenv();
}
+#endif
int mv_load_fpga(void)
{
--
1.7.5.4
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-15 9:09 ` [U-Boot] [PATCH 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Michael Jones
@ 2011-07-18 14:58 ` Michael Jones
2011-07-27 6:07 ` Heiko Schocher
0 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-18 14:58 UTC (permalink / raw)
To: u-boot
This allows the EEPROM layer to send a single i2c write command
per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
i2c write commands.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
drivers/i2c/omap24xx_i2c.c | 134 ++++++++++++++++++-------------------------
1 files changed, 56 insertions(+), 78 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 966ffc4..4ae03bc 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -216,77 +216,6 @@ read_exit:
return i2c_error;
}
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- writew (2, &i2c_base->cnt);
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send register offset */
- writeb(regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
- /* send data */
- writeb(value, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
- break;
-#else
- /* send out two bytes */
- writew((value << 8) + regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-#endif
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
- wait_for_bb();
-
- status = readw(&i2c_base->stat);
- if (status & I2C_STAT_NACK)
- i2c_error = 1;
-
-write_exit:
- flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
- return i2c_error;
-}
-
static void flush_fifo(void)
{ u16 stat;
@@ -372,26 +301,75 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
int i;
+ u16 status;
+ int i2c_error = 0;
if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
+ printf("I2C write: address 0x%x + 0x%x out of range\n");
return 1;
}
+ /* wait until bus not busy */
+ wait_for_bb();
+
+ /* start address phase - will write regoffset + len bytes data */
+ /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+ writew(alen+len, &i2c_base->cnt);
+ /* set slave address */
+ writew(chip, &i2c_base->sa);
+ /* stop bit needed here */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con);
+
+ /* Send address byte */
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(addr & 0xFF, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ /* address phase is over, now write data */
for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("%s:%d error status=0x%x\n",
+ __func__, __LINE__, status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(buffer[i], &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("%s:%d i=%d error status=0x%x\n",
+ __func__, __LINE__, i, status);
+ goto write_exit;
}
}
- return 0;
+write_exit:
+ flush_fifo();
+ writew(0xFFFF, &i2c_base->stat);
+ return i2c_error;
}
static void wait_for_bb (void)
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-15 9:09 ` [U-Boot] [PATCH 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X Michael Jones
@ 2011-07-18 15:00 ` Michael Jones
2011-07-27 9:57 ` Igor Grinberg
2011-08-04 13:46 ` [U-Boot] [PATCH v3] " Michael Jones
0 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-18 15:00 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
MAINTAINERS | 4 +
MAKEALL | 1 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 171 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 312 +++++++++++++++++++++++++
12 files changed, 1591 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 2bba7b4..866f75a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -678,6 +678,10 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/MAKEALL b/MAKEALL
index 51db13e..fc06e86 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -434,6 +434,7 @@ LIST_ARMV7=" \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
+ omap3_mvblx \
omap4_panda \
omap4_sdp4430 \
s5p_goni \
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..9ad83d8
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/arch/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (omap_request_gpio(GPIO_DCLK) ||
+ omap_request_gpio(GPIO_nSTATUS) ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_request_gpio(GPIO_CONF_DONE) ||
+#endif
+ omap_request_gpio(GPIO_nCONFIG) ||
+ omap_request_gpio(GPIO_DATA0) ||
+ omap_request_gpio(GPIO_DATA1) ||
+ omap_request_gpio(GPIO_DATA2) ||
+ omap_request_gpio(GPIO_DATA3) ||
+ omap_request_gpio(GPIO_DATA4) ||
+ omap_request_gpio(GPIO_DATA5) ||
+ omap_request_gpio(GPIO_DATA6) ||
+ omap_request_gpio(GPIO_DATA7)) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ omap_set_gpio_direction(GPIO_DCLK, 0);
+ omap_set_gpio_direction(GPIO_nCONFIG, 0);
+ omap_set_gpio_direction(GPIO_DATA0, 0);
+ omap_set_gpio_direction(GPIO_DATA1, 0);
+ omap_set_gpio_direction(GPIO_DATA2, 0);
+ omap_set_gpio_direction(GPIO_DATA3, 0);
+ omap_set_gpio_direction(GPIO_DATA4, 0);
+ omap_set_gpio_direction(GPIO_DATA5, 0);
+ omap_set_gpio_direction(GPIO_DATA6, 0);
+ omap_set_gpio_direction(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ */
+
+ /* set up inputs */
+ omap_set_gpio_direction(GPIO_nSTATUS, 1);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_set_gpio_direction(GPIO_CONF_DONE, 1);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ omap_set_gpio_dataout(GPIO_nCONFIG, !assert);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (omap_get_gpio_datain(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ omap_free_gpio(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = omap_get_gpio_datain(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ /* TODO it takes ~7s to call this routine 368,011 times
+ * even when the udelay() calls are removed completely.
+ * Where does all this time come from?
+ */
+ omap_set_gpio_dataout(GPIO_DATA0, byte & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA1, (byte >> 1) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA2, (byte >> 2) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA3, (byte >> 3) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA4, (byte >> 4) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA5, (byte >> 5) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA6, (byte >> 6) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ omap_set_gpio_dataout(GPIO_DCLK, 1);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..e117e84
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..1b8a005
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,171 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* board id for Linux */
+ gd->bd->bi_arch_number = MACH_TYPE_MVBLX;
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..4c0fc49
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+/* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+/*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..029cf20
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index dfefc3f..3c8b762 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -151,6 +151,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 460950d..b0d875c 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..eb41b12
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,312 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE
2011-07-15 9:09 ` [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE Michael Jones
2011-07-18 14:45 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-07-18 17:39 ` Mike Frysinger
1 sibling, 0 replies; 48+ messages in thread
From: Mike Frysinger @ 2011-07-18 17:39 UTC (permalink / raw)
To: u-boot
On Fri, Jul 15, 2011 at 05:09, Michael Jones wrote:
> Doesn't make sense to provide this function to boards which defined
> CONFIG_ENV_IS_NOWHERE. Such a board gets a linking error because
> common/env_nowhere.c doesn't define saveenv().
Acked-by: Mike Frysinger <vapier@gentoo.org>
-mike
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot
2011-07-15 9:09 ` [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot Michael Jones
2011-07-18 14:40 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-07-19 2:06 ` Jaehoon Chung
2011-07-20 8:51 ` Michael Jones
1 sibling, 1 reply; 48+ messages in thread
From: Jaehoon Chung @ 2011-07-19 2:06 UTC (permalink / raw)
To: u-boot
Hi Michael.
I have some question. there are some mmc_init().
But you are only checked there..
Did you have any special reason?
Regards,
Jaehoon Chung
Michael Jones wrote:
> Fail in 'mmc rescan' if mmc_init() returns error
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> common/cmd_mmc.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
> index 176646d..28918f6 100644
> --- a/common/cmd_mmc.c
> +++ b/common/cmd_mmc.c
> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> }
>
> mmc->has_init = 0;
> - mmc_init(mmc);
>
> - return 0;
> + if (mmc_init(mmc))
> + return 1;
> + else
> + return 0;
> } else if (strncmp(argv[1], "part", 4) == 0) {
> block_dev_desc_t *mmc_dev;
> struct mmc *mmc = find_mmc_device(curr_device);
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot
2011-07-19 2:06 ` [U-Boot] [PATCH " Jaehoon Chung
@ 2011-07-20 8:51 ` Michael Jones
2011-07-20 9:52 ` Jaehoon Chung
0 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-07-20 8:51 UTC (permalink / raw)
To: u-boot
Hi Jaehoon Chung,
On 07/19/2011 04:06 AM, Jaehoon Chung wrote:
>
> Hi Michael.
>
> I have some question. there are some mmc_init().
> But you are only checked there..
> Did you have any special reason?
>
> Regards,
> Jaehoon Chung
The purpose of my patch was to enable an if/else to detect whether there
was a card in the slot. Among the available mmc commands, I thought 'mmc
rescan' was the most logical to be able to use to detect whether a slot
was empty or not.
Below is a survey of other places where a similar check could be done. I
think that if a similar check is to be made in these cases, they could
be in separate patch(es) from this one.
- 'mmc read/write': These commands should fail anyway if the slot were
empty.
- 'mmc part' prints "## Unknown partition table" if the slot is empty,
although the command itself still returns successfully. I suppose the
check could make sense here.
- 'mmc dev': I thought there was perhaps a use case where it makes sense
to switch to a mmc device which is currently empty. If that is not true,
it would probably make sense to do the same check there.
- 'mmcinfo': Currently this basically prints '0' for all the fields when
the slot is empty. It probably would be more logical to print "device
init failed" or similar instead.
-Michael
>
> Michael Jones wrote:
>> Fail in 'mmc rescan' if mmc_init() returns error
>>
>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>> ---
>> common/cmd_mmc.c | 6 ++++--
>> 1 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
>> index 176646d..28918f6 100644
>> --- a/common/cmd_mmc.c
>> +++ b/common/cmd_mmc.c
>> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> }
>>
>> mmc->has_init = 0;
>> - mmc_init(mmc);
>>
>> - return 0;
>> + if (mmc_init(mmc))
>> + return 1;
>> + else
>> + return 0;
>> } else if (strncmp(argv[1], "part", 4) == 0) {
>> block_dev_desc_t *mmc_dev;
>> struct mmc *mmc = find_mmc_device(curr_device);
>
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot
2011-07-20 8:51 ` Michael Jones
@ 2011-07-20 9:52 ` Jaehoon Chung
0 siblings, 0 replies; 48+ messages in thread
From: Jaehoon Chung @ 2011-07-20 9:52 UTC (permalink / raw)
To: u-boot
Hi Michael
Thanks for your explanation. :)
Regards,
Jaehoon Chung
Michael Jones wrote:
> Hi Jaehoon Chung,
>
> On 07/19/2011 04:06 AM, Jaehoon Chung wrote:
>> Hi Michael.
>>
>> I have some question. there are some mmc_init().
>> But you are only checked there..
>> Did you have any special reason?
>>
>> Regards,
>> Jaehoon Chung
>
> The purpose of my patch was to enable an if/else to detect whether there
> was a card in the slot. Among the available mmc commands, I thought 'mmc
> rescan' was the most logical to be able to use to detect whether a slot
> was empty or not.
>
> Below is a survey of other places where a similar check could be done. I
> think that if a similar check is to be made in these cases, they could
> be in separate patch(es) from this one.
>
> - 'mmc read/write': These commands should fail anyway if the slot were
> empty.
> - 'mmc part' prints "## Unknown partition table" if the slot is empty,
> although the command itself still returns successfully. I suppose the
> check could make sense here.
> - 'mmc dev': I thought there was perhaps a use case where it makes sense
> to switch to a mmc device which is currently empty. If that is not true,
> it would probably make sense to do the same check there.
> - 'mmcinfo': Currently this basically prints '0' for all the fields when
> the slot is empty. It probably would be more logical to print "device
> init failed" or similar instead.
>
> -Michael
>
>> Michael Jones wrote:
>>> Fail in 'mmc rescan' if mmc_init() returns error
>>>
>>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>>> ---
>>> common/cmd_mmc.c | 6 ++++--
>>> 1 files changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
>>> index 176646d..28918f6 100644
>>> --- a/common/cmd_mmc.c
>>> +++ b/common/cmd_mmc.c
>>> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> }
>>>
>>> mmc->has_init = 0;
>>> - mmc_init(mmc);
>>>
>>> - return 0;
>>> + if (mmc_init(mmc))
>>> + return 1;
>>> + else
>>> + return 0;
>>> } else if (strncmp(argv[1], "part", 4) == 0) {
>>> block_dev_desc_t *mmc_dev;
>>> struct mmc *mmc = find_mmc_device(curr_device);
>
>
> MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
> Registergericht: Amtsgericht Stuttgart, HRB 271090
> Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-18 14:58 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-07-27 6:07 ` Heiko Schocher
2011-07-27 7:42 ` Michael Jones
0 siblings, 1 reply; 48+ messages in thread
From: Heiko Schocher @ 2011-07-27 6:07 UTC (permalink / raw)
To: u-boot
Hello Michael,
Sorry for the long delay...
Michael Jones wrote:
> This allows the EEPROM layer to send a single i2c write command
> per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
> i2c write commands.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> drivers/i2c/omap24xx_i2c.c | 134 ++++++++++++++++++-------------------------
> 1 files changed, 56 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index 966ffc4..4ae03bc 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
[...]
> @@ -372,26 +301,75 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
> int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
> {
> int i;
> + u16 status;
> + int i2c_error = 0;
>
> if (alen > 1) {
> - printf ("I2C read: addr len %d not supported\n", alen);
> + printf("I2C write: addr len %d not supported\n", alen);
> return 1;
> }
>
> if (addr + len > 256) {
> - printf ("I2C read: address out of range\n");
> + printf("I2C write: address 0x%x + 0x%x out of range\n");
> return 1;
> }
>
> + /* wait until bus not busy */
> + wait_for_bb();
> +
> + /* start address phase - will write regoffset + len bytes data */
> + /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
Do we have this usecase?
> + writew(alen+len, &i2c_base->cnt);
please change to "alen + len"
> + /* set slave address */
> + writew(chip, &i2c_base->sa);
> + /* stop bit needed here */
> + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
> + I2C_CON_STP, &i2c_base->con);
> +
> + /* Send address byte */
> + status = wait_for_pin();
> +
> + if (status == 0 || status & I2C_STAT_NACK) {
> + i2c_error = 1;
> + printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
Can you change this printf to output some more info, instead __func__, __LINE__?
> + goto write_exit;
> + }
> +
> + if (status & I2C_STAT_XRDY) {
> + writeb(addr & 0xFF, &i2c_base->data);
> + writew(I2C_STAT_XRDY, &i2c_base->stat);
> + } else {
> + i2c_error = 1;
> + printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
here too.
> + goto write_exit;
> + }
> +
> + /* address phase is over, now write data */
> for (i = 0; i < len; i++) {
> - if (i2c_write_byte (chip, addr + i, buffer[i])) {
> - printf ("I2C read: I/O error\n");
> - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
> - return 1;
> + status = wait_for_pin();
> +
> + if (status == 0 || status & I2C_STAT_NACK) {
> + i2c_error = 1;
> + printf("%s:%d error status=0x%x\n",
> + __func__, __LINE__, status);
also here ...
> + goto write_exit;
> + }
> +
> + if (status & I2C_STAT_XRDY) {
> + writeb(buffer[i], &i2c_base->data);
> + writew(I2C_STAT_XRDY, &i2c_base->stat);
> + } else {
> + i2c_error = 1;
> + printf("%s:%d i=%d error status=0x%x\n",
> + __func__, __LINE__, i, status);
and here.
> + goto write_exit;
> }
> }
>
> - return 0;
> +write_exit:
> + flush_fifo();
> + writew(0xFFFF, &i2c_base->stat);
> + return i2c_error;
> }
>
> static void wait_for_bb (void)
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-27 6:07 ` Heiko Schocher
@ 2011-07-27 7:42 ` Michael Jones
2011-07-27 7:53 ` Heiko Schocher
2011-07-27 21:00 ` [U-Boot] [PATCH v2 6/7] " Wolfgang Denk
0 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-27 7:42 UTC (permalink / raw)
To: u-boot
Hi Heiko,
Thanks for the review.
On 07/27/2011 08:07 AM, Heiko Schocher wrote:
>
> Hello Michael,
>
> Sorry for the long delay...
>
> Michael Jones wrote:
>> This allows the EEPROM layer to send a single i2c write command
>> per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
>> i2c write commands.
>>
>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>> ---
>> Changes for v2:
>> - None. Resubmitting to include custodian in cc:
>>
>> drivers/i2c/omap24xx_i2c.c | 134 ++++++++++++++++++-------------------------
>> 1 files changed, 56 insertions(+), 78 deletions(-)
>>
>> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
>> index 966ffc4..4ae03bc 100644
>> --- a/drivers/i2c/omap24xx_i2c.c
>> +++ b/drivers/i2c/omap24xx_i2c.c
> [...]
>> @@ -372,26 +301,75 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
>> int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
>> {
>> int i;
>> + u16 status;
>> + int i2c_error = 0;
>>
>> if (alen > 1) {
>> - printf ("I2C read: addr len %d not supported\n", alen);
>> + printf("I2C write: addr len %d not supported\n", alen);
>> return 1;
>> }
>>
>> if (addr + len > 256) {
>> - printf ("I2C read: address out of range\n");
>> + printf("I2C write: address 0x%x + 0x%x out of range\n");
>> return 1;
>> }
>>
>> + /* wait until bus not busy */
>> + wait_for_bb();
>> +
>> + /* start address phase - will write regoffset + len bytes data */
>> + /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
>
> Do we have this usecase?
I don't know, I assumed so, as there is the following #ifdef in the part
I removed:
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
defined(CONFIG_OMAP44XX)
#else
/* there is code here that I didn't consider when replacing it. */
#endif
>
>> + writew(alen+len, &i2c_base->cnt);
>
> please change to "alen + len"
OK. I thought checkpatch.pl would've found that.
>
>> + /* set slave address */
>> + writew(chip, &i2c_base->sa);
>> + /* stop bit needed here */
>> + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
>> + I2C_CON_STP, &i2c_base->con);
>> +
>> + /* Send address byte */
>> + status = wait_for_pin();
>> +
>> + if (status == 0 || status & I2C_STAT_NACK) {
>> + i2c_error = 1;
>> + printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
>
> Can you change this printf to output some more info, instead __func__, __LINE__?
OK, I will make these more informative. Do you not want __func__ to be
in the output? I originally put __LINE__ in as well because the strings
were otherwise identical, so I'm fine with getting rid of that once the
messages are unique.
[snip]
>
> bye,
> Heiko
Question about cosmetics: the README says "In sources originating from
U-Boot a style corresponding to "Lindent -pcs" (adding spaces before
parameters to function calls) is actually used." Currently this is not
uniform in this file, because checkpatch.pl doesn't like the spaces
between function names and '(' (and neither do I). Are there supposed to
be such spaces in U-Boot code? Or can we uniformly remove them in this file?
-Michael
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-27 7:42 ` Michael Jones
@ 2011-07-27 7:53 ` Heiko Schocher
2011-07-27 12:41 ` [U-Boot] [PATCH v3] " Michael Jones
2011-07-27 21:00 ` [U-Boot] [PATCH v2 6/7] " Wolfgang Denk
1 sibling, 1 reply; 48+ messages in thread
From: Heiko Schocher @ 2011-07-27 7:53 UTC (permalink / raw)
To: u-boot
Hello Michael,
Michael Jones wrote:
> Hi Heiko,
>
> Thanks for the review.
>
> On 07/27/2011 08:07 AM, Heiko Schocher wrote:
>> Hello Michael,
>>
>> Sorry for the long delay...
>>
>> Michael Jones wrote:
>>> This allows the EEPROM layer to send a single i2c write command
>>> per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
>>> i2c write commands.
>>>
>>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>>> ---
>>> Changes for v2:
>>> - None. Resubmitting to include custodian in cc:
>>>
>>> drivers/i2c/omap24xx_i2c.c | 134 ++++++++++++++++++-------------------------
>>> 1 files changed, 56 insertions(+), 78 deletions(-)
>>>
>>> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
>>> index 966ffc4..4ae03bc 100644
>>> --- a/drivers/i2c/omap24xx_i2c.c
>>> +++ b/drivers/i2c/omap24xx_i2c.c
>> [...]
>>> @@ -372,26 +301,75 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
>>> int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
>>> {
>>> int i;
>>> + u16 status;
>>> + int i2c_error = 0;
>>>
>>> if (alen > 1) {
>>> - printf ("I2C read: addr len %d not supported\n", alen);
>>> + printf("I2C write: addr len %d not supported\n", alen);
>>> return 1;
>>> }
>>>
>>> if (addr + len > 256) {
>>> - printf ("I2C read: address out of range\n");
>>> + printf("I2C write: address 0x%x + 0x%x out of range\n");
>>> return 1;
>>> }
>>>
>>> + /* wait until bus not busy */
>>> + wait_for_bb();
>>> +
>>> + /* start address phase - will write regoffset + len bytes data */
>>> + /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
>> Do we have this usecase?
>
> I don't know, I assumed so, as there is the following #ifdef in the part
> I removed:
>
> #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
> defined(CONFIG_OMAP44XX)
> #else
> /* there is code here that I didn't consider when replacing it. */
> #endif
Hmm.. I have to look at this deeper, but your patch shouldn;t break
any existing board...
>>> + writew(alen+len, &i2c_base->cnt);
>> please change to "alen + len"
>
> OK. I thought checkpatch.pl would've found that.
Yes, I also checked your patch with checkpatch, but it didn;t found
this ...
>>> + /* set slave address */
>>> + writew(chip, &i2c_base->sa);
>>> + /* stop bit needed here */
>>> + writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
>>> + I2C_CON_STP, &i2c_base->con);
>>> +
>>> + /* Send address byte */
>>> + status = wait_for_pin();
>>> +
>>> + if (status == 0 || status & I2C_STAT_NACK) {
>>> + i2c_error = 1;
>>> + printf("%s:%d error status=0x%x\n", __func__, __LINE__, status);
>> Can you change this printf to output some more info, instead __func__, __LINE__?
>
> OK, I will make these more informative. Do you not want __func__ to be
> in the output? I originally put __LINE__ in as well because the strings
> were otherwise identical, so I'm fine with getting rid of that once the
> messages are unique.
Thanks! I think, we don;t need __func__ and __LINE__, if you make
informative printfs ...
> [snip]
>
>> bye,
>> Heiko
>
> Question about cosmetics: the README says "In sources originating from
> U-Boot a style corresponding to "Lindent -pcs" (adding spaces before
> parameters to function calls) is actually used." Currently this is not
> uniform in this file, because checkpatch.pl doesn't like the spaces
> between function names and '(' (and neither do I). Are there supposed to
> be such spaces in U-Boot code? Or can we uniformly remove them in this file?
We should get this "checkpatch compatible". If you do such a
cosmetic change, please split this in a seperate patch, thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-18 15:00 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-07-27 9:57 ` Igor Grinberg
2011-08-04 13:46 ` [U-Boot] [PATCH v3] " Michael Jones
1 sibling, 0 replies; 48+ messages in thread
From: Igor Grinberg @ 2011-07-27 9:57 UTC (permalink / raw)
To: u-boot
Hi Michael,
On 07/18/11 18:00, Michael Jones wrote:
> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
> intelligent camera.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
[...]
> new file mode 100644
> index 0000000..1b8a005
> --- /dev/null
> +++ b/board/matrix_vision/mvblx/mvblx.c
[...]
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
> + /* board id for Linux */
> + gd->bd->bi_arch_number = MACH_TYPE_MVBLX;
This should be done in the board config file.
Please, see the CONFIG_MACH_TYPE in the U-Boot documentation (README file).
--
Regards,
Igor.
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-27 7:53 ` Heiko Schocher
@ 2011-07-27 12:41 ` Michael Jones
2011-07-27 12:41 ` [U-Boot] [PATCH] ARMV7: OMAP: I2C driver: cosmetic: make checkpatch-compatible Michael Jones
2011-08-01 9:12 ` [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Heiko Schocher
0 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-27 12:41 UTC (permalink / raw)
To: u-boot
This allows the EEPROM layer to send a single i2c write command
per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
i2c write commands.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v3:
- Rewrote error messages to be more descriptive.
Changes for v2:
- None. Resubmitting to include custodian in cc:
drivers/i2c/omap24xx_i2c.c | 135 ++++++++++++++++++-------------------------
1 files changed, 57 insertions(+), 78 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 966ffc4..19e024d 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -216,77 +216,6 @@ read_exit:
return i2c_error;
}
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- writew (2, &i2c_base->cnt);
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send register offset */
- writeb(regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
- /* send data */
- writeb(value, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
- break;
-#else
- /* send out two bytes */
- writew((value << 8) + regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-#endif
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
- wait_for_bb();
-
- status = readw(&i2c_base->stat);
- if (status & I2C_STAT_NACK)
- i2c_error = 1;
-
-write_exit:
- flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
- return i2c_error;
-}
-
static void flush_fifo(void)
{ u16 stat;
@@ -372,26 +301,76 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
int i;
+ u16 status;
+ int i2c_error = 0;
if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
+ printf("I2C write: address 0x%x + 0x%x out of range\n");
return 1;
}
+ /* wait until bus not busy */
+ wait_for_bb();
+
+ /* start address phase - will write regoffset + len bytes data */
+ /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+ writew(alen + len, &i2c_base->cnt);
+ /* set slave address */
+ writew(chip, &i2c_base->sa);
+ /* stop bit needed here */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con);
+
+ /* Send address byte */
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("error waiting for i2c address ACK (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(addr & 0xFF, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("i2c bus not ready for transmit (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ /* address phase is over, now write data */
for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("i2c error waiting for data ACK (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(buffer[i], &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("i2c bus not ready for Tx (i=%d)\n", i);
+ goto write_exit;
}
}
- return 0;
+write_exit:
+ flush_fifo();
+ writew(0xFFFF, &i2c_base->stat);
+ return i2c_error;
}
static void wait_for_bb (void)
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH] ARMV7: OMAP: I2C driver: cosmetic: make checkpatch-compatible
2011-07-27 12:41 ` [U-Boot] [PATCH v3] " Michael Jones
@ 2011-07-27 12:41 ` Michael Jones
2011-08-01 9:12 ` [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Heiko Schocher
1 sibling, 0 replies; 48+ messages in thread
From: Michael Jones @ 2011-07-27 12:41 UTC (permalink / raw)
To: u-boot
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
drivers/i2c/omap24xx_i2c.c | 105 ++++++++++++++++++++++----------------------
1 files changed, 53 insertions(+), 52 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 19e024d..c812001 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -31,8 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define I2C_TIMEOUT 1000
-static void wait_for_bb (void);
-static u16 wait_for_pin (void);
+static void wait_for_bb(void);
+static u16 wait_for_pin(void);
static void flush_fifo(void);
static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
@@ -40,7 +40,7 @@ static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE;
static unsigned int bus_initialized[I2C_BUS_MAX];
static unsigned int current_bus;
-void i2c_init (int speed, int slaveadd)
+void i2c_init(int speed, int slaveadd)
{
int psc, fsscll, fssclh;
int hsscll = 0, hssclh = 0;
@@ -107,9 +107,9 @@ void i2c_init (int speed, int slaveadd)
sclh = (unsigned int)fssclh;
}
- if (readw (&i2c_base->con) & I2C_CON_EN) {
- writew (0, &i2c_base->con);
- udelay (50000);
+ if (readw(&i2c_base->con) & I2C_CON_EN) {
+ writew(0, &i2c_base->con);
+ udelay(50000);
}
writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
@@ -130,35 +130,36 @@ void i2c_init (int speed, int slaveadd)
writew(sclh, &i2c_base->sclh);
/* own address */
- writew (slaveadd, &i2c_base->oa);
- writew (I2C_CON_EN, &i2c_base->con);
+ writew(slaveadd, &i2c_base->oa);
+ writew(I2C_CON_EN, &i2c_base->con);
/* have to enable intrrupts or OMAP i2c module doesn't work */
- writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
+ writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
- udelay (1000);
+ udelay(1000);
flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
+ writew(0xFFFF, &i2c_base->stat);
+ writew(0, &i2c_base->cnt);
if (gd->flags & GD_FLG_RELOC)
bus_initialized[current_bus] = 1;
}
-static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
+static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value)
{
int i2c_error = 0;
u16 status;
/* wait until bus not busy */
- wait_for_bb ();
+ wait_for_bb();
/* one byte only */
- writew (1, &i2c_base->cnt);
+ writew(1, &i2c_base->cnt);
/* set slave address */
- writew (devaddr, &i2c_base->sa);
+ writew(devaddr, &i2c_base->sa);
/* no stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con);
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
+ I2C_CON_TRX, &i2c_base->con);
/* send register offset */
while (1) {
@@ -196,7 +197,7 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
}
if (status & I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
+ defined(CONFIG_OMAP44XX)
*value = readb(&i2c_base->data);
#else
*value = readw(&i2c_base->data);
@@ -211,8 +212,8 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value)
read_exit:
flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
+ writew(0xFFFF, &i2c_base->stat);
+ writew(0, &i2c_base->cnt);
return i2c_error;
}
@@ -222,38 +223,37 @@ static void flush_fifo(void)
/* note: if you try and read data when its not there or ready
* you get a bus error
*/
- while(1){
+ while (1) {
stat = readw(&i2c_base->stat);
- if(stat == I2C_STAT_RRDY){
+ if (stat == I2C_STAT_RRDY) {
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
+ defined(CONFIG_OMAP44XX)
readb(&i2c_base->data);
#else
readw(&i2c_base->data);
#endif
- writew(I2C_STAT_RRDY,&i2c_base->stat);
+ writew(I2C_STAT_RRDY, &i2c_base->stat);
udelay(1000);
- }else
+ } else
break;
}
}
-int i2c_probe (uchar chip)
+int i2c_probe(uchar chip)
{
u16 status;
int res = 1; /* default = fail */
- if (chip == readw (&i2c_base->oa)) {
+ if (chip == readw(&i2c_base->oa))
return res;
- }
/* wait until bus not busy */
- wait_for_bb ();
+ wait_for_bb();
/* try to write one byte */
- writew (1, &i2c_base->cnt);
+ writew(1, &i2c_base->cnt);
/* set slave address */
- writew (chip, &i2c_base->sa);
+ writew(chip, &i2c_base->sa);
/* stop bit needed here */
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
@@ -268,29 +268,30 @@ int i2c_probe (uchar chip)
writew(0, &i2c_base->con);
flush_fifo();
- writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/
+ /* don't allow any more data in... we don't want it. */
+ writew(0, &i2c_base->cnt);
writew(0xFFFF, &i2c_base->stat);
return res;
}
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int i;
if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C read: addr len %d not supported\n", alen);
return 1;
}
if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
+ printf("I2C read: address out of range\n");
return 1;
}
for (i = 0; i < len; i++) {
- if (i2c_read_byte (chip, addr + i, &buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ if (i2c_read_byte(chip, addr + i, &buffer[i])) {
+ printf("I2C read: I/O error\n");
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 1;
}
}
@@ -298,7 +299,7 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
return 0;
}
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int i;
u16 status;
@@ -373,40 +374,40 @@ write_exit:
return i2c_error;
}
-static void wait_for_bb (void)
+static void wait_for_bb(void)
{
int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
- while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
- writew (stat, &i2c_base->stat);
+ while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
+ writew(stat, &i2c_base->stat);
udelay(1000);
}
if (timeout <= 0) {
- printf ("timed out in wait_for_bb: I2C_STAT=%x\n",
- readw (&i2c_base->stat));
+ printf("timed out in wait_for_bb: I2C_STAT=%x\n",
+ readw(&i2c_base->stat));
}
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
}
-static u16 wait_for_pin (void)
+static u16 wait_for_pin(void)
{
u16 status;
int timeout = I2C_TIMEOUT;
do {
- udelay (1000);
- status = readw (&i2c_base->stat);
- } while ( !(status &
+ udelay(1000);
+ status = readw(&i2c_base->stat);
+ } while (!(status &
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
I2C_STAT_AL)) && timeout--);
if (timeout <= 0) {
- printf ("timed out in wait_for_pin: I2C_STAT=%x\n",
- readw (&i2c_base->stat));
+ printf("timed out in wait_for_pin: I2C_STAT=%x\n",
+ readw(&i2c_base->stat));
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
@@ -421,7 +422,7 @@ int i2c_set_bus_num(unsigned int bus)
return -1;
}
-#if I2C_BUS_MAX==3
+#if I2C_BUS_MAX == 3
if (bus == 2)
i2c_base = (struct i2c *)I2C_BASE3;
else
@@ -433,7 +434,7 @@ int i2c_set_bus_num(unsigned int bus)
current_bus = bus;
- if(!bus_initialized[current_bus])
+ if (!bus_initialized[current_bus])
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
return 0;
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-27 7:42 ` Michael Jones
2011-07-27 7:53 ` Heiko Schocher
@ 2011-07-27 21:00 ` Wolfgang Denk
1 sibling, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-07-27 21:00 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <4E2FC14F.6080907@matrix-vision.de> you wrote:
>
> Question about cosmetics: the README says "In sources originating from
> U-Boot a style corresponding to "Lindent -pcs" (adding spaces before
> parameters to function calls) is actually used." Currently this is not
This was the old (aka "my own") style. But I got overruled.
I'm going to post a patch to fix the README.
> uniform in this file, because checkpatch.pl doesn't like the spaces
> between function names and '(' (and neither do I). Are there supposed to
> be such spaces in U-Boot code? Or can we uniformly remove them in this file?
Please remove them.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"A little knowledge is a dangerous thing." - Doug Gwyn
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5
2011-07-15 9:09 ` [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5 Michael Jones
@ 2011-07-28 14:46 ` Wolfgang Denk
0 siblings, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-07-28 14:46 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <1310720986-5474-2-git-send-email-michael.jones@matrix-vision.de> you wrote:
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> include/ACEX1K.h | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"Gravitation cannot be held responsible for people falling in love."
- Albert Einstein
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration
2011-07-15 9:09 ` [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration Michael Jones
@ 2011-07-28 14:47 ` Wolfgang Denk
0 siblings, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-07-28 14:47 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <1310720986-5474-3-git-send-email-michael.jones@matrix-vision.de> you wrote:
> Support FPGAs which use Fast Passive Parallel configuration
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> drivers/fpga/cyclon2.c | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
It is easier to write an incorrect program than understand a correct
one.
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE
2011-07-18 14:45 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-07-28 14:49 ` Wolfgang Denk
0 siblings, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-07-28 14:49 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <1311000325-8030-1-git-send-email-michael.jones@matrix-vision.de> you wrote:
> Doesn't make sense to provide this function to boards which defined
> CONFIG_ENV_IS_NOWHERE. Such a board gets a linking error because
> common/env_nowhere.c doesn't define saveenv().
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> board/matrix_vision/common/mv_common.c | 2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
Applied, thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Fascinating, a totally parochial attitude.
-- Spock, "Metamorphosis", stardate 3219.8
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-07-27 12:41 ` [U-Boot] [PATCH v3] " Michael Jones
2011-07-27 12:41 ` [U-Boot] [PATCH] ARMV7: OMAP: I2C driver: cosmetic: make checkpatch-compatible Michael Jones
@ 2011-08-01 9:12 ` Heiko Schocher
2011-08-01 10:14 ` [U-Boot] [PATCH v4] " Michael Jones
1 sibling, 1 reply; 48+ messages in thread
From: Heiko Schocher @ 2011-08-01 9:12 UTC (permalink / raw)
To: u-boot
Hello Michael,
Michael Jones wrote:
> This allows the EEPROM layer to send a single i2c write command
> per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
> i2c write commands.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v3:
> - Rewrote error messages to be more descriptive.
>
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> drivers/i2c/omap24xx_i2c.c | 135 ++++++++++++++++++-------------------------
> 1 files changed, 57 insertions(+), 78 deletions(-)
Doing a "MAKEALL" for the omap boards throws following
warning:
Configuring for cm_t35 board...
omap24xx_i2c.c: In function 'i2c_write':
omap24xx_i2c.c:314: warning: too few arguments for format
text data bss dec hex filename
287288 8156 221036 516480 7e180 ./u-boot
Configuring for omap3_overo board...
omap24xx_i2c.c: In function 'i2c_write':
omap24xx_i2c.c:314: warning: too few arguments for format
text data bss dec hex filename
256804 7556 212180 476540 7457c ./u-boot
Configuring for omap3_pandora board...
omap24xx_i2c.c: In function 'i2c_write':
omap24xx_i2c.c:314: warning: too few arguments for format
text data bss dec hex filename
366033 7956 206620 580609 8dc01 ./u-boot
[...]
Please fix!
>
> diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
> index 966ffc4..19e024d 100644
> --- a/drivers/i2c/omap24xx_i2c.c
> +++ b/drivers/i2c/omap24xx_i2c.c
[...]
> @@ -372,26 +301,76 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
> int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
> {
> int i;
> + u16 status;
> + int i2c_error = 0;
>
> if (alen > 1) {
> - printf ("I2C read: addr len %d not supported\n", alen);
> + printf("I2C write: addr len %d not supported\n", alen);
> return 1;
> }
>
> if (addr + len > 256) {
> - printf ("I2C read: address out of range\n");
> + printf("I2C write: address 0x%x + 0x%x out of range\n");
^^^^ ^^^^
missing Arguments here!
@Sandeep Paulraj, beside of that warning, could you Ack/Nack this patch,
so I can apply this patch to u-boot-i2c, or do you pick up this patch?
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-08-01 9:12 ` [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Heiko Schocher
@ 2011-08-01 10:14 ` Michael Jones
2011-08-02 6:37 ` Heiko Schocher
0 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-08-01 10:14 UTC (permalink / raw)
To: u-boot
This allows the EEPROM layer to send a single i2c write command
per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
i2c write commands.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v4:
- Added missing args for printf on out-of-range
Changes for v3:
- Rewrote error messages to be more descriptive.
Changes for v2:
- None. Resubmitting to include custodian in cc:
drivers/i2c/omap24xx_i2c.c | 136 +++++++++++++++++++-------------------------
1 files changed, 58 insertions(+), 78 deletions(-)
diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c
index 966ffc4..8effc5d 100644
--- a/drivers/i2c/omap24xx_i2c.c
+++ b/drivers/i2c/omap24xx_i2c.c
@@ -216,77 +216,6 @@ read_exit:
return i2c_error;
}
-static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value)
-{
- int i2c_error = 0;
- u16 status;
-
- /* wait until bus not busy */
- wait_for_bb ();
-
- /* two bytes */
- writew (2, &i2c_base->cnt);
- /* set slave address */
- writew (devaddr, &i2c_base->sa);
- /* stop bit needed here */
- writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
- I2C_CON_STP, &i2c_base->con);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
-#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \
- defined(CONFIG_OMAP44XX)
- /* send register offset */
- writeb(regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-
- while (1) {
- status = wait_for_pin();
- if (status == 0 || status & I2C_STAT_NACK) {
- i2c_error = 1;
- goto write_exit;
- }
- if (status & I2C_STAT_XRDY) {
- /* send data */
- writeb(value, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
- break;
-#else
- /* send out two bytes */
- writew((value << 8) + regoffset, &i2c_base->data);
- writew(I2C_STAT_XRDY, &i2c_base->stat);
-#endif
- }
- if (status & I2C_STAT_ARDY) {
- writew(I2C_STAT_ARDY, &i2c_base->stat);
- break;
- }
- }
-
- wait_for_bb();
-
- status = readw(&i2c_base->stat);
- if (status & I2C_STAT_NACK)
- i2c_error = 1;
-
-write_exit:
- flush_fifo();
- writew (0xFFFF, &i2c_base->stat);
- writew (0, &i2c_base->cnt);
- return i2c_error;
-}
-
static void flush_fifo(void)
{ u16 stat;
@@ -372,26 +301,77 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
{
int i;
+ u16 status;
+ int i2c_error = 0;
if (alen > 1) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
if (addr + len > 256) {
- printf ("I2C read: address out of range\n");
+ printf("I2C write: address 0x%x + 0x%x out of range\n",
+ addr, len);
return 1;
}
+ /* wait until bus not busy */
+ wait_for_bb();
+
+ /* start address phase - will write regoffset + len bytes data */
+ /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */
+ writew(alen + len, &i2c_base->cnt);
+ /* set slave address */
+ writew(chip, &i2c_base->sa);
+ /* stop bit needed here */
+ writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
+ I2C_CON_STP, &i2c_base->con);
+
+ /* Send address byte */
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("error waiting for i2c address ACK (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(addr & 0xFF, &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("i2c bus not ready for transmit (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ /* address phase is over, now write data */
for (i = 0; i < len; i++) {
- if (i2c_write_byte (chip, addr + i, buffer[i])) {
- printf ("I2C read: I/O error\n");
- i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- return 1;
+ status = wait_for_pin();
+
+ if (status == 0 || status & I2C_STAT_NACK) {
+ i2c_error = 1;
+ printf("i2c error waiting for data ACK (status=0x%x)\n",
+ status);
+ goto write_exit;
+ }
+
+ if (status & I2C_STAT_XRDY) {
+ writeb(buffer[i], &i2c_base->data);
+ writew(I2C_STAT_XRDY, &i2c_base->stat);
+ } else {
+ i2c_error = 1;
+ printf("i2c bus not ready for Tx (i=%d)\n", i);
+ goto write_exit;
}
}
- return 0;
+write_exit:
+ flush_fifo();
+ writew(0xFFFF, &i2c_base->stat);
+ return i2c_error;
}
static void wait_for_bb (void)
--
1.7.5.4
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-08-01 10:14 ` [U-Boot] [PATCH v4] " Michael Jones
@ 2011-08-02 6:37 ` Heiko Schocher
2011-09-04 17:59 ` Paulraj, Sandeep
0 siblings, 1 reply; 48+ messages in thread
From: Heiko Schocher @ 2011-08-02 6:37 UTC (permalink / raw)
To: u-boot
Hello Paulraj,
Michael Jones wrote:
> This allows the EEPROM layer to send a single i2c write command
> per page, and wait CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS between
> i2c write commands.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v4:
> - Added missing args for printf on out-of-range
>
> Changes for v3:
> - Rewrote error messages to be more descriptive.
>
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> drivers/i2c/omap24xx_i2c.c | 136 +++++++++++++++++++-------------------------
> 1 files changed, 58 insertions(+), 78 deletions(-)
This patch is now checkpatch and makeall clean, can you Ack/Nack
this patch, so I can pick it up, if you give your ack?
(Or do you want to apply it, so I can Ack it)
There is also a cosmetic (checkpatch cleanup) patch for this driver,
see:
http://patchwork.ozlabs.org/patch/107052/
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v3] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-18 15:00 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-27 9:57 ` Igor Grinberg
@ 2011-08-04 13:46 ` Michael Jones
2011-10-06 22:06 ` Wolfgang Denk
1 sibling, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-08-04 13:46 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v3:
- Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
Changes for v2:
- None. Resubmitting to include custodian in cc:
MAINTAINERS | 4 +
MAKEALL | 1 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
12 files changed, 1590 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f8d8559..78d4a14 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -685,6 +685,10 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/MAKEALL b/MAKEALL
index 266e231..cdd691e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -433,6 +433,7 @@ LIST_ARMV7=" \
omap3_sdp3430 \
omap3_zoom1 \
omap3_zoom2 \
+ omap3_mvblx \
omap4_panda \
omap4_sdp4430 \
s5p_goni \
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..9ad83d8
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/arch/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (omap_request_gpio(GPIO_DCLK) ||
+ omap_request_gpio(GPIO_nSTATUS) ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_request_gpio(GPIO_CONF_DONE) ||
+#endif
+ omap_request_gpio(GPIO_nCONFIG) ||
+ omap_request_gpio(GPIO_DATA0) ||
+ omap_request_gpio(GPIO_DATA1) ||
+ omap_request_gpio(GPIO_DATA2) ||
+ omap_request_gpio(GPIO_DATA3) ||
+ omap_request_gpio(GPIO_DATA4) ||
+ omap_request_gpio(GPIO_DATA5) ||
+ omap_request_gpio(GPIO_DATA6) ||
+ omap_request_gpio(GPIO_DATA7)) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ omap_set_gpio_direction(GPIO_DCLK, 0);
+ omap_set_gpio_direction(GPIO_nCONFIG, 0);
+ omap_set_gpio_direction(GPIO_DATA0, 0);
+ omap_set_gpio_direction(GPIO_DATA1, 0);
+ omap_set_gpio_direction(GPIO_DATA2, 0);
+ omap_set_gpio_direction(GPIO_DATA3, 0);
+ omap_set_gpio_direction(GPIO_DATA4, 0);
+ omap_set_gpio_direction(GPIO_DATA5, 0);
+ omap_set_gpio_direction(GPIO_DATA6, 0);
+ omap_set_gpio_direction(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ */
+
+ /* set up inputs */
+ omap_set_gpio_direction(GPIO_nSTATUS, 1);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_set_gpio_direction(GPIO_CONF_DONE, 1);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ omap_set_gpio_dataout(GPIO_nCONFIG, !assert);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (omap_get_gpio_datain(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ omap_free_gpio(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = omap_get_gpio_datain(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ /* TODO it takes ~7s to call this routine 368,011 times
+ * even when the udelay() calls are removed completely.
+ * Where does all this time come from?
+ */
+ omap_set_gpio_dataout(GPIO_DATA0, byte & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA1, (byte >> 1) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA2, (byte >> 2) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA3, (byte >> 3) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA4, (byte >> 4) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA5, (byte >> 5) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA6, (byte >> 6) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ omap_set_gpio_dataout(GPIO_DCLK, 1);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..e117e84
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..74b5b19
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..4c0fc49
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+/* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+/*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..029cf20
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3e79c82..10ce951 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -157,6 +157,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 460950d..b0d875c 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..bda83c6
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,313 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.6
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 4/7] mmc: rescan fails on empty slot
2011-07-18 14:40 ` [U-Boot] [PATCH v2 " Michael Jones
@ 2011-08-17 2:15 ` Andy Fleming
2011-08-17 2:30 ` Andy Fleming
0 siblings, 1 reply; 48+ messages in thread
From: Andy Fleming @ 2011-08-17 2:15 UTC (permalink / raw)
To: u-boot
On Mon, Jul 18, 2011 at 9:40 AM, Michael Jones
<michael.jones@matrix-vision.de> wrote:
> Fail in 'mmc rescan' if mmc_init() returns error
I think, if we're going to do this, we should change them all.
Also, for the purpose you want, it seems like we should consider
adding or modifying a command to just report whether the slot has a
card.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v2:
> ?- None. Resubmitting to include custodian in cc:
>
> ?common/cmd_mmc.c | ? ?6 ++++--
> ?1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
> index 176646d..28918f6 100644
> --- a/common/cmd_mmc.c
> +++ b/common/cmd_mmc.c
> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> ? ? ? ? ? ? ? ?}
>
> ? ? ? ? ? ? ? ?mmc->has_init = 0;
> - ? ? ? ? ? ? ? mmc_init(mmc);
>
> - ? ? ? ? ? ? ? return 0;
> + ? ? ? ? ? ? ? if (mmc_init(mmc))
> + ? ? ? ? ? ? ? ? ? ? ? return 1;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? return 0;
Is there a reason to return 1 instead of returning whatever error
mmc_init() returns?
ie:
return mmc_init(mmc);
Andy
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 4/7] mmc: rescan fails on empty slot
2011-08-17 2:15 ` Andy Fleming
@ 2011-08-17 2:30 ` Andy Fleming
2011-08-17 7:46 ` Michael Jones
0 siblings, 1 reply; 48+ messages in thread
From: Andy Fleming @ 2011-08-17 2:30 UTC (permalink / raw)
To: u-boot
Ok, I feel dumb. I apparently applied this already. But I'm still
interested in a response to my comments/questions. :)
On Tue, Aug 16, 2011 at 9:15 PM, Andy Fleming <afleming@gmail.com> wrote:
> On Mon, Jul 18, 2011 at 9:40 AM, Michael Jones
> <michael.jones@matrix-vision.de> wrote:
>> Fail in 'mmc rescan' if mmc_init() returns error
>
> I think, if we're going to do this, we should change them all.
>
> Also, for the purpose you want, it seems like we should consider
> adding or modifying a command to just report whether the slot has a
> card.
>
>
>>
>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>> ---
>> Changes for v2:
>> ?- None. Resubmitting to include custodian in cc:
>>
>> ?common/cmd_mmc.c | ? ?6 ++++--
>> ?1 files changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
>> index 176646d..28918f6 100644
>> --- a/common/cmd_mmc.c
>> +++ b/common/cmd_mmc.c
>> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>> ? ? ? ? ? ? ? ?}
>>
>> ? ? ? ? ? ? ? ?mmc->has_init = 0;
>> - ? ? ? ? ? ? ? mmc_init(mmc);
>>
>> - ? ? ? ? ? ? ? return 0;
>> + ? ? ? ? ? ? ? if (mmc_init(mmc))
>> + ? ? ? ? ? ? ? ? ? ? ? return 1;
>> + ? ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? ? return 0;
>
>
> Is there a reason to return 1 instead of returning whatever error
> mmc_init() returns?
>
> ie:
>
> return mmc_init(mmc);
>
>
> Andy
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v2 4/7] mmc: rescan fails on empty slot
2011-08-17 2:30 ` Andy Fleming
@ 2011-08-17 7:46 ` Michael Jones
0 siblings, 0 replies; 48+ messages in thread
From: Michael Jones @ 2011-08-17 7:46 UTC (permalink / raw)
To: u-boot
Hi Andy,
On 08/17/2011 04:30 AM, Andy Fleming wrote:
>
> Ok, I feel dumb. I apparently applied this already. But I'm still
> interested in a response to my comments/questions. :)
OK, I'll humor you :)
>
> On Tue, Aug 16, 2011 at 9:15 PM, Andy Fleming <afleming@gmail.com> wrote:
>> On Mon, Jul 18, 2011 at 9:40 AM, Michael Jones
>> <michael.jones@matrix-vision.de> wrote:
>>> Fail in 'mmc rescan' if mmc_init() returns error
>>
>> I think, if we're going to do this, we should change them all.
I agree it would be logical to return failed from the other mmc commands
if mmc_init() fails. I can submit such a patch for that if you want
after we agree the best way to structure the 'return' (see below).
>>
>> Also, for the purpose you want, it seems like we should consider
>> adding or modifying a command to just report whether the slot has a
>> card.
Yes, that would be logical and tidier than the current solution.
However, the way it is now also meets my needs, although it's ugly
because it prints "Card did not respond to voltage select!".
>>
>>
>>>
>>> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
>>> ---
>>> Changes for v2:
>>> - None. Resubmitting to include custodian in cc:
>>>
>>> common/cmd_mmc.c | 6 ++++--
>>> 1 files changed, 4 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
>>> index 176646d..28918f6 100644
>>> --- a/common/cmd_mmc.c
>>> +++ b/common/cmd_mmc.c
>>> @@ -165,9 +165,11 @@ int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>>> }
>>>
>>> mmc->has_init = 0;
>>> - mmc_init(mmc);
>>>
>>> - return 0;
>>> + if (mmc_init(mmc))
>>> + return 1;
>>> + else
>>> + return 0;
>>
>>
>> Is there a reason to return 1 instead of returning whatever error
>> mmc_init() returns?
>>
>> ie:
>>
>> return mmc_init(mmc);
It looked to me like do_mmcops should only return either a 1 for fail or
0 for success. mmc_init() returns UNUSABLE_ERR (interesting that it's
not NO_CARD_ERR) when there is no card.
This is the command I wanted to enable with the patch:
if mmc rescan; then echo "rescan true"; else echo "rescan false"; fi;
As it is, when the slot is empty this prints:
Card did not respond to voltage select!
rescan false
If UNUSABLE_ERR is returned directly from do_mmcops, I get:
Card did not respond to voltage select!
exit not allowed from main input shell.
Do you want something more compact like 'return !!mmc_init(mmc)' or
return mmc_init(mmc) ? 1 : 0; ?
>>
>>
>> Andy
>>
-Michael
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (6 preceding siblings ...)
2011-07-15 9:09 ` [U-Boot] [PATCH 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X Michael Jones
@ 2011-08-17 8:55 ` Michael Jones
2011-10-06 21:51 ` Wolfgang Denk
2011-10-05 15:08 ` [U-Boot] [PATCH v5] " Michael Jones
8 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-08-17 8:55 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
I haven't had any real feedback on this submission yet, and I don't
know if there is still any hope of getting it in to v2011.09. The
previous version didn't build on top of the latest u-boot-arm branch
anymore, so I'm rebasing it in the hopes that this will ease the
review process.
v3 introduced a change which causes the board not to run on the
current arm master branch until this patch is applied:
http://patchwork.ozlabs.org/patch/107021/
But this is a runtime problem.
Changes for v4:
- rebased on top of u-boot-arm master (f0628a67)
Changes for v3:
- Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
Changes for v2:
- None. Resubmitting to include custodian in cc:
MAINTAINERS | 4 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
11 files changed, 1589 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f895e9a..2ae2f91 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -690,6 +690,10 @@ Gary Jennejohn <garyj@denx.de>
smdk2400 ARM920T
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..e403e19
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/omap_gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (omap_request_gpio(GPIO_DCLK) ||
+ omap_request_gpio(GPIO_nSTATUS) ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_request_gpio(GPIO_CONF_DONE) ||
+#endif
+ omap_request_gpio(GPIO_nCONFIG) ||
+ omap_request_gpio(GPIO_DATA0) ||
+ omap_request_gpio(GPIO_DATA1) ||
+ omap_request_gpio(GPIO_DATA2) ||
+ omap_request_gpio(GPIO_DATA3) ||
+ omap_request_gpio(GPIO_DATA4) ||
+ omap_request_gpio(GPIO_DATA5) ||
+ omap_request_gpio(GPIO_DATA6) ||
+ omap_request_gpio(GPIO_DATA7)) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ omap_set_gpio_direction(GPIO_DCLK, 0);
+ omap_set_gpio_direction(GPIO_nCONFIG, 0);
+ omap_set_gpio_direction(GPIO_DATA0, 0);
+ omap_set_gpio_direction(GPIO_DATA1, 0);
+ omap_set_gpio_direction(GPIO_DATA2, 0);
+ omap_set_gpio_direction(GPIO_DATA3, 0);
+ omap_set_gpio_direction(GPIO_DATA4, 0);
+ omap_set_gpio_direction(GPIO_DATA5, 0);
+ omap_set_gpio_direction(GPIO_DATA6, 0);
+ omap_set_gpio_direction(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ */
+
+ /* set up inputs */
+ omap_set_gpio_direction(GPIO_nSTATUS, 1);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ omap_set_gpio_direction(GPIO_CONF_DONE, 1);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ omap_set_gpio_dataout(GPIO_nCONFIG, !assert);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (omap_get_gpio_datain(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ omap_free_gpio(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = omap_get_gpio_datain(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ /* TODO it takes ~7s to call this routine 368,011 times
+ * even when the udelay() calls are removed completely.
+ * Where does all this time come from?
+ */
+ omap_set_gpio_dataout(GPIO_DATA0, byte & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA1, (byte >> 1) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA2, (byte >> 2) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA3, (byte >> 3) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA4, (byte >> 4) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA5, (byte >> 5) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA6, (byte >> 6) & 0x01);
+ omap_set_gpio_dataout(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ omap_set_gpio_dataout(GPIO_DCLK, 1);
+ udelay(1);
+ omap_set_gpio_dataout(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..3d427bf
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..f96a657
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/omap_gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..4c0fc49
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+/* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+/*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..029cf20
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index c31114d..ac29988 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -190,6 +190,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 460950d..b0d875c 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..bda83c6
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,313 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.6
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-08-02 6:37 ` Heiko Schocher
@ 2011-09-04 17:59 ` Paulraj, Sandeep
2011-09-05 5:34 ` Heiko Schocher
0 siblings, 1 reply; 48+ messages in thread
From: Paulraj, Sandeep @ 2011-09-04 17:59 UTC (permalink / raw)
To: u-boot
>
> This patch is now checkpatch and makeall clean, can you Ack/Nack
> this patch, so I can pick it up, if you give your ack?
> (Or do you want to apply it, so I can Ack it)
>
> There is also a cosmetic (checkpatch cleanup) patch for this driver,
> see:
>
> http://patchwork.ozlabs.org/patch/107052/
>
> bye,
> Heiko
OK I'll apply it
Regards,
Sandeep
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write
2011-09-04 17:59 ` Paulraj, Sandeep
@ 2011-09-05 5:34 ` Heiko Schocher
0 siblings, 0 replies; 48+ messages in thread
From: Heiko Schocher @ 2011-09-05 5:34 UTC (permalink / raw)
To: u-boot
Hello Sandeep,
Paulraj, Sandeep wrote:
>> This patch is now checkpatch and makeall clean, can you Ack/Nack
>> this patch, so I can pick it up, if you give your ack?
>> (Or do you want to apply it, so I can Ack it)
>>
>> There is also a cosmetic (checkpatch cleanup) patch for this driver,
>> see:
>>
>> http://patchwork.ozlabs.org/patch/107052/
>>
>> bye,
>> Heiko
>
> OK I'll apply it
Ok, so I give you my:
Acked-by: Heiko Schocher<hs@denx.de>
for the
http://patchwork.ozlabs.org/patch/107711/
http://patchwork.ozlabs.org/patch/107052/
patches, Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v5] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
` (7 preceding siblings ...)
2011-08-17 8:55 ` [U-Boot] [PATCH v4] " Michael Jones
@ 2011-10-05 15:08 ` Michael Jones
2011-10-10 15:08 ` [U-Boot] [PATCH v6] " Michael Jones
2011-10-18 17:31 ` [U-Boot] [PATCH v5] " Tom Rini
8 siblings, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-10-05 15:08 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
This has been rebased on top of u-boot master (4f7549d2dc0)
Changes for v2:
- None. Resubmitting to include custodian in cc:
Changes for v3:
- Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
Changes for v4:
- rebased on top of u-boot-arm master (f0628a67)
Changes for v5:
- Use generic gpio API
- change formatting to get rid of checkpatch warnings
about long lines, especially in mvblx.h
MAINTAINERS | 4 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 219 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
11 files changed, 1586 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ab38fa..abae9dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -662,6 +662,10 @@ Grazvydas Ignotas <notasas@gmail.com>
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..dacc138
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (gpio_request(GPIO_DCLK, "dclk") ||
+ gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+ gpio_request(GPIO_nCONFIG, "nConfig") ||
+ gpio_request(GPIO_DATA0, "data0") ||
+ gpio_request(GPIO_DATA1, "data1") ||
+ gpio_request(GPIO_DATA2, "data2") ||
+ gpio_request(GPIO_DATA3, "data3") ||
+ gpio_request(GPIO_DATA4, "data4") ||
+ gpio_request(GPIO_DATA5, "data5") ||
+ gpio_request(GPIO_DATA6, "data6") ||
+ gpio_request(GPIO_DATA7, "data7")) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ gpio_direction_output(GPIO_DCLK, 0);
+ gpio_direction_output(GPIO_nCONFIG, 0);
+ gpio_direction_output(GPIO_DATA0, 0);
+ gpio_direction_output(GPIO_DATA1, 0);
+ gpio_direction_output(GPIO_DATA2, 0);
+ gpio_direction_output(GPIO_DATA3, 0);
+ gpio_direction_output(GPIO_DATA4, 0);
+ gpio_direction_output(GPIO_DATA5, 0);
+ gpio_direction_output(GPIO_DATA6, 0);
+ gpio_direction_output(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ * Q: presumably gpio_free() has the same effect?
+ */
+
+ /* set up inputs */
+ gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ gpio_set_value(GPIO_nCONFIG, !assert);
+ udelay(1);
+ gpio_set_value(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio_get_value(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ gpio_free(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = gpio_get_value(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ gpio_set_value(GPIO_DATA0, byte & 0x01);
+ gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+ gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+ gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+ gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+ gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+ gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+ gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ gpio_set_value(GPIO_DCLK, 1);
+ udelay(1);
+ gpio_set_value(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..3d427bf
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..74b5b19
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..4609cff
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..945a36d
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 3254702..17ec059 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -175,6 +175,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1768cdd..fe98a59 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx_config
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..a0252a2
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,313 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.4.1
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-08-17 8:55 ` [U-Boot] [PATCH v4] " Michael Jones
@ 2011-10-06 21:51 ` Wolfgang Denk
2011-10-07 9:06 ` Michael Jones
0 siblings, 1 reply; 48+ messages in thread
From: Wolfgang Denk @ 2011-10-06 21:51 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <1313571318-17795-1-git-send-email-michael.jones@matrix-vision.de> you wrote:
> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
> intelligent camera.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
>
> I haven't had any real feedback on this submission yet, and I don't
> know if there is still any hope of getting it in to v2011.09. The
> previous version didn't build on top of the latest u-boot-arm branch
> anymore, so I'm rebasing it in the hopes that this will ease the
> review process.
>
> v3 introduced a change which causes the board not to run on the
> current arm master branch until this patch is applied:
> http://patchwork.ozlabs.org/patch/107021/
> But this is a runtime problem.
>
> Changes for v4:
> - rebased on top of u-boot-arm master (f0628a67)
>
> Changes for v3:
> - Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
>
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> MAINTAINERS | 4 +
> board/matrix_vision/mvblx/Makefile | 53 +++++
> board/matrix_vision/mvblx/config.mk | 33 +++
> board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
> board/matrix_vision/mvblx/fpga.h | 32 +++
> board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
> board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
> board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.omap3 | 5 +
> include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
> 11 files changed, 1589 insertions(+), 0 deletions(-)
> create mode 100644 board/matrix_vision/mvblx/Makefile
> create mode 100644 board/matrix_vision/mvblx/config.mk
> create mode 100644 board/matrix_vision/mvblx/fpga.c
> create mode 100644 board/matrix_vision/mvblx/fpga.h
> create mode 100644 board/matrix_vision/mvblx/mvblx.c
> create mode 100644 board/matrix_vision/mvblx/mvblx.h
> create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
> create mode 100644 include/configs/omap3_mvblx.h
Checkpatch says:
total: 0 errors, 49 warnings, 1607 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If you believe that feeling bad or worrying long enough will change a
past or future event, then you are residing on another planet with a
different reality system.
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v3] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-08-04 13:46 ` [U-Boot] [PATCH v3] " Michael Jones
@ 2011-10-06 22:06 ` Wolfgang Denk
0 siblings, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-10-06 22:06 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <1312465577-20517-1-git-send-email-michael.jones@matrix-vision.de> you wrote:
> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
> intelligent camera.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> Changes for v3:
> - Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
>
> Changes for v2:
> - None. Resubmitting to include custodian in cc:
>
> MAINTAINERS | 4 +
> MAKEALL | 1 +
> board/matrix_vision/mvblx/Makefile | 53 +++++
> board/matrix_vision/mvblx/config.mk | 33 +++
> board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
> board/matrix_vision/mvblx/fpga.h | 32 +++
> board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
> board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
> board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
> boards.cfg | 1 +
> doc/README.omap3 | 5 +
> include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
> 12 files changed, 1590 insertions(+), 0 deletions(-)
> create mode 100644 board/matrix_vision/mvblx/Makefile
> create mode 100644 board/matrix_vision/mvblx/config.mk
> create mode 100644 board/matrix_vision/mvblx/fpga.c
> create mode 100644 board/matrix_vision/mvblx/fpga.h
> create mode 100644 board/matrix_vision/mvblx/mvblx.c
> create mode 100644 board/matrix_vision/mvblx/mvblx.h
> create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
> create mode 100644 include/configs/omap3_mvblx.h
Checkpatch says:
total: 0 errors, 49 warnings, 1614 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
On the subject of C program indentation: "In My Egotistical Opinion,
most people's C programs should be indented six feet downward and
covered with dirt." - Blair P. Houghton
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-10-06 21:51 ` Wolfgang Denk
@ 2011-10-07 9:06 ` Michael Jones
2011-10-09 19:59 ` Wolfgang Denk
0 siblings, 1 reply; 48+ messages in thread
From: Michael Jones @ 2011-10-07 9:06 UTC (permalink / raw)
To: u-boot
Hi Wolfgang,
On 10/06/2011 11:51 PM, Wolfgang Denk wrote:
>
> Dear Michael Jones,
>
> In message<1313571318-17795-1-git-send-email-michael.jones@matrix-vision.de> you wrote:
>> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
>> intelligent camera.
>>
>> Signed-off-by: Michael Jones<michael.jones@matrix-vision.de>
>> ---
>>
>> I haven't had any real feedback on this submission yet, and I don't
>> know if there is still any hope of getting it in to v2011.09. The
>> previous version didn't build on top of the latest u-boot-arm branch
>> anymore, so I'm rebasing it in the hopes that this will ease the
>> review process.
>>
>> v3 introduced a change which causes the board not to run on the
>> current arm master branch until this patch is applied:
>> http://patchwork.ozlabs.org/patch/107021/
>> But this is a runtime problem.
>>
>> Changes for v4:
>> - rebased on top of u-boot-arm master (f0628a67)
>>
>> Changes for v3:
>> - Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
>>
>> Changes for v2:
>> - None. Resubmitting to include custodian in cc:
>>
>> MAINTAINERS | 4 +
>> board/matrix_vision/mvblx/Makefile | 53 +++++
>> board/matrix_vision/mvblx/config.mk | 33 +++
>> board/matrix_vision/mvblx/fpga.c | 222 ++++++++++++++++++
>> board/matrix_vision/mvblx/fpga.h | 32 +++
>> board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
>> board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
>> board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
>> boards.cfg | 1 +
>> doc/README.omap3 | 5 +
>> include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
>> 11 files changed, 1589 insertions(+), 0 deletions(-)
>> create mode 100644 board/matrix_vision/mvblx/Makefile
>> create mode 100644 board/matrix_vision/mvblx/config.mk
>> create mode 100644 board/matrix_vision/mvblx/fpga.c
>> create mode 100644 board/matrix_vision/mvblx/fpga.h
>> create mode 100644 board/matrix_vision/mvblx/mvblx.c
>> create mode 100644 board/matrix_vision/mvblx/mvblx.h
>> create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
>> create mode 100644 include/configs/omap3_mvblx.h
>
> Checkpatch says:
>
> total: 0 errors, 49 warnings, 1607 lines checked
>
> Please clean up and resubmit. Thanks.
>
> Best regards,
>
> Wolfgang Denk
>
I've already submitted v5 [1], which was mainly to get rid of exactly
those warnings. There remain 4 warnings, but they look Linux-specific.
But while we're on the topic- Most of those old warnings were because my
board/matrix_vision/mvblx/mvblx.h was based on board/ti/beagle/beagle.h,
which would've itself had lots of checkpatch warnings from long lines.
Sandeep advised me that this was a poor argument for submitting a patch
with warnings, so I submitted v5. Now I've researched this again and
found the patch which introduced the warnings for beagle.h and the
discussion [2] around it. If it was decided back then to indent the
lines with tabs although it caused checkpatch warnings, isn't it
reasonable for mvblx.h to be formatted in the same way? I don't care
how it's formatted, but I find the inconsistency ugly.
If you agree that the checkpatch warnings from mvblx.h are preferable to
being inconsistent with the formatting of beagle.h, I will submit v6
with mvblx.h changed back to be formatted like the current beagle.h.
-Michael
[1]http://patchwork.ozlabs.org/patch/117879/
[2]http://http://lists.denx.de/pipermail/u-boot/2009-September/061619.html
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v4] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-10-07 9:06 ` Michael Jones
@ 2011-10-09 19:59 ` Wolfgang Denk
0 siblings, 0 replies; 48+ messages in thread
From: Wolfgang Denk @ 2011-10-09 19:59 UTC (permalink / raw)
To: u-boot
Dear Michael Jones,
In message <4E8EC11B.8040207@matrix-vision.de> you wrote:
>
> But while we're on the topic- Most of those old warnings were because my
> board/matrix_vision/mvblx/mvblx.h was based on board/ti/beagle/beagle.h,
> which would've itself had lots of checkpatch warnings from long lines.
> Sandeep advised me that this was a poor argument for submitting a patch
> with warnings, so I submitted v5. Now I've researched this again and
> found the patch which introduced the warnings for beagle.h and the
> discussion [2] around it. If it was decided back then to indent the
> lines with tabs although it caused checkpatch warnings, isn't it
> reasonable for mvblx.h to be formatted in the same way? I don't care
> how it's formatted, but I find the inconsistency ugly.
There are a few cases where longer lines actually provide better
readbility than wrapping the code - these are things like tables of
MUX initializations, and the like.
But "normal" code or header files has a strict 80 char line length
limit.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Star Trek Lives!
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v6] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-10-05 15:08 ` [U-Boot] [PATCH v5] " Michael Jones
@ 2011-10-10 15:08 ` Michael Jones
2011-10-18 17:31 ` [U-Boot] [PATCH v5] " Tom Rini
1 sibling, 0 replies; 48+ messages in thread
From: Michael Jones @ 2011-10-10 15:08 UTC (permalink / raw)
To: u-boot
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
Changes for v2:
- None. Resubmitting to include custodian in cc:
Changes for v3:
- Use CONFIG_MACH_TYPE to set gd->bd->bi_arch_number
Changes for v4:
- rebased on top of u-boot-arm master (f0628a67)
Changes for v5:
- Use generic gpio API
- change formatting to get rid of checkpatch warnings
about long lines, especially in mvblx.h
Changes for v6:
- re-introduce tab indentation in mux init (mvblx.h) to be
consistent with result of discussion for BeagleBoard's mux init,
although this creates checkpatch warnings.
checkpatch gives 49 warnings:
- 45 of them are lines over 80 characters in the mux init header.
This file used board/ti/beagle/beagle.h as a model, which had
the same warnings introduced in commit fc9165fdb3b ("Clean up
whitespace in mux configs") after a discussion on the ML [1]
- The other 4 are the following, all of which look Linux-specific
and can be ignored:
WARNING: Use #include <linux/gpio.h> instead of <asm/gpio.h>
WARNING: Use #include <linux/io.h> instead of <asm/io.h>
WARNING: consider using kstrto* in preference to simple_strtoul
WARNING: consider using kstrto* in preference to simple_strtoul
[1]http://lists.denx.de/pipermail/u-boot/2009-September/061619.html
MAINTAINERS | 4 +
board/matrix_vision/mvblx/Makefile | 53 +++++
board/matrix_vision/mvblx/config.mk | 33 +++
board/matrix_vision/mvblx/fpga.c | 219 ++++++++++++++++++
board/matrix_vision/mvblx/fpga.h | 32 +++
board/matrix_vision/mvblx/mvblx.c | 169 ++++++++++++++
board/matrix_vision/mvblx/mvblx.h | 362 +++++++++++++++++++++++++++++
board/matrix_vision/mvblx/sys_eeprom.c | 395 ++++++++++++++++++++++++++++++++
boards.cfg | 1 +
doc/README.omap3 | 5 +
include/configs/omap3_mvblx.h | 313 +++++++++++++++++++++++++
11 files changed, 1586 insertions(+), 0 deletions(-)
create mode 100644 board/matrix_vision/mvblx/Makefile
create mode 100644 board/matrix_vision/mvblx/config.mk
create mode 100644 board/matrix_vision/mvblx/fpga.c
create mode 100644 board/matrix_vision/mvblx/fpga.h
create mode 100644 board/matrix_vision/mvblx/mvblx.c
create mode 100644 board/matrix_vision/mvblx/mvblx.h
create mode 100644 board/matrix_vision/mvblx/sys_eeprom.c
create mode 100644 include/configs/omap3_mvblx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ab38fa..abae9dc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -662,6 +662,10 @@ Grazvydas Ignotas <notasas@gmail.com>
omap3_pandora ARM ARMV7 (OMAP3xx SoC)
+Michael Jones <michael.jones@matrix-vision.de>
+
+ omap3_mvblx ARM ARMV7 (OMAP3xx SoC)
+
Matthias Kaehlcke <matthias@kaehlcke.net>
edb9301 ARM920T (EP9301)
edb9302 ARM920T (EP9302)
diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile
new file mode 100644
index 0000000..01cb517
--- /dev/null
+++ b/board/matrix_vision/mvblx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS-y += mvblx.o fpga.o
+COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o
+COBJS := $(COBJS-y)
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+CFLAGS += -Werror
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/matrix_vision/mvblx/config.mk b/board/matrix_vision/mvblx/config.mk
new file mode 100644
index 0000000..cf055db
--- /dev/null
+++ b/board/matrix_vision/mvblx/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+CONFIG_SYS_TEXT_BASE = 0x80008000
diff --git a/board/matrix_vision/mvblx/fpga.c b/board/matrix_vision/mvblx/fpga.c
new file mode 100644
index 0000000..dacc138
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.c
@@ -0,0 +1,219 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater at mvis.com.
+ *
+ * (C) Copyright 2011
+ * Andre Schwarz, Matrix Vision GmbH, andre.schwarz at matrix-vision.de
+ * Michael Jones, Matrix Vision GmbH, michael.jones at matrix-vision.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ACEX1K.h>
+#include <command.h>
+#include <asm/gpio.h>
+#include "fpga.h"
+
+#ifdef FPGA_DEBUG
+#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
+#else
+#define fpga_debug(fmt, args...)
+#endif
+
+Altera_CYC2_Passive_Serial_fns altera_fns = {
+ fpga_null_fn, /* Altera_pre_fn */
+ fpga_config_fn,
+ fpga_status_fn,
+ fpga_done_fn,
+ fpga_wr_fn,
+ fpga_null_fn,
+ fpga_null_fn,
+};
+
+Altera_desc cyclone2 = {
+ Altera_CYC2,
+ fast_passive_parallel,
+ Altera_EP3C5_SIZE,
+ (void *) &altera_fns,
+ NULL,
+ 0
+};
+
+#define GPIO_RESET 43
+#define GPIO_DCLK 65
+#define GPIO_nSTATUS 157
+#define GPIO_CONF_DONE 158
+#define GPIO_nCONFIG 159
+#define GPIO_DATA0 54
+#define GPIO_DATA1 55
+#define GPIO_DATA2 56
+#define GPIO_DATA3 57
+#define GPIO_DATA4 58
+#define GPIO_DATA5 60
+#define GPIO_DATA6 61
+#define GPIO_DATA7 62
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* return FPGA_SUCCESS on success, else FPGA_FAIL
+ */
+int mvblx_init_fpga(void)
+{
+ fpga_debug("Initializing FPGA interface\n");
+ fpga_init();
+ fpga_add(fpga_altera, &cyclone2);
+
+ if (gpio_request(GPIO_DCLK, "dclk") ||
+ gpio_request(GPIO_nSTATUS, "nStatus") ||
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_request(GPIO_CONF_DONE, "conf_done") ||
+#endif
+ gpio_request(GPIO_nCONFIG, "nConfig") ||
+ gpio_request(GPIO_DATA0, "data0") ||
+ gpio_request(GPIO_DATA1, "data1") ||
+ gpio_request(GPIO_DATA2, "data2") ||
+ gpio_request(GPIO_DATA3, "data3") ||
+ gpio_request(GPIO_DATA4, "data4") ||
+ gpio_request(GPIO_DATA5, "data5") ||
+ gpio_request(GPIO_DATA6, "data6") ||
+ gpio_request(GPIO_DATA7, "data7")) {
+ printf("%s: error requesting GPIOs.", __func__);
+ return FPGA_FAIL;
+ }
+
+ /* set up outputs */
+ gpio_direction_output(GPIO_DCLK, 0);
+ gpio_direction_output(GPIO_nCONFIG, 0);
+ gpio_direction_output(GPIO_DATA0, 0);
+ gpio_direction_output(GPIO_DATA1, 0);
+ gpio_direction_output(GPIO_DATA2, 0);
+ gpio_direction_output(GPIO_DATA3, 0);
+ gpio_direction_output(GPIO_DATA4, 0);
+ gpio_direction_output(GPIO_DATA5, 0);
+ gpio_direction_output(GPIO_DATA6, 0);
+ gpio_direction_output(GPIO_DATA7, 0);
+
+ /* NB omap_free_gpio() resets to an input, so we can't
+ * free ie. nCONFIG, or else the FPGA would reset
+ * Q: presumably gpio_free() has the same effect?
+ */
+
+ /* set up inputs */
+ gpio_direction_input(GPIO_nSTATUS);
+#ifndef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ gpio_direction_input(GPIO_CONF_DONE);
+#endif
+
+ fpga_config_fn(0, 1, 0);
+ udelay(60);
+
+ return FPGA_SUCCESS;
+}
+
+int fpga_null_fn(int cookie)
+{
+ return 0;
+}
+
+int fpga_config_fn(int assert, int flush, int cookie)
+{
+ fpga_debug("SET config : %s=%d\n", assert ? "low" : "high", assert);
+ if (flush) {
+ gpio_set_value(GPIO_nCONFIG, !assert);
+ udelay(1);
+ gpio_set_value(GPIO_nCONFIG, assert);
+ }
+
+ return assert;
+}
+
+int fpga_done_fn(int cookie)
+{
+ int result = 0;
+
+ /* since revA of BLX, we will not get this signal. */
+ udelay(10);
+#ifdef CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+ fpga_debug("not waiting for CONF_DONE.");
+ result = 1;
+#else
+ fpga_debug("CONF_DONE check ... ");
+ if (gpio_get_value(GPIO_CONF_DONE)) {
+ fpga_debug("high\n");
+ result = 1;
+ } else
+ fpga_debug("low\n");
+ gpio_free(GPIO_CONF_DONE);
+#endif
+
+ return result;
+}
+
+int fpga_status_fn(int cookie)
+{
+ int result = 0;
+ fpga_debug("STATUS check ... ");
+
+ result = gpio_get_value(GPIO_nSTATUS);
+
+ if (result < 0)
+ fpga_debug("error\n");
+ else if (result > 0)
+ fpga_debug("high\n");
+ else
+ fpga_debug("low\n");
+
+ return result;
+}
+
+static inline int _write_fpga(u8 byte)
+{
+ gpio_set_value(GPIO_DATA0, byte & 0x01);
+ gpio_set_value(GPIO_DATA1, (byte >> 1) & 0x01);
+ gpio_set_value(GPIO_DATA2, (byte >> 2) & 0x01);
+ gpio_set_value(GPIO_DATA3, (byte >> 3) & 0x01);
+ gpio_set_value(GPIO_DATA4, (byte >> 4) & 0x01);
+ gpio_set_value(GPIO_DATA5, (byte >> 5) & 0x01);
+ gpio_set_value(GPIO_DATA6, (byte >> 6) & 0x01);
+ gpio_set_value(GPIO_DATA7, (byte >> 7) & 0x01);
+
+ /* clock */
+ gpio_set_value(GPIO_DCLK, 1);
+ udelay(1);
+ gpio_set_value(GPIO_DCLK, 0);
+ udelay(1);
+
+ return 0;
+}
+
+int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
+{
+ unsigned char *data = (unsigned char *) buf;
+ int i;
+
+ fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
+ for (i = 0; i < len; i++)
+ _write_fpga(data[i]);
+ fpga_debug("-%s\n", __func__);
+
+ return FPGA_SUCCESS;
+}
diff --git a/board/matrix_vision/mvblx/fpga.h b/board/matrix_vision/mvblx/fpga.h
new file mode 100644
index 0000000..3d427bf
--- /dev/null
+++ b/board/matrix_vision/mvblx/fpga.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland at enterasys.com.
+ * Keith Outwater, keith_outwater@mvis.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+extern int mvblx_init_fpga(void);
+
+extern int fpga_status_fn(int cookie);
+extern int fpga_config_fn(int assert, int flush, int cookie);
+extern int fpga_done_fn(int cookie);
+extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
+extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c
new file mode 100644
index 0000000..74b5b19
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.c
@@ -0,0 +1,169 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from Beagle and Overo
+ *
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Sunil Kumar <sunilsaini05@gmail.com>
+ * Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+#include <asm/mach-types.h>
+#include "mvblx.h"
+#include "fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void);
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+ return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+ printf("mvBlueLYNX-X\n");
+ if (get_cpu_family() == CPU_OMAP36XX)
+ setenv("mpurate", "1000");
+ else
+ setenv("mpurate", "600");
+
+ twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+ setup_net_chip();
+#endif /* CONFIG_CMD_NET */
+
+ mvblx_init_fpga();
+
+ mac_read_from_eeprom();
+
+ dieid_num_r();
+
+ return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_MVBLX();
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+ omap_mmc_init(0);
+ omap_mmc_init(1);
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_CMD_NET)
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ * Ethernet hardware.
+ */
+static void setup_net_chip(void)
+{
+ struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE;
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ /* Configure GPMC registers */
+ writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[0].config1);
+ writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[0].config2);
+ writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[0].config3);
+ writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[0].config4);
+ writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[0].config5);
+ writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[0].config6);
+ writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[0].config7);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+
+ /* Make GPIO 139 as output pin */
+ writel(readl(&gpio5_base->oe) & ~(GPIO11), &gpio5_base->oe);
+
+ /* Now send a pulse on the GPIO pin */
+ writel(GPIO11, &gpio5_base->setdataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->cleardataout);
+ udelay(1);
+ writel(GPIO11, &gpio5_base->setdataout);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
+
+int overwrite_console(void)
+{
+ /* return TRUE if console should be overwritten */
+ return 0;
+}
+
+#endif /* CONFIG_CMD_NET */
diff --git a/board/matrix_vision/mvblx/mvblx.h b/board/matrix_vision/mvblx/mvblx.h
new file mode 100644
index 0000000..cda5b0b
--- /dev/null
+++ b/board/matrix_vision/mvblx/mvblx.h
@@ -0,0 +1,362 @@
+/*
+ * (C) Copyright 2008
+ * Dirk Behme <dirk.behme@gmail.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _MVBLX_H_
+#define _MVBLX_H_
+
+#include <asm/arch/sys_proto.h>
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "OMAP3 mvBlueLYNX-X camera",
+ "no NAND",
+};
+
+/*
+ * IEN - Input Enable
+ * IDIS - Input Disable
+ * PTD - Pull type Down
+ * PTU - Pull type Up
+ * DIS - Pull type selection is inactive
+ * EN - Pull type selection is active
+ * M0 - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MVBLX() \
+ /*SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
+ /*GPMC*/\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M4)) /*GPIO_41*/\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO_42*/\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO_43*/\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
+ MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO54*/\
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)) /*GPIO55*/\
+ MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) /*GPIO56*/\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTU | EN | M4)) /*GPIO57*/\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)) /*GPIO58*/\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTU | EN | M0)) /*GPMC_CLK*/\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IEN | PTU | EN | M4)) /*GPIO60*/\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTU | EN | M4)) /*GPIO61*/\
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTU | EN | M4)) /*GPIO62*/\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
+ MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)) /*GPIO65*/\
+ /*DSS*/\
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M4)) /*not_used*/\
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)) /*DSS_DATA0*/\
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)) /*DSS_DATA1*/\
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)) /*DSS_DATA2*/\
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)) /*DSS_DATA3*/\
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)) /*DSS_DATA4*/\
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)) /*DSS_DATA5*/\
+ /*CAMERA*/\
+ MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) /*CAM_HS */\
+ MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) /*CAM_VS */\
+ MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
+ MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) /*CAM_PCLK*/\
+ MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
+ MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
+ MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
+ MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
+ MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
+ MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
+ MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
+ MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
+ MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
+ MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
+ MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
+ MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
+ MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
+ MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
+ MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
+ MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
+ MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\
+ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\
+ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) /*CSI2_DX1*/\
+ MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) /*CSI2_DY1*/\
+ /*Audio Interface */\
+ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
+ MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
+ MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
+ MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
+ /*Expansion card 1*/\
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
+ MUX_VAL(CP(MMC1_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT5), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_?*/\
+ MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | DIS | M7)) /*GPIO_129 disabled*/\
+ /*Expansion card 2 */\
+ MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M0)) /*MMC2_CLK*/\
+ MUX_VAL(CP(MMC2_CMD), (IEN | PTU | DIS | M0)) /*MMC2_CMD*/\
+ MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | DIS | M0)) /*MMC2_DAT0*/\
+ MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | DIS | M0)) /*MMC2_DAT1*/\
+ MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | DIS | M0)) /*MMC2_DAT2*/\
+ MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | DIS | M0)) /*MMC2_DAT3*/\
+ MUX_VAL(CP(MMC2_DAT4), (IDIS | PTU | DIS | M4)) /*GPIO_136*/\
+ MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
+ MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | DIS | M4)) /*GPIO_138*/\
+ MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
+ /*Bluetooth*/\
+ MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M1)) /*UART2_CTS*/\
+ MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
+ MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
+ MUX_VAL(CP(MCBSP3_FSX), (IDIS | PTD | DIS | M1)) /*UART2_RX*/\
+ /*Modem Interface */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
+ MUX_VAL(CP(UART1_CTS), (IEN | PTU | EN | M4)) /*GPIO_150*/ \
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
+ MUX_VAL(CP(MCBSP1_CLKR), (IDIS | PTD | DIS | M4)) /*GPIO_156*/\
+ MUX_VAL(CP(MCBSP1_FSR), (IEN | PTU | EN | M4)) /*GPIO_157*/\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTU | DIS | M4)) /*GPIO_158 1-wire */\
+ MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
+ MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161*/\
+ MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162*/\
+ /*Serial Interface*/\
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
+ MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
+ MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
+ MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
+ MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
+ MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
+ MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
+ MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
+ MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
+ MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
+ MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
+ MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
+ MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
+ MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
+ MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
+ MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
+ MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
+ MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*GPIO_170*/\
+ MUX_VAL(CP(MCSPI1_CLK), (IDIS | PTU | DIS | M4)) /*GPIO_171*/\
+ MUX_VAL(CP(MCSPI1_SIMO), (IDIS | PTU | DIS | M4)) /*GPIO_172*/\
+ MUX_VAL(CP(MCSPI1_SOMI), (IDIS | PTU | DIS | M4)) /*GPIO_173*/\
+ MUX_VAL(CP(MCSPI1_CS0), (IDIS | PTD | DIS | M4)) /*GPIO_174*/\
+ MUX_VAL(CP(MCSPI1_CS3), (IDIS | PTU | DIS | M4)) /*GPIO_177*/\
+ /* USB EHCI (port 2) not used */\
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) /*McSPI2_CLK*/\
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) /*McSPI2_SIMO*/\
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) /*McSPI2_SOMI*/\
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)) /*McSPI2_CS0*/\
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)) /*McSPI2_CS1*/\
+ /*Control and debug */\
+ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
+ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
+ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
+ MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)) /*DSS_DATA18*/\
+ MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)) /*DSS_DATA19*/\
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\
+ MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)) /*DSS_DATA20*/\
+ MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)) /*DSS_DATA21*/\
+ MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)) /*DSS_DATA22*/\
+ MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)) /*DSS_DATA23*/ \
+ MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
+ MUX_VAL(CP(SYS_CLKOUT1), (IDIS | PTD | DIS | M4)) /*GPIO_10*/\
+ MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTD | DIS | M0)) /*SYS_CLKOUT2*/\
+ /* USB EHCI (port 1) */\
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\
+ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTU | EN | M4)) /*GPIO_24*/\
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M4)) /*GPIO_25*/\
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTU | DIS | M4)) /*GPIO_26*/\
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTU | DIS | M4)) /*GPIO_27*/\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | DIS | M4)) /*GPIO_28*/\
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTU | DIS | M4)) /*GPIO_29*/\
+ /*Die to Die */\
+ MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
+ MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
+ MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
+ MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
+ MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
+ MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
+ MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
+ MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
+ MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
+ MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
+ MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
+ MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
+ MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
+ MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
+ MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
+ MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
+ MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
+ MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
+ MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
+ MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
+ MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
+ MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
+ MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
+ MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
+ MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
+ MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
+ MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
+ MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
+ MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
+ MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
+ MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
+ MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
+ MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
+ MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
+ MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
+ MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
+ MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
+ MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
+ MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
+ MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
+ MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
+ MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
+ MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
+ MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
+ MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
+ MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
+ MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
+ MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
+ MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
+ MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
+ MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
+ MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
+ MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
+ MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
+ MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
+ MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
+ MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
+ MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
+ MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
+
+#endif
diff --git a/board/matrix_vision/mvblx/sys_eeprom.c b/board/matrix_vision/mvblx/sys_eeprom.c
new file mode 100644
index 0000000..945a36d
--- /dev/null
+++ b/board/matrix_vision/mvblx/sys_eeprom.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ * York Sun (yorksun at freescale.com)
+ * Haiying Wang (haiying.wang at freescale.com)
+ * Timur Tabi (timur at freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+
+/* #define DEBUG */
+
+/*
+ * static eeprom: EEPROM layout
+ */
+static struct __attribute__ ((__packed__)) eeprom {
+ u8 id[16]; /* 0x01 - 0x0F Type e.g. 100wG-5111 */
+ u8 sn[10]; /* 0x10 - 0x19 Serial Number */
+ u8 date[6]; /* 0x1A - 0x1F Build Date */
+ u8 mac[6]; /* 0x20 - 0x25 MAC address */
+ u8 reserved[10];/* 0x26 - 0x2f reserved */
+ u32 crc; /* x+1 CRC32 checksum */
+} e;
+
+/* Set to 1 if we've read EEPROM into memory */
+static int has_been_read;
+
+/**
+ * show_eeprom - display the contents of the EEPROM
+ */
+static void show_eeprom(void)
+{
+ unsigned int crc;
+ char safe_string[16];
+
+#ifdef DEBUG
+ int i;
+#endif
+ u8 *p;
+
+ /* ID */
+ strncpy(safe_string, (char *)e.id, sizeof(e.id));
+ safe_string[sizeof(e.id)-1] = 0;
+ printf("ID: mvBlueLYNX-X%s\n", safe_string);
+
+ /* Serial number */
+ strncpy(safe_string, (char *)e.sn, sizeof(e.sn));
+ safe_string[sizeof(e.sn)-1] = 0;
+ printf("SN: %s\n", safe_string);
+
+ /* Build date, BCD date values, as YYMMDDhhmmss */
+ printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
+ e.date[0], e.date[1], e.date[2],
+ e.date[3] & 0x7F, e.date[4], e.date[5],
+ e.date[3] & 0x80 ? "PM" : "");
+
+ /* Show MAC address */
+ p = e.mac;
+ printf("Eth: %02x:%02x:%02x:%02x:%02x:%02x\n",
+ p[0], p[1], p[2], p[3], p[4], p[5]);
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+
+ if (crc == be32_to_cpu(e.crc))
+ printf("CRC: %08x\n", be32_to_cpu(e.crc));
+ else
+ printf("CRC: %08x (should be %08x)\n", be32_to_cpu(e.crc), crc);
+
+#ifdef DEBUG
+ printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
+ for (i = 0; i < sizeof(e); i++) {
+ if ((i % 16) == 0)
+ printf("%02X: ", i);
+ printf("%02X ", ((u8 *)&e)[i]);
+ if (((i % 16) == 15) || (i == sizeof(e) - 1))
+ printf("\n");
+ }
+#endif
+}
+
+/**
+ * read_eeprom - read the EEPROM into memory
+ */
+static int read_eeprom(void)
+{
+ int ret;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ if (has_been_read)
+ return 0;
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+#ifdef DEBUG
+ show_eeprom();
+#endif
+
+ has_been_read = (ret == 0) ? 1 : 0;
+
+ return ret;
+}
+
+/**
+ * update_crc - update the CRC
+ *
+ * This function should be called after each update to the EEPROM structure,
+ * to make sure the CRC is always correct.
+ */
+static void update_crc(void)
+{
+ u32 crc;
+
+ crc = crc32(0, (void *)&e, sizeof(e) - 4);
+ e.crc = cpu_to_be32(crc);
+}
+
+/**
+ * prog_eeprom - write the EEPROM from memory
+ */
+static int prog_eeprom(void)
+{
+ int ret = 0;
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ unsigned int bus;
+#endif
+
+ update_crc();
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ bus = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
+#endif
+
+ ret = eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e, sizeof(e));
+
+ if (!ret) {
+ /* Verify the write by reading back the EEPROM and comparing */
+ struct eeprom e2;
+#ifdef DEBUG
+ printf("%s verifying...\n", __func__);
+#endif
+ ret = eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
+ (uchar *)&e2, sizeof(e2));
+
+ if (!ret && memcmp(&e, &e2, sizeof(e)))
+ ret = -1;
+ }
+
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
+ i2c_set_bus_num(bus);
+#endif
+
+ if (ret) {
+ printf("Programming failed.\n");
+ has_been_read = 0;
+ return -1;
+ }
+
+ printf("Programming passed.\n");
+ return 0;
+}
+
+/**
+ * h2i - converts hex character into a number
+ *
+ * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
+ * the integer equivalent.
+ */
+static inline u8 h2i(char p)
+{
+ if ((p >= '0') && (p <= '9'))
+ return p - '0';
+
+ if ((p >= 'A') && (p <= 'F'))
+ return (p - 'A') + 10;
+
+ if ((p >= 'a') && (p <= 'f'))
+ return (p - 'a') + 10;
+
+ return 0;
+}
+
+/**
+ * set_date - stores the build date into the EEPROM
+ *
+ * This function takes a pointer to a string in the format "YYMMDDhhmmss"
+ * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
+ * and stores it in the build date field of the EEPROM local copy.
+ */
+static void set_date(const char *string)
+{
+ unsigned int i;
+
+ if (strlen(string) != 12) {
+ printf("Usage: mac date YYMMDDhhmmss\n");
+ return;
+ }
+
+ for (i = 0; i < 6; i++)
+ e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
+
+ update_crc();
+}
+
+/**
+ * set_mac_address - stores a MAC address into the EEPROM
+ *
+ * This function takes a pointer to MAC address string
+ * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
+ * stores it in the MAC address field in the EEPROM local copy.
+ */
+static void set_mac_address(const char *string)
+{
+ char *p = (char *) string;
+ unsigned int i;
+
+ for (i = 0; *p && (i < 6); i++) {
+ e.mac[i] = simple_strtoul(p, &p, 16);
+ if (*p == ':')
+ p++;
+ }
+
+ update_crc();
+}
+
+int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char cmd;
+
+ if (argc == 1) {
+ show_eeprom();
+ return 0;
+ }
+
+ cmd = argv[1][0];
+
+ if (cmd == 'r') {
+#ifdef DEBUG
+ printf("%s read\n", __func__);
+#endif
+ read_eeprom();
+ return 0;
+ }
+
+ if (argc == 2) {
+ switch (cmd) {
+ case 's': /* save */
+#ifdef DEBUG
+ printf("%s save\n", __func__);
+#endif
+ prog_eeprom();
+ break;
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+ }
+
+ /* We know we have@least one parameter */
+
+ switch (cmd) {
+ case 'n': /* serial number */
+#ifdef DEBUG
+ printf("%s serial number\n", __func__);
+#endif
+ memset(e.sn, 0, sizeof(e.sn));
+ strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
+ update_crc();
+ break;
+ case 'd': /* date BCD format YYMMDDhhmmss */
+ set_date(argv[2]);
+ break;
+ case 'e': /* errata */
+ printf("mac errata not implemented\n");
+ break;
+ case 'i': /* id */
+ memset(e.id, 0, sizeof(e.id));
+ strncpy((char *)e.id, argv[2], sizeof(e.id) - 1);
+ update_crc();
+ break;
+ case 'p': /* ports */
+ printf("mac ports not implemented (always 1 port)\n");
+ break;
+ case '0' ... '9':
+ /* we only have "mac 0" but any digit can be used here */
+ set_mac_address(argv[2]);
+ break;
+ case 'h': /* help */
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+int mac_read_from_eeprom(void)
+{
+ u32 crc, crc_offset = offsetof(struct eeprom, crc);
+ u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
+
+ if (read_eeprom()) {
+ printf("EEPROM Read failed.\n");
+ return -1;
+ }
+
+ crc = crc32(0, (void *)&e, crc_offset);
+ crcp = (void *)&e + crc_offset;
+ if (crc != be32_to_cpu(*crcp)) {
+ printf("EEPROM CRC mismatch (%08x != %08x)\n", crc,
+ be32_to_cpu(e.crc));
+ return -1;
+ }
+
+ if (memcmp(&e.mac, "\0\0\0\0\0\0", 6) &&
+ memcmp(&e.mac, "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
+ char ethaddr[9];
+
+ sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ e.mac[0],
+ e.mac[1],
+ e.mac[2],
+ e.mac[3],
+ e.mac[4],
+ e.mac[5]);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("ethaddr"))
+ setenv("ethaddr", ethaddr);
+ }
+
+ if (memcmp(&e.sn, "\0\0\0\0\0\0\0\0\0\0", 10) &&
+ memcmp(&e.sn, "\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF", 10)) {
+ char serial_num[12];
+
+ strncpy(serial_num, (char *)e.sn, sizeof(e.sn) - 1);
+ /* Only initialize environment variables that are blank
+ * (i.e. have not yet been set)
+ */
+ if (!getenv("serial#"))
+ setenv("serial#", serial_num);
+ }
+
+ /* TODO should I calculate CRC here? */
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ char *serial = getenv("serial#");
+
+ if (serial && (strlen(serial) > 3)) {
+ /* use the numerical part of the serial number LXnnnnnn */
+ serialnr->high = 0;
+ serialnr->low = simple_strtoul(serial + 2, NULL, 10);
+ } else {
+ serialnr->high = 0;
+ serialnr->low = 0;
+ }
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index 65482ac..9e0af1c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -179,6 +179,7 @@ am3517_evm arm armv7 am3517evm logicpd
dig297 arm armv7 dig297 comelit omap3
omap3_zoom1 arm armv7 zoom1 logicpd omap3
omap3_zoom2 arm armv7 zoom2 logicpd omap3
+omap3_mvblx arm armv7 mvblx matrix_vision omap3
omap3_beagle arm armv7 beagle ti omap3
omap3_evm arm armv7 evm ti omap3
omap3_sdp3430 arm armv7 sdp3430 ti omap3
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1768cdd..fe98a59 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -68,6 +68,11 @@ make
make cm_t35_config
make
+* BlueLYNX-X:
+
+make omap3_mvblx_config
+make
+
Custom commands
===============
diff --git a/include/configs/omap3_mvblx.h b/include/configs/omap3_mvblx.h
new file mode 100644
index 0000000..a0252a2
--- /dev/null
+++ b/include/configs/omap3_mvblx.h
@@ -0,0 +1,313 @@
+/*
+ * MATRIX VISION GmbH mvBlueLYNX-X
+ *
+ * Derived from omap3_beagle.h:
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ *
+ * Configuration settings for the TI OMAP3530 Beagle board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP34XX 1 /* which is a 34XX */
+#define CONFIG_OMAP3430 1 /* which is in a 3430 */
+#define CONFIG_MVBLX 1 /* working with mvBlueLYNX-X */
+#define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
+
+#define CONFIG_SDRC /* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO 1
+#define CONFIG_DISPLAY_BOARDINFO 1
+
+/* Clock Defines */
+#define V_OSCK 26000000 /* Clock output from T2 */
+#define V_SCLK (V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ /* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_OF_LIBFDT 1
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+#define CONFIG_REVISION_TAG 1
+#define CONFIG_SERIAL_TAG 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE (2 << 10) /* 2 KiB */
+ /* Sector */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX 3
+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
+#define CONFIG_SERIAL3 3 /* UART3 */
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
+ 115200}
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_MMC 1
+#define CONFIG_OMAP_HSMMC 1
+#define CONFIG_DOS_PARTITION 1
+
+/* DDR - I use Micron DDR */
+#define CONFIG_OMAP3_MICRON_DDR 1
+
+/* USB */
+#define CONFIG_MUSB_UDC 1
+#define CONFIG_USB_OMAP3 1
+#define CONFIG_TWL4030_USB 1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE 1
+#define CONFIG_USB_TTY 1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
+#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
+#define CONFIG_USBD_VENDORID 0x164c
+#define CONFIG_USBD_PRODUCTID_GSERIAL 0x0201
+#define CONFIG_USBD_PRODUCTID_CDCACM 0x0201
+#define CONFIG_USBD_MANUFACTURER "MATRIX VISION GmbH"
+#define CONFIG_USBD_PRODUCT_NAME "mvBlueLYNX-X"
+
+/* no FLASH available */
+#define CONFIG_SYS_NO_FLASH
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2 /* EXT2 Support */
+#define CONFIG_CMD_FAT /* FAT support */
+#define CONFIG_CMD_I2C /* I2C serial bus support */
+#define CONFIG_CMD_MMC /* MMC support */
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_IMI /* iminfo */
+#undef CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#define CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_FPGA
+
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0
+#define CONFIG_SYS_I2C_BUS 0 /* This isn't used anywhere ?? */
+#define CONFIG_SYS_I2C_BUS_SELECT 1 /* This isn't used anywhere ?? */
+#define CONFIG_DRIVER_OMAP34XX_I2C 1
+#define CONFIG_I2C_MULTI_BUS 1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER 1
+
+/* Environment information */
+#undef CONFIG_ENV_OVERWRITE /* disallow overwriting serial# and ethaddr */
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=0x82000000\0" \
+ "usbtty=cdc_acm\0" \
+ "console=ttyO2,115200n8\0" \
+ "mpurate=600\0" \
+ "vram=12M\0" \
+ "dvimode=1024x768-24 at 60\0" \
+ "defaultdisplay=dvi\0" \
+ "fpgafilename=mvbluelynx_x.rbf\0" \
+ "loadfpga=if fatload mmc ${mmcdev} ${loadaddr} ${fpgafilename}; then " \
+ "fpga load 0 ${loadaddr} ${filesize}; " \
+ "fi;\0" \
+ "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
+ "mmcargs=setenv bootargs console=${console} " \
+ "mpurate=${mpurate} " \
+ "vram=${vram} " \
+ "omapfb.mode=dvi:${dvimode} " \
+ "omapfb.debug=y " \
+ "omapdss.def_disp=${defaultdisplay} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype} " \
+ "${cmdline_suffix}\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
+ "importbootenv=echo Importing environment from mmc ...; " \
+ "env import -t $loadaddr $filesize\0" \
+ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm ${loadaddr}\0" \
+ "mmcbootcmd= " \
+ "echo Trying mmc${mmcdev}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "setenv mmcroot /dev/mmcblk${mmcdev}p2 rw; " \
+ "echo SD/MMC found on device ${mmcdev};" \
+ "if run loadbootenv; then " \
+ "echo Loading boot environment from mmc${mmcdev}; " \
+ "run importbootenv; " \
+ "fi;" \
+ "run loadfpga; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...;" \
+ "run uenvcmd;" \
+ "fi;" \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "fi;" \
+ "fi\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "setenv mmcdev 1;" \
+ "run mmcbootcmd || " \
+ "setenv mmcdev 0;" \
+ "run mmcbootcmd"
+
+
+#define CONFIG_AUTO_COMPLETE 1
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "mvblx # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_ALT_MEMTEST 1 /* alternative memtest with looping */
+#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END (0x9dffffff) /* end = 448 MB */
+#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ 1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
+#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE (32 << 20) /*@least 32 MiB */
+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C 1
+
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/*----------------------------------------------------------------------------
+ * Network Subsystem (SMSC9211 Ethernet from SMSC9118 family)
+ *----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_NET_MULTI
+ #define CONFIG_SMC911X 1
+ #define CONFIG_SMC911X_32_BIT
+ #define CONFIG_SMC911X_BASE 0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_FPGA_COUNT 1
+#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2
+#define CONFIG_FPGA_ALTERA
+#define CONFIG_FPGA_CYCLON2
+#define CONFIG_SYS_FPGA_PROG_FEEDBACK
+#define CONFIG_SYS_FPGA_DONT_USE_CONF_DONE
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 0xA0>>1 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 2^4 = 16-byte pages */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#define CONFIG_SYS_EEPROM_SIZE 256 /* Bytes */
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_EEPROM_BUS_NUM 2
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_OMAP3_SPI
+
+#endif /* __CONFIG_H */
--
1.7.4.1
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v5] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-10-05 15:08 ` [U-Boot] [PATCH v5] " Michael Jones
2011-10-10 15:08 ` [U-Boot] [PATCH v6] " Michael Jones
@ 2011-10-18 17:31 ` Tom Rini
2011-10-19 8:16 ` Michael Jones
2011-10-20 11:37 ` [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning Michael Jones
1 sibling, 2 replies; 48+ messages in thread
From: Tom Rini @ 2011-10-18 17:31 UTC (permalink / raw)
To: u-boot
On Wed, Oct 5, 2011 at 8:08 AM, Michael Jones
<michael.jones@matrix-vision.de> wrote:
> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
> intelligent camera.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Configuring for omap3_mvblx board...
mv_common.c:32:14: warning: 'entries_to_keep' defined but not used
text data bss dec hex filename
225583 4696 215012 445291 6cb6b ./u-boot
Please fix the warning, thanks.
--
Tom
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH v5] OMAP3: mvblx: Initial support for mvBlueLYNX-X
2011-10-18 17:31 ` [U-Boot] [PATCH v5] " Tom Rini
@ 2011-10-19 8:16 ` Michael Jones
2011-10-20 11:37 ` [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning Michael Jones
1 sibling, 0 replies; 48+ messages in thread
From: Michael Jones @ 2011-10-19 8:16 UTC (permalink / raw)
To: u-boot
Hi Tom,
On 10/18/2011 07:31 PM, Tom Rini wrote:
> On Wed, Oct 5, 2011 at 8:08 AM, Michael Jones
> <michael.jones@matrix-vision.de> wrote:
>> Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
>> intelligent camera.
>>
>> Signed-off-by: Michael Jones<michael.jones@matrix-vision.de>
>
> Configuring for omap3_mvblx board...
> mv_common.c:32:14: warning: 'entries_to_keep' defined but not used
> text data bss dec hex filename
> 225583 4696 215012 445291 6cb6b ./u-boot
>
> Please fix the warning, thanks.
>
Sorry I overlooked that. I think this fix belongs in its own patch,
which I will submit soon.
You replied to v5 of this patch, please note that the latest is v6:
http://patchwork.ozlabs.org/patch/118751/
-Michael
MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler
Registergericht: Amtsgericht Stuttgart, HRB 271090
Geschaeftsfuehrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Erhard Meier
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning
2011-10-18 17:31 ` [U-Boot] [PATCH v5] " Tom Rini
2011-10-19 8:16 ` Michael Jones
@ 2011-10-20 11:37 ` Michael Jones
2011-10-20 11:48 ` Andre Schwarz
2011-12-03 12:32 ` Anatolij Gustschin
1 sibling, 2 replies; 48+ messages in thread
From: Michael Jones @ 2011-10-20 11:37 UTC (permalink / raw)
To: u-boot
When CONFIG_ENV_IS_NOWHERE, got following warning:
mv_common.c:32:14: warning: 'entries_to_keep' defined but not used.
Get rid of this warning.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
---
board/matrix_vision/common/mv_common.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
index 404c8b4..acb72c5 100644
--- a/board/matrix_vision/common/mv_common.c
+++ b/board/matrix_vision/common/mv_common.c
@@ -29,6 +29,7 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_ENV_IS_NOWHERE
static char* entries_to_keep[] = {
"serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
"fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
@@ -38,7 +39,6 @@ static char* entries_to_keep[] = {
#define MV_MAX_ENV_ENTRY_LENGTH 64
#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
-#ifndef CONFIG_ENV_IS_NOWHERE
void mv_reset_environment(void)
{
int i;
--
1.7.4.1
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning
2011-10-20 11:37 ` [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning Michael Jones
@ 2011-10-20 11:48 ` Andre Schwarz
2011-12-03 12:32 ` Anatolij Gustschin
1 sibling, 0 replies; 48+ messages in thread
From: Andre Schwarz @ 2011-10-20 11:48 UTC (permalink / raw)
To: u-boot
Am 20.10.2011 13:37, schrieb Michael Jones:
> When CONFIG_ENV_IS_NOWHERE, got following warning:
> mv_common.c:32:14: warning: 'entries_to_keep' defined but not used.
> Get rid of this warning.
>
> Signed-off-by: Michael Jones<michael.jones@matrix-vision.de>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
> ---
> board/matrix_vision/common/mv_common.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c
> index 404c8b4..acb72c5 100644
> --- a/board/matrix_vision/common/mv_common.c
> +++ b/board/matrix_vision/common/mv_common.c
> @@ -29,6 +29,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +#ifndef CONFIG_ENV_IS_NOWHERE
> static char* entries_to_keep[] = {
> "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt",
> "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr",
> @@ -38,7 +39,6 @@ static char* entries_to_keep[] = {
> #define MV_MAX_ENV_ENTRY_LENGTH 64
> #define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep)
>
> -#ifndef CONFIG_ENV_IS_NOWHERE
> void mv_reset_environment(void)
> {
> int i;
^ permalink raw reply [flat|nested] 48+ messages in thread
* [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning
2011-10-20 11:37 ` [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning Michael Jones
2011-10-20 11:48 ` Andre Schwarz
@ 2011-12-03 12:32 ` Anatolij Gustschin
1 sibling, 0 replies; 48+ messages in thread
From: Anatolij Gustschin @ 2011-12-03 12:32 UTC (permalink / raw)
To: u-boot
On Thu, 20 Oct 2011 13:37:18 +0200
Michael Jones <michael.jones@matrix-vision.de> wrote:
> When CONFIG_ENV_IS_NOWHERE, got following warning:
> mv_common.c:32:14: warning: 'entries_to_keep' defined but not used.
> Get rid of this warning.
>
> Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
> ---
> board/matrix_vision/common/mv_common.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
Applied to u-boot-staging/agust at denx.de. Thanks!
Anatolij
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2011-12-03 12:32 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-07-15 9:09 [U-Boot] [PATCH 0/7] OMAP3: Add support for mvBlueLYNX-X Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 1/7] fpga: add #define for Altera Cyclone EP3C5 Michael Jones
2011-07-28 14:46 ` Wolfgang Denk
2011-07-15 9:09 ` [U-Boot] [PATCH 2/7] fpga: support FPP Cyclone configuration Michael Jones
2011-07-28 14:47 ` Wolfgang Denk
2011-07-15 9:09 ` [U-Boot] [PATCH 3/7] ARMV7: OMAP3: Add 37xx ESx revision numbers Michael Jones
2011-07-18 14:36 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-15 9:09 ` [U-Boot] [PATCH 4/7] mmc: rescan fails on empty slot Michael Jones
2011-07-18 14:40 ` [U-Boot] [PATCH v2 " Michael Jones
2011-08-17 2:15 ` Andy Fleming
2011-08-17 2:30 ` Andy Fleming
2011-08-17 7:46 ` Michael Jones
2011-07-19 2:06 ` [U-Boot] [PATCH " Jaehoon Chung
2011-07-20 8:51 ` Michael Jones
2011-07-20 9:52 ` Jaehoon Chung
2011-07-15 9:09 ` [U-Boot] [PATCH 5/7] mv_common.c: don't compile reset_environment if ENV_IS_NOWHERE Michael Jones
2011-07-18 14:45 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-28 14:49 ` Wolfgang Denk
2011-07-18 17:39 ` [U-Boot] [PATCH " Mike Frysinger
2011-07-15 9:09 ` [U-Boot] [PATCH 6/7] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Michael Jones
2011-07-18 14:58 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-27 6:07 ` Heiko Schocher
2011-07-27 7:42 ` Michael Jones
2011-07-27 7:53 ` Heiko Schocher
2011-07-27 12:41 ` [U-Boot] [PATCH v3] " Michael Jones
2011-07-27 12:41 ` [U-Boot] [PATCH] ARMV7: OMAP: I2C driver: cosmetic: make checkpatch-compatible Michael Jones
2011-08-01 9:12 ` [U-Boot] [PATCH v3] ARMV7: OMAP: I2C driver: Write more than 1 byte at a time in i2c_write Heiko Schocher
2011-08-01 10:14 ` [U-Boot] [PATCH v4] " Michael Jones
2011-08-02 6:37 ` Heiko Schocher
2011-09-04 17:59 ` Paulraj, Sandeep
2011-09-05 5:34 ` Heiko Schocher
2011-07-27 21:00 ` [U-Boot] [PATCH v2 6/7] " Wolfgang Denk
2011-07-15 9:09 ` [U-Boot] [PATCH 7/7] OMAP3: mvblx: Initial support for mvBlueLYNX-X Michael Jones
2011-07-18 15:00 ` [U-Boot] [PATCH v2 " Michael Jones
2011-07-27 9:57 ` Igor Grinberg
2011-08-04 13:46 ` [U-Boot] [PATCH v3] " Michael Jones
2011-10-06 22:06 ` Wolfgang Denk
2011-08-17 8:55 ` [U-Boot] [PATCH v4] " Michael Jones
2011-10-06 21:51 ` Wolfgang Denk
2011-10-07 9:06 ` Michael Jones
2011-10-09 19:59 ` Wolfgang Denk
2011-10-05 15:08 ` [U-Boot] [PATCH v5] " Michael Jones
2011-10-10 15:08 ` [U-Boot] [PATCH v6] " Michael Jones
2011-10-18 17:31 ` [U-Boot] [PATCH v5] " Tom Rini
2011-10-19 8:16 ` Michael Jones
2011-10-20 11:37 ` [U-Boot] [PATCH] mv_common.c: get rid of 'defined but not used' warning Michael Jones
2011-10-20 11:48 ` Andre Schwarz
2011-12-03 12:32 ` Anatolij Gustschin
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