[U-Boot] [PATCH v2 0/10] x86: Patches to enable running U-Boot from coreboot

[U-Boot] [PATCH v2 0/10] x86: Patches to enable running U-Boot from coreboot

[Simon Glass]

This series carries on from Gabe Black's work to upstream support for
running U-Boot from coreboot.

Aditional follow-on patches are also required, depending on feedback
here.

Changes in v2:
- Put CONFIG_NO_RESET_CODE into Makefile instead of source files
- Add new patch to remove coreboot start16 code.

Gabe Black (4):
  x86: Allow excluding reset vector code from u-boot
  x86: Add some missing includes.
  x86: coreboot: Tell u-boot about PCI bus 0 when initializing
  x86: coreboot: Implement recursively scanning PCI busses

Simon Glass (4):
  x86: Change board baud_rate to ulong
  x86: Add initial memory barrier macros
  x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE
  x86: Remove coreboot start16 code

Stefan Reinauer (1):
  x86: coreboot: Move non-board specific files to coreboot arch
    directory

Vadim Bendebury (1):
  x86: coreboot: Modify u-boot code to allow building coreboot payload

 Makefile                                           |    7 +++-
 arch/x86/cpu/Makefile                              |    5 ++-
 arch/x86/cpu/coreboot/Makefile                     |    2 +
 .../x86/cpu}/coreboot/coreboot.c                   |    0
 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c  |   35 ++++++++++++++++++
 arch/x86/cpu/u-boot.lds                            |    3 ++
 arch/x86/include/asm/global_data.h                 |    2 +
 arch/x86/include/asm/io.h                          |    8 ++++
 arch/x86/include/asm/pci.h                         |    2 +-
 arch/x86/include/asm/u-boot.h                      |    5 ++-
 board/chromebook-x86/coreboot/Makefile             |    2 -
 board/chromebook-x86/coreboot/config.mk            |   37 ++++++++++++++++++++
 board/chromebook-x86/coreboot/coreboot_start16.S   |   13 -------
 common/cmd_bdinfo.c                                |    2 +-
 include/configs/coreboot.h                         |    6 +++-
 15 files changed, 107 insertions(+), 22 deletions(-)
 rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%)
 rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (51%)
 create mode 100644 board/chromebook-x86/coreboot/config.mk

-- 
1.7.7.3

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Simon Glass]

This is a ulong for some architectures and just unsigned for others.
Change x86 to be consistent.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/u-boot.h |    2 +-
 common/cmd_bdinfo.c           |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
index da667c5..0671b8d 100644
--- a/arch/x86/include/asm/u-boot.h
+++ b/arch/x86/include/asm/u-boot.h
@@ -48,7 +48,7 @@ typedef struct bd_info {
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned int	bi_baudrate;	/* Console Baudrate */
+	unsigned long	bi_baudrate;	/* Console Baudrate */
 	unsigned long   bi_boot_params;	/* where this board expects params */
 	struct				/* RAM configuration */
 	{
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 23bd8a5..9bc0ebc 100644
--- a/common/cmd_bdinfo.c
+++ b/common/cmd_bdinfo.c
@@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("ip_addr     = %s\n", getenv("ipaddr"));
 	print_mhz("ethspeed",	    bd->bi_ethspeed);
 #endif
-	printf("baudrate    = %d bps\n", bd->bi_baudrate);
+	printf("baudrate    = %ld bps\n", bd->bi_baudrate);
 
 	return 0;
 }
-- 
1.7.7.3

[U-Boot] [PATCH v2 02/10] x86: Add initial memory barrier macros

[Simon Glass]

These are available on other architectures, so add them on x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/io.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 9b757d4..b12bdd8 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -234,4 +234,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
 	return (phys_addr_t)(vaddr);
 }
 
+/*
+ * TODO: The kernel offers some more advanced versions of barriers, it might
+ * have some advantages to use them instead of the simple one here.
+ */
+#define dmb()		__asm__ __volatile__ ("" : : : "memory")
+#define __iormb()	dmb()
+#define __iowmb()	dmb()
+
 #endif
-- 
1.7.7.3

[U-Boot] [PATCH v2 03/10] x86: Allow excluding reset vector code from u-boot

[Simon Glass]

From: Gabe Black <gabeblack@chromium.org>

When running from coreboot we don't want this code.

This version works by ifdef-ing out all of the code that would go
into those sections and all the code that refers to it. The sections are
then empty, and the linker will either leave them empty for the loader
to ignore or remove them entirely.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Put CONFIG_NO_RESET_CODE into Makefile instead of source files

 Makefile                |    7 +++++--
 arch/x86/cpu/Makefile   |    5 ++++-
 arch/x86/cpu/u-boot.lds |    3 +++
 3 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 34d9075..6c2f357 100644
--- a/Makefile
+++ b/Makefile
@@ -212,9 +212,12 @@ endif
 # U-Boot objects....order is important (i.e. start must be first)
 
 OBJS  = $(CPUDIR)/start.o
+OBJS  = $(CPUDIR)/start.o
 ifeq ($(CPU),x86)
-OBJS += $(CPUDIR)/start16.o
-OBJS += $(CPUDIR)/resetvec.o
+	ifneq ($(CONFIG_NO_RESET_CODE),y)
+		OBJS += $(CPUDIR)/start16.o
+		OBJS += $(CPUDIR)/resetvec.o
+	endif
 endif
 ifeq ($(CPU),ppc4xx)
 OBJS += $(CPUDIR)/resetvec.o
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f1fc18..1eb70a7 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
-START	= start.o start16.o resetvec.o
+START	= start.o
+ifneq ($(CONFIG_NO_RESET_CODE),y)
+START	+= resetvec.o start16.o
+endif
 COBJS	= interrupts.o cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index fe28030..2a90a01 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -85,6 +85,8 @@ SECTIONS
 	__bios_start = LOADADDR(.bios);
 	__bios_size = SIZEOF(.bios);
 
+#ifndef CONFIG_NO_RESET_CODE
+
 	/*
 	 * The following expressions place the 16-bit Real-Mode code and
 	 * Reset Vector at the end of the Flash ROM
@@ -94,4 +96,5 @@ SECTIONS
 
 	. = RESET_VEC_LOC;
 	.resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
+#endif
 }
-- 
1.7.7.3

[U-Boot] [PATCH v2 04/10] x86: Add some missing includes.

[Simon Glass]

From: Gabe Black <gabeblack@chromium.org>

I suspect these includes were usually available because something else
included them earlier or because they were brought in transitively.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/include/asm/global_data.h |    2 ++
 arch/x86/include/asm/u-boot.h      |    3 +++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 6d29c0b..3c79508 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -33,6 +33,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/u-boot.h>
+
 typedef	struct global_data {
 	/* NOTE: gd_addr MUST be first member of struct global_data! */
 	unsigned long	gd_addr;	/* Location of Global Data */
diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
index 0671b8d..e2ba845 100644
--- a/arch/x86/include/asm/u-boot.h
+++ b/arch/x86/include/asm/u-boot.h
@@ -36,6 +36,9 @@
 #ifndef _U_BOOT_H_
 #define _U_BOOT_H_	1
 
+#include <config.h>
+#include <compiler.h>
+
 typedef struct bd_info {
 	unsigned long	bi_memstart;	/* start of DRAM memory */
 	phys_size_t	bi_memsize;	/* size	 of DRAM memory in bytes */
-- 
1.7.7.3

[U-Boot] [PATCH v2 05/10] x86: coreboot: Move non-board specific files to coreboot arch directory

[Simon Glass]

From: Stefan Reinauer <reinauer@chromium.org>

coreboot.c and coreboot_pci.c don't contain board specific but only
coreboot specific code. Hence move it to the coreboot directory in
arch/x86/cpu (which should probably be moved out of cpu/ in another
commit)

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/coreboot/Makefile                     |    2 ++
 .../x86/cpu}/coreboot/coreboot.c                   |    0
 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c  |    0
 board/chromebook-x86/coreboot/Makefile             |    2 --
 4 files changed, 2 insertions(+), 2 deletions(-)
 rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%)
 rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)

diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
index 13f5f8a..fbf5a00 100644
--- a/arch/x86/cpu/coreboot/Makefile
+++ b/arch/x86/cpu/coreboot/Makefile
@@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(SOC).o
 
+COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o
 COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
 COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
 COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
 COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o
+COBJS-$(CONFIG_PCI) += pci.o
 
 SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
 
diff --git a/board/chromebook-x86/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot.c
rename to arch/x86/cpu/coreboot/coreboot.c
diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/arch/x86/cpu/coreboot/pci.c
similarity index 100%
rename from board/chromebook-x86/coreboot/coreboot_pci.c
rename to arch/x86/cpu/coreboot/pci.c
diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
index cfcc0df..2bddf04 100644
--- a/board/chromebook-x86/coreboot/Makefile
+++ b/board/chromebook-x86/coreboot/Makefile
@@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).o
 
-COBJS-y	+= coreboot.o
-COBJS-$(CONFIG_PCI) += coreboot_pci.o
 SOBJS-y	+= coreboot_start16.o
 SOBJS-y	+= coreboot_start.o
 
-- 
1.7.7.3

[U-Boot] [PATCH v2 06/10] x86: coreboot: Tell u-boot about PCI bus 0 when initializing

[Simon Glass]

From: Gabe Black <gabeblack@chromium.org>

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization of
the coreboot "board" which implements some of X86's basic PCI semantics. This
relies on some existing generic code, but also duplicates a little bit of code
from the sc520 implementation. Ideally we'd eliminate that duplication at some
point.

It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
generic PCI configuration code what to do if it encounters a bridge,
specifically to scan the bus on the other side of it.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/coreboot/pci.c |   15 +++++++++++++++
 arch/x86/include/asm/pci.h  |    2 +-
 2 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 732ca3c..0ddc975 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -25,6 +25,21 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller coreboot_hose;
+
 void pci_init_board(void)
 {
+	coreboot_hose.first_busno = 0;
+	coreboot_hose.last_busno = 0xff;
+	coreboot_hose.region_count = 0;
+
+	pci_setup_type1(&coreboot_hose);
+
+	pci_register_hose(&coreboot_hose);
+
+	coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
 }
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 37cc7e3..6d68ab6 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -24,7 +24,7 @@
  */
 
 #ifndef _PCI_I386_H_
-#define _PCI_I386_H_	1
+#define _PCI_I386_H_
 
 #define DEFINE_PCI_DEVICE_TABLE(_table) \
 	const struct pci_device_id _table[]
-- 
1.7.7.3

[U-Boot] [PATCH v2 07/10] x86: coreboot: Modify u-boot code to allow building coreboot payload

[Simon Glass]

From: Vadim Bendebury <vbendeb@chromium.org>

This prevents the preprocessor from complaining when processing
variadic macros

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 board/chromebook-x86/coreboot/config.mk |   37 +++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 board/chromebook-x86/coreboot/config.mk

diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk
new file mode 100644
index 0000000..f720851
--- /dev/null
+++ b/board/chromebook-x86/coreboot/config.mk
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above
+# copyright notice, this list of conditions and the following disclaimer
+# in the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Google Inc. nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Alternatively, this software may be distributed under the terms of the
+# GNU General Public License ("GPL") version 2 as published by the Free
+# Software Foundation.
+#
+
+HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
-- 
1.7.7.3

[U-Boot] [PATCH v2 08/10] x86: coreboot: Implement recursively scanning PCI busses

[Simon Glass]

From: Gabe Black <gabeblack@chromium.org>

A hook is installed to configure PCI bus bridges as they encountered by u-boot.
The hook extracts the secondary bus number from the bridge's config space and
then recursively scans that bus.

On Coreboot, the PCI bus address space has identity mapping with the
physical address space, so declare it as such to ensure that the "pci_map_bar"
function used by some PCI drivers is behaving properly. This fixes the
EHCI PCI driver initialization on Stumpy.

This was tested as follows:

Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
bus 1, and empty busses 2 through 5. This matches the bridges
reported on bus 0 and the PCI configuration output from coreboot.

Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

 arch/x86/cpu/coreboot/pci.c |   26 +++++++++++++++++++++++---
 1 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 0ddc975..8f94167 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -31,15 +31,35 @@
 
 static struct pci_controller coreboot_hose;
 
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+			      struct pci_config_table *table)
+{
+	u8 secondary;
+	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+	hose->last_busno = max(hose->last_busno, secondary);
+	pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_coreboot_config_table[] = {
+	/* vendor, device, class, bus, dev, func */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+	{}
+};
+
 void pci_init_board(void)
 {
+	coreboot_hose.config_table = pci_coreboot_config_table;
 	coreboot_hose.first_busno = 0;
-	coreboot_hose.last_busno = 0xff;
-	coreboot_hose.region_count = 0;
+	coreboot_hose.last_busno = 0;
+
+	pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
+		PCI_REGION_MEM);
+	coreboot_hose.region_count = 1;
 
 	pci_setup_type1(&coreboot_hose);
 
 	pci_register_hose(&coreboot_hose);
 
-	coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
+	pci_hose_scan(&coreboot_hose);
 }
-- 
1.7.7.3

[U-Boot] [PATCH v2 09/10] x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE

[Simon Glass]

Coreboot boards have an LPC TPM connected, so enable this. We also need
to skip the reset code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

 include/configs/coreboot.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 2c65d74..75db176 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -37,7 +37,7 @@
 #define CONFIG_SYS_COREBOOT
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
-
+#define CONFIG_NO_RESET_CODE
 
 /*-----------------------------------------------------------------------
  * Watchdog Configuration
@@ -45,6 +45,10 @@
 #undef CONFIG_WATCHDOG
 #undef CONFIG_HW_WATCHDOG
 
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
 /*-----------------------------------------------------------------------
  * Real Time Clock Configuration
  */
-- 
1.7.7.3

[U-Boot] [PATCH v2 10/10] x86: Remove coreboot start16 code

[Simon Glass]

Now that coreboot doesn't need the start16 code, remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v2:
- Add new patch to remove coreboot start16 code.

 board/chromebook-x86/coreboot/coreboot_start16.S |   13 -------------
 1 files changed, 0 insertions(+), 13 deletions(-)

diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S
index 9ad06df..6b3d92d 100644
--- a/board/chromebook-x86/coreboot/coreboot_start16.S
+++ b/board/chromebook-x86/coreboot/coreboot_start16.S
@@ -22,19 +22,6 @@
  * MA 02111-1307 USA
  */
 
-/*
- * 16bit initialization code.
- * This code have to map the area of the boot flash
- * that is used by U-boot to its final destination.
- */
-
-.text
-.section .start16, "ax"
-.code16
-.globl board_init16
-board_init16:
-	jmp	board_init16_ret
-
 .section .bios, "ax"
 .code16
 .globl realmode_reset
-- 
1.7.7.3

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> This is a ulong for some architectures and just unsigned for others.
> Change x86 to be consistent.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/u-boot.h |    2 +-
>  common/cmd_bdinfo.c           |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
> index da667c5..0671b8d 100644
> --- a/arch/x86/include/asm/u-boot.h
> +++ b/arch/x86/include/asm/u-boot.h
> @@ -48,7 +48,7 @@ typedef struct bd_info {
>         unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
>         unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
>         unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
> -       unsigned int    bi_baudrate;    /* Console Baudrate */
> +       unsigned long   bi_baudrate;    /* Console Baudrate */
>         unsigned long   bi_boot_params; /* where this board expects params */
>         struct                          /* RAM configuration */
>         {
> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
> index 23bd8a5..9bc0ebc 100644
> --- a/common/cmd_bdinfo.c
> +++ b/common/cmd_bdinfo.c
> @@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>         printf("ip_addr     = %s\n", getenv("ipaddr"));
>         print_mhz("ethspeed",       bd->bi_ethspeed);
>  #endif
> -       printf("baudrate    = %d bps\n", bd->bi_baudrate);
> +       printf("baudrate    = %ld bps\n", bd->bi_baudrate);
>
>         return 0;
>  }
> --
> 1.7.7.3
>

Ack-by: Graeme Russ <graeme,russ@gmail,com>

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Graeme Russ]

Hi Simon,

Let's do it by the book this time :)

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> This is a ulong for some architectures and just unsigned for others.
> Change x86 to be consistent.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/u-boot.h |    2 +-
>  common/cmd_bdinfo.c           |    2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
> index da667c5..0671b8d 100644
> --- a/arch/x86/include/asm/u-boot.h
> +++ b/arch/x86/include/asm/u-boot.h
> @@ -48,7 +48,7 @@ typedef struct bd_info {
>         unsigned short  bi_ethspeed;    /* Ethernet speed in Mbps */
>         unsigned long   bi_intfreq;     /* Internal Freq, in MHz */
>         unsigned long   bi_busfreq;     /* Bus Freq, in MHz */
> -       unsigned int    bi_baudrate;    /* Console Baudrate */
> +       unsigned long   bi_baudrate;    /* Console Baudrate */
>         unsigned long   bi_boot_params; /* where this board expects params */
>         struct                          /* RAM configuration */
>         {
> diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
> index 23bd8a5..9bc0ebc 100644
> --- a/common/cmd_bdinfo.c
> +++ b/common/cmd_bdinfo.c
> @@ -439,7 +439,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>         printf("ip_addr     = %s\n", getenv("ipaddr"));
>         print_mhz("ethspeed",       bd->bi_ethspeed);
>  #endif
> -       printf("baudrate    = %d bps\n", bd->bi_baudrate);
> +       printf("baudrate    = %ld bps\n", bd->bi_baudrate);
>
>         return 0;
>  }
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 02/10] x86: Add initial memory barrier macros

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> These are available on other architectures, so add them on x86.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/io.h |    8 ++++++++
>  1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
> index 9b757d4..b12bdd8 100644
> --- a/arch/x86/include/asm/io.h
> +++ b/arch/x86/include/asm/io.h
> @@ -234,4 +234,12 @@ static inline phys_addr_t virt_to_phys(void * vaddr)
>         return (phys_addr_t)(vaddr);
>  }
>
> +/*
> + * TODO: The kernel offers some more advanced versions of barriers, it might
> + * have some advantages to use them instead of the simple one here.
> + */
> +#define dmb()          __asm__ __volatile__ ("" : : : "memory")
> +#define __iormb()      dmb()
> +#define __iowmb()      dmb()
> +
>  #endif
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 03/10] x86: Allow excluding reset vector code from u-boot

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Gabe Black <gabeblack@chromium.org>
>
> When running from coreboot we don't want this code.
>
> This version works by ifdef-ing out all of the code that would go
> into those sections and all the code that refers to it. The sections are
> then empty, and the linker will either leave them empty for the loader
> to ignore or remove them entirely.
>
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v2:
> - Put CONFIG_NO_RESET_CODE into Makefile instead of source files
>
>  Makefile                |    7 +++++--
>  arch/x86/cpu/Makefile   |    5 ++++-
>  arch/x86/cpu/u-boot.lds |    3 +++
>  3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/Makefile b/Makefile
> index 34d9075..6c2f357 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -212,9 +212,12 @@ endif
>  # U-Boot objects....order is important (i.e. start must be first)
>
>  OBJS  = $(CPUDIR)/start.o
> +OBJS  = $(CPUDIR)/start.o
>  ifeq ($(CPU),x86)
> -OBJS += $(CPUDIR)/start16.o
> -OBJS += $(CPUDIR)/resetvec.o
> +       ifneq ($(CONFIG_NO_RESET_CODE),y)
> +               OBJS += $(CPUDIR)/start16.o
> +               OBJS += $(CPUDIR)/resetvec.o
> +       endif
>  endif
>  ifeq ($(CPU),ppc4xx)
>  OBJS += $(CPUDIR)/resetvec.o
> diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
> index 7f1fc18..1eb70a7 100644
> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
>
>  LIB    = $(obj)lib$(CPU).o
>
> -START  = start.o start16.o resetvec.o
> +START  = start.o
> +ifneq ($(CONFIG_NO_RESET_CODE),y)
> +START  += resetvec.o start16.o
> +endif
>  COBJS  = interrupts.o cpu.o
>
>  SRCS   := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
> diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
> index fe28030..2a90a01 100644
> --- a/arch/x86/cpu/u-boot.lds
> +++ b/arch/x86/cpu/u-boot.lds
> @@ -85,6 +85,8 @@ SECTIONS
>         __bios_start = LOADADDR(.bios);
>         __bios_size = SIZEOF(.bios);
>
> +#ifndef CONFIG_NO_RESET_CODE
> +
>         /*
>          * The following expressions place the 16-bit Real-Mode code and
>          * Reset Vector at the end of the Flash ROM
> @@ -94,4 +96,5 @@ SECTIONS
>
>         . = RESET_VEC_LOC;
>         .resetvec : AT (CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE + RESET_VEC_LOC)) { KEEP(*(.resetvec)); }
> +#endif
>  }
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 04/10] x86: Add some missing includes.

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Gabe Black <gabeblack@chromium.org>
>
> I suspect these includes were usually available because something else
> included them earlier or because they were brought in transitively.
>
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/include/asm/global_data.h |    2 ++
>  arch/x86/include/asm/u-boot.h      |    3 +++
>  2 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
> index 6d29c0b..3c79508 100644
> --- a/arch/x86/include/asm/global_data.h
> +++ b/arch/x86/include/asm/global_data.h
> @@ -33,6 +33,8 @@
>
>  #ifndef __ASSEMBLY__
>
> +#include <asm/u-boot.h>
> +
>  typedef        struct global_data {
>         /* NOTE: gd_addr MUST be first member of struct global_data! */
>         unsigned long   gd_addr;        /* Location of Global Data */
> diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h
> index 0671b8d..e2ba845 100644
> --- a/arch/x86/include/asm/u-boot.h
> +++ b/arch/x86/include/asm/u-boot.h
> @@ -36,6 +36,9 @@
>  #ifndef _U_BOOT_H_
>  #define _U_BOOT_H_     1
>
> +#include <config.h>
> +#include <compiler.h>
> +
>  typedef struct bd_info {
>         unsigned long   bi_memstart;    /* start of DRAM memory */
>         phys_size_t     bi_memsize;     /* size  of DRAM memory in bytes */
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 05/10] x86: coreboot: Move non-board specific files to coreboot arch directory

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Stefan Reinauer <reinauer@chromium.org>
>
> coreboot.c and coreboot_pci.c don't contain board specific but only
> coreboot specific code. Hence move it to the coreboot directory in
> arch/x86/cpu (which should probably be moved out of cpu/ in another
> commit)
>
> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/coreboot/Makefile                     |    2 ++
>  .../x86/cpu}/coreboot/coreboot.c                   |    0
>  .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c  |    0
>  board/chromebook-x86/coreboot/Makefile             |    2 --
>  4 files changed, 2 insertions(+), 2 deletions(-)
>  rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%)
>  rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (100%)
>
> diff --git a/arch/x86/cpu/coreboot/Makefile b/arch/x86/cpu/coreboot/Makefile
> index 13f5f8a..fbf5a00 100644
> --- a/arch/x86/cpu/coreboot/Makefile
> +++ b/arch/x86/cpu/coreboot/Makefile
> @@ -33,10 +33,12 @@ include $(TOPDIR)/config.mk
>
>  LIB    := $(obj)lib$(SOC).o
>
> +COBJS-$(CONFIG_SYS_COREBOOT) += coreboot.o
>  COBJS-$(CONFIG_SYS_COREBOOT) += tables.o
>  COBJS-$(CONFIG_SYS_COREBOOT) += ipchecksum.o
>  COBJS-$(CONFIG_SYS_COREBOOT) += sdram.o
>  COBJS-$(CONFIG_SYS_COREBOOT) += sysinfo.o
> +COBJS-$(CONFIG_PCI) += pci.o
>
>  SOBJS-$(CONFIG_SYS_COREBOOT) += coreboot_car.o
>
> diff --git a/board/chromebook-x86/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
> similarity index 100%
> rename from board/chromebook-x86/coreboot/coreboot.c
> rename to arch/x86/cpu/coreboot/coreboot.c
> diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/arch/x86/cpu/coreboot/pci.c
> similarity index 100%
> rename from board/chromebook-x86/coreboot/coreboot_pci.c
> rename to arch/x86/cpu/coreboot/pci.c
> diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile
> index cfcc0df..2bddf04 100644
> --- a/board/chromebook-x86/coreboot/Makefile
> +++ b/board/chromebook-x86/coreboot/Makefile
> @@ -32,8 +32,6 @@ include $(TOPDIR)/config.mk
>
>  LIB    = $(obj)lib$(BOARD).o
>
> -COBJS-y        += coreboot.o
> -COBJS-$(CONFIG_PCI) += coreboot_pci.o
>  SOBJS-y        += coreboot_start16.o
>  SOBJS-y        += coreboot_start.o
>
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 06/10] x86: coreboot: Tell u-boot about PCI bus 0 when initializing

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Gabe Black <gabeblack@chromium.org>
>
> U-boot needs a host controller or "hose" to interact with the PCI busses
> behind them. This change installs a host controller during initialization of
> the coreboot "board" which implements some of X86's basic PCI semantics. This
> relies on some existing generic code, but also duplicates a little bit of code
> from the sc520 implementation. Ideally we'd eliminate that duplication at some
> point.
>
> It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's
> generic PCI configuration code what to do if it encounters a bridge,
> specifically to scan the bus on the other side of it.
>
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/coreboot/pci.c |   15 +++++++++++++++
>  arch/x86/include/asm/pci.h  |    2 +-
>  2 files changed, 16 insertions(+), 1 deletions(-)
>
> diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
> index 732ca3c..0ddc975 100644
> --- a/arch/x86/cpu/coreboot/pci.c
> +++ b/arch/x86/cpu/coreboot/pci.c
> @@ -25,6 +25,21 @@
>   * MA 02111-1307 USA
>   */
>
> +#include <common.h>
> +#include <pci.h>
> +#include <asm/pci.h>
> +
> +static struct pci_controller coreboot_hose;
> +
>  void pci_init_board(void)
>  {
> +       coreboot_hose.first_busno = 0;
> +       coreboot_hose.last_busno = 0xff;
> +       coreboot_hose.region_count = 0;
> +
> +       pci_setup_type1(&coreboot_hose);
> +
> +       pci_register_hose(&coreboot_hose);
> +
> +       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
>  }
> diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
> index 37cc7e3..6d68ab6 100644
> --- a/arch/x86/include/asm/pci.h
> +++ b/arch/x86/include/asm/pci.h
> @@ -24,7 +24,7 @@
>   */
>
>  #ifndef _PCI_I386_H_
> -#define _PCI_I386_H_   1
> +#define _PCI_I386_H_
>
>  #define DEFINE_PCI_DEVICE_TABLE(_table) \
>         const struct pci_device_id _table[]
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 07/10] x86: coreboot: Modify u-boot code to allow building coreboot payload

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Vadim Bendebury <vbendeb@chromium.org>
>
> This prevents the preprocessor from complaining when processing
> variadic macros
>
> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  board/chromebook-x86/coreboot/config.mk |   37 +++++++++++++++++++++++++++++++
>  1 files changed, 37 insertions(+), 0 deletions(-)
>  create mode 100644 board/chromebook-x86/coreboot/config.mk
>
> diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk
> new file mode 100644
> index 0000000..f720851
> --- /dev/null
> +++ b/board/chromebook-x86/coreboot/config.mk
> @@ -0,0 +1,37 @@
> +#
> +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
> +# Use of this source code is governed by a BSD-style license that can be
> +# found in the LICENSE file.
> +#
> +# Redistribution and use in source and binary forms, with or without
> +# modification, are permitted provided that the following conditions are
> +# met:
> +#
> +# * Redistributions of source code must retain the above copyright
> +# notice, this list of conditions and the following disclaimer.
> +# * Redistributions in binary form must reproduce the above
> +# copyright notice, this list of conditions and the following disclaimer
> +# in the documentation and/or other materials provided with the
> +# distribution.
> +# * Neither the name of Google Inc. nor the names of its
> +# contributors may be used to endorse or promote products derived from
> +# this software without specific prior written permission.
> +#
> +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
> +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
> +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
> +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
> +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +#
> +# Alternatively, this software may be distributed under the terms of the
> +# GNU General Public License ("GPL") version 2 as published by the Free
> +# Software Foundation.
> +#
> +
> +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 08/10] x86: coreboot: Implement recursively scanning PCI busses

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:12 AM, Simon Glass <sjg@chromium.org> wrote:
> From: Gabe Black <gabeblack@chromium.org>
>
> A hook is installed to configure PCI bus bridges as they encountered by u-boot.
> The hook extracts the secondary bus number from the bridge's config space and
> then recursively scans that bus.
>
> On Coreboot, the PCI bus address space has identity mapping with the
> physical address space, so declare it as such to ensure that the "pci_map_bar"
> function used by some PCI drivers is behaving properly. This fixes the
> EHCI PCI driver initialization on Stumpy.
>
> This was tested as follows:
>
> Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on
> bus 1, and empty busses 2 through 5. This matches the bridges
> reported on bus 0 and the PCI configuration output from coreboot.
>
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  arch/x86/cpu/coreboot/pci.c |   26 +++++++++++++++++++++++---
>  1 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
> index 0ddc975..8f94167 100644
> --- a/arch/x86/cpu/coreboot/pci.c
> +++ b/arch/x86/cpu/coreboot/pci.c
> @@ -31,15 +31,35 @@
>
>  static struct pci_controller coreboot_hose;
>
> +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
> +                             struct pci_config_table *table)
> +{
> +       u8 secondary;
> +       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
> +       hose->last_busno = max(hose->last_busno, secondary);
> +       pci_hose_scan_bus(hose, secondary);
> +}
> +
> +static struct pci_config_table pci_coreboot_config_table[] = {
> +       /* vendor, device, class, bus, dev, func */
> +       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
> +               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
> +       {}
> +};
> +
>  void pci_init_board(void)
>  {
> +       coreboot_hose.config_table = pci_coreboot_config_table;
>         coreboot_hose.first_busno = 0;
> -       coreboot_hose.last_busno = 0xff;
> -       coreboot_hose.region_count = 0;
> +       coreboot_hose.last_busno = 0;
> +
> +       pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
> +               PCI_REGION_MEM);
> +       coreboot_hose.region_count = 1;
>
>         pci_setup_type1(&coreboot_hose);
>
>         pci_register_hose(&coreboot_hose);
>
> -       coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose);
> +       pci_hose_scan(&coreboot_hose);
>  }
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 09/10] x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:13 AM, Simon Glass <sjg@chromium.org> wrote:
> Coreboot boards have an LPC TPM connected, so enable this. We also need
> to skip the reset code.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
>  include/configs/coreboot.h |    6 +++++-
>  1 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
> index 2c65d74..75db176 100644
> --- a/include/configs/coreboot.h
> +++ b/include/configs/coreboot.h
> @@ -37,7 +37,7 @@
>  #define CONFIG_SYS_COREBOOT
>  #undef CONFIG_SHOW_BOOT_PROGRESS
>  #define CONFIG_LAST_STAGE_INIT
> -
> +#define CONFIG_NO_RESET_CODE
>
>  /*-----------------------------------------------------------------------
>   * Watchdog Configuration
> @@ -45,6 +45,10 @@
>  #undef CONFIG_WATCHDOG
>  #undef CONFIG_HW_WATCHDOG
>
> +/* Generic TPM interfaced through LPC bus */
> +#define CONFIG_GENERIC_LPC_TPM
> +#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
> +
>  /*-----------------------------------------------------------------------
>   * Real Time Clock Configuration
>   */
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 10/10] x86: Remove coreboot start16 code

[Graeme Russ]

Hi Simon,

On Thu, Oct 11, 2012 at 10:13 AM, Simon Glass <sjg@chromium.org> wrote:
> Now that coreboot doesn't need the start16 code, remove it.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v2:
> - Add new patch to remove coreboot start16 code.
>
>  board/chromebook-x86/coreboot/coreboot_start16.S |   13 -------------
>  1 files changed, 0 insertions(+), 13 deletions(-)
>
> diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S
> index 9ad06df..6b3d92d 100644
> --- a/board/chromebook-x86/coreboot/coreboot_start16.S
> +++ b/board/chromebook-x86/coreboot/coreboot_start16.S
> @@ -22,19 +22,6 @@
>   * MA 02111-1307 USA
>   */
>
> -/*
> - * 16bit initialization code.
> - * This code have to map the area of the boot flash
> - * that is used by U-boot to its final destination.
> - */
> -
> -.text
> -.section .start16, "ax"
> -.code16
> -.globl board_init16
> -board_init16:
> -       jmp     board_init16_ret
> -
>  .section .bios, "ax"
>  .code16
>  .globl realmode_reset
> --
> 1.7.7.3
>

Acked-by: Graeme Russ <graeme.russ@gmail.com>

[U-Boot] [PATCH v2 09/10] x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE

[Marek Vasut]

Dear Graeme Russ,

> Hi Simon,
> 
> On Thu, Oct 11, 2012 at 10:13 AM, Simon Glass <sjg@chromium.org> wrote:
> > Coreboot boards have an LPC TPM connected, so enable this. We also need
> > to skip the reset code.
> > 
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> > 
> >  include/configs/coreboot.h |    6 +++++-
> >  1 files changed, 5 insertions(+), 1 deletions(-)
> > 
> > diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
> > index 2c65d74..75db176 100644
> > --- a/include/configs/coreboot.h
> > +++ b/include/configs/coreboot.h
> > @@ -37,7 +37,7 @@
> > 
> >  #define CONFIG_SYS_COREBOOT
> >  #undef CONFIG_SHOW_BOOT_PROGRESS
> >  #define CONFIG_LAST_STAGE_INIT
> > 
> > -
> > +#define CONFIG_NO_RESET_CODE
> > 
> >  /*----------------------------------------------------------------------
> >  -
> >  
> >   * Watchdog Configuration
> > 
> > @@ -45,6 +45,10 @@
> > 
> >  #undef CONFIG_WATCHDOG
> >  #undef CONFIG_HW_WATCHDOG
> > 
> > +/* Generic TPM interfaced through LPC bus */
> > +#define CONFIG_GENERIC_LPC_TPM
> > +#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
> > +
> > 
> >  /*----------------------------------------------------------------------
> >  -
> >  
> >   * Real Time Clock Configuration
> >   */
> > 
> > --
> > 1.7.7.3
> 
> Acked-by: Graeme Russ <graeme.russ@gmail.com>

Well, spliting it into two patches -- since each hunk does something else -- 
won't hurt. But I think it doesn't matter.

Best regards,
Marek Vasut

[U-Boot] [PATCH v2 09/10] x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE

[Graeme Russ]

Hi Marek,

On Thu, Oct 11, 2012 at 2:45 PM, Marek Vasut <marek.vasut@gmail.com> wrote:
> Dear Graeme Russ,
>
>> Hi Simon,
>>
>> On Thu, Oct 11, 2012 at 10:13 AM, Simon Glass <sjg@chromium.org> wrote:
>> > Coreboot boards have an LPC TPM connected, so enable this. We also need
>> > to skip the reset code.
>> >
>> > Signed-off-by: Simon Glass <sjg@chromium.org>
>> > ---
>> >
>> >  include/configs/coreboot.h |    6 +++++-
>> >  1 files changed, 5 insertions(+), 1 deletions(-)
>> >
>> > diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
>> > index 2c65d74..75db176 100644
>> > --- a/include/configs/coreboot.h
>> > +++ b/include/configs/coreboot.h
>> > @@ -37,7 +37,7 @@
>> >
>> >  #define CONFIG_SYS_COREBOOT
>> >  #undef CONFIG_SHOW_BOOT_PROGRESS
>> >  #define CONFIG_LAST_STAGE_INIT
>> >
>> > -
>> > +#define CONFIG_NO_RESET_CODE
>> >
>> >  /*----------------------------------------------------------------------
>> >  -
>> >
>> >   * Watchdog Configuration
>> >
>> > @@ -45,6 +45,10 @@
>> >
>> >  #undef CONFIG_WATCHDOG
>> >  #undef CONFIG_HW_WATCHDOG
>> >
>> > +/* Generic TPM interfaced through LPC bus */
>> > +#define CONFIG_GENERIC_LPC_TPM
>> > +#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
>> > +
>> >
>> >  /*----------------------------------------------------------------------
>> >  -
>> >
>> >   * Real Time Clock Configuration
>> >   */
>> >
>> > --
>> > 1.7.7.3
>>
>> Acked-by: Graeme Russ <graeme.russ@gmail.com>
>
> Well, spliting it into two patches -- since each hunk does something else --
> won't hurt. But I think it doesn't matter.

It's board level config - I see no reason to atomise it. If it was
global / arch / SoC / CPU level then I would to help maintain
bisectability.

Regards,

Graeme

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Wolfgang Denk]

Dear Simon Glass,

In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
> This is a ulong for some architectures and just unsigned for others.
> Change x86 to be consistent.

Given the limited range for this variable it makes no sense to use a
long for this.  Please fix this the other way round, i. e. change the
architectures that use a long.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Always try to do things in chronological order; it's  less  confusing
that way.

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Graeme Russ]

Hi Wolfgang,

On Oct 11, 2012 6:32 PM, "Wolfgang Denk" <wd@denx.de> wrote:
>
> Dear Simon Glass,
>
> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
> > This is a ulong for some architectures and just unsigned for others.
> > Change x86 to be consistent.
>
> Given the limited range for this variable it makes no sense to use a
> long for this.  Please fix this the other way round, i. e. change the
> architectures that use a long.

Will unsigned hold 115200?

Regards,

Graeme

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Simon Glass]

Hi Wolfgang,

On Thu, Oct 11, 2012 at 12:32 AM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Simon Glass,
>
> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
>> This is a ulong for some architectures and just unsigned for others.
>> Change x86 to be consistent.
>
> Given the limited range for this variable it makes no sense to use a
> long for this.  Please fix this the other way round, i. e. change the
> architectures that use a long.

OK I will send out a series that changes them to unsigned long.

This sort of thing relates to the unified board init series I was
working on earlier it the year, since then all archs can use the same
structures for generic fields like baud rate. I hope to get back to
that one day.

Regards,
Simon

>
> Thanks.
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> Always try to do things in chronological order; it's  less  confusing
> that way.

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Graeme Russ]

Hi Simon,

On Fri, Oct 12, 2012 at 11:46 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi Wolfgang,
>
> On Thu, Oct 11, 2012 at 12:32 AM, Wolfgang Denk <wd@denx.de> wrote:
>> Dear Simon Glass,
>>
>> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
>>> This is a ulong for some architectures and just unsigned for others.
>>> Change x86 to be consistent.
>>
>> Given the limited range for this variable it makes no sense to use a
>> long for this.  Please fix this the other way round, i. e. change the
>> architectures that use a long.
>
> OK I will send out a series that changes them to unsigned long.

Should we just change them all to u32 to be clear on the value range?

Regards,

Graeme

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Simon Glass]

Hi,

On Thu, Oct 11, 2012 at 5:51 PM, Graeme Russ <graeme.russ@gmail.com> wrote:
> Hi Simon,
>
> On Fri, Oct 12, 2012 at 11:46 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi Wolfgang,
>>
>> On Thu, Oct 11, 2012 at 12:32 AM, Wolfgang Denk <wd@denx.de> wrote:
>>> Dear Simon Glass,
>>>
>>> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
>>>> This is a ulong for some architectures and just unsigned for others.
>>>> Change x86 to be consistent.
>>>
>>> Given the limited range for this variable it makes no sense to use a
>>> long for this.  Please fix this the other way round, i. e. change the
>>> architectures that use a long.
>>
>> OK I will send out a series that changes them to unsigned long.
>
> Should we just change them all to u32 to be clear on the value range?

Sorry, I meant unsigned int.

Are there architectures in U-Boot which use a 16-bit int?

Regards,
Simon

>
> Regards,
>
> Graeme

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Graeme Russ]

Hi Simon,

On Fri, Oct 12, 2012 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
> Hi,
>
> On Thu, Oct 11, 2012 at 5:51 PM, Graeme Russ <graeme.russ@gmail.com> wrote:
>> Hi Simon,
>>
>> On Fri, Oct 12, 2012 at 11:46 AM, Simon Glass <sjg@chromium.org> wrote:
>>> Hi Wolfgang,
>>>
>>> On Thu, Oct 11, 2012 at 12:32 AM, Wolfgang Denk <wd@denx.de> wrote:
>>>> Dear Simon Glass,
>>>>
>>>> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
>>>>> This is a ulong for some architectures and just unsigned for others.
>>>>> Change x86 to be consistent.
>>>>
>>>> Given the limited range for this variable it makes no sense to use a
>>>> long for this.  Please fix this the other way round, i. e. change the
>>>> architectures that use a long.
>>>
>>> OK I will send out a series that changes them to unsigned long.
>>
>> Should we just change them all to u32 to be clear on the value range?
>
> Sorry, I meant unsigned int.
>
> Are there architectures in U-Boot which use a 16-bit int?

The C standard does not guarantee unsigned int will be at least
32-bits. It is possible (although I have not checked it) that
compiling 'real-mode' x86 code can produce 16-bit ints (not that we do
that in U-Boot)

using u32 will always guarantee a 32-bit unsigned value - better to be
safe than sorry

Regards,

Graeme

[U-Boot] [PATCH v2 01/10] x86: Change board baud_rate to ulong

[Simon Glass]

Hi Graham,

On Thu, Oct 11, 2012 at 6:00 PM, Graeme Russ <graeme.russ@gmail.com> wrote:
> Hi Simon,
>
> On Fri, Oct 12, 2012 at 11:55 AM, Simon Glass <sjg@chromium.org> wrote:
>> Hi,
>>
>> On Thu, Oct 11, 2012 at 5:51 PM, Graeme Russ <graeme.russ@gmail.com> wrote:
>>> Hi Simon,
>>>
>>> On Fri, Oct 12, 2012 at 11:46 AM, Simon Glass <sjg@chromium.org> wrote:
>>>> Hi Wolfgang,
>>>>
>>>> On Thu, Oct 11, 2012 at 12:32 AM, Wolfgang Denk <wd@denx.de> wrote:
>>>>> Dear Simon Glass,
>>>>>
>>>>> In message <1349910781-32088-2-git-send-email-sjg@chromium.org> you wrote:
>>>>>> This is a ulong for some architectures and just unsigned for others.
>>>>>> Change x86 to be consistent.
>>>>>
>>>>> Given the limited range for this variable it makes no sense to use a
>>>>> long for this.  Please fix this the other way round, i. e. change the
>>>>> architectures that use a long.
>>>>
>>>> OK I will send out a series that changes them to unsigned long.
>>>
>>> Should we just change them all to u32 to be clear on the value range?
>>
>> Sorry, I meant unsigned int.
>>
>> Are there architectures in U-Boot which use a 16-bit int?
>
> The C standard does not guarantee unsigned int will be at least
> 32-bits. It is possible (although I have not checked it) that
> compiling 'real-mode' x86 code can produce 16-bit ints (not that we do
> that in U-Boot)
>
> using u32 will always guarantee a 32-bit unsigned value - better to be
> safe than sorry
>

That's fine, but what about all the other fields? Does the same apply
here? It seems that everything uses 'unsigned int' for u32:

arch/nds32/include/asm/types.h:47:typedef unsigned int u32;
arch/avr32/include/asm/types.h:65:typedef unsigned int u32;
arch/arm/include/asm/types.h:37:typedef unsigned int u32;
arch/sandbox/include/asm/types.h:59:typedef unsigned int u32;
arch/blackfin/include/asm/types.h:70:typedef unsigned int u32;
arch/openrisc/include/asm/types.h:64:typedef unsigned int u32;
arch/mips/include/asm/types.h:62:typedef unsigned int u32;
arch/x86/include/asm/types.h:37:typedef unsigned int u32;
arch/nios2/include/asm/types.h:45:typedef unsigned int u32;
arch/sh/include/asm/types.h:46:typedef unsigned int u32;
arch/microblaze/include/asm/types.h:45:typedef unsigned int u32;
arch/powerpc/include/asm/types.h:37:typedef unsigned int u32;
arch/m68k/include/asm/types.h:37:typedef unsigned int u32;
arch/sparc/include/asm/types.h:58:typedef unsigned int u32;


I wonder then if we need to decide which to use (int or long). I
presume 'long' was used to cope with 16-bit machines, but we don't
actually have any (which is presumably Wolfgang's point). If we don't
have any, then 'int' is safe. I'm just a bit unsure about changing a
single field in these two structures to u32, when all the others are
unsigned long/short.

For example:

typedef struct bd_info {
    int			bi_baudrate;	/* serial console baudrate */
    ulong	        bi_arch_number;	/* unique id for this board */
    ulong	        bi_boot_params;	/* where this board expects params */
	unsigned long	bi_arm_freq; /* arm frequency */
	unsigned long	bi_dsp_freq; /* dsp core frequency */
	unsigned long	bi_ddr_freq; /* ddr frequency */
    struct				/* RAM configuration */
    {
	ulong start;
	ulong size;
    }			bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;


typedef	struct	global_data {
	bd_t		*bd;
	unsigned long	flags;
	unsigned long	baudrate;
	unsigned long	have_console;	/* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
#endif
	unsigned long	env_addr;	/* Address  of Environment struct */
	unsigned long	env_valid;	/* Checksum of Environment valid? */
	unsigned long	fb_base;	/* base address of frame buffer */
#ifdef CONFIG_FSL_ESDHC
	unsigned long	sdhc_clk;
#endif
#ifdef CONFIG_AT91FAMILY
	/* "static data" needed by at91's clock.c */
	unsigned long	cpu_clk_rate_hz;
	unsigned long	main_clk_rate_hz;
	unsigned long	mck_rate_hz;
	unsigned long	plla_rate_hz;
	unsigned long	pllb_rate_hz;
	unsigned long	at91_pllb_usb_init;
#endif
#ifdef CONFIG_ARM
	/* "static data" needed by most of timer.c on ARM platforms */
	unsigned long	timer_rate_hz;
	unsigned long	tbl;
	unsigned long	tbu;
	unsigned long long	timer_reset_value;
	unsigned long	lastinc;


Guidance appreciated!

....

> Regards,
>
> Graeme

Regards,
Simon

[U-Boot] [PATCH v2 03/10] x86: Allow excluding reset vector code from u-boot

[Wolfgang Denk]

Dear Simon Glass,

In message <1349910781-32088-4-git-send-email-sjg@chromium.org> you wrote:
> From: Gabe Black <gabeblack@chromium.org>
> 
> When running from coreboot we don't want this code.
> 
> This version works by ifdef-ing out all of the code that would go
> into those sections and all the code that refers to it. The sections are
> then empty, and the linker will either leave them empty for the loader
> to ignore or remove them entirely.
> 
> Signed-off-by: Gabe Black <gabeblack@chromium.org>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
> Changes in v2:
> - Put CONFIG_NO_RESET_CODE into Makefile instead of source files

What exactly is CONFIG_NO_RESET_CODE ?

There is no documentation anywhere for such a config option as is
mandatory when introducing it, nor is there any comment why it would
be needed, nor are there any users for it.


>  Makefile                |    7 +++++--
>  arch/x86/cpu/Makefile   |    5 ++++-
>  arch/x86/cpu/u-boot.lds |    3 +++
>  3 files changed, 12 insertions(+), 3 deletions(-)
> 
> diff --git a/Makefile b/Makefile
> index 34d9075..6c2f357 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -212,9 +212,12 @@ endif
>  # U-Boot objects....order is important (i.e. start must be first)
>  
>  OBJS  = $(CPUDIR)/start.o
> +OBJS  = $(CPUDIR)/start.o
>  ifeq ($(CPU),x86)
> -OBJS += $(CPUDIR)/start16.o
> -OBJS += $(CPUDIR)/resetvec.o
> +	ifneq ($(CONFIG_NO_RESET_CODE),y)
> +		OBJS += $(CPUDIR)/start16.o
> +		OBJS += $(CPUDIR)/resetvec.o
> +	endif

NAK. Bad indentation, and please do without 'if's or the like.

> --- a/arch/x86/cpu/Makefile
> +++ b/arch/x86/cpu/Makefile
> @@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
>  
>  LIB	= $(obj)lib$(CPU).o
>  
> -START	= start.o start16.o resetvec.o
> +START	= start.o
> +ifneq ($(CONFIG_NO_RESET_CODE),y)
> +START	+= resetvec.o start16.o
> +endif

Ditto.

> --- a/arch/x86/cpu/u-boot.lds
> +++ b/arch/x86/cpu/u-boot.lds
> @@ -85,6 +85,8 @@ SECTIONS
>  	__bios_start = LOADADDR(.bios);
>  	__bios_size = SIZEOF(.bios);
>  
> +#ifndef CONFIG_NO_RESET_CODE

Undocumented.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
If I can have honesty, it's easier to overlook mistakes.
	-- Kirk, "Space Seed", stardate 3141.9

[U-Boot] [PATCH v2 03/10] x86: Allow excluding reset vector code from u-boot

[Simon Glass]

Hi Wolfgang,

On Mon, Nov 19, 2012 at 10:56 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Simon Glass,
>
> In message <1349910781-32088-4-git-send-email-sjg@chromium.org> you wrote:
>> From: Gabe Black <gabeblack@chromium.org>
>>
>> When running from coreboot we don't want this code.
>>
>> This version works by ifdef-ing out all of the code that would go
>> into those sections and all the code that refers to it. The sections are
>> then empty, and the linker will either leave them empty for the loader
>> to ignore or remove them entirely.
>>
>> Signed-off-by: Gabe Black <gabeblack@chromium.org>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>> Changes in v2:
>> - Put CONFIG_NO_RESET_CODE into Makefile instead of source files
>
> What exactly is CONFIG_NO_RESET_CODE ?
>
> There is no documentation anywhere for such a config option as is
> mandatory when introducing it, nor is there any comment why it would
> be needed, nor are there any users for it.
>

Based on your comments I will come up with another way of doing this
and send a new patch.

>
>>  Makefile                |    7 +++++--
>>  arch/x86/cpu/Makefile   |    5 ++++-
>>  arch/x86/cpu/u-boot.lds |    3 +++
>>  3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/Makefile b/Makefile
>> index 34d9075..6c2f357 100644
>> --- a/Makefile
>> +++ b/Makefile
>> @@ -212,9 +212,12 @@ endif
>>  # U-Boot objects....order is important (i.e. start must be first)
>>
>>  OBJS  = $(CPUDIR)/start.o
>> +OBJS  = $(CPUDIR)/start.o
>>  ifeq ($(CPU),x86)
>> -OBJS += $(CPUDIR)/start16.o
>> -OBJS += $(CPUDIR)/resetvec.o
>> +     ifneq ($(CONFIG_NO_RESET_CODE),y)
>> +             OBJS += $(CPUDIR)/start16.o
>> +             OBJS += $(CPUDIR)/resetvec.o
>> +     endif
>
> NAK. Bad indentation, and please do without 'if's or the like.
>
>> --- a/arch/x86/cpu/Makefile
>> +++ b/arch/x86/cpu/Makefile
>> @@ -28,7 +28,10 @@ include $(TOPDIR)/config.mk
>>
>>  LIB  = $(obj)lib$(CPU).o
>>
>> -START        = start.o start16.o resetvec.o
>> +START        = start.o
>> +ifneq ($(CONFIG_NO_RESET_CODE),y)
>> +START        += resetvec.o start16.o
>> +endif
>
> Ditto.
>
>> --- a/arch/x86/cpu/u-boot.lds
>> +++ b/arch/x86/cpu/u-boot.lds
>> @@ -85,6 +85,8 @@ SECTIONS
>>       __bios_start = LOADADDR(.bios);
>>       __bios_size = SIZEOF(.bios);
>>
>> +#ifndef CONFIG_NO_RESET_CODE
>
> Undocumented.
>
>
> Best regards,
>
> Wolfgang Denk
>
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
> If I can have honesty, it's easier to overlook mistakes.
>         -- Kirk, "Space Seed", stardate 3141.9

Regards,
Simon